Method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method, which comprises the following steps: providing a substrate, wherein the substrate comprises a high-voltage area, a source-drain area and an isolation area; forming a silicon nitride layer to cover the substrate, and etching and removing at least part of the thickness of the silicon nitride layer on the isolation area; etching and removing part of the thickness of the silicon nitride layer on the high-voltage area, so that the silicon nitride layer on the high-voltage area and the silicon nitride layer on the source-drain area have a height difference after etching; etching the substrate with the silicon nitride layer as a mask to form an isolation groove in the isolation area, and synchronously etching and removing the silicon nitride layer on the high-voltage area, so that the high-voltage area and the source-drain area have a height difference after etching, and the top edge of the high-voltage area is arc-shaped; and forming a first oxide layer to fill the isolation groove and cover the high-voltage area, and the surface of the first oxide layer is flat, and the first oxide layer on the high-voltage area serves as a gate oxide layer. The application can solve the problem of the warped foot of the high-voltage area edge, and does not increase the manufacturing cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor device. Background Technology

[0002] High-voltage semiconductor devices typically require thicker gate oxide layers due to their high operating voltages. Current fabrication processes usually involve first dry etching isolation trenches, which creates angled sidewalls, followed by the deposition of an isolation material layer to fill the trenches. Next, the high-voltage region is dry-etched to create grooves, and a gate oxide layer is grown within these grooves. During this step, edge lifting of the high-voltage region is a common occurrence.

[0003] Figure 1 This is a schematic cross-sectional view of the semiconductor device fabrication process after the isolation trench has been formed. Please refer to the diagram. Figure 1 A substrate 10 is provided, the substrate 10 includes a high voltage region 11, a first silicon nitride layer 21 is formed on the substrate 10, the first silicon nitride layer 21 is patterned using a photomask, and after patterning, the first silicon nitride layer 21 is used as a hard mask, and the substrate 10 is dry etched to form a plurality of isolation trenches 30, and the substrate 10 between some adjacent two isolation trenches 30 is the high voltage region 11.

[0004] Figure 2 This is a schematic cross-sectional view of the semiconductor device fabrication process after the deposition of an isolation material layer. Figure 3 This is a schematic cross-sectional view of the semiconductor device fabrication process after removing the first silicon nitride layer. Please refer to the diagram. Figure 2 A layer of deposited isolation material is filled into the isolation trench 30 to obtain the trench isolation structure 32; please refer to Figure 3 Remove the retained first silicon nitride layer 21.

[0005] Figure 4 This is a cross-sectional schematic diagram showing the formation of a second silicon nitride layer and a patterned photoresist layer in a conventional semiconductor device fabrication method. Please refer to... Figure 4 A second silicon nitride layer 22 and a patterned photoresist layer 40 are sequentially formed on the substrate 10 and the trench isolation structure 32.

[0006] Figure 5 This is a schematic cross-sectional view of the high-voltage region after etching to form a groove in a conventional semiconductor device fabrication method. Figure 6 This is a partial electron microscope (EM) schematic diagram of the process after etching a high-voltage region to form a groove in a conventional semiconductor device fabrication method. Please refer to [reference needed]. Figure 5The second silicon nitride layer 22 is etched using a patterned photoresist layer 40 to expose the high-voltage region 11. Then, the high-voltage region 11 is dry-etched to form a trench 12. Subsequently, the second silicon nitride layer 22 and the patterned photoresist layer 40 are removed. Because the sidewalls of the isolation trench have a certain angle, the edges of the high-voltage region 11 are irregularly etched after etching, resulting in a warped corner. Figure 5 (As shown in the dotted circular frame), and this step will cause damage to the isolation material layer within the isolation trench. Please refer to... Figure 6 The black, upward-curving part within the circular dashed frame represents the formed upturned corner, and the black area in the diagram represents the high-voltage zone, with trench isolation structures on both sides of the high-voltage zone.

[0007] Figure 7 This is a schematic cross-sectional view of the semiconductor device after the gate oxide layer has been formed in a conventional semiconductor device fabrication method. Figure 8 This is a partial electron microscope (EM) schematic diagram of the semiconductor device fabrication process after the formation of the gate oxide layer. Please refer to [reference needed]. Figure 7 A gate oxide layer 50 is grown in the trench. Because the previous etching step causes loss of the isolation material layer within the isolation trench, the surface of the gate oxide layer 50 and the trench isolation structure 32 becomes uneven after the gate oxide layer 50 is formed, affecting the subsequent fabrication window. Please refer to... Figure 8 The recess in the circular dashed frame indicates that the surface of the gate oxide layer and the trench isolation structure is not flat.

[0008] Currently, the common method to improve warp is to reduce its degree using over-etching. However, due to the angle of the isolation trench, warp cannot be completely eliminated. Furthermore, excessive etching can cause excessive loss of the isolation material layer within the trench, resulting in uneven surfaces where the gate oxide layer and the trench isolation structure are close together, affecting subsequent fabrication windows. In summary, after forming the gate oxide layer, the following problems may occur: 1. Warp causes the gate oxide layer at the edge of the high-voltage region to be thinner, affecting device reliability; 2. A thinner gate oxide layer at the edge of the high-voltage region reduces the equivalent oxide layer thickness of the device, exacerbating the short-channel effect; 3. Warp at the edge of the high-voltage region makes the electric field more concentrated during device operation, increasing carrier scattering and affecting the device's electrical performance; 4. Uneven surfaces above the high-voltage region affect subsequent fabrication windows. Summary of the Invention

[0009] The purpose of this invention is to provide a method for fabricating semiconductor devices that solves the problem of edge lifting in the high-voltage region without increasing the fabrication cost.

[0010] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device, comprising:

[0011] A substrate is provided, the substrate comprising a high-voltage region, a source / drain region, and an isolation region;

[0012] A silicon nitride layer is formed to cover the substrate, and the silicon nitride layer with at least a portion of its thickness on the isolation region is etched away.

[0013] The silicon nitride layer with a certain thickness on the high voltage region is removed by etching. After etching, the silicon nitride layer on the high voltage region and the silicon nitride layer on the source and drain regions have a height difference.

[0014] The substrate is etched using the silicon nitride layer as a mask to form isolation trenches in the isolation region, and the silicon nitride layer on the high voltage region is simultaneously etched away. After etching, the high voltage region and the source / drain region have a height difference, and the top edge of the high voltage region is arc-shaped.

[0015] A first oxide layer is formed to fill the isolation trench and cover the high voltage region, and the surface of the first oxide layer is flat. The first oxide layer on the high voltage region serves as the gate oxide layer.

[0016] Optionally, the step of etching away a portion of the silicon nitride layer on the upper part of the isolation region includes:

[0017] A first patterned photoresist layer is formed to cover the silicon nitride layer on the high voltage region and the source / drain region;

[0018] Using the first patterned photoresist layer as a mask, a portion of the silicon nitride layer on the upper part of the isolation region is etched away;

[0019] Remove the first patterned photoresist layer.

[0020] Optionally, the step of etching away a portion of the silicon nitride layer in the high-voltage region includes:

[0021] A second patterned photoresist layer is formed to cover the silicon nitride layer on the isolation region and the source / drain region;

[0022] Using the second patterned photoresist layer as a mask, a portion of the silicon nitride layer on the high voltage region is etched away. After etching, the thickness of the silicon nitride layer on the high voltage region is between the thickness of the silicon nitride layer on the isolation region and the thickness of the silicon nitride layer on the source / drain region.

[0023] Remove the second patterned photoresist layer.

[0024] Optionally, before etching the substrate using the silicon nitride layer as a mask, the process further includes etching away the remaining thickness of the silicon nitride layer on the isolation region.

[0025] Optionally, the step of etching away the silicon nitride layer on the isolation region includes:

[0026] A first patterned photoresist layer is formed to cover the silicon nitride layer on the high voltage region and the source / drain region;

[0027] Using the first patterned photoresist layer as a mask, the silicon nitride layer on the isolation region is etched away.

[0028] Remove the first patterned photoresist layer.

[0029] Optionally, the step of etching away a portion of the silicon nitride layer in the high-voltage region includes:

[0030] A second patterned photoresist layer is formed to cover the silicon nitride layer and the isolation region on the source / drain regions;

[0031] Using the second patterned photoresist layer as a mask, the silicon nitride layer with a portion of its thickness in the high voltage region is etched away.

[0032] Remove the second patterned photoresist layer.

[0033] Optionally, after etching the substrate using the silicon nitride layer as a mask, a portion of the thickness of the silicon nitride layer is retained on the source / drain regions.

[0034] Optionally, after etching the substrate using the silicon nitride layer as a mask, the process further includes removing the silicon nitride layer retained on the source / drain regions.

[0035] Optionally, after removing the silicon nitride layer retained on the source / drain region, a second oxide layer is formed on the surface of the substrate using a thermal oxidation process.

[0036] Optionally, the step of forming the first oxide layer to fill the isolation trench and cover the high-voltage area includes:

[0037] The first oxide layer is deposited to fill the isolation trench and cover the source / drain region and the high-voltage region;

[0038] A chemical mechanical polishing process is performed on the first oxide layer to remove the first oxide layer on the source / drain region to expose the surface of the source / drain region.

[0039] The method for fabricating a semiconductor device provided by the present invention includes: providing a substrate, the substrate including a high-voltage region, a source / drain region, and an isolation region; forming a silicon nitride layer to cover the substrate, and etching away at least a portion of the thickness of the silicon nitride layer on the isolation region; etching away a portion of the thickness of the silicon nitride layer on the high-voltage region, such that after etching, the silicon nitride layer on the high-voltage region and the silicon nitride layer on the source / drain region have a height difference; etching the substrate using the silicon nitride layer as a mask to form an isolation trench in the isolation region, and simultaneously etching away the silicon nitride layer on the high-voltage region, such that after etching, the high-voltage region and the source / drain region have a height difference, and the top edge of the high-voltage region is arc-shaped; forming a first oxide layer to fill the isolation trench and cover the high-voltage region, wherein the surface of the first oxide layer is flat, and the first oxide layer on the high-voltage region serves as a gate oxide layer. The unexpected technical effect of this invention is that by first etching the silicon nitride layer to create a height difference between the silicon nitride layer on the high-voltage region and the silicon nitride layer on the source / drain region, and then using the silicon nitride layer as a mask to etch the substrate to form an isolation trench, the high-voltage region and the source / drain region have a height difference after etching, and the top edge of the high-voltage region is arc-shaped, so that there is no edge lifting of the high-voltage region, thereby solving the edge lifting problem of the high-voltage region. Furthermore, after the first oxide layer is formed to fill the isolation trench and cover the high-voltage region, the surface of the first oxide layer is flat. Moreover, this invention does not require an additional photomask and will not increase the manufacturing cost. Attached Figure Description

[0040] Figure 1 This is a schematic cross-sectional view of the semiconductor device fabrication method in the prior art after the isolation trench has been formed.

[0041] Figure 2 This is a schematic cross-sectional view of the semiconductor device fabrication method in the prior art after the deposition of an isolation material layer.

[0042] Figure 3 This is a schematic cross-sectional view of the semiconductor device fabrication method in the prior art after removing the first silicon nitride layer.

[0043] Figure 4 This is a cross-sectional schematic diagram of the semiconductor device fabrication method in the prior art after the formation of the second silicon nitride layer and the patterned photoresist layer.

[0044] Figure 5 This is a cross-sectional schematic diagram of the high-voltage region after etching to form a groove in the existing semiconductor device fabrication method.

[0045] Figure 6 This is a partial electron microscope (EM) schematic diagram of the process after etching a high-voltage region to form a groove in the fabrication method of semiconductor devices in the prior art.

[0046] Figure 7 This is a schematic cross-sectional view of the semiconductor device after the gate oxide layer has been formed in the existing semiconductor device fabrication method.

[0047] Figure 8This is a partial electron microscope (EM) schematic diagram of the semiconductor device fabrication process after the formation of the gate oxide layer.

[0048] Figure 9 A flowchart of a method for fabricating a semiconductor device provided by the present invention.

[0049] Figure 10 This is a cross-sectional schematic diagram of a portion of the silicon nitride layer on the isolation region after etching in the semiconductor device fabrication method provided in Embodiment 1 of the present invention.

[0050] Figure 11 This is a cross-sectional schematic diagram of the silicon nitride layer after etching in the high-voltage region in the method for fabricating a semiconductor device according to Embodiment 1 of the present invention.

[0051] Figure 12 This is a cross-sectional schematic diagram after etching the remaining silicon nitride layer on the isolation region in the method for fabricating a semiconductor device according to Embodiment 1 of the present invention.

[0052] Figure 13 This is a cross-sectional schematic diagram of the semiconductor device fabrication method provided in Embodiment 1 of the present invention after the isolation trench has been formed.

[0053] Figure 14 This is a cross-sectional schematic diagram of the semiconductor device fabrication method provided in Embodiment 1 of the present invention after the formation of the second oxide layer.

[0054] Figure 15 This is a cross-sectional schematic diagram of the semiconductor device fabrication method provided in Embodiment 1 of the present invention after the formation of the first oxide layer.

[0055] Figure 16 This is a cross-sectional schematic diagram of the semiconductor device fabrication method provided in Embodiment 1 of the present invention after performing a chemical mechanical polishing process.

[0056] Figure 17 This is a cross-sectional schematic diagram after etching the silicon nitride layer on the isolation region in the method for fabricating a semiconductor device according to Embodiment 2 of the present invention.

[0057] Figure 18 This is a cross-sectional schematic diagram of the silicon nitride layer after etching in the high-voltage region in the semiconductor device fabrication method provided in Embodiment 2 of the present invention.

[0058] in, Figures 1-8 The attached figures are labeled as follows:

[0059] 10-Substrate; 11-High voltage region; 12-Groove; 21-First silicon nitride layer; 22-Second silicon nitride layer; 30-Isolation trench; 32-Trench isolation structure; 40-Patterned photoresist layer; 50-Gate oxide layer.

[0060] Figures 10-18The attached figures are labeled as follows:

[0061] 100 - Substrate; 110 - High voltage region; 120 - Isolation region; 130 - Source / drain region; 200 - Silicon nitride layer; 310 - First patterned photoresist layer; 320 - Second patterned photoresist layer; 400 - Isolation trench; 510 - First oxide layer; 520 - Second oxide layer. Detailed Implementation

[0062] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0063] Please refer to Figure 9 This invention provides a method for fabricating a semiconductor device, comprising:

[0064] Step S1: Provide a substrate, which includes a high-voltage region, a source / drain region, and an isolation region;

[0065] Step S2: Form a silicon nitride layer to cover the substrate, and etch away at least a portion of the thickness of the silicon nitride layer on the isolation region;

[0066] Step S3: Etch away the silicon nitride layer of a certain thickness in the high voltage region. After etching, the silicon nitride layer in the high voltage region and the silicon nitride layer in the source and drain regions have a height difference.

[0067] Step S4: Use the silicon nitride layer as a mask to etch the substrate to form isolation trenches in the isolation region, and the silicon nitride layer on the high voltage region is simultaneously etched away. After etching, the high voltage region and the source / drain region have a height difference, and the top edge of the high voltage region is arc-shaped.

[0068] Step S5: A first oxide layer is formed to fill the isolation trench and cover the high voltage region, and the surface of the first oxide layer is flat. The first oxide layer on the high voltage region serves as the gate oxide layer.

[0069] This invention first etches a silicon nitride layer to create a height difference between the silicon nitride layer on the high-voltage region and the silicon nitride layer on the source / drain region. Then, using the silicon nitride layer as a mask, it etches the substrate to form an isolation trench. After etching, the high-voltage region and the source / drain region have a height difference, and the top edge of the high-voltage region is arc-shaped, so that the edge of the high-voltage region will not have a raised edge, thus solving the problem of raised edge of the high-voltage region. Furthermore, after the first oxide layer is formed to fill the isolation trench and cover the high-voltage region, the surface of the first oxide layer is flat. Moreover, this invention does not require an additional photomask and will not increase the manufacturing cost.

[0070] Example 1

[0071] The following is combined with Figures 10-16The method for fabricating the semiconductor device provided in this embodiment will be described in detail.

[0072] Please refer to Figure 10 Step S1: Provide a substrate 100, wherein the substrate 100 is preferably a silicon substrate; the substrate 100 includes a high voltage region 110, a source / drain region 130 and an isolation region 120, the isolation region 120 is located between the source / drain region 130 and the high voltage region 110. The semiconductor device in this embodiment is a high voltage device, and the source / drain region 130 and the high voltage region 110 need to be isolated by the isolation region 120.

[0073] Please refer to Figure 10 Step S2 is executed as follows: a silicon nitride layer 200 is formed to cover the substrate 100 (high voltage region 110, source / drain region 130, and isolation region 120), and a first patterned photoresist layer 310 is formed to cover the silicon nitride layer 200 on the high voltage region 110 and the source / drain region 130; then, using the first patterned photoresist layer 310 as a mask, a portion of the thickness of the silicon nitride layer 200 on the isolation region 120 is etched away, and then the first patterned photoresist layer 310 is removed. In this embodiment, etching away a portion of the thickness of the silicon nitride layer 200 on the isolation region 120 while retaining a portion of the silicon nitride layer 200 on the isolation region 120 can protect the surface of the isolation region 120 from contacting the subsequently formed second patterned photoresist layer.

[0074] Please refer to Figure 11 Step S3: A second patterned photoresist layer 320 is formed to cover the silicon nitride layer 200 on the isolation region 120 and the source / drain region 130, exposing the silicon nitride layer 200 on the high voltage region 110. Since a portion of the silicon nitride layer 200 is retained on the isolation region 120, the second patterned photoresist layer 320 does not directly contact the surface of the isolation region 120, thus avoiding photoresist residue on the surface of the isolation region 120 after the second patterned photoresist layer 320 is removed. Then, using the second patterned photoresist layer 320 as a mask, the silicon nitride layer 200 on the high voltage region 110 is etched away. A partial thickness of silicon nitride layer 200, after etching, the silicon nitride layer 200 on the high voltage region 110 and the silicon nitride layer 200 on the source / drain region 130 have a height difference, specifically, the top surface of the silicon nitride layer 200 on the high voltage region 110 is lower than the top surface of the silicon nitride layer 200 on the source / drain region 130 (the height difference between the two top surfaces is h1), and the thickness of the silicon nitride layer 200 on the high voltage region 110 after etching is between the thickness of the silicon nitride layer 200 on the isolation region 120 and the thickness of the silicon nitride layer 200 on the source / drain region 130; then the second patterned photoresist layer 320 is removed.

[0075] Further, please refer to Figure 12Since a portion of the silicon nitride layer 200 is retained on the isolation region 120, before etching the substrate 100 using the silicon nitride layer 200 as a mask, the remaining thickness of the silicon nitride layer 200 on the isolation region 120 is removed by etching. This etching step uses dry etching, which does not require a photomask and directly etches the silicon nitride layer 200. Since the thicknesses of the silicon nitride layer 200 on the high voltage region 110, the source / drain region 130, and the isolation region 120 are different, the etching time is controlled to simultaneously etch the silicon nitride layer 200 on the high voltage region 110, the source / drain region 130, and the isolation region 120, so that the etching stops at the surface of the isolation region 120. After etching, the silicon nitride layer 200 is retained on the high voltage region 110 and the source / drain region 130, and the silicon nitride layer 200 on the high voltage region 110 and the source / drain region 130 has a height difference (the height difference is still approximately the same as before etching, which is h1).

[0076] In this embodiment, the etching conditions for etching away the remaining thickness of the silicon nitride layer 200 on the isolation region 120 are as follows: the etching gas includes CF4 and O2, and the etching is performed at a pressure of 50 mtorr and a power of 400 W. Under these etching conditions, the etching rate of the silicon nitride layer 200 is 300 Å / min. Since the thicknesses of the silicon nitride layer 200 on the high voltage region 110, the source / drain region 130, and the isolation region 120 are different—for example, the thickness of the silicon nitride layer 200 on the source / drain region 130 is 300 Å, the thickness of the silicon nitride layer 200 on the high voltage region 110 is 200 Å, and the thickness of the silicon nitride layer 200 on the isolation region 120 is 100 Å—the etching time can be selected as 20 s based on the above etching conditions. After etching, the thickness of the silicon nitride layer 200 on the source / drain region 130 is 200 Å, the thickness of the silicon nitride layer 200 on the high voltage region 110 is 100 Å, and there is no silicon nitride layer 200 on the isolation region 120.

[0077] Please refer to Figure 13Step S4 is executed: using the silicon nitride layer 200 as a mask, the substrate 100 (isolation region 120 and high voltage region 110) is etched to form an isolation trench 400 in the isolation region 120. Since the high voltage region 110 and the source / drain region 130 have silicon nitride layers 200 as masks, the isolation region 120 is not masked and will be etched in large quantities to form isolation trenches 400. Furthermore, since the thickness of the silicon nitride layer 200 on the high voltage region 110 is thinner than that on the source / drain region 130, the silicon nitride layers 200 on the source / drain region 130 and the high voltage region 110 are etched simultaneously during the etching process. This results in the simultaneous removal of the silicon nitride layer 200 on the high voltage region 110, and also removes part of the thickness of the high voltage region 110. This results in a height difference between the high voltage region 110 and the source / drain region 130 after etching. Specifically, the top surface of the high voltage region 110 is lower than the top surface of the source / drain region 130 (the height difference between the two top surfaces is h2. Since the etching involves different materials, the height difference h2 after etching may be different from h1). This etching step uses dry etching. After etching, the sidewalls of the isolation trench 400 are tilted, and the top edge of the high voltage zone 110 is a smooth arc, so that the edge of the high voltage zone 110 will not have raised edges, thus solving the problem of raised edges of the high voltage zone 110.

[0078] In this embodiment, the etching conditions for etching the substrate 100 using the silicon nitride layer 200 as a mask are as follows: the etching gas includes hydrogen bromide and helium, and etching is performed at a pressure of 20 mtorr to 30 mtorr and a power of 200 W. Under these etching conditions, the etching rate for the substrate 100 (silicon material) is 2000 Å / min, and the etching rate for the silicon nitride layer 200 is 100 Å / min. Because the substrate 100 and the silicon nitride layer 200 are made of different materials and have different etching rates, the silicon nitride layer 200 on the source / drain region 130 and the high-voltage region 110 are etched simultaneously when the isolation trench 400 is formed. For example, if the required depth of the isolation trench 400 is 3000 Å, then according to the above etching conditions, the etching time can be selected as 90 s. The thickness of the remaining silicon nitride layer 200 on the high voltage region 110 and the source / drain region 130 can be precisely adjusted in advance through this etching condition so that the etching reaches the target depth of the isolation trench 400 and the etching depth of the high voltage region 110 reaches the expected set value.

[0079] Furthermore, after etching the substrate 100 using the silicon nitride layer 200 as a mask, a portion of the silicon nitride layer 200 is retained on the source / drain region 130 to avoid etching the source / drain region 130. By controlling the thickness difference (i.e., adjusting the height difference) between the high voltage region 110 and the silicon nitride layer 200 on the source / drain region 130, the depth of the isolation trench 400 and the thickness removed by etching the high voltage region 110 can be controlled.

[0080] Furthermore, after etching the substrate 100 using the silicon nitride layer 200 as a mask, the process also includes removing the silicon nitride layer 200 retained on the source / drain region 130 by hot phosphoric acid wet etching.

[0081] Further, please refer to Figure 14 After removing the silicon nitride layer 200 retained on the source / drain region 130, the process further includes forming a second oxide layer 520 on the surface of the substrate 100 using a thermal oxidation process. Specifically, the second oxide layer 520 is formed to cover the inner wall of the isolation trench 400, the high voltage region 110, and the source / drain region 130. The second oxide layer 520 is formed by high-temperature oxidation of the substrate 100, which can repair damage to the surface of the substrate 100 and improve electrical parameters. The second oxide layer 520 is thin and dense. The thickness of the second oxide layer 520 is less than the height difference between the high voltage region 110 and the source / drain region 130. Preferably, the thickness of the second oxide layer 520 is less than half of the height difference between the high voltage region 110 and the source / drain region 130.

[0082] Please refer to Figure 15 and 16 Step S5: A first oxide layer 510 is deposited to fill the isolation trench 400 and cover the source / drain region 130 and the high voltage region 110. Then, the first oxide layer 510 is thermally annealed to improve its density and improve defects. Then, a chemical mechanical polishing process is performed on the first oxide layer 510 to polish and remove the first oxide layer 510 on the source / drain region 130 to expose the surface of the source / drain region 130. After polishing, the surface of the first oxide layer 510 is flat, and the first oxide layer 510 on the high voltage region 110 serves as the gate oxide layer.

[0083] In this embodiment, the silicon nitride layer is first etched to create a height difference between the silicon nitride layer on the high-voltage region and the silicon nitride layer on the source / drain region. Then, the substrate is etched using the silicon nitride layer as a mask to form an isolation trench. After etching, the high-voltage region and the source / drain region have a height difference, and the top edge of the high-voltage region is arc-shaped, preventing edge warping and thus solving the edge warping problem of the high-voltage region. Furthermore, after the first oxide layer is formed to fill the isolation trench and cover the high-voltage region, the surface of the first oxide layer is flat, which is beneficial for subsequent fabrication windows. In addition, in the prior art, photomasks (two photomasks) are used when etching to form the isolation trench and etching the high-voltage region. In this embodiment, photomasks (two photomasks) are used when etching the silicon nitride layer in the isolation region and the silicon nitride layer in the high-voltage region. Therefore, this embodiment does not require additional photomasks and will not increase the fabrication cost.

[0084] Example 2

[0085] Please refer to Figure 17 and Figure 18 The difference between this embodiment and Embodiment 1 is that in step S2, all the silicon nitride layer 200 on the isolation region 120 is etched away (the silicon nitride layer 200 is not retained, see reference). Figure 17 ), and in step S3, a second patterned photoresist layer 320 is formed to cover the silicon nitride layer 200 and the isolation region 120 on the source / drain region 130 (the second patterned photoresist layer 320 is in direct contact with the isolation region 120, see reference). Figure 18 Therefore, since the silicon nitride layer 200 is not retained on the isolation region 120, this embodiment does not require additional etching to remove the silicon nitride layer 200 retained on the isolation region 120 as in Embodiment 1.

[0086] For details, please refer to Figure 17 The step of etching away the silicon nitride layer 200 on the isolation region 120 includes: forming a first patterned photoresist layer 310 to cover the silicon nitride layer 200 on the high voltage region 110 and the source / drain region 130; then, using the first patterned photoresist layer 310 as a mask, etching away the silicon nitride layer 200 on the isolation region 120, and then removing the first patterned photoresist layer 310.

[0087] Please refer to Figure 18 The step of etching away a portion of the thickness of the silicon nitride layer 200 on the high voltage region 110 includes: forming a second patterned photoresist layer 320 to cover the silicon nitride layer 200 and the isolation region 120 on the source / drain region 130; then, using the second patterned photoresist layer 320 as a mask, etching away a portion of the thickness of the silicon nitride layer 200 on the high voltage region 110. After etching, the silicon nitride layer 200 on the high voltage region 110 and the silicon nitride layer 200 on the source / drain region 130 have a height difference, specifically, the top surface of the silicon nitride layer 200 on the high voltage region 110 is lower than the top surface of the silicon nitride layer 200 on the source / drain region 130 (the height difference between the two top surfaces is h1); and then removing the second patterned photoresist layer 320.

[0088] In summary, the method for fabricating a semiconductor device provided by the present invention includes: providing a substrate, the substrate including a high-voltage region, a source / drain region, and an isolation region; forming a silicon nitride layer to cover the substrate, and etching away at least a portion of the thickness of the silicon nitride layer on the isolation region; etching away a portion of the thickness of the silicon nitride layer on the high-voltage region, such that after etching, the silicon nitride layer on the high-voltage region and the silicon nitride layer on the source / drain region have a height difference; etching the substrate using the silicon nitride layer as a mask to form an isolation trench in the isolation region, and simultaneously etching away the silicon nitride layer on the high-voltage region, such that after etching, the high-voltage region and the source / drain region have a height difference, and the top edge of the high-voltage region is arc-shaped; forming a first oxide layer to fill the isolation trench and cover the high-voltage region, and the surface of the first oxide layer is flat, the first oxide layer on the high-voltage region serving as a gate oxide layer. The unexpected technical effect of this invention is that by first etching the silicon nitride layer to create a height difference between the silicon nitride layer on the high-voltage region and the silicon nitride layer on the source / drain region, and then using the silicon nitride layer as a mask to etch the substrate to form an isolation trench, the high-voltage region and the source / drain region have a height difference after etching, and the top edge of the high-voltage region is arc-shaped, so that there is no edge lifting of the high-voltage region, thereby solving the edge lifting problem of the high-voltage region. Furthermore, after the first oxide layer is formed to fill the isolation trench and cover the high-voltage region, the surface of the first oxide layer is flat. Moreover, this invention does not require an additional photomask and will not increase the manufacturing cost.

[0089] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising a high-voltage region, a source / drain region, and an isolation region; A silicon nitride layer is formed to cover the substrate, and the silicon nitride layer with at least a portion of its thickness on the isolation region is etched away. The silicon nitride layer with a certain thickness on the high voltage region is removed by etching. After etching, the silicon nitride layer on the high voltage region and the silicon nitride layer on the source and drain regions have a height difference. The substrate is etched using the silicon nitride layer as a mask to form isolation trenches in the isolation region, and the silicon nitride layer on the high voltage region is simultaneously etched away. After etching, the high voltage region and the source / drain region have a height difference, and the top edge of the high voltage region is arc-shaped. A first oxide layer is formed to fill the isolation trench and cover the high voltage region, and the surface of the first oxide layer is flat. The first oxide layer on the high voltage region serves as the gate oxide layer.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of etching away a portion of the silicon nitride layer on top of the isolation region includes: A first patterned photoresist layer is formed to cover the silicon nitride layer on the high voltage region and the source / drain region; Using the first patterned photoresist layer as a mask, a portion of the silicon nitride layer on the upper part of the isolation region is etched away; Remove the first patterned photoresist layer.

3. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The step of etching away a portion of the silicon nitride layer in the high-voltage region includes: A second patterned photoresist layer is formed to cover the silicon nitride layer on the isolation region and the source / drain region; Using the second patterned photoresist layer as a mask, a portion of the silicon nitride layer on the high voltage region is etched away. After etching, the thickness of the silicon nitride layer on the high voltage region is between the thickness of the silicon nitride layer on the isolation region and the thickness of the silicon nitride layer on the source / drain region. Remove the second patterned photoresist layer.

4. The method for fabricating a semiconductor device as described in claim 2, characterized in that, Before etching the substrate using the silicon nitride layer as a mask, the process further includes etching away the remaining thickness of the silicon nitride layer on the isolation region.

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of etching away the silicon nitride layer on the isolation region includes: A first patterned photoresist layer is formed to cover the silicon nitride layer on the high voltage region and the source / drain region; Using the first patterned photoresist layer as a mask, the silicon nitride layer on the isolation region is etched away. Remove the first patterned photoresist layer.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The step of etching away a portion of the silicon nitride layer in the high-voltage region includes: A second patterned photoresist layer is formed to cover the silicon nitride layer and the isolation region on the source / drain regions; Using the second patterned photoresist layer as a mask, the silicon nitride layer with a portion of its thickness in the high voltage region is etched away. Remove the second patterned photoresist layer.

7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, After etching the substrate using the silicon nitride layer as a mask, a portion of the thickness of the silicon nitride layer remains on the source / drain regions.

8. The method for fabricating a semiconductor device as described in claim 7, characterized in that, After etching the substrate using the silicon nitride layer as a mask, the process further includes removing the silicon nitride layer remaining on the source / drain regions.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, After removing the silicon nitride layer retained on the source / drain region, a second oxide layer is formed on the surface of the substrate using a thermal oxidation process.

10. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of forming the first oxide layer to fill the isolation trench and cover the high-voltage area includes: The first oxide layer is deposited to fill the isolation trench and cover the source / drain region and the high-voltage region; A chemical mechanical polishing process is performed on the first oxide layer to remove the first oxide layer on the source / drain region to expose the surface of the source / drain region.

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