Switched capacitor network band-gap voltage reference circuit and temperature compensation method thereof

Abstract

The invention discloses a switched capacitor network band-gap voltage reference circuit and a temperature compensation method thereof, and the circuit comprises a clock signal and VEB voltage generation circuit, a switched capacitor network circuit and a deep n-well NMOS transistor leakage current compensation circuit, the clock signal and VEB voltage generation circuit is used for generating a clock control signal, a first negative temperature coefficient voltage and a second negative temperature coefficient voltage; the deep n-well NMOS transistor leakage current compensation circuit is used for generating compensation current according to the clock signal and the output of the VEB voltage generation circuit; the switched capacitor network circuit is used for generating a reference voltage according to the clock control signal, the first negative temperature coefficient voltage, the second negative temperature coefficient voltage and the compensation current. According to the band-gap voltage reference circuit, the temperature sensitivity of the reference voltage can be reduced through the leakage current compensation circuit, and then the precision of the band-gap voltage reference circuit is further improved. The circuit can be widely applied to the technical field of power management integrated circuits.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power management integrated circuits, and in particular to a switched capacitor network bandgap voltage reference circuit and a temperature compensation method thereof. BACKGROUND

[0002] Bandgap reference voltage source (BGR) is one of the basic constituent circuits in integrated circuits, and its purpose is to provide an accurate reference voltage for other circuits which is not sensitive to working temperature, power supply voltage, process deviation and circuit load. Internet of Things (IoT) is a rapidly developing market, and a large number of IoT devices rely on batteries for power supply. Frequent replacement of batteries will increase the maintenance difficulty and cost of IoT devices.

[0003] Due to the low power consumption characteristics (usually only tens of nW) of the BGR based on the switched capacitor network (SCN), such design is very suitable for use in IoT devices. However, the most advanced SCN BGRs currently still require a supply voltage greater than or equal to 0.5V, and therefore cannot directly use an energy harvesting source (usually only 0.35V) as the supply voltage, which will greatly reduce the overall efficiency of the system. In addition, due to the reasons such as BJT bias, leakage current, non-linear parasitic effects in SCN and lack of curvature compensation, SCN BGRs have a large temperature coefficient (TC) and a limited temperature range. Although curvature compensation technology is very common in traditional BGR circuits, existing curvature compensation technologies consume a large current and thus result in high power consumption, and therefore are not suitable for SCN BGRs.

[0004] In summary, the technical problems in the related art need to be improved. SUMMARY

[0005] The main purpose of the embodiments of the present application is to provide a switched capacitor network bandgap voltage reference circuit and a temperature compensation method thereof, which can reduce the temperature sensitivity of the reference voltage through a leakage current compensation circuit, and further improve the accuracy of the bandgap voltage reference circuit.

[0006] To achieve the above purpose, one aspect of the embodiments of the present application provides a switched capacitor network bandgap voltage reference circuit, which comprises a clock signal and VEB voltage generation circuit, a switched capacitor network circuit and a deep n-well NMOS transistor leakage current compensation circuit, wherein a first output end of the clock signal and VEB voltage generation circuit is connected with an input end of the deep n-well NMOS transistor leakage current compensation circuit, a second output end of the clock signal and VEB voltage generation circuit and an output end of the deep n-well NMOS transistor leakage current compensation circuit are respectively connected with an input end of the switched capacitor network circuit, and wherein:

[0007] The clock signal and VEB voltage generation circuit is configured to generate a clock control signal, a first negative temperature coefficient voltage, and a second negative temperature coefficient voltage.

[0008] The deep n-well NMOS transistor leakage current compensation circuit is configured to generate a compensation current according to outputs of the clock signal and VEB voltage generation circuit.

[0009] The switched capacitor network circuit is configured to generate a reference voltage according to the clock control signal, the first negative temperature coefficient voltage, the second negative temperature coefficient voltage, and the compensation current.

[0010] In some embodiments, the clock signal and VEB voltage generation circuit comprises a clock signal generation circuit and a voltage generator, wherein:

[0011] The clock signal generation circuit is configured to generate the clock control signal.

[0012] The voltage generator is configured to generate the first negative temperature coefficient voltage and the second negative temperature coefficient voltage.

[0013] In some embodiments, the clock signal and VEB voltage generation circuit further comprises a first positive temperature coefficient frequency oscillator, a second positive temperature coefficient frequency oscillator, a non-overlapping circuit, a first clock booster, a second clock booster, a third clock booster, a bootstrap circuit, a triple charge pump, and a negative temperature coefficient voltage generation core circuit, an output terminal of the first positive temperature coefficient frequency oscillator is connected to an output terminal of the non-overlapping circuit, a first output terminal of the non-overlapping circuit is connected to an input terminal of the first clock booster, a second output terminal of the non-overlapping circuit is connected to an input terminal of the second clock booster, output terminals of the first clock booster and the second clock booster are respectively connected to input terminals of the triple charge pump, an output terminal of the second positive temperature coefficient frequency oscillator is connected to an input terminal of the third clock booster, an output terminal of the third clock booster is connected to a first input terminal of the bootstrap circuit, a first output terminal of the triple charge pump is connected to a second input terminal of the bootstrap circuit, and a second output terminal of the triple charge pump is connected to an input terminal of the negative temperature coefficient voltage generation core circuit, wherein:

[0014] The first positive temperature coefficient frequency oscillator is configured to generate a low voltage domain high frequency clock signal.

[0015] The second positive temperature coefficient frequency oscillator is configured to generate a low voltage domain low frequency clock signal.

[0016] The non-overlapping circuit is configured to generate a first non-overlapping inverted high frequency clock signal and a second non-overlapping inverted high frequency clock signal according to the low voltage domain high frequency clock signal.

[0017] The first clock booster is configured to perform pull-up processing on the first non-overlapping inverted high-frequency clock signal, and output a first high-voltage-domain non-overlapping inverted high-frequency clock signal;

[0018] The second clock booster is configured to perform pull-up processing on the second non-overlapping inverted high-frequency clock signal, and output a second high-voltage-domain non-overlapping inverted high-frequency clock signal;

[0019] The third clock booster is configured to perform inversion processing on the low-voltage-domain low-frequency clock signal, and obtain a first medium-voltage-domain inverted low-frequency clock signal and a second medium-voltage-domain inverted low-frequency clock signal;

[0020] The bootstrap circuit is configured to generate, according to the first medium-voltage-domain inverted low-frequency clock signal and the second medium-voltage-domain inverted low-frequency clock signal, a first high-voltage-domain non-overlapping low-frequency clock signal, a second high-voltage-domain non-overlapping low-frequency clock signal, a third high-voltage-domain non-overlapping low-frequency clock signal, a first high-voltage-domain non-overlapping inverted low-frequency clock signal, and a second high-voltage-domain non-overlapping inverted low-frequency clock signal;

[0021] The triple charge pump is configured to perform amplification processing on the first high-voltage-domain non-overlapping inverted high-frequency clock signal and the second high-voltage-domain non-overlapping inverted high-frequency clock signal to obtain a triple output voltage;

[0022] The negative temperature coefficient voltage generation core circuit is configured to generate, according to the triple output voltage, the first negative temperature coefficient voltage and the second negative temperature coefficient voltage.

[0023] In some embodiments, the switched capacitor network circuit includes a voltage division switched capacitor network, a leakage current compensation circuit, and a series-parallel switched capacitor network, the voltage division switched capacitor network is connected in series with the series-parallel switched capacitor network, and an output end of the leakage current compensation circuit is connected to an input end of the series-parallel switched capacitor network, wherein:

[0024] The voltage division switched capacitor network is configured to generate a negative temperature coefficient voltage according to the first negative temperature coefficient voltage, the first high-voltage-domain non-overlapping inverted low-frequency clock signal, and the second high-voltage-domain non-overlapping inverted low-frequency clock signal;

[0025] The leakage current compensation circuit is configured to generate a compensation current according to the first negative temperature coefficient voltage, the first medium-voltage-domain inverted low-frequency clock signal, and the second medium-voltage-domain inverted low-frequency clock signal;

[0026] The series-parallel switched capacitor network is configured to generate a positive temperature coefficient voltage based on the first negative temperature coefficient voltage, the second negative temperature coefficient voltage, the first high voltage domain non-overlapping low frequency clock signal, the second high voltage domain non-overlapping low frequency clock signal, and the third high voltage domain non-overlapping low frequency clock signal.

[0027] In some embodiments, the voltage divider switched capacitor network comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor, wherein a first terminal of the first switch is connected to a first terminal of the third capacitor, a second terminal of the first switch, a first terminal of the second switch, and a first terminal of the first capacitor are connected, a second terminal of the second switch, a first terminal of the third switch, a first terminal of the fifth switch, a second terminal of the third capacitor, a first terminal of the fourth capacitor are connected, a second terminal of the third switch, a first terminal of the fourth switch, and a second terminal of the first capacitor are connected, a second terminal of the fifth switch, a first terminal of the sixth switch, and a first terminal of the second capacitor are connected, a second terminal of the sixth switch, a first terminal of the seventh switch, a second terminal of the fourth capacitor, and a first terminal of the fifth capacitor are connected, a second terminal of the seventh switch, a second terminal of the second capacitor, and a first terminal of the eighth switch are connected, a second terminal of the eighth switch is connected to a second terminal of the fifth capacitor and grounded, and a second terminal of the fourth switch is grounded.

[0028] In some embodiments, the series-parallel switched capacitor network comprises a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixth capacitor, a seventh capacitor, and an output capacitor, wherein a first terminal of the tenth switch is connected to a first terminal of the thirteenth switch, a second terminal of the tenth switch, a first terminal of the sixth capacitor, and a first terminal of the twelfth switch are connected, a second terminal of the sixth capacitor, a second terminal of the ninth switch, and a first terminal of the eleventh switch are connected, a second terminal of the thirteenth switch, a first terminal of the seventh capacitor, and a first terminal of the fifteenth switch are connected, a second terminal of the fifteenth switch is connected to a first terminal of the output capacitor, a second terminal of the twelfth switch, a second terminal of the seventh capacitor, and a first terminal of the fourteenth switch are connected, and a second terminal of the eleventh switch is connected to a second terminal of the fourteenth switch.

[0029] In some embodiments, the method further comprises:

[0030] The G terminal of the deep n-well NMOS transistor leakage current compensation circuit, the S terminal of the deep n-well NMOS transistor leakage current compensation circuit, and the B terminal of the deep n-well NMOS transistor leakage current compensation circuit are respectively connected to the leakage current compensation circuit.

[0031] The D end of the deep n-well NMOS transistor leakage current compensation circuit is connected with the negative temperature coefficient voltage generation core circuit;

[0032] The NW end of the deep n-well NMOS transistor leakage current compensation circuit is connected with the three times charge pump.

[0033] To achieve the above object, another aspect of the embodiment of the present application proposes a temperature compensation method of a switched capacitor network bandgap voltage reference circuit, which comprises:

[0034] The clock control signal, the first negative temperature coefficient voltage and the second negative temperature coefficient voltage are determined, and the clock control signal comprises the first high voltage domain non-overlapping low frequency clock signal, the second high voltage domain non-overlapping low frequency clock signal, the third high voltage domain non-overlapping low frequency clock signal, the first high voltage domain non-overlapping inverted low frequency clock signal, the second high voltage domain non-overlapping inverted low frequency clock signal, the first medium voltage domain inverted low frequency clock signal and the second medium voltage domain inverted low frequency clock signal;

[0035] The negative temperature coefficient voltage is generated according to the first high voltage domain non-overlapping inverted low frequency clock signal, the second high voltage domain non-overlapping inverted low frequency clock signal and the first negative temperature coefficient voltage;

[0036] The compensation current is generated according to the first medium voltage domain inverted low frequency clock signal, the second medium voltage domain inverted low frequency clock signal and the first negative temperature coefficient voltage;

[0037] The positive temperature coefficient voltage is generated according to the first negative temperature coefficient voltage, the second negative temperature coefficient voltage, the compensation current, the first high voltage domain non-overlapping low frequency clock signal, the second high voltage domain non-overlapping low frequency clock signal and the third high voltage domain non-overlapping low frequency clock signal;

[0038] The reference voltage is obtained by combining the negative temperature coefficient voltage and the positive temperature coefficient voltage.

[0039] In some embodiments, the compensation current is generated according to the first medium voltage domain inverted low frequency clock signal, the second medium voltage domain inverted low frequency clock signal and the first negative temperature coefficient voltage, which comprises:

[0040] The first medium voltage domain inverted low frequency clock signal, the second medium voltage domain inverted low frequency clock signal and the first negative temperature coefficient voltage are obtained to generate the gate tunneling leakage current and the channel leakage current;

[0041] The compensation current is generated by compensating according to the gate tunneling leakage current and the channel leakage current.

[0042] In some embodiments, the generation expression of the reference voltage is specifically as follows:

[0043] V REF = aV EB3 + gAV EB + V COMP

[0044] In the above formula, V REF represents the reference voltage, a represents a negative temperature voltage coefficient, V EB3 represents a first negative temperature coefficient voltage, g represents a positive temperature voltage coefficient, AV EB represents a positive temperature coefficient voltage, and V COMP represents a compensation voltage.

[0045] The embodiments of the present application at least have the following beneficial effects: the present application provides a switched capacitor network bandgap voltage reference circuit and a temperature compensation method thereof, the scheme generates a negative temperature coefficient voltage through a clock signal voltage generation circuit and controls a switched capacitor network circuit through a clock control signal, introduces a deep n-well NMOS transistor drain current compensation circuit to perform current voltage compensation processing on the switched capacitor network circuit, can effectively reduce the minimum supply voltage requirement, and further reduce the power consumption of the switched capacitor network bandgap voltage reference circuit, and further improve the accuracy of the bandgap voltage reference circuit. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 FIG. 1 is a structural schematic diagram of a switched capacitor network bandgap voltage reference circuit provided by an embodiment of the present application;

[0047] Figure 2 FIG. 5 is a circuit principle schematic diagram of a voltage division switched capacitor network and a series-parallel switched capacitor network provided by an embodiment of the present application;

[0048] Figure 3 FIG. 7 is a schematic diagram of a voltage division switched capacitor network and a series-parallel switched capacitor network in a first state provided by an embodiment of the present application;

[0049] Figure 4 FIG. 9 is a schematic diagram of a voltage division switched capacitor network and a series-parallel switched capacitor network in a second state provided by an embodiment of the present application;

[0050] Figure 5 FIG. 11 is a circuit principle schematic diagram of a deep n-well NMOS transistor drain current compensation circuit provided by an embodiment of the present application;

[0051] Figure 6 FIG. 13 is a simulation diagram of compensation current of a deep n-well NMOS transistor drain current compensation circuit provided by an embodiment of the present application;

[0052] Figure 7 is a simulation diagram of a compensation voltage of a deep n-well NMOS transistor leakage current compensation circuit provided by an embodiment of the present application;

[0053] Figure 8 is a schematic diagram of a change result of the compensation voltage after compensation provided by an embodiment of the present application;

[0054] Figure 9 is a schematic diagram of a step of implementing temperature compensation in a switched capacitor network bandgap voltage reference circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application. When the following description refers to the accompanying drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all the implementations consistent with embodiments of the present application, but are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0056] It can be understood that the terms "first", "second", and the like used in the present application can be used herein to describe various concepts, but unless specifically stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to determining".

[0057] The terms "at least one", "multiple", "each", "any" and the like used in the present application include one, two or more than two, multiple includes two or more than two, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by a person skilled in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0059] Before the embodiments of the present application are described in detail, it should be explained that:

[0060] Bandgap reference voltage source (BGR) is one of the basic building blocks in integrated circuits, which aims to provide an accurate reference voltage for other circuits that is insensitive to operating temperature, power supply voltage, process variations, and circuit load. Compared to off-chip power supply, BGR has better accuracy and stability, and can effectively reduce the circuit area, so it has been widely used in integrated circuit systems such as data converters, power management circuits, and memories.

[0061] Nowadays, the Internet of Things (IoT) is a fast-growing market that has received a lot of attention. It is estimated that there will be more than 2 billion IoT devices connected to the Internet by 2025. A large number of IoT devices will run in remote areas, harsh geographical environments, or environments with limited power supply, so most of them will rely on batteries for power supply; since frequent battery replacement will increase the difficulty and cost of maintaining IoT devices, system power consumption has become an important concern in IoT systems. To reduce power consumption, many IoT devices operate in standby mode in most cases; but even in standby mode, the voltage reference circuit is still an important part of the system on chip (SoC) that must be turned on and becomes the main source of standby power consumption. Traditional BGR circuits have strong resistance to process, voltage, and temperature (PVT) variations, but their power consumption (usually greater than 1 μW) is too high for IoT systems.

[0062] Due to the low power consumption characteristics (usually only a few tens of nW) of the BGR based on the switched capacitor network (SCN), this design is very suitable for IoT devices. However, the most advanced SCN BGRs currently still require a supply voltage greater than or equal to 0.5 V, so they cannot directly use energy harvesting sources (usually only 0.35 V) as the supply voltage, which will greatly reduce the overall performance of the system. In addition, due to BJT bias, leakage current, non-linear parasitic effects in SCN, and lack of curvature compensation, SCN BGRs have a large temperature coefficient (TC) and a limited temperature range. Although curvature compensation techniques are very common in traditional BGR circuits, existing curvature compensation techniques require large current consumption, which in turn leads to high power consumption, so they are not suitable for SCN BGRs. In summary, it is still a challenging problem to reduce the supply voltage and TC of SCN BGRs while keeping their power consumption below 50 nW.

[0063] Based on this, the embodiment of the present application aims to reduce the supply voltage and TC based on SCN BGR, so that it can directly use the energy collection source as the supply voltage and output a reference voltage less affected by temperature changes. The step-down switched capacitor technology proposed in the embodiment of the present application can effectively eliminate the fixed value error, so as to effectively reduce the minimum supply voltage requirement. In addition, unlike the traditional temperature compensation technology which requires huge power consumption, the embodiment of the present application proposes to use the drain current generated by the MOS device to generate a carefully controlled temperature-related current curve. The method proposed in the embodiment of the present application can reduce the TC by more than 30% without consuming additional power.

[0064] With reference to Figure 1 , Figure 1 A structural schematic diagram of a switched capacitor network bandgap voltage reference circuit provided by the embodiment of the present application is shown in FIG. 1. Figure 1 The circuit includes a clock signal and VEB voltage generation circuit, a switched capacitor network circuit and a deep n-well NMOS transistor drain current compensation circuit, wherein the first output end of the clock signal and VEB voltage generation circuit is connected with the input end of the deep n-well NMOS transistor drain current compensation circuit, and the second output end of the clock signal and VEB voltage generation circuit and the output end of the deep n-well NMOS transistor drain current compensation circuit are respectively connected with the input end of the switched capacitor network circuit.

[0065] It should be noted that:

[0066] The clock signal and VEB voltage generation circuit are used to generate a clock control signal, a first negative temperature coefficient voltage and a second negative temperature coefficient voltage.

[0067] Specifically, the clock signal and VEB voltage generation circuit includes a clock signal generation circuit and a voltage generator, the clock signal generation circuit is used to generate a clock control signal, and the voltage generator is used to generate a first negative temperature coefficient voltage and a second negative temperature coefficient voltage.

[0068] Furthermore, the clock signal and VEB voltage generating circuit further includes a first positive temperature coefficient frequency oscillator, a second positive temperature coefficient frequency oscillator, a non-overlapping circuit, a first clock booster, a second clock booster, a third clock booster, a bootstrap circuit, a triple charge pump, and a negative temperature coefficient voltage generating core circuit. The output end of the first positive temperature coefficient frequency oscillator is connected to the output end of the non-overlapping circuit, the first output end of the non-overlapping circuit is connected to the input end of the first clock booster, the second output end of the non-overlapping circuit is connected to the input end of the second clock booster, the output end of the first clock booster and the output end of the second clock booster are respectively connected to the input end of the triple charge pump, the output end of the second positive temperature coefficient frequency oscillator is connected to the input end of the third clock booster, the output end of the third clock booster is connected to the first input end of the bootstrap circuit, the first output end of the triple charge pump is connected to the second input end of the bootstrap circuit, and the second output end of the triple charge pump is connected to the input end of the negative temperature coefficient voltage generating core circuit, wherein:

[0069] The first positive temperature coefficient frequency oscillator is used to generate a low-voltage domain high-frequency clock signal; the second positive temperature coefficient frequency oscillator is used to generate a low-voltage domain low-frequency clock signal; the non-overlapping circuit is used to generate a first non-overlapping inverted high-frequency clock signal and a second non-overlapping inverted high-frequency clock signal according to the low-voltage domain high-frequency clock signal; the first clock booster is used to pull up the first non-overlapping inverted high-frequency clock signal and output a first high-voltage domain non-overlapping inverted high-frequency clock signal; the second clock booster is used to pull up the second non-overlapping inverted high-frequency clock signal and output a second high-voltage domain non-overlapping inverted high-frequency clock signal; the third clock booster is used to invert the low-voltage domain low-frequency clock signal to obtain a first medium-voltage domain inverted low-frequency clock signal. a bootstrap circuit for generating a first high-voltage domain non-overlapping low-frequency clock signal, a second high-voltage domain non-overlapping low-frequency clock signal, a third high-voltage domain non-overlapping low-frequency clock signal, a first high-voltage domain non-overlapping inverted low-frequency clock signal, and a second high-voltage domain non-overlapping inverted low-frequency clock signal according to the first medium-voltage domain inverted low-frequency clock signal and the second medium-voltage domain inverted low-frequency clock signal; a triple charge pump for combining and amplifying the first high-voltage domain non-overlapping inverted high-frequency clock signal and the second high-voltage domain non-overlapping inverted high-frequency clock signal to obtain a tripled output voltage; a negative temperature coefficient voltage generation core circuit for generating a first negative temperature coefficient voltage and a second negative temperature coefficient voltage according to the tripled output voltage.

[0070] In this embodiment, the clock signal generating circuit is used to generate various clock signals for controlling the switched capacitor network. EB The voltage generator is used to generate two negative temperature coefficient (CTAT) voltages (V EB3 and V EB4), while switched-capacitor network is used to generate CTAT voltage coefficient (α), positive temperature coefficient (PTAT) voltage (ΔV EB ), PTAT voltage coefficient (γ) and compensation voltage (V COMP ).

[0071] First, two positive temperature coefficient frequency oscillators (PTAT Freq. Oscillator), namely a first positive temperature coefficient frequency oscillator (PTAT Fast Freq. Oscillator) and a second positive temperature coefficient frequency oscillator (PTAT Slow Freq. Oscillator), generate a low-voltage high-frequency clock signal (CLK F ) and a low-voltage low-frequency clock signal (CLK S ), respectively. The low-voltage high-frequency clock signal is first connected to a non-overlap circuit (Nonoverlap Circuit) to generate a pair of non-overlapping inverted high-frequency clock signals. Then, the pair of non-overlapping inverted high-frequency clock phases will be connected to two independent clock boosters, namely a first clock booster and a second clock booster (Clock Booster 1 and Clock Booster 2), to boost the voltage of the pair of clock signals to a high-voltage domain (Φ F and ); while the low-voltage low-frequency clock signal is first connected to a third clock booster (Clock Booster 3) to generate a pair of medium-voltage inverted low-frequency clock signals (Φ S and ), and then connected to a clock bootstrap circuit (Clock Bootstrap) to generate three high-voltage non-overlapping low-frequency clock signals (Φ S1 , Φ S2 , Φ S3 ) and a pair of high-voltage non-overlapping inverted low-frequency clock signals (Φ ESC and ). Then, the high-voltage non-overlapping inverted high-frequency clock signals (Φ F and ) and the supply voltage are connected to a 3X charge pump (3X Charge Pump) to generate a 3 times voltage of the supply voltage (3V DD ). 3V DD is connected back to the clock bootstrap circuit to ensure the high potential levels of Φ S , Φ S1 , Φ S2 and Φ S3 . Finally, 3V DD is connected to a V EB generation core (V EB Generator) to generate VEB3 and V EB4 .

[0072] The deep n-well NMOS transistor leakage current compensation circuit generates a compensation current according to the clock signal and the output of the VEB voltage generation circuit.

[0073] Specifically, the G end of the deep n-well NMOS transistor, the S end of the deep n-well NMOS transistor, and the B end of the deep n-well NMOS transistor in the leakage current compensation circuit are connected with the leakage current compensation circuit respectively; the D end of the deep n-well NMOS transistor is connected with the negative temperature coefficient voltage generation core circuit; and the NW end of the deep n-well NMOS transistor is connected with the three times charge pump.

[0074] In the embodiment, as shown in Figure 5 , Figure 6 and Figure 7 , the deep n-well NMOS transistor leakage current compensation circuit is described. The G, S and B ends will be connected to the node with voltage αV EB3 +ΔV EB , the D end will be connected to V EB3 , and the NW (n-well) end will be connected to 3V DD . Through the above connection, two dominant leakage currents will be generated, i.e. the gate tunneling leakage current (I1) from the G end to the D end and the D-S channel leakage current (I2). The formula for generating I1 is:

[0075] I1≈n·W eff ·T oxRatioEdge ·(V GD ) 2

[0076] Where W eff is the effective width of the transistor and T oxRatioEdge is a parameter based on the gate oxide thickness (T ox ), which is related to the process.

[0077] Therefore, I1 is related to the product of the voltage difference between the G end and the D end and the size of the deep n-well NMOS transistor leakage current compensation circuit (i.e. W·L).

[0078] The formula for generating I2 is:

[0079]

[0080] In the above formula, I2 represents the channel leakage current, μ0 represents the electron zero-bias mobility, C ox represents the gate oxide capacitance value, m represents the sub-threshold swing coefficient, V T represents the transistor thermal voltage, V GS represents the voltage from the G end to the D end, and V THRepresents the transistor threshold voltage, V DS Indicates the voltage from D to S.

[0081] Therefore, I2 is related to the threshold voltage and size ratio (i.e. W / L) of the deep n-well NMOS transistor. Next, we will discuss the compensation current I generated by it. COMP and compensation voltage V COMP At low temperatures, due to the large threshold voltage, the compensation current will be dominated by I1. As the temperature rises, the voltage difference between the G and D terminals will slowly decrease, so the current I1 will show a downward trend as the temperature rises. When the temperature rises to around 50 degrees, the threshold voltage will drop to a smaller level, so the compensation current will be dominated by I2. As the temperature rises, the threshold voltage will become smaller and smaller, so the current I2 will show an upward trend as the temperature rises. After adjustment, the voltage at the node V X2 Injection I COMP To the switched capacitor network, a corresponding compensation voltage V COMP . Because V before the compensation voltage is injected REF The function of temperature change is a downward-opening parabola, and V COMP The function of temperature change is a parabola that opens upward, so it is exactly the same as V before the compensation voltage is injected. REF and complement, and can effectively reduce V REF Voltage changes due to temperature changes, such as Figure 8 The final reference voltage after compensation by the solution proposed by the present invention is:

[0082] V REF =αV EB3 +γΔV EB +V COMP

[0083] In the above formula, V REF represents the reference voltage, α represents the negative temperature voltage coefficient, V EB3 represents the first negative temperature coefficient voltage, γ represents the positive temperature voltage coefficient, ΔV EB Represents positive temperature coefficient voltage, V COMP Indicates the compensation voltage.

[0084] Because I COMP The leakage current compensation technology proposed in this paper significantly improves TC while having little negative impact on other BGR performance indicators.

[0085] The switched capacitor network circuit is used for generating a reference voltage according to a clock control signal, a first negative temperature coefficient voltage, a second negative temperature coefficient voltage and a compensation current.

[0086] The switch capacitor network circuit comprises a voltage division switch capacitor network, a leakage current compensation circuit and a series-parallel switch capacitor network, the voltage division switch capacitor network is connected in series with the series-parallel switch capacitor network, and the output end of the leakage current compensation circuit is connected with the input end of the series-parallel switch capacitor network, wherein:

[0087] The voltage division switch capacitor network is configured to generate a negative temperature coefficient voltage according to a first negative temperature coefficient voltage, a first high voltage domain non-overlapping anti-phase low frequency clock signal and a second high voltage domain non-overlapping anti-phase low frequency clock signal; the leakage current compensation circuit is configured to generate a compensation current according to the first negative temperature coefficient voltage, a first medium voltage domain anti-phase low frequency clock signal and a second medium voltage domain anti-phase low frequency clock signal; and the series-parallel switch capacitor network is configured to generate a positive temperature coefficient voltage according to the first negative temperature coefficient voltage, a second negative temperature coefficient voltage, a first high voltage domain non-overlapping low frequency clock signal, a second high voltage domain non-overlapping low frequency clock signal and a third high voltage domain non-overlapping low frequency clock signal.

[0088] Further, the voltage division switch capacitor network comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a fifth capacitor, wherein the first end of the first switch is connected with the first end of the third capacitor, the second end of the first switch, the first end of the second switch and the first end of the first capacitor are connected, the second end of the second switch, the first end of the third switch, the first end of the fifth switch, the second end of the third capacitor and the first end of the fourth capacitor are connected, the second end of the third switch, the first end of the fourth switch and the second end of the first capacitor are connected, the second end of the fifth switch, the first end of the sixth switch and the first end of the second capacitor are connected, the second end of the sixth switch, the first end of the seventh switch, the second end of the fourth capacitor and the first end of the fifth capacitor are connected, the second end of the seventh switch, the second end of the second capacitor and the first end of the eighth switch are connected, the second end of the eighth switch is connected with the second end of the fifth capacitor and grounded, and the second end of the fourth switch is grounded.

[0089] The series-parallel switch capacitor network comprises a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixth capacitor, a seventh capacitor and an output capacitor, wherein the first end of the tenth switch is connected with the first end of the thirteenth switch, the second end of the tenth switch, the first end of the sixth capacitor and the first end of the twelfth switch are connected, the second end of the sixth capacitor, the second end of the ninth switch and the first end of the eleventh switch are connected, the second end of the thirteenth switch, the first end of the seventh capacitor and the first end of the fifteenth switch are connected, the second end of the fifteenth switch is connected with the first end of the output capacitor, the second end of the twelfth switch, the second end of the seventh capacitor and the first end of the fourteenth switch are connected, and the second end of the eleventh switch is connected with the second end of the fourteenth switch.

[0090] In this embodiment, first, V EB3 , Φ ESC and Connect to the step-down voltage divider switch capacitor network (SCN) to generate αV EB3 Then, V EB3 and αV EB3 +ΔV EB Connect to the leakage current compensation circuit to generate compensation current (I COMP ). I COMP will pass through the circuit node V X2 ,like Figure 2 As shown, a series-parallel switched capacitor network (Series-Parallel SCN) is injected to generate a compensation voltage (V COMP ). Then, V EB3 、V EB4 , Φ S1 , Φ S2 , Φ S3 Connected to a series-parallel switched capacitor network to generate the PTAT voltage γΔV EB Finally, the voltage divider switched capacitor network and the series-shunt switched capacitor network are connected in series to generate the reference voltage V REF .

[0091] It should be noted that if Figure 3 As shown in FIG, the first state of the step-down voltage divider switch capacitor network (Step-down Voltage Divider SCN) is described. The step-down voltage divider switch capacitor network consists of 8 switches and 5 capacitors. Its output voltage αV EB1 Where α=1 / (2N), N is the number of flying capacitors. Since two flying capacitors are used, α is 0.25 in the embodiment of the present invention. By adjusting the number of flying capacitors used, the design can output different reference voltages. The step-down switch capacitor network has two working states. In the first state, the first switch S1, the third switch S3, the sixth switch S6, and the eighth switch S8 are not conducting, and the second switch S2, the fourth switch S4, the fifth switch S5, and the seventh switch S7 are conducting. The upper ends of the first capacitor C1 and the second capacitor C2 are simultaneously connected to the output voltage node V X1 , the lower end of the first capacitor C1 is connected to the ground, and the lower end of the second capacitor C2 is connected to the ground through the fifth capacitor C5. Figure 4As shown, in the second state, the first switch S1, the third switch S3, the sixth switch S6 and the eighth switch S8 are turned on, and the second switch S2, the fourth switch S4, the fifth switch S5 and the seventh switch S7 are turned off. The upper ends of the first capacitor C1 and the second capacitor C2 are connected to the voltage V EB3 and the output voltage αV EB3 respectively, and the lower ends are connected to the next stage output voltage node V X1 and the ground (GND) respectively. After a plurality of working periods, the output voltage of each stage will converge to half of its input voltage, i.e. V X1 = 0.5V EB3 and αV EB3 = 0.5V X1 . Compared with the conventional voltage division switched capacitor network, the voltage division switched capacitor network of the embodiment of the present application does not need to discharge the charge on the capacitor to the ground, and thus the problem of settling error does not occur. This feature can effectively reduce the bias current required for generating V EB3 , thereby reducing the overall power consumption of the BGR, and reducing the load pressure of the charge pump, and thus a 3 times charge pump can be used to reduce the supply voltage to 0.35V. Next, the series-parallel switched capacitor network (Series-Parallel SCN) is discussed. The series-parallel switched capacitor network is composed of 6 switches and 3 capacitors. It has two working states: in the first state, the tenth switch S10, the eleventh switch S11, the thirteenth switch S13 and the fourteenth switch S14 are turned on, and the ninth switch S9 and the twelfth switch S12 are turned off. The upper ends of the sixth capacitor C6 and the seventh capacitor C7 are connected to the voltage VEB3, and the lower ends are connected to V EB4 . Thus, the voltage stored on the sixth capacitor C6 and the seventh capacitor C7 is ΔV EB = V EB3 -V EB4 ; in the second state, the tenth switch S10, the eleventh switch S11, the thirteenth switch S13 and the fourteenth switch S14 are turned off, and the ninth switch S9 and the twelfth switch S12 are turned on. The sixth capacitor C6 and the seventh capacitor C7 are in series, and the lower end of the sixth capacitor C6 is connected to the voltage αV EB3 , and thus the output voltage of the series-parallel switched capacitor network is αV EB3 + γΔV EB = 0.25V EB3 + 2ΔV EB . Wherein, γ is the number of capacitors used. Finally, when the series-parallel switched capacitor network is in the second working state, S15 will be turned on, and thus the uncompensated reference voltage is V REF = αV EB3 + γΔV EB .

[0092] The specific parameters of the switch capacitor network bandgap voltage reference circuit constructed by the embodiment of the application are shown in Table 1:

[0093] Table 1: Parameter table of the switch capacitor network bandgap voltage reference circuit

[0094] Parameter Value CMOS process 65 nm Average output reference voltage 314 mV Power consumption 40 nW Minimum supply voltage 0.35V Temperature coefficient 29 ppm / °C Operating temperature range -40–120℃ Line regulation 1.44％ / V Supply voltage rejection ratio -50 dB @ DC Output ripple 300 μV Area 0.1174 mm2

[0095] Referring to Figure 9 The embodiment of the application also provides a temperature compensation method of a switch capacitor network bandgap voltage reference circuit, which can implement the above-described switch capacitor network bandgap voltage reference circuit, and the method comprises the following steps:

[0096] S1, determining a clock control signal, a first negative temperature coefficient voltage and a second negative temperature coefficient voltage, wherein the clock control signal comprises a first high-voltage domain non-overlapping low-frequency clock signal, a second high-voltage domain non-overlapping low-frequency clock signal, a third high-voltage domain non-overlapping low-frequency clock signal, a first high-voltage domain non-overlapping inverted low-frequency clock signal, a second high-voltage domain non-overlapping inverted low-frequency clock signal, a first medium-voltage domain inverted low-frequency clock signal and a second medium-voltage domain inverted low-frequency clock signal;

[0097] S2, generating a negative temperature coefficient voltage according to the first high-voltage domain non-overlapping inverted low-frequency clock signal, the second high-voltage domain non-overlapping inverted low-frequency clock signal and the first negative temperature coefficient voltage;

[0098] S3, generating a compensation current according to the first medium-voltage domain inverted low-frequency clock signal, the second medium-voltage domain inverted low-frequency clock signal and the first negative temperature coefficient voltage;

[0099] Specifically, step S3 further comprises:

[0100] S31, obtaining the first medium-voltage domain inverted low-frequency clock signal, the second medium-voltage domain inverted low-frequency clock signal and the first negative temperature coefficient voltage, and generating a gate tunneling leakage current and a channel leakage current;

[0101] S32, compensating according to the gate tunneling leakage current and the channel leakage current to generate the compensation current.

[0102] S4, generating a positive temperature coefficient voltage according to the first negative temperature coefficient voltage, the second negative temperature coefficient voltage, the compensation current, the first high-voltage domain non-overlapping low-frequency clock signal, the second high-voltage domain non-overlapping low-frequency clock signal and the third high-voltage domain non-overlapping low-frequency clock signal;

[0103] S5, combining the negative temperature coefficient voltage and the positive temperature coefficient voltage to obtain a reference voltage.

[0104] It can be understood that the contents in the method embodiments described above are applicable to the circuit embodiments, the circuit embodiments specifically implement the functions of the method embodiments, and achieve the beneficial effects same as those of the method embodiments.

[0105] The preferred embodiments of the application are described above with reference to the accompanying drawings, and are not intended to limit the scope of the application. Any modifications, equivalent replacements and improvements made by those skilled in the art without departing from the scope and essence of the application shall be within the scope of the application.

Claims

1. A switched-capacitor network bandgap voltage reference circuit, characterized by, The circuit comprises a clock signal and VEB voltage generation circuit, a switched capacitor network circuit and a deep n-well NMOS transistor drain current compensation circuit, wherein the first output end of the clock signal and VEB voltage generation circuit is connected with the input end of the deep n-well NMOS transistor drain current compensation circuit, the second output end of the clock signal and VEB voltage generation circuit and the output end of the deep n-well NMOS transistor drain current compensation circuit are respectively connected with the input end of the switched capacitor network circuit, and wherein: The clock signal and VEB voltage generation circuit is used for generating a clock control signal, a first negative temperature coefficient voltage and a second negative temperature coefficient voltage. The deep n-well NMOS transistor drain current compensation circuit is used for generating a compensation current according to the output of the clock signal and VEB voltage generation circuit. The switched capacitor network circuit is used for generating a reference voltage according to the clock control signal, the first negative temperature coefficient voltage, the second negative temperature coefficient voltage and the compensation current.

2. The circuit of claim 1, wherein, The clock signal and VEB voltage generation circuit comprises a clock signal generation circuit and a voltage generator, wherein: The clock signal generation circuit is used for generating the clock control signal. The voltage generator is used for generating the first negative temperature coefficient voltage and the second negative temperature coefficient voltage.

3. The circuit of claim 1, wherein, The clock signal and VEB voltage generation circuit further comprises a first positive temperature coefficient frequency oscillator, a second positive temperature coefficient frequency oscillator, a non-overlapping circuit, a first clock booster, a second clock booster, a third clock booster, a bootstrap circuit, a triple charge pump and a negative temperature coefficient voltage generation core circuit, the output end of the first positive temperature coefficient frequency oscillator is connected with the output end of the non-overlapping circuit, the first output end of the non-overlapping circuit is connected with the input end of the first clock booster, the second output end of the non-overlapping circuit is connected with the input end of the second clock booster, the output end of the first clock booster and the output end of the second clock booster are respectively connected with the input end of the triple charge pump, the output end of the second positive temperature coefficient frequency oscillator is connected with the input end of the third clock booster, the output end of the third clock booster is connected with the first input end of the bootstrap circuit, the first output end of the triple charge pump is connected with the second input end of the bootstrap circuit, and the second output end of the triple charge pump is connected with the input end of the negative temperature coefficient voltage generation core circuit, and wherein: The first positive temperature coefficient frequency oscillator is used for generating a low-voltage domain high-frequency clock signal. The second positive temperature coefficient frequency oscillator is used for generating a low-voltage domain low-frequency clock signal. The non-overlapping circuit is used for generating a first non-overlapping inverted high-frequency clock signal and a second non-overlapping inverted high-frequency clock signal according to the low-voltage domain high-frequency clock signal. The first clock booster is used for performing pull-up processing on the first non-overlapping inverted high-frequency clock signal to output a first high-voltage domain non-overlapping inverted high-frequency clock signal. The second clock booster is used for performing pull-up processing on the second non-overlapping inverted high-frequency clock signal to output a second high-voltage domain non-overlapping inverted high-frequency clock signal. The third clock booster is used for generating a first high-voltage domain low-frequency clock signal and a second high-voltage domain low-frequency clock signal according to the low-voltage domain low-frequency clock signal. The bootstrap circuit is used for generating a first bootstrap voltage and a second bootstrap voltage according to the first high-voltage domain non-overlapping inverted high-frequency clock signal and the second high-voltage domain non-overlapping inverted high-frequency clock signal. The negative temperature coefficient voltage generation core circuit is used for generating a first negative temperature coefficient voltage and a second negative temperature coefficient voltage according to the first bootstrap voltage and the second bootstrap voltage. The second clock booster is used to pull up the second non-overlapping inverted high-frequency clock signal and output a second high-voltage domain non-overlapping inverted high-frequency clock signal; The third clock booster is used to invert the low-voltage domain low-frequency clock signal to obtain a first medium-voltage domain inverted low-frequency clock signal and a second medium-voltage domain inverted low-frequency clock signal; The bootstrap circuit is configured to generate a first high-voltage domain non-overlapping low-frequency clock signal, a second high-voltage domain non-overlapping low-frequency clock signal, a third high-voltage domain non-overlapping low-frequency clock signal, a first high-voltage domain non-overlapping inverted low-frequency clock signal, and a second high-voltage domain non-overlapping inverted low-frequency clock signal according to the first medium-voltage domain inverted low-frequency clock signal and the second medium-voltage domain inverted low-frequency clock signal; The triple charge pump is used to amplify the supply voltage by using the first high-voltage domain non-overlapping inverted high-frequency clock signal and the second high-voltage domain non-overlapping inverted high-frequency clock signal to obtain a tripled output voltage; The negative temperature coefficient voltage generation core circuit is used to generate the first negative temperature coefficient voltage and the second negative temperature coefficient voltage according to the tripled output voltage.

4. The circuit of claim 1, wherein, The switched capacitor network circuit includes a voltage-dividing switched capacitor network, a leakage current compensation circuit, and a series-parallel switched capacitor network. The voltage-dividing switched capacitor network is connected in series with the series-parallel switched capacitor network. The output end of the leakage current compensation circuit is connected to the input end of the series-parallel switched capacitor network. The voltage-dividing switched capacitor network is configured to generate a negative temperature coefficient voltage according to the first negative temperature coefficient voltage, the first high-voltage domain non-overlapping inverted low-frequency clock signal, and the second high-voltage domain non-overlapping inverted low-frequency clock signal; The leakage current compensation circuit is configured to generate a compensation current according to the first negative temperature coefficient voltage, the first medium voltage domain inverted low frequency clock signal, and the second medium voltage domain inverted low frequency clock signal; The series-parallel switched capacitor network is used to generate a positive temperature coefficient voltage based on the first negative temperature coefficient voltage, the second negative temperature coefficient voltage, the first high-voltage domain non-overlapping low-frequency clock signal, the second high-voltage domain non-overlapping low-frequency clock signal and the third high-voltage domain non-overlapping low-frequency clock signal.

5. The circuit of claim 4, wherein, The voltage division switch capacitor network comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a fifth capacitor, wherein the first end of the first switch is connected with the first end of the third capacitor, the second end of the first switch, the first end of the second switch and the first end of the first capacitor are connected, the second end of the second switch, the first end of the third switch, the first end of the fifth switch, the second end of the third capacitor, the first end of the fourth capacitor are connected, the second end of the third switch, the first end of the fourth switch and the second end of the first capacitor are connected, the second end of the fifth switch, the first end of the sixth switch and the first end of the second capacitor are connected, the second end of the sixth switch, the first end of the seventh switch, the second end of the fourth capacitor and the first end of the fifth capacitor are connected, the second end of the seventh switch, the second end of the second capacitor and the first end of the eighth switch are connected, the second end of the eighth switch is connected with the second end of the fifth capacitor and grounded, and the second end of the fourth switch is grounded.

6. The circuit of claim 4, wherein, The series-parallel switch capacitor network comprises a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixth capacitor, a seventh capacitor and an output capacitor, wherein the first end of the tenth switch is connected with the first end of the thirteenth switch, the second end of the tenth switch, the first end of the sixth capacitor and the first end of the twelfth switch are connected, the second end of the sixth capacitor, the second end of the ninth switch and the first end of the eleventh switch are connected, the second end of the thirteenth switch, the first end of the seventh capacitor and the first end of the fifteenth switch are connected, the second end of the fifteenth switch is connected with the first end of the output capacitor, the second end of the twelfth switch, the second end of the seventh capacitor and the first end of the fourteenth switch are connected, and the second end of the eleventh switch is connected with the second end of the fourteenth switch.

7. The circuit of claim 4, wherein, Further comprising: The G end of the deep n-well NMOS transistor leakage current compensation circuit, the S end of the deep n-well NMOS transistor leakage current compensation circuit and the B end of the deep n-well NMOS transistor leakage current compensation circuit are respectively connected with the leakage current compensation circuit; The D end of the deep n-well NMOS transistor leakage current compensation circuit is connected with the negative temperature coefficient voltage generation core circuit; The NW end of the deep n-well NMOS transistor leakage current compensation circuit is connected with the triple charge pump.

8. A method of temperature compensation for a switched-capacitor bandgap voltage reference circuit, comprising: The method comprises: determining the clock control signals, the first negative temperature coefficient voltage and the second negative temperature coefficient voltage, the clock control signals including the first high voltage domain non-overlapping low frequency clock signal, the second high voltage domain non-overlapping low frequency clock signal, the third high voltage domain non-overlapping low frequency clock signal, the first high voltage domain non-overlapping inverted low frequency clock signal, the second high voltage domain non-overlapping inverted low frequency clock signal, the first medium voltage domain inverted low frequency clock signal and the second medium voltage domain inverted low frequency clock signal; generating a negative temperature coefficient voltage according to the first high voltage domain non-overlapping inverted low frequency clock signal, the second high voltage domain non-overlapping inverted low frequency clock signal and the first negative temperature coefficient voltage; generating a compensation current according to the first medium voltage domain inverted low frequency clock signal, the second medium voltage domain inverted low frequency clock signal and the first negative temperature coefficient voltage; generating a positive temperature coefficient voltage according to the first negative temperature coefficient voltage, the second negative temperature coefficient voltage, the compensation current, the first high voltage domain non-overlapping low frequency clock signal, the second high voltage domain non-overlapping low frequency clock signal and the third high voltage domain non-overlapping low frequency clock signal; combining the negative temperature coefficient voltage and the positive temperature coefficient voltage to obtain the reference voltage.

9. The method of claim 8, wherein, The generating of the compensation current according to the first medium voltage domain inverted low frequency clock signal, the second medium voltage domain inverted low frequency clock signal and the first negative temperature coefficient voltage includes: obtaining the first medium voltage domain inverted low frequency clock signal, the second medium voltage domain inverted low frequency clock signal and the first negative temperature coefficient voltage to generate a gate tunneling leakage current and a channel leakage current; compensating according to the gate tunneling leakage current and the channel leakage current to generate the compensation current.

10. The method of claim 9, wherein, The generating expression of the reference voltage is specifically as follows: V REF = αV eB3 + γΔV EB + V COMP In the above equation, V REF represents a reference voltage, a represents a negative temperature voltage coefficient, V EB3 represents a first negative temperature coefficient voltage, γ represents a positive temperature voltage coefficient, ΔV EB represents a positive temperature coefficient voltage, V COMP represents a compensation voltage.

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