Storage device, operating method thereof, and computing system including the same

Abstract

The invention relates to a storage device, an operating method thereof, and a computing system including the storage device. The storage device for efficiently performing garbage collection may include: a memory device including a plurality of partitions corresponding to consecutive logical address groups provided from a host device, the plurality of partitions including a first partition and a second partition; and a memory controller for receiving a garbage collection request from the host device and controlling the memory device to store the plurality of pieces of valid data stored in the first partition in the second partition in response to the garbage collection request. The garbage collection request may include first identification information identifying the first partition, a plurality of pieces of first offset information indicating locations in the first partition where the plurality of pieces of valid data are stored, second identification information identifying the second partition, and second offset information indicating locations in the second partition where the plurality of pieces of valid data are to be stored.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0050682, filed on April 16, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to a semiconductor device, and more particularly, to a memory device, an operating method thereof, and a computing system including the memory device. Background Art

[0004] A storage device is a device that stores data under the control of a host device, including computers, mobile terminals such as smartphones and tablets, and various other electronic devices. A storage device may include a memory device that stores data and a memory controller that controls the memory device. The storage device converts logical addresses transmitted from the host device into physical addresses to be used. Therefore, the logical area of ​​the host device and the physical area of ​​the storage device are associated with each other.

[0005] The host device can manage logical areas using partitions as units. Partitions can be mapped one-to-one to physical areas to be managed in the storage device. The host device can also control garbage collection. For example, if there are insufficient partitions for storing data, the host device can move valid data in the target partition to a new partition and reset the target partition to ensure a free partition.

[0006] To move valid data to a new partition during garbage collection, the host device can receive the valid data and re-provide it to the storage device, requesting that the storage device store the valid data in the new partition. This transmission and reception of valid data between the host device and the storage device can increase the time required for garbage collection. Therefore, a plan for efficiently executing garbage collection is necessary. Summary of the Invention

[0007] Embodiments of the present disclosure provide a storage device, an operating method thereof, and a computing system including the storage device, wherein a garbage collection request including information about a location to which valid data is to be moved is received from a host device, so that garbage collection can be efficiently performed because there is no process of sending / receiving valid data between the host device and the storage device.

[0008] According to an embodiment of the disclosure, there is provided a storage device including a memory device including a plurality of zones corresponding to a set of consecutive logical addresses provided from a host device, the plurality of zones including a first zone and a second zone; and a memory controller configured to receive a garbage collection request from the host device, and control the memory device to store a plurality of valid data stored in the first zone in the second zone in response to the garbage collection request, wherein the garbage collection request includes first identification information identifying the first zone, a plurality of first offset information indicating locations in the first zone where the plurality of valid data is stored, second identification information identifying the second zone, and second offset information indicating a location in the second zone where the plurality of valid data is to be stored.

[0009] According to another embodiment of the disclosure, there is provided a method of operating a storage device, the method including receiving, from a host device, first identification information identifying a first zone among a plurality of zones of a memory device, a plurality of first offset information indicating locations in the first zone where a plurality of valid data is stored, second identification information identifying a second zone among the plurality of zones, and second offset information indicating a location in the second zone where the plurality of valid data is to be stored; based on the first identification information and the plurality of first offset information, obtaining a plurality of first physical addresses indicating memory areas in which the plurality of valid data is stored; reading the plurality of valid data from the memory areas indicated by the plurality of first physical addresses included in the first zone; based on the second identification information and the second offset information, obtaining a plurality of second physical addresses indicating memory areas in which the plurality of valid data is to be stored; and storing the read plurality of valid data in the memory areas indicated by the plurality of second physical addresses included in the second zone.

[0010] According to still another embodiment of the disclosure, there is provided a computing system including a host device configured to provide, when a garbage collection is requested, first identification information identifying a first zone among a plurality of zones, first offset information including distance information from a start address of the first zone to an address indicating a first memory area in which valid data is stored, second identification information identifying a second zone among the plurality of zones, and second offset information including distance information from a start address of the second zone to an address indicating a second memory area in which the valid data is to be stored; and a storage device including the plurality of zones, and configured to receive the first identification information, the first offset information, the second identification information, and the second offset information from the host device, and move the valid data stored in the first memory area to the second memory area based on the first identification information, the first offset information, the second identification information, and the second offset information. BRIEF DESCRIPTION OF DRAWINGS

[0011] Various embodiments of the disclosure will now be described more fully hereinafter with reference to the accompanying drawings; however, embodiments can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0012] In the drawings, the size of some of the elements can be exaggerated for clarity and clarity. It will be understood that, when an element is referred to as being "between" two elements, only one element can be present between the two elements or one or more intermediate elements can also be present. The same reference numbers denote the same elements throughout the disclosure.

[0013] Figure 1 is a diagram illustrating a computing system according to an embodiment of the disclosure.

[0014] Figure 2 is a diagram illustrating a partition according to an embodiment of the disclosure.

[0015] Figure 3 is a diagram illustrating a logical address allocated to a partition according to an embodiment of the disclosure.

[0016] Figure 4 is a diagram illustrating mapping data indicating a mapping relationship between offset information and a physical address according to an embodiment of the disclosure.

[0017] Figure 5 is a diagram illustrating an example of reading valid data in a sacrifice partition according to an embodiment of the disclosure.

[0018] Figure 6 is a diagram illustrating an example of storing read valid data in a new partition according to an embodiment of the disclosure.

[0019] Figure 7 is a flowchart illustrating an operating method of a storage device according to an embodiment of the disclosure.

[0020] Figure 8 is a diagram illustrating a memory controller according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0021] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of the disclosure. Embodiments according to the concept of the disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0022] Figure 1 is a diagram illustrating a computing system 10 according to an embodiment of the disclosure.

[0023] Referring to Figure 1The computing system 10 can include a storage device 50 and a host device 300.

[0024] The storage device 50 can be a device that stores data under the control of the host device 300 such as a mobile phone, a smartphone, an MP3 player, a laptop computer, a server computer, a desktop computer, a game console, a TV, a tablet PC, or a car infotainment system.

[0025] The storage device 50 can include a memory device 100 and a memory controller 200 that controls the operation of the memory device 100.

[0026] The storage device 50 can be configured as any of a solid state drive (SSD), a multimedia card in the form of an MMC and an eMMC, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a peripheral component interconnect (PCI) card type storage device, a high speed PCI (PCI-e or PCIe) card type storage device, a compact flash (CF) card, a smart media card (SMC), and a memory stick, according to a communication scheme with the host device 300.

[0027] The storage device 50 can be manufactured as any of various package types. For example, the storage device 50 can be manufactured as any of various package types such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer level package (WFP), and a wafer level stack package (WSP).

[0028] The memory device 100 can store data. The memory device 100 can include a plurality of memory blocks for storing data. Each memory block can include a plurality of memory cells.

[0029] In an embodiment, the memory device 100 can be a non-volatile memory in which data does not disappear even if power supply is interrupted. In this specification, a case in which the memory device 100 is a NAND flash memory is described for convenience of description.

[0030] In an embodiment, the memory device 100 can receive a command and an address from the memory controller 200. The memory device 100 can perform an operation indicated by the command on a region selected by the address. For example, the memory device 100 can perform a write operation (or a program operation), a read operation, and an erase operation.

[0031] In an embodiment, the memory device 100 can include a plurality of zones ZONE1 to ZONEn. Each zone can include a plurality of memory blocks and can be allocated to a logical address group configured with a continuous logical address provided by the host device 300. It will be described with reference to FIGS. 2 to 4.Figure 2 The detailed description partitions.

[0032] The memory controller 200 can control the entire operation of the storage device 50.

[0033] When power is supplied to the storage device 50, the memory controller 200 can execute firmware (FW). When the memory device 100 is a flash memory device, the FW can include a host interface layer (HIL) for controlling communication with the host device 300, a flash translation layer (FTL) for controlling communication between the host device 300 and the memory device 100, and a flash interface layer (FIL) for controlling communication with the memory device 100.

[0034] In an embodiment, the memory controller 200 can receive data and a logical block address (LBA) from the host device 300, and convert the LBA into a physical block address (PBA) indicating an address of a memory cell including data to be stored in the memory device 100. In this specification, the LBA and "logical address" or "logical addresses" can be used in the same meaning. In this specification, the PBA and "physical address" can be used in the same meaning.

[0035] In an embodiment, the memory controller 200 can provide a command, an address, or data corresponding to a program operation, a read operation, an erase operation, or the like, to the memory device 100 according to a request of the host device 300, to perform a corresponding operation.

[0036] In an embodiment, the memory controller 200 can autonomously generate a command, an address, and data without any request of the host device 300, and transmit the command, the address, and the data to the memory device 100. For example, the memory controller 200 can provide the memory device 100 with a command, an address, and data for performing a program operation and a read operation accompanied when an internal operation such as a wear leveling operation, a read recycling operation, a garbage collection operation, or the like is performed.

[0037] In an embodiment, the memory controller 200 can include a partition controller 210.

[0038] The partition controller 210 can control a read operation, a program operation, a reset operation, or the like, with respect to a partition according to a request of the host device 300.

[0039] In an embodiment, the zone controller 210 can receive a garbage collection request GC REQ from the host device 300 and control the memory device 100 to store a plurality of valid data stored in a victim zone among a plurality of zones ZONE1 to ZONEn in a new zone. The victim zone is a target zone of garbage collection, and can mean a zone that is a target of a reset operation for the purpose of securing a free zone.

[0040] In an embodiment, the garbage collection request GC REQ can include first identification information ID1 identifying the victim zone, a plurality of first offset information OFFSET1 indicating a location in which a plurality of valid data is stored in the victim zone, second identification information ID2 identifying a new zone in which the plurality of valid data is to be stored, and second offset information OFFSET2 indicating a location in which the plurality of valid data is to be stored in the new zone.

[0041] For example, the zone controller 210 can receive the first identification information ID1, the first offset information OFFSET1, the second identification information ID2, and the second offset information OFFSET2 from the host device 300. Also, the zone controller 210 can move a valid data piece stored in the victim zone to the new zone based on the first identification information ID1, the first offset information OFFSET1, the second identification information ID2, and the second offset information OFFSET2.

[0042] Also, the zone controller 210 can move the valid data piece stored in the victim zone to the new zone and then perform a reset operation on the victim zone.

[0043] In an embodiment, after the zone controller 210 moves the valid data piece stored in the victim zone to the new zone, the zone controller 210 can provide the host device 300 with three pieces of offset information indicating a start position of a free memory region included in the new zone as a response REP to the garbage collection request GC REQ.

[0044] The host device 300 can communicate with the memory device 50 using at least one of various communication standards or interfaces such as Universal Serial Bus (USB), Serial AT Attachment (SATA), High Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multi-Media Card (MMC), Embedded MMC (eMMC), Dual In-Line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0045] The host device 300 can include an operating system (OS), an application program running on the OS, a file system that allocates a logical address of data to be stored or determines a logical address of data to be read, etc.

[0046] In an embodiment, the host device 300 can include a zone manager 310 and a garbage collection controller 320.

[0047] The zone manager 310 can manage a plurality of zones ZONE1 to ZONEn.

[0048] In an embodiment, the zone manager 310 can allocate a logical address group to each of the plurality of zones ZONE1 to ZONEn. The zone manager 310 can request the storage device 50 to transmit state information of the plurality of zones ZONE1 to ZONEn, and request the storage device 50 to perform a read operation, a write operation, a reset operation, etc., based on the state information of the plurality of zones. The state information can include information of an open state, a closed state, etc. In addition, the zone manager 310 can store a write pointer indicating a position of data to be stored in each zone.

[0049] The garbage collection controller 320 can control a garbage collection operation on the plurality of zones ZONE1 to ZONEn. For example, when the number of free zones in which data can be stored among the plurality of zones ZONE1 to ZONEn is a threshold value or less, the garbage collection controller 320 can control the garbage collection operation. The garbage collection controller 320 can determine a victim zone by considering the number of valid pages in the zone, the state information of the zone, etc. For example, the garbage collection controller 320 can determine a zone in a closed state among the plurality of zones ZONE1 to ZONEn as a victim zone, and determine a zone in which the number of valid pages is greater among the zones in the closed state as a victim zone.

[0050] In an embodiment, when garbage collection is triggered, the garbage collection controller 320 can generate first identification information ID1, first offset information OFFSET1, second identification information ID2, and second offset information OFFSET2, and provide the first identification information ID1, the first offset information OFFSET1, the second identification information ID2, and the second offset information OFFSET2 to the storage device 50.

[0051] According to an embodiment of the disclosure, the position in which valid data is stored in the victim zone and the position in which valid data is to be stored in the new zone are provided together at the time of receiving the garbage collection request GCREQ, so that since there is no process of transmitting / receiving valid data between the host device 300 and the storage device 50, the time required for garbage collection can be reduced and garbage collection can be efficiently performed.

[0052] Figure 2is a diagram illustrating partitioning of a memory device according to an embodiment of the disclosure.

[0053] Referring to Figure 2 , each of the plurality of partitions ZONE1 to ZONEn can include a plurality of memory blocks. In an embodiment, the number of memory blocks included in the plurality of partitions ZONE1 to ZONEn can be different from or the same as each other. For example, the memory device 100 can include a plurality of dies DIE1 to DIEn. Each partition can include a plurality of memory blocks included in different dies.

[0054] In some embodiments, unlike the example shown in Figure 2 , each partition can be configured within one memory block. That is, each partition can be configured with a memory region configured in at least one erase operation unit.

[0055] The partition can be a region in which data corresponding to a logical address input from the host device 300 is stored. In particular, the plurality of partitions ZONE1 to ZONEn can be regions in which data corresponding to assigned logical address groups, respectively, are stored. Each logical address group can include consecutive logical addresses.

[0056] In some embodiments, the plurality of partitions ZONE1 to ZONEn can have an open state and a closed state according to a request of the host device 300. A partition having the open state can be designated as an open partition, and a partition having the closed state can be designated as a closed partition. The open partition refers to a partition in which data can be written, i.e., a writable partition. The memory controller 200 can perform a write operation on data in the open partition. The closed partition refers to a partition in which data cannot be written. Until the state of the closed partition becomes the open state, the memory controller 200 cannot perform a write operation on data in the closed partition.

[0057] In addition, each of the plurality of partitions ZONE1 to ZONEn can perform a reset operation according to a reset request input from the host device 300. The reset operation can be an operation of erasing data stored in a memory block included in a partition that is a target of the reset request. For example, when a reset request for the first partition ZONE1 is input, the memory device 100 can perform an erase operation on a memory block included in the first partition ZONE1.

[0058] Figure 3 is a diagram illustrating logical addresses assigned to a partition according to an embodiment of the disclosure.

[0059] Referring to Figure 3The plurality of zones ZONE1 to ZONEn can be respectively allocated to the logical address groups. For example, the first zone ZONE1 can be allocated to a first logical address group LBAG1. The first logical address group LBAG1 can include consecutive zeroth to ninth logical addresses LBA0 to LBA9. The second zone ZONE2 can be allocated to a second logical address group LBAG2. The second logical address group LBAG2 can include consecutive tenth to nineteenth logical addresses LBA10 to LBA19.

[0060] The first zone ZONE1 can store data DATA0 to DATA9 corresponding to the zeroth to ninth logical addresses LBA0 to LBA9 received from the host device 300. The write pointer WP can indicate a position where data corresponding to a logical address is last stored in a zone or a start position of an empty memory area. Since data up to the ninth data DATA9 corresponding to the ninth logical address LBA9 is already stored in the first zone ZONE1, the write pointer WP of the first zone ZONE1 can indicate the last position of the ninth logical address LBA9. In an embodiment, the offset of the write pointer WP of the first zone ZONE1 can be 10. The first zone ZONE1 can be in a state where all memory areas store data.

[0061] The second zone ZONE2 can store data DATA10 to DATA14 corresponding to the tenth to fourteenth logical addresses LBA10 to LBA14 received from the host device 300. Since data up to the fourteenth data DATA14 corresponding to the fourteenth logical address LBA14 is already stored in the second zone ZONE2, the write pointer WP of the second zone ZONE2 can indicate the fifteenth logical address LBA15. In an embodiment, the offset of the write pointer WP of the second zone ZONE2 can be 5.

[0062] In an embodiment, one logical address can correspond to one physical address. Although the logical addresses are consecutive, the physical addresses corresponding to the respective logical addresses can be consecutive or can be non-consecutive.

[0063] Although not described in the above example, each of the other zones other than the first zone ZONE1 and the second zone ZONE2 can also be allocated to a logical address group in the same manner as the first zone ZONE1 and the second zone ZONE2.

[0064] Figure 4 FIG. 1 is a diagram illustrating mapping data indicating a mapping relationship between offset information and a physical address according to an embodiment of the disclosure.

[0065] Referring to Figure 4The storage device 50 can store a plurality of mapping data MAP_ZONE1 to MAP_ZONEn. For example, the plurality of mapping data MAP_ZONE1 to MAP_ZONEn can be stored in the memory controller 200 or the memory device 100.

[0066] In an embodiment, each of the plurality of mapping data MAP_ZONE1 to MAP_ZONEn can include a mapping relationship between offset information OFFSET provided by the host device 300 with respect to each of the plurality of zones ZONE1 to ZONEn and a physical address PBA indicating a location in which data is stored in the memory device 100.

[0067] For example, the first mapping data MAP_ZONE1 can indicate a mapping relationship between offset information with respect to the first zone ZONE1 and a physical address. Specifically, in the first mapping data MAP_ZONE1, offset information 0 can be mapped to a fifth physical address PBA5, offset information 1 can be mapped to a sixth physical address PBA6, offset information 2 can be mapped to a seventh physical address PBA7, offset information 3 can be mapped to an eighth physical address PBA8, offset information 4 can be mapped to a tenth physical address PBA10, offset information 5 can be mapped to a ninth physical address PBA9, offset information 6 can be mapped to a fifteenth physical address PBA15, offset information 7 can be mapped to a sixteenth physical address PBA16, offset information 8 can be mapped to a seventeenth physical address PBA17, and offset information 9 can be mapped to an eighteenth physical address PBA18.

[0068] The second mapping data MAP_ZONE2 can indicate a mapping relationship between offset information with respect to the second zone ZONE2 and a physical address. Specifically, in the second mapping data MAP_ZONE2, offset information 0 can be mapped to a forty-fifth physical address PBA45, offset information 1 can be mapped to a forty-sixth physical address PBA46, offset information 2 can be mapped to a forty-seventh physical address PBA47, offset information 3 can be mapped to a fifty-third physical address PBA53, offset information 4 can be mapped to a fifty-fourth physical address PBA54, offset information 5 can be mapped to a fifty-fifth physical address PBA55, offset information 6 can be mapped to a sixtieth physical address PBA60, offset information 7 can be mapped to a sixty-first physical address PBA61, offset information 8 can be mapped to a sixty-fourth physical address PBA64, and offset information 9 can be mapped to a sixty-fifth physical address PBA65.

[0069] Although not described in the above example, each of other mapping data other than the first mapping data MAP_ZONE1 and the second mapping data MAP_ZONE2 can also indicate a mapping relationship between offset information and a physical address in the same manner as the first mapping data MAP_ZONE1 and the second mapping data MAP_ZONE2.

[0070] Figure 5 is a diagram illustrating an example of reading valid data in a sacrifice zone according to an embodiment of the disclosure.

[0071] In Figure 5 , it is shown that the sacrifice zone is the first zone ZONE1. In addition, the diagonal line or the shaded area can represent a memory area storing data.

[0072] Referring to Figure 4 and Figure 5 , in an embodiment, the plurality of first offset information OFFSET1_1 to OFFSET1_3 about the first zone ZONE1 can include distance information from a start logical address of the first zone ZONE1 to a plurality of first logical addresses indicating memory areas storing the plurality of valid data VALID1 to VALID3. The plurality of first logical addresses can respectively correspond to a plurality of first physical addresses PBA5, PBA8 and PBA9 indicating the memory areas storing the plurality of valid data VALID1 to VALID3.

[0073] In an embodiment, the memory controller 200 can acquire the plurality of first physical addresses PBA5, PBA8 and PBA9 indicating the memory areas storing the plurality of valid data VALID1 to VALID3 based on the first identification information and the plurality of first offset information OFFSET1_1 to OFFSET1_3.

[0074] For example, the memory controller 200 can determine first mapping data MAP_ZONE1 about the first zone ZONE1 among the plurality of mapping data based on the first identification information. The memory controller 200 can acquire a plurality of first physical addresses mapped to a plurality of first offset information OFFSET1_1 to OFFSET1_3 based on the determined first mapping data MAP_ZONE1. Specifically, since the first (1-1) offset information OFFSET1_1 corresponds to 0, the first (1-1) offset information OFFSET1_1 can indicate a starting logical address of the first zone ZONE1. The memory controller 200 can convert the offset information 0 into a fifth physical address PBA5 based on the first mapping data MAP_ZONE1. Since the first (1-2) offset information OFFSET1_2 corresponds to 3, the first (1-2) offset information OFFSET1_2 can indicate a logical address that is offset by 3 from the starting logical address of the first zone ZONE1. The memory controller 200 can convert the offset information 3 into an eighth physical address PBA8 based on the first mapping data MAP_ZONE1. Since the first (1-3) offset information OFFSET1_3 corresponds to 5, the first (1-3) offset information OFFSET1_3 can indicate a logical address that is offset by 5 from the starting logical address of the first zone ZONE1. The memory controller 200 can convert the offset information 5 into a ninth physical address PBA9 based on the first mapping data MAP_ZONE1.

[0075] In an embodiment, the memory controller 200 can control the memory device 100 to read a plurality of valid data VALID1 to VALID3 from a memory region indicated by the plurality of first physical addresses PBA5, PBA8, and PBA9 included in the first zone ZONE1.

[0076] For example, the memory controller 200 can provide a read command and the plurality of first physical addresses PBA5, PBA8, and PBA9 to the memory device 100. The memory device 100 can read the plurality of valid data VALID1 to VALID3 from the memory region indicated by the plurality of first physical addresses PBA5, PBA8, and PBA9 in response to the read command and provide the plurality of valid data VALID1 to VALID3 to the memory controller 200.

[0077] Figure 6 is a diagram illustrating an example of storing read valid data in a new zone according to an embodiment of the disclosure.

[0078] In Figure 6 , it is shown that the new zone is a second zone ZONE2. In addition, a diagonal line or a shaded region can represent a memory region in which data is stored.

[0079] Referring toFigure 4 and Figure 6 In an embodiment, the second offset information OFFSET2 can include distance information from the start logical address of the second zone ZONE2 to a second logical address indicating a memory region where the plurality of valid data VALID1 to VALID3 are to be stored.

[0080] In an embodiment, the memory controller 200 can acquire a plurality of second physical addresses PBA55, PBA60 and PBA61 respectively indicating memory regions where the plurality of valid data VALID1 to VALID3 are to be stored based on the second identification information and the second offset information OFFSET2.

[0081] For example, the memory controller 200 can determine second mapping data MAP_ZONE2 about the second zone ZONE2 based on the second identification information. The memory controller 200 can acquire a plurality of second physical addresses PBA55, PBA60 and PBA61 mapped to the second offset information OFFSET2 and offset information OFFSET_SEQ consecutive to the second offset information OFFSET2 based on the determined second mapping data MAP_ZONE2. Specifically, since the second offset information OFFSET2 corresponds to 5, the second offset information OFFSET2 can indicate a logical address having an offset of 5 from the start logical address of the second zone ZONE2. The memory controller 200 can convert the offset information 5 to the fifty-fifth physical address PBA55 based on the second mapping data MAP_ZONE2.

[0082] The memory controller 200 can determine offset information OFFSET_SEQ consecutive to the second offset information OFFSET2. For example, the memory controller 200 can determine the offset information OFFSET_SEQ according to the number of the plurality of valid data VALID1 to VALID3. Specifically, the memory controller 200 can determine the offset information OFFSET_SEQ so that the number of the offset information OFFSET_SEQ consecutive to the second offset information OFFSET2 coincides with the number of the plurality of valid data VALID1 to VALID3. Specifically, according to the second offset information OFFSET2, since there are two valid data VALID2 and VALID3 in addition to the valid data VALID1 to be stored, the memory controller 200 can determine two offset information OFFSET_SEQ consecutive to the second offset information OFFSET2.

[0083] Since the two consecutive offset information OFFSET_SEQ correspond to 6 and 7, respectively, the two consecutive offset information OFFSET_SEQ can indicate logical addresses that are offset by 6 and 7 from the starting logical address of the second zone ZONE2. The memory controller 200 can convert the offset information 6 and 7 to the sixtieth physical address PBA60 and the sixty-first physical address PBA61, respectively, based on the second mapping data MAP_ZONE2.

[0084] In an embodiment, the memory controller 200 can control the memory device 100 to store the plurality of valid data VALID1 to VALID3 in the memory region indicated by the plurality of second physical addresses PBA55, PBA60, and PBA61 included in the second zone ZONE2.

[0085] For example, the memory controller 200 can provide the memory device 100 with a write command, the plurality of valid data VALID1 to VALID3, and the plurality of second physical addresses PBA55, PBA60, and PBA61. The memory device 100 can store the plurality of valid data VALID1 to VALID3 in the memory region indicated by the plurality of second physical addresses PBA55, PBA60, and PBA61 in response to the write command.

[0086] In an embodiment, after storing the plurality of valid data VALID1 to VALID3 in the second zone ZONE2, the memory controller 200 can provide the host device 300 with third offset information OFFSET3 including distance information from the starting logical address of the second zone ZONE2 to a logical address indicating an empty memory region, as a response to the garbage collection request.

[0087] For example, when the garbage collection operation is completed, the memory controller 200 can provide the host device 300 with the third offset information OFFSET3 indicating a position where the valid data VALID3 is last stored in the second zone ZONE2 or a starting position of an empty memory region. That is, the third offset information OFFSET3 can indicate a position where a write operation can be started in the second zone ZONE2. When a write request for the second zone ZONE2 is subsequently received, the host device 300 can refer to the third offset information OFFSET3 to provide the memory device 50 with the write request.

[0088] Figure 7 is a diagram illustrating an operation method of a memory device according to an embodiment of the disclosure.

[0089] Figure 7 The illustrated operation method can be performed by Figure 1 the memory device 50 illustrated.

[0090] Referring to Figure 7 In S701, the storage device 50 can receive, from the host device 300, first identification information identifying a first partition, a plurality of first offset information indicating positions in the first partition in which a plurality of valid data are stored, second identification information identifying a second partition, and second offset information indicating positions in the second partition in which the plurality of valid data are to be stored.

[0091] In S703, the storage device 50 can acquire a plurality of first physical addresses indicating memory areas in which the plurality of valid data are stored, based on the first identification information and the plurality of first offset information.

[0092] For example, the storage device 50 can determine mapping data about the first partition based on the first identification information. Also, the storage device 50 can convert the plurality of first offset information into the plurality of first physical addresses based on the mapping data.

[0093] In S705, the storage device 50 can read the plurality of valid data from the memory areas indicated by the plurality of first physical addresses included in the first partition.

[0094] In S707, the storage device 50 can acquire a plurality of second physical addresses indicating memory areas in which the plurality of valid data are to be stored, based on the second identification information and the second offset information.

[0095] For example, the storage device 50 can determine mapping data about the second partition based on the second identification information. Also, the storage device 50 can convert the second offset information and offset information consecutive to the second offset information into the plurality of second physical addresses based on the mapping data.

[0096] In S709, the storage device 50 can store the read plurality of valid data in the memory areas indicated by the plurality of second physical addresses included in the second partition.

[0097] In S711, the storage device 50 can provide, to the host device 300, third offset information including distance information from a start logical address of the second partition to a logical address indicating an empty memory area, as a response to the garbage collection request.

[0098] Figure 8 is a diagram illustrating a memory controller according to an embodiment of the disclosure.

[0099] Referring to Figure 8 The memory controller 200 can include a partition controller 210, a processor 220, a memory 230, an error correction circuit 240, a host interface 250, a memory interface 260, and a communication bus 270. Figure 8 The illustrated partition controller 210 representsFigure 1 The illustrated partition controller 210 will thus omit detailed description thereof.

[0100] The processor 220 can control general operations of the memory controller 200.

[0101] In an embodiment, the processor 220 can execute firmware, code, or one or more commands including various information required when the memory controller 200 operates.

[0102] The memory 230 can serve as a buffer memory, a cache memory, a working memory, etc.

[0103] In addition, the memory 230 can store firmware, code, or one or more commands including various information required when the memory controller 200 operates.

[0104] The error correction circuit 240 can perform error correction when data is stored or read. For example, the error correction circuit 240 can perform error correction code (ECC) encoding based on data to be written to the memory device 100. The encoded data can be transferred to the memory device 100. The error correction circuit 240 can perform ECC decoding on data received from the memory device 100.

[0105] The memory controller 200 can communicate with an external device (e.g., a host device 300, an application processor, etc.) through the host interface 250.

[0106] The memory controller 200 can communicate with the memory device 100 through the memory interface 260. The memory controller 200 can transmit a command, an address, a control signal, etc. to the memory device 100 through the memory interface 260 and receive data from the memory device 100 through the memory interface 260.

[0107] The partition controller 210, the processor 220, the memory 230, the error correction circuit 240, the host interface 250, and the memory interface 260 can communicate with each other through the communication bus 270.

[0108] According to embodiments of the disclosure, a memory device that can efficiently perform garbage collection, an operating method thereof, and a computing system including the memory device can be provided.

[0109] While the disclosure has been illustrated and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the disclosure should not be limited to the above-described embodiments but should be determined by not only the appended claims but also the equivalents thereof.

[0110] In the above-described embodiments, all operations can be selectively performed or some operations can be omitted. In each embodiment, the operations are not necessarily performed in the order described, but can be rearranged. The embodiments disclosed in the specification and drawings are only for the convenience of understanding examples of the disclosure, and the disclosure is not limited to these embodiments. That is, it is obvious to those skilled in the art that various modifications can be made based on the technical scope of the disclosure.

[0111] Embodiments of the disclosure have been described in the accompanying drawings and specification. Although specific terms are used herein, these terms are used only for describing the embodiments of the disclosure. Accordingly, the disclosure is not limited to the above-described embodiments, and many variations are possible within the spirit and scope of the disclosure. It is obvious to those skilled in the art that various modifications can be made based on the technical scope of the disclosure in addition to the embodiments disclosed herein. Furthermore, the embodiments can be combined to form additional embodiments.

Claims

1. A storage device, comprising: a memory device including a plurality of zones corresponding to a set of consecutive logical addresses provided from a host device, the plurality of zones including a first zone and a second zone; and a memory controller receiving a garbage collection request from the host device and controlling the memory device to store a plurality of valid data stored in the first zone in the second zone in response to the garbage collection request, wherein the garbage collection request includes first identification information identifying the first zone, a plurality of first offset information indicating locations in the first zone where the plurality of valid data is stored, second identification information identifying the second zone, and second offset information indicating a location in the second zone where the plurality of valid data is to be stored. 2.The storage device of claim 1, wherein the plurality of first offset information includes distance information from a start logical address of the first zone to a plurality of first logical addresses indicating memory regions where the plurality of valid data is stored. 3.The storage device of claim 1, wherein the second offset information includes distance information from a start logical address of the second zone to a second logical address indicating a memory region where the plurality of valid data is to be stored. the memory controller stores mapping data indicating a mapping relationship between offset information about the plurality of zones provided from the host device and physical addresses indicating locations where data is stored in the memory device.

4. The memory device of claim 1, wherein, the memory controller determines mapping data about the first zone based on the first identification information, and acquires a plurality of first physical addresses mapped to the plurality of first offset information based on the determined mapping data.

5. The memory device of claim 4, wherein, the memory controller controls the memory device to read the plurality of valid data from memory regions included in the first zone and indicated by the plurality of first physical addresses.

6. The memory device of claim 5, wherein, the memory controller determines mapping data of the second zone based on the second identification information, and acquires a plurality of second physical addresses mapped to the second offset information and offset information consecutive to the second offset information based on the determined mapping data.

7. The memory device of claim 4, wherein, the memory controller controls the memory device to store the plurality of valid data in memory regions included in the second zone and indicated by the plurality of second physical addresses.

8. The memory device of claim 7, wherein, the memory controller stores the plurality of valid data in the second zone, and then provides third offset information to the host device, the third offset information including distance information from a start logical address of the second zone to a logical address indicating an empty memory region.

9. The memory device of claim 1, wherein, 10.A method of operating a storage device, comprising: receiving, from a host device, first identification information identifying a first zone among a plurality of zones of a memory device, a plurality of first offset information indicating locations in the first zone where a plurality of valid data is stored, second identification information identifying a second zone among the plurality of zones, and second offset information indicating a location in the second zone where the plurality of valid data is to be stored; ​ based on the first identification information and the plurality of first offset information, obtaining a plurality of first physical addresses indicating memory regions storing the plurality of valid data; reading the plurality of valid data from the memory regions indicated by the plurality of first physical addresses included in the first partition; based on the second identification information and the second offset information, obtaining a plurality of second physical addresses indicating memory regions to store the plurality of valid data; and storing the read plurality of valid data in the memory regions indicated by the plurality of second physical addresses included in the second partition.

11. The method of claim 10, wherein the plurality of first offset information includes distance information from a starting logical address of the first partition to a plurality of first logical addresses indicating memory regions storing the plurality of valid data.

12. The method of claim 10, wherein the second offset information includes distance information from a starting logical address of the second partition to a second logical address indicating a memory region to start storing the plurality of valid data.

13. The method of claim 10, wherein obtaining the plurality of first physical addresses comprises: determining mapping data about the first partition based on the first identification information; and converting the plurality of first offset information to the plurality of first physical addresses based on the mapping data.

14. The method of claim 10, wherein obtaining the plurality of second physical addresses comprises: determining mapping data about the second partition based on the second identification information; and converting the second offset information and offset information consecutive to the second offset information to the plurality of second physical addresses.

15. The method of claim 10, further comprising providing third offset information to the host device after storing the read plurality of valid data, the third offset information including distance information from a starting logical address of the second partition to a logical address indicating an empty memory region.

16. A computing system comprising: a host device, upon requesting garbage collection, providing first identification information identifying a first partition among a plurality of partitions, first offset information including distance information from a starting address of the first partition to an address indicating a first memory region storing valid data, second identification information identifying a second partition among the plurality of partitions, and second offset information including distance information from a starting address of the second partition to an address indicating a second memory region to store the valid data; and a storage device including the plurality of partitions, and receiving the first identification information, the first offset information, the second identification information, and the second offset information from the host device, and moving valid data stored in the first memory region to the second memory region based on the first identification information, the first offset information, the second identification information, and the second offset information. ​ ​ 17. The computing system of claim 16, wherein, The storage device obtains a first physical address indicating the first memory region based on the first identification information and the first offset information, and reads the valid data from the first memory region based on the first physical address.

18. The computing system of claim 16, wherein, The storage device obtains a second physical address indicating the second memory region based on the second identification information and the second offset information, and stores the valid data in the second memory region based on the second physical address.

19. The computing system of claim 18, wherein, The storage device obtains the second physical address by: determining mapping data of the second partition based on the second identification information; and converting the second offset information and offset information continuous with the second offset information into the second physical address.

20. The computing system of claim 18, wherein, After storing the valid data in the second memory region, the storage device provides third offset information to the host device, the third offset information including distance information from a start logical address of the second partition to a logical address indicating an empty memory region.

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