Data storage device, memory controller, and operating method of data storage device

Abstract

The invention provides a data storage device which efficiently utilizes a data buffer, a memory controller of the data storage device, and an operation method of the data storage device. A data storage device may include a memory device and a memory controller. The memory controller may be configured to receive one or more write commands from an external device, combine the one or more write commands, transmit a program command corresponding to the combined write command to the memory device, and transmit the program command to the memory device after the one or more write commands are combined, before or after the program command is generated. Write data related to the combined write command is received from an external device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2024-0053497, filed on April 22, 2024, and Application No. 10-2024-0134063, filed on October 2, 2024, which are hereby incorporated by reference in their entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a data storage device, and particularly, to a data storage device that efficiently utilizes a data buffer, a memory controller of the data storage device, and an operating method of the data storage device. Background Art

[0004] The data storage device can write data provided by an external device to the storage medium, or can read data stored in the storage medium and provide the read data to the external device. For example, a non-volatile memory device (e.g., a flash memory device) can be used as the storage medium.

[0005] In order to compensate for the difference in operating speed between the external device and the storage medium, the data storage device may use a data buffer.

[0006] The chip size of the data storage device is closely related to the size of the data buffer. Therefore, in order to reduce the chip size of the data storage device, the size of the data buffer needs to be reduced. Summary of the Invention

[0007] Embodiments of the present disclosure may provide a data storage device that efficiently utilizes a data buffer, a memory controller of the data storage device, and an operating method of the data storage device.

[0008] In an embodiment of the present disclosure, a data storage device may include: a memory device; and a memory controller configured to: receive one or more write commands from an external device, combine the one or more write commands based on size information of write data corresponding to the one or more write commands, send a programming command corresponding to the combined write command to the memory device, and after combining the one or more write commands, before or after generating the programming command, receive write data related to the combined write command from the external device.

[0009] In an embodiment of the present disclosure, a memory controller may include: a programming control circuit configured to generate a programming command based on a write command received from an external device; and a data transfer control circuit configured to receive write data from the external device before starting an encoding operation on the write data associated with the programming command.

[0010] In an embodiment of the disclosure, an operating method of a data storage device including a memory device and a memory controller controlling the memory device can include: combining, by the memory controller, one or more write commands based on size information of write data corresponding to the one or more write commands received from an external device; generating, by the memory controller, a program command corresponding to the combined write command; and receiving, by the memory controller, write data related to the combined write command from the external device before or after the program command is generated, after the one or more write commands are combined.

[0011] According to an embodiment of the disclosure, by receiving write data from an external device in units of a program size as data is programmed into a memory device and buffering the received write data, the size of a data buffer can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a configuration diagram of a data processing system according to an embodiment of the disclosure.

[0013] Figure 2 is a configuration diagram of a data processing system according to an embodiment of the disclosure.

[0014] Figure 3 is a configuration diagram of a memory device according to an embodiment of the disclosure.

[0015] Figure 4 is a configuration diagram of a write control circuit according to an embodiment of the disclosure.

[0016] Figure 5 is a flowchart for describing an operating method of a data storage device according to an embodiment of the disclosure.

[0017] Figure 6 is a configuration diagram of a write control circuit according to an embodiment of the disclosure.

[0018] Figure 7 is a diagram for describing an operating method of a data storage device according to an embodiment of the disclosure.

[0019] Figure 8 is a diagram for describing an operating method of a data storage device according to an embodiment of the disclosure.

[0020] Figure 9 is a diagram for describing a relationship between a program command transmission sequence and a program completion signal transmission sequence. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0022] Figure 1 is a configuration diagram of a data processing system 10 according to an embodiment of the disclosure.

[0023] Referring to Figure 1 , the data processing system 10 can include an external device 100 and a data storage device 200.

[0024] The external device 100 can include at least one processor. The external device 100 can be a processor itself, or can be an electronic device or system including the processor.

[0025] The data storage device 200 can include a memory controller 210 and a memory device 260.

[0026] The memory controller 210 can include a data buffer 220 and a write control circuit 30. The data buffer 220 can be disposed inside and / or outside the memory controller 210.

[0027] The memory device 260 can include at least a plurality of non-volatile memory devices (NVMs) 230, 240, and 250.

[0028] To write data, the external device 100 can transmit a write request including a write command WT and an address ADD to the data storage device 200, and can transmit write data DATA to the data storage device 200 based on a response of the data storage device 200 to the write request. The write command WT can include size information of the write data DATA. Based on the write request, the memory controller 210 of the data storage device 200 can control the memory device 260 to program the write data DATA transmitted by the external device 100 into the memory device 260.

[0029] To read data, the external device 100 can transmit a read request including a read command RD and an address ADD to the data storage device 200. The memory controller 210 of the data storage device 200 can control the memory device 260 to read data DATA requested to be read from the memory device 260, and can transmit the read data DATA to the external device 100.

[0030] In addition to performing the read and write requests of the external device 100, the data storage device 200 can read data from or write data to the memory device 260 in order to perform internal operations. The internal operations can include house keeping operations, such as garbage collection, wear leveling, and read recycling, which are performed for efficient use of storage space of the memory device 260 or guaranteeing reliability of data stored in the memory device 260 without a request from the external device 100.

[0031] The memory controller 210 provides an interface connection between the external device 100 and the data storage device 200.

[0032] The data buffer 220 can temporarily store data transmitted and received between the external device 100 and the data storage device 200 after a write or read operation is initiated.

[0033] The write control circuit 30 can receive a write command WT from the external device 100, and can generate a program command by combining one or more write commands WT based on size information of write data DATA corresponding to each of the one or more write commands WT. The size information of the write data can be transmitted by being included in the write command WT. After combining the one or more write commands WT, the write control circuit 30 can receive the write data DATA from the external device 100, and can transmit the program command and the write data DATA to the memory device 260.

[0034] The write control circuit 30 can combine one or more write commands WT such that each of the one or more write commands WT corresponds to a unit program size, i.e., a size of data programmed when the memory device 260 performs a single program operation. Also, the write control circuit 30 can generate a program command corresponding to the combined write command WT.

[0035] Before the combining operation of the write commands WT, the write data DATA associated with the write commands WT can not be transmitted from the external device 100 to the data storage device 200.

[0036] The write control circuit 30 can combine one or more write commands WT, and can receive the write data DATA from the external device 100 in a unit program size and store the received write data DATA in the data buffer 220 after or before transmitting a program command corresponding to the combined write command WT to the memory device 260. Accordingly, the data buffer 220 can have a size that can store the write data DATA corresponding to a unit program size associated with the program command.

[0037] In some embodiments, the data storage device 200 can be implemented using a DRAM-less device. The DRAM-less device can refer to a device that does not include a buffer memory device that stores meta information (e.g., logical-physical address (logical-to-physical) mapping data). Although Figure 1 An external device 100 that communicates with the DRAM-less device can include a memory buffer that stores the meta information, although not shown in FIG. 1.

[0038] Figure 2 is a configuration diagram of a data processing system 10 according to an embodiment of the disclosure.

[0039] Referring to Figure 2 The data processing system 10 can include an external device 100 and a data storage device 200.

[0040] The external device 100 can include a processor 110, a memory buffer 120, and a command buffer 130.

[0041] The processor 110 can control the overall operation of the external device 100 and can transmit commands, such as a write command and a read command, to the data storage device 200.

[0042] The processor 110 can include at least one of a central processing unit (CPU), an image signal processor (ISP), a digital signal processor (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), a field programmable gate array (FPGA), and a neural processing unit (NPU).

[0043] The memory buffer 120 can temporarily store codes and data to be executed and referenced by the processor 110. The processor 110 can execute codes, such as an operating system or an application program, by utilizing the memory buffer 120, and can process data. The memory buffer 120 can be selected from a random access memory including a volatile memory device, such as a static RAM (SRAM), a dynamic RAM (DRAM), and a synchronous DRAM (SDRAM), or a non-volatile memory device, such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FeRAM).

[0044] The memory buffer 120 can temporarily store metadata, such as mapping data for supporting the operation of the data storage device 200. Since the mapping data is stored in the memory buffer 120, the data storage device 200 can access the memory device 260 by receiving the mapping data from the memory buffer 120.

[0045] The command buffer 130 can include a send queue SQ and a completion queue CQ. The send queue SQ can store commands generated by the processor 110 and to be executed by the data storage device 200. The completion queue CQ can be a memory space for writing a command processing result when the data storage device 200 processes the commands stored in the send queue SQ.

[0046] The data storage device 200 can include a memory controller 210 and a memory device 260.

[0047] Figure 3 is a configuration diagram of the memory device 260 according to an embodiment of the disclosure.

[0048] Referring to Figure 3 The memory device 260 can include a plurality of dies, such as a first die D1 and a second die D2.

[0049] Each of the first die D1 and the second die D2 can include a plurality of planes PLANE1 and PLANE2. For example, the first die D1 can include a first plane 2242a and a second plane 2242b. The second die D2 can include a first plane 2244a and a second plane 2244b. Figure 3 Two planes are shown to be included in one die, but the number of planes included in each die is not limited to two. The page buffer groups 2232a, 2232b, 2234a, and 2234b can be collectively electrically coupled to the first and second planes 2242a, 2242b, 2244a, and 2244b, respectively. Each page buffer group in a die can be electrically coupled to a plurality of planes within the same die.

[0050] The first die D1 and the second die D2 can be electrically coupled to the same channel or different channels. A channel is independent and is an interface path that can be accessed at the same time. Thus, if the first die D1 and the second die D2 are independent channels, the first die D1 and the second die D2 can be independently accessed at the same time. If the first die D1 and the second die D2 share a channel, the first die D1 and the second die D2 can be accessed in parallel through an interleaving method.

[0051] The memory device 260 can operate in a die interleaving manner or a plane interleaving manner, but is not limited thereto.

[0052] Each of the planes 2242a, 2242b, 2244a, and 2244b can include a plurality of memory blocks BLK1 to BLKi. Each of the memory blocks BLK1 to BLKi can include a plurality of pages P1 to P16. Each of the pages P1 to P16 can be a group of memory cells sharing a word line.

[0053] Data to be programmed through a single programming operation can be stored in the page buffer groups 2232a, 2232b, 2234a, and 2234b.

[0054] Referring again to Figure 2 The memory controller 210 can include a processor 211, an external device interface 213, an encryption and decryption circuit 215, a memory interface 217, a write control circuit 30, and a data buffer 220. The data buffer 220 can be disposed inside and / or outside the memory controller 210.

[0055] The processor 211 can be configured to operate as firmware or software that is provided to perform various operations of the memory controller 210, and is executed on hardware. The processor 211 can be implemented in a form of hardware and firmware or software that operates on hardware in combination. In an embodiment, the processor 211 can perform a function for managing a flash translation layer (FTL) of the memory device 260.

[0056] The external device interface 213 can receive a command and a clock signal from the external device 100 under the control of the processor 211, and provide a communication channel for controlling data input and output. Specifically, the external device interface 213 can provide a physical connection between the external device 100 and the memory device 260.

[0057] In an embodiment, the external device interface 213 can communicate with the external device 100 based on an interface using at least one of various interface protocols, such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-e or PCIe) protocol, an advanced technology attachment (ATA) protocol, a serial ATA (SATA) protocol, a parallel ATA (PATA) protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a proprietary protocol, a system management bus (SMBus) protocol, an inter-integrated circuit (I2C) protocol, and an improved inter-integrated circuit (I3C) protocol.

[0058] The external device interface 213 can communicate with the external device 100 based on a command queue-based interface. For the operation of the command queue-based interface, the external device interface 213 can include a submission queue doorbell register SQ DBR and a completion queue doorbell register CQ DBR. Each of the submission queue doorbell register SQ DBR and the completion queue doorbell register CQ DBR can be a register that manages or controls a queue pair SQ and CQ generated by the external device 100. Each of the submission queue doorbell register SQ DBR and the completion queue doorbell register CQ DBR can correspond to a queue pair including a submission queue SQ and a completion queue CQ. The data storage device 200 can process a command requested by the external device 100 and provide a notification of a processing result by accessing the submission queue SQ and the completion queue CQ through the submission queue doorbell register SQ DBR and the completion queue doorbell register CQ DBR.

[0059] The external device interface 213 can store write data provided by the external device 100 in the data buffer 220 under the control of the processor 211. In addition, read data read by the memory device 260 and stored in the data buffer 220 can be provided to the external device 100.

[0060] The data buffer 220 can be constituted of a random access memory device (e.g., dynamic random access memory (DRAM) or static random access memory (SRAM)). The data buffer 220 can store firmware driven by the processor 211. In addition, the data buffer 220 can operate as a buffer memory for storing mapping data.

[0061] The encryption and decryption circuit 215 can include at least one encoder and at least one decoder. The encryption and decryption circuit 215 can encrypt data transmitted by the external device 100 and provide the encrypted data to the memory device 260 through the memory interface 217. The encryption and decryption circuit 215 can decrypt data read from the memory device 260 and provide the decrypted data to the external device 100 through the external device interface 213.

[0062] The memory interface 217 can provide a communication path for signal transmission and reception between the memory controller 210 and the memory device 260. The memory interface 217 can transmit data that has been temporarily stored in the data buffer 220 under the control of the processor 211, in order to program the data into the memory device 260. The memory interface 217 can transmit read data read from the memory device 260 to the data buffer 220 under the control of the processor 211, in order to temporarily store the read data in the data buffer 220.

[0063] The write control circuit 30 can combine one or more write commands based on a unit programming size of the memory device 260 in response to a write command of the external device 100. The write control circuit 30 can generate a programming command corresponding to the combined write command and control a timing at which the external device 100 transmits write data associated with the programming command.

[0064] In an embodiment, one or more write commands of the external device 100 can be stored in a submission queue SQ. The external device interface 213 can acquire and parse the one or more write commands. The write control circuit 30 can combine the one or more write commands based on size information of write data corresponding to the one or more write commands and a unit programming size.

[0065] In an embodiment, the unit programming size can be a size of a page buffer group. If the memory device 260 includes a plurality of channels, the unit programming size can be determined as [size of a page buffer group × number of channels].

[0066] To improve the operation speed, a double buffering method can be introduced. In this case, the unit program size can be determined as [size of a page buffer group x number of channels x 2]. The double buffering method can refer to a method of managing the data buffer 220 as a first part of receiving the write data of the external device 100 and a second part of transmitting the write data of the data buffer 220 to the memory device 260.

[0067] If the program command is generated after receiving and combining the write data corresponding to one or more write commands, a data buffer corresponding to a size of "[size of a page buffer group x number of channels x number of storage bits per cell x number of planes]" is required. If the double buffering method is used, a data buffer corresponding to a size of "[size of a page buffer group x number of channels x number of storage bits per cell x number of planes x 2]" is required.

[0068] In the present disclosure, the program command can be generated before the external device 100 transmits the write data after combining one or more write commands. In this case, since the write data is received from the external device 100 before the memory device 260 starts the program operation, the write data can also be buffered in the data buffer 220 having the unit program size.

[0069] Since the size of the data buffer 220 required for the write operation can be reduced as described above, the chip size of the data storage device 200 can be reduced.

[0070] Figure 4 is a configuration diagram of a write control circuit 30-1 according to an embodiment of the present disclosure. The write control circuit 30-1 corresponds to Figure 2 a write control circuit 30 of

[0071] Referring to Figure 4 , the write control circuit 30-1 can include a command combining circuit 311, a program control circuit 313, a data transfer control circuit 315, and an error processing circuit 317.

[0072] When the external device 100 transmits one or more write requests, the command combining circuit 311 can combine one or more write commands based on size information of write data included in the one or more write requests so that the one or more write commands correspond to a set unit program size.

[0073] In an embodiment, the command combining circuit 311 can combine one or more write commands so that the total size of write data included in one or more write commands constituting the combined write command becomes the unit program size or less.

[0074] The program control circuit 313 can generate a program command related to the combined write command.

[0075] The data transfer control circuit 315 can receive write data related to the combined write command. The data transfer control circuit 315 can receive write data related to the combined write command after the one or more write commands are combined. Accordingly, the write data can not be transmitted to the data storage device 200 before the write data is combined.

[0076] The data transfer control circuit 315 can receive write data from the external device 100 before or after the program command is generated by the program control circuit 313 after the write command is combined.

[0077] The error processing circuit 317 can check whether an error is detected in the write data received from the external device 100. When the error is detected, the error processing circuit 317 can notify the external device 100 of the error occurrence information. In an embodiment, the error processing circuit 317 can store the error occurrence information in the completion queue CQ of the external device 100 through the external device interface 213.

[0078] When notified that the error occurs, the external device 100 can retransmit a write request related to the write data in which the error occurs.

[0079] When the error is detected to occur, the error processing circuit 317 can control the memory device 260 to program dummy data into the memory device 260.

[0080] Figure 5 is a flowchart for describing an operation method of the data storage device 200 according to an embodiment of the disclosure.

[0081] Referring to Figure 5 , the memory controller 210 of the data storage device 200 can receive at least one write request from the external device 100 (S101).

[0082] The memory controller 210 can combine one or more write commands based on size information of write data included in each of the one or more write commands such that a total size of the write data becomes a unit programming size or less (S103).

[0083] In an embodiment, the memory controller 210 can generate a program command related to the combined write command (S105). After the program command is generated, the memory controller 210 can receive write data associated with the generated program command from the external device 100 (S107).

[0084] In an embodiment, the memory controller 210 can receive write data associated with the combined write command from the external device 100 after combining the one or more write commands (S107). After receiving the write data, the memory controller 210 can generate a program command related to the combined write command (S105).

[0085] The memory controller 210 can transmit the program command and the write data associated with the combined write command to the memory device 260 (S109). Accordingly, the memory device 260 can program the write data associated with the combined write command.

[0086] Figure 6 is a configuration diagram of a write control circuit 30-2 according to an embodiment of the disclosure. The write control circuit 30-2 corresponds to Figure 2 the write control circuit 30 of FIG. 1. Figure 6 The write control circuit 30-2 illustrated in FIG. 2 can include, in addition to the elements of the write control circuit 30-1 illustrated in FIG. 1, Figure 4 the write control circuit 30-1 illustrated in FIG. 1, can include a workload detection circuit 319.

[0087] The workload detection circuit 319 can detect a command queue depth (QD), that is, the number of write and read (write / read) commands simultaneously transmitted by the external device 100, and the size of data to be processed by each command, and can determine a workload.

[0088] In an embodiment, the workload can be a high queue depth (QD) workload as a first workload or a low QD workload as a second workload. The command QD can refer to the number of IO works that the external device 100 can provide to the data storage device 200 before the external device 100 receives a response to a command transmitted to the data storage device 200.

[0089] In an embodiment, the workload detection circuit 319 can compare the command QD with a set first reference value. When the command QD is greater than the first reference value, the workload detection circuit 319 can determine that the current service situation is a high QD workload requiring high performance service. When the command QD is less than or equal to the first reference value, the workload detection circuit 319 can determine that the current service situation is a low QD workload requiring a high-speed response.

[0090] In an embodiment, the workload detection circuit 319 can determine a workload based on a unit program size and a maximum data transfer size. The maximum data transfer size can be determined as a product of the command QD and the size of the write data contained in the one or more write commands.

[0091] When the maximum data transfer size is greater than or equal to the second reference value, the memory controller 210 can determine that the current service situation is a high QD workload, and when the maximum data transfer size is less than the second reference value, the memory controller 210 can determine that the current service situation is a low QD workload.

[0092] When the unit program size is 128 KB, the command QD can be 8, and the size of the write data can be 256 KB. In this example, since the maximum data transfer size is 2 MB, which is greater than the unit program size, the program control circuit 313 is in a state in which the program control circuit 313 can generate and immediately process the program command. Therefore, such a workload can be determined as a high QD workload requiring high performance service.

[0093] When the unit program size is 128 KB, the command QD can be 8, and the size of the write data can be 4 KB. In this example, since the maximum data transfer size is 32 KB, which is less than the unit program size, the workload detection circuit 319 can wait in order to combine one or more program commands to meet the unit program size. Since the command combining circuit 311 does not transmit a program completion signal to the external device 100 until one or more program commands are combined based on the unit program size, the delay can increase. Therefore, the workload detection circuit 319 can determine such a workload as a low QD workload requiring a high-speed response.

[0094] The data transfer control circuit 315 can determine the timing of receiving the write data based on the workload determined by the workload detection circuit 319.

[0095] In an embodiment, in the case of a high QD workload, the data transfer control circuit 315 can perform control so that the write data is received after a program command corresponding to the combined write data is generated.

[0096] In an embodiment, in the case of a low QD workload, the data transfer control circuit 315 can perform control so that the program command is generated after the write data corresponding to the combined write data is received.

[0097] Figure 7 is a diagram for describing an operation method of a data storage device according to an embodiment of the disclosure.

[0098] Referring to Figure 7 , the memory controller 210 can receive a command from the external device 100 (S201), and can determine a workload based on the command of the external device 100 (S203).

[0099] In an embodiment, the memory controller 210 can determine the workload based on the command QD (i.e., the number of commands concurrently transmitted by the external device 100). For example, the memory controller 210 can compare the command QD with a set first reference value. When the command QD is greater than the first reference value, the memory controller 210 can determine that the current service situation is a high QD workload requiring high performance service. When the command QD is less than or equal to the first reference value, the memory controller 210 can determine that the current service situation is a low QD workload requiring a high-speed response.

[0100] In an embodiment, the memory controller 210 can determine the workload based on the unit program size and the maximum data transfer size. The maximum data transfer size can be determined as a product of the command QD and the size of the write data contained in one or more write commands.

[0101] When the maximum data transfer size is greater than or equal to the second reference value, the memory controller 210 can determine that the current service situation is a high QD workload. When the maximum data transfer size is less than the second reference value, the memory controller 210 can determine that the current service situation is a low QD workload.

[0102] The memory controller 210 can combine one or more write commands based on the size information of the write data contained in the one or more write commands transmitted by the external device 100 and the unit program size, such that the combined write command corresponds to the unit program size (S205). In an embodiment, the memory controller 210 can combine one or more write commands such that the total size of the write data contained in the one or more write commands constituting the combined write command is the unit program size or less.

[0103] When it is determined that the current workload is a high QD workload, the memory controller 210 can generate a program command corresponding to the combined write command (S207), and can receive the write data from the external device 100 (S209). Upon receiving the write data, the memory controller 210 can transmit a program completion signal to the external device 100 (S211).

[0104] The received write data can be stored in the data buffer 220-1. To support a high QD workload, the data buffer 220-1 can operate as a first portion H2C that stores write data of the external device 100 and a second portion C2N that transmits the stored write data to the memory device 260. The first portion H1C and the second portion C2N can operate by alternately changing their roles. That is, when the first portion H2C receives write data of the external device 100, the second portion C2N can transmit the write data to the memory device 260. When the first portion H2C transmits write data to the memory device 260, the second portion C2N can receive write data from the external device 100.

[0105] The memory controller 210 can encode the write data stored in the data buffer 220-1 (S213), and can control the memory device 260 to perform programming by transmitting a program command and the encoded write data to the memory device 260.

[0106] From Figure 7 As can be seen, the write data related to the combined write command can be transmitted to the memory controller 210 before the encoding operation S213.

[0107] Figure 8 is a diagram for describing an operation method of a data storage device according to an embodiment of the disclosure.

[0108] Referring to Figure 8 , the memory controller 210 can receive a command from the external device 100 (S301), and can determine a workload based on the command of the external device 100 (S303).

[0109] In an embodiment, the memory controller 210 can determine the workload based on the command QD (i.e., the number of commands simultaneously transmitted by the external device 100). For example, the memory controller 210 can compare the command QD with a set first reference value. When the command QD is greater than the first reference value, the memory controller 210 can determine that the current service situation is a high QD workload that requires high performance service. When the command QD is less than or equal to the first reference value, the memory controller 210 can determine that the current service situation is a low QD workload that requires a high-speed response.

[0110] In an embodiment, the memory controller 210 can determine the workload based on a unit programming size and a maximum data transfer size. The maximum data transfer size can be determined as a product of the command QD and the size of the write data contained in one or more write commands.

[0111] When the maximum data transfer size is greater than or equal to the second reference value, the memory controller 210 can determine that the current service situation is a high QD workload. When the maximum data transfer size is less than the second reference value, the memory controller 210 can determine that the current service situation is a low QD workload.

[0112] The memory controller 210 can combine the one or more write commands based on size information of the write data included in the one or more write commands transmitted by the external device 100 and the unit programming size, such that the combined write command corresponds to the unit programming size (S305). In an embodiment, the memory controller 210 can combine the one or more write commands such that the total size of the write data included in the one or more write commands constituting the combined write command becomes the unit programming size or less.

[0113] When it is determined that the current workload is a low QD workload, the memory controller 210 can receive write data from the external device 100 before generating a program command (S307). The received write data can be stored in the data buffer 220-2. After storing the write data, the memory controller 210 can transmit a program completion signal to the external device 100 (S309).

[0114] The memory controller 210 can generate a program command corresponding to the combined write command (S311), can encode the write data stored in the data buffer 220-2 (S313), and can control the memory device 260 to perform programming by transmitting the program command and the encoded write data to the memory device 260.

[0115] Under a low QD workload, the memory controller 210 can receive a next command after processing a command of the external device 100 and transmitting a program completion signal. Accordingly, the data buffer 220-2 can store write data related to a current combined write command, can complete programming of the stored write data, and then can store write data related to a next combined write command.

[0116] From Figure 8 As can be seen, the write data related to the combined write command can be transmitted to the memory controller 210 before the encoding operation S313.

[0117] Since the memory controller 210 combines the one or more write commands such that the combined write command corresponds to the unit programming size, receives the write data, and then transmits the program completion signal, the order in which the external device 100 transmits the one or more write commands and the order in which the external device 100 receives the corresponding program completion signal can be the same or different.

[0118] Figure 9 is a diagram for describing a relationship between a programming command sending order and a programming completion signal sending order.

[0119] Referring to Figure 9 , the external device 100 can sequentially send the first write command WC1, the second write command WC2, the third write command WC3, the fourth write command WC4, the fifth write command WC5, and the sixth write command WC6 to the data storage device 200.

[0120] In the illustrated embodiment, the size of the write data corresponding to the first write command WC1 is 128 KB, the size of the write data corresponding to the second write command WC2 is 64 KB, the size of the write data corresponding to the third write command WC3 is 32 KB, the size of the write data corresponding to the fourth write command WC4 is 128 KB, the size of the write data corresponding to the fifth write command WC5 is 64 KB, the size of the write data corresponding to the sixth write command WC6 is 64 KB, and the unit programming size is 128 KB.

[0121] When the first write command WC1 of which the write data is 128 KB is received, since the size of the write data satisfies the unit programming size 128 KB, the memory controller 210 of the data storage device 200 can generate a programming command without combining the first write command WC1 with other write commands. Accordingly, the memory controller 210 can send a programming completion signal WC1_RESP to the external device 100 after receiving the write data corresponding to the first write command WC1 based on a workload.

[0122] When the second write command WC2 is received, since the size 64 KB of the write data corresponding to the second write command WC2 is smaller than the unit programming size 128 KB, the memory controller 210 can postpone the processing of the second write command WC2 in order to combine the second write command WC2 with other write commands.

[0123] When the third write command WC3 is received, since the size 32 KB of the write data corresponding to the third write command WC3 is smaller than the unit programming size 128 KB, the memory controller 210 can combine the third write command WC3 with other write commands that have been received or write commands that will be received later.

[0124] The size of the write data corresponding to the second write command WC2 that has been received and postponed to be combined with other write commands is 64 KB. Accordingly, the total size of the size 64 KB of the write data corresponding to the second write command WC2 and the size 32 KB of the write data corresponding to the third write command WC3 does not satisfy the unit programming size 128 KB. The memory controller 210 can postpone the second write command WC2 and the third write command WC3 in order to combine the second write command WC2 and the third write command WC3 with other write commands.

[0125] When the fourth write command WC4 of which the write data size is 128 KB, which is equal to the unit programming size 128 KB, is received, the memory controller 210 can transmit the programming completion signal WC4_RESP to the external device 100 after receiving the write data corresponding to the fourth write command WC4 based on the workload.

[0126] When the fifth write command WC5 is received, since the size 64 KB of the write data corresponding to the fifth write command WC5 is smaller than the unit programming size 128 KB, the memory controller 210 can postpone the processing of the fifth write command WC5 in order to combine the fifth write command WC5 with other write commands.

[0127] In this case, the total size of the size 64 KB of the write data corresponding to the second write command WC2 that has been received and postponed and the size 32 KB of the write data corresponding to the third write command WC3 that has been received and postponed is 96 KB. If the second write command WC2 and the third write command WC3 are combined with the fifth write command WC5, the total size 160 KB of the size 96 KB of the write data corresponding to the second write command WC2 and the third write command WC3 and the size 64 KB of the write data corresponding to the fifth write command WC5 is greater than the unit programming size 128 KB, and thus the memory controller 210 can postpone the processing of the fifth write command WC5.

[0128] When the sixth write command WC6 of which the write data size is 64 KB is received, the memory controller 210 can combine the sixth write command WC6 with the postponed fifth write command WC5. Also, the memory controller 210 can transmit the programming completion signals WC5_RESP and WC6_RESP to the external device 100 after receiving the write data corresponding to the fifth write command WC5 and the sixth write command WC6 based on the workload.

[0129] The postponed second write command WC2 and the third write command WC3 can be combined with a subsequent write command having an appropriate size. Subsequently, the programming completion signals WC2_RESP and WC3_RESP can be transmitted to the external device 100.

[0130] Since the write data is received after one or more write commands of the external device 100 are combined as described above, the order in which the external device 100 transmits the write commands can be different from the order in which the external device 100 receives the corresponding program completion signals.

[0131] In the present disclosure, the write data can be received from the external device 100 before or after the timing of generating the program command after one or more write commands are combined such that the combined write command corresponds to a unit program size. Thus, compared to the case where the write data is combined after the write data is received, the size of the data buffer 220, 220-1, or 220-2 can be minimized because the data buffer 220, 220-1, or 220-2 buffers only the data required for a single program operation.

[0132] As described above, it will be appreciated by persons skilled in the art that the embodiments of the present disclosure can be implemented in various other forms without departing from the technical spirit or essential characteristics of the present disclosure. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and are not restrictive. The scope of the present disclosure is defined by the appended claims rather than the specific embodiments and all modifications or variations derived from the meaning and scope of the claims and their equivalents should be understood to be included in the scope of the present disclosure. Furthermore, the embodiments can be combined to form additional embodiments.

Claims

1. A data storage device comprising: a memory device; and a memory controller: receiving one or more write commands from an external device, combining the one or more write commands based on size information of write data corresponding to the one or more write commands, sending a program command corresponding to the combined write command to the memory device, and receiving write data related to the combined write command from the external device after combining the one or more write commands, before or after generating the program command. The memory controller combines the one or more write commands such that the combined write command corresponds to a unit program size, the unit program size being a size of data programmed into the memory device when a single program operation is performed by the memory device.

2. The data storage device of claim 1, wherein, The memory controller receives the write data after generating the program command when a workload is determined to be a first workload based on commands sent by the external device.

3. The data storage device of claim 1, wherein, 4. The data storage device of claim 3, wherein the workload is determined based on a number of commands sent simultaneously by the external device and a size of the write data, and the first workload is a workload in which the number of commands sent simultaneously is greater than a set first reference value or a product of the number of commands sent simultaneously and the size of the write data is greater than or equal to a set second reference value. The memory controller sends a program completion signal to the external device after receiving the write data.

5. The data storage device of claim 3, wherein, The memory controller determines a workload based on a number of commands sent simultaneously by the external device and a size of the write data, and 6. The data storage device of claim 1, wherein, a second workload is a workload in which the number of commands sent simultaneously is less than or equal to a set first reference value or a product of the number of commands sent simultaneously and the size of the write data is less than a set second reference value. The memory controller accesses the memory device based on mapping data received from the external device.

7. The data storage device of claim 1, wherein, 8. A memory controller comprising: a program control circuit that generates a program command based on a write command received from an external device; and a data transfer control circuit that receives write data associated with the program command from the external device before starting an encoding operation on the write data.

9. The memory controller of claim 8, further comprising a command combining circuit that combines one or more write commands based on size information of write data included in the one or more write commands. The command combining circuit combines the one or more write commands such that the combined write command corresponds to a unit program size, the unit program size being a size of data programmed into a memory device when a single program operation is performed by the memory device. The data transfer control circuit receives the write data after generating the program command when a workload is determined to be a first workload based on commands sent by the external device.

10. The memory controller of claim 9, wherein, ​ 11. The memory controller of claim 8, wherein, ​ 12. The memory controller of claim 8, wherein, The data transfer control circuit generates the program command after receiving the write data when it is determined that a workload is a second workload based on a command transmitted from the external device. 13.An operating method of a data storage device including a memory device and a memory controller controlling the memory device, the operating method comprising: combining, by the memory controller, one or more write commands based on size information of write data corresponding to the one or more write commands received from an external device; generating, by the memory controller, a program command corresponding to the combined write command; and receiving, by the memory controller, write data related to the combined write command from the external device after combining the one or more write commands and before or after generating the program command.

14. The method of operation of claim 13, wherein, The combining the one or more write commands includes combining the one or more write commands such that the combined write command corresponds to a unit program size, the unit program size being a size of data programmed into the memory device when a single program operation is performed by the memory device. 15.The operating method of claim 13, further comprising: determining, by the memory controller, a workload based on a command transmitted from the external device; and and receiving the write data after generating the program command when it is determined that the workload is a first workload. 16.The operating method of claim 15, wherein the workload is determined based on a number of commands transmitted simultaneously by the external device and a size of the write data, and the first workload is a workload in which the number of the commands transmitted simultaneously is greater than a set first reference value or a workload in which a product of the number of the commands transmitted simultaneously and the size of the write data is greater than or equal to a set second reference value.

17. The method of operation of claim 15, further comprising: transmitting, by the memory controller, a program completion signal to the external device after receiving the write data. 18.The operating method of claim 13, further comprising: determining, by the memory controller, a workload based on a command transmitted from the external device; and and generating the program command after receiving the write data when it is determined that the workload is a second workload. 19.The operating method of claim 18, wherein the workload is determined based on a number of commands transmitted simultaneously by the external device and a size of the write data, and the second workload is a workload in which the number of the commands transmitted simultaneously is less than or equal to a set first reference value or a workload in which a product of the number of the commands transmitted simultaneously and the size of the write data is less than a set second reference value.

20. The method of operation of claim 18, further comprising: transmitting, by the memory controller, a program completion signal to the external device after receiving the write data.

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