Flash memory checking method, device and equipment based on CRC (Cyclic Redundancy Check) check code
By performing multiple rounds of reading and data compression processing on a flash memory with a bit width higher than a preset value, a CRC check code is generated, which solves the problem of low flash memory check efficiency and improves the operation frequency and detection capability.
Patent Information
- Application Number
- CN202410480523.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-19
- Publication Date
- 2025-10-24
AI Technical Summary
The flash memory verification efficiency in the existing technology is low and cannot effectively deal with problems such as bit flipping and noise interference.
A flash memory with a bit width higher than a preset value is used, and the data to be verified is read through multiple rounds and compressed before reading, and then a CRC operation is performed to generate a check code.
The operation frequency and efficiency of flash memory verification are improved, the operation logic is reduced, and the detection capability of bit flip and noise interference is enhanced.
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Figure CN120832264A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of data processing, and in particular to a flash memory checking method, device and equipment based on CRC check code. BACKGROUND
[0002] CRC (Cyclic Redundancy Check) is an error detection technique widely used in data communication and storage systems. It generates a checksum by performing a specific mathematical operation on the data, and then appends this checksum to the original data. The receiving party performs the same CRC operation after receiving the data, and compares the result with the appended checksum to determine whether the data has been corrupted during transmission or storage.
[0003] In flash memory technology, CRC checking plays a crucial role because flash memory is used to store various types of data, including operating systems, application programs, and user files. Flash memory storage devices may face various potential problems, such as bit flips, noise interference, electromagnetic radiation, etc., which may cause errors in stored data. Therefore, it is necessary to check the data in the flash memory area before the program starts. Based on the CRC polynomial, the flash memory data is operated, and the pre-stored checksum is compared with the calculation result to determine whether the program data is normal.
[0004] Therefore, there is an urgent need to provide a more reliable flash memory checking scheme. SUMMARY
[0005] The present application aims to provide a flash memory checking method, device and equipment based on CRC check code, to solve the problem of low efficiency of flash memory checking in the prior art.
[0006] In order to achieve the above-mentioned purpose, the present application provides the following technical scheme:
[0007] In a first aspect, the present application provides a flash memory checking method based on CRC check code, the method comprising:
[0008] receiving a checking instruction;
[0009] based on the checking instruction, reading the data to be checked from the CRC operation memory range of the flash memory in multiple rounds; the flash memory is a flash memory with a bit width higher than a preset value;
[0010] compressing the data to be checked read in each round to obtain operation data;
[0011] performing CRC operation on the operation data to obtain CRC check code.
[0012] Compared with the prior art, the flash memory checking method based on CRC check code provided by the application receives a checking instruction; based on the checking instruction, the flash memory checking method based on CRC check code reads the to-be-checked data from the CRC operation memory range of the flash memory in multiple rounds; the flash memory is a flash memory with bit width higher than a preset value; the to-be-checked data read in each round is compressed to obtain operation data; and the operation data is subjected to CRC operation to obtain the CRC check code. The high flash memory with bit width higher than the preset value is used to store data, the to-be-checked data is read from the CRC operation memory range of the flash memory in multiple rounds, the to-be-checked data read in each round is compressed before CRC operation, the operation logic is reduced, and the operation frequency is improved.
[0013] In a second aspect, the application provides a flash memory checking device based on CRC check code, which comprises:
[0014] a checking instruction receiving module configured to receive a checking instruction;
[0015] a to-be-checked data reading module configured to read to-be-checked data from the CRC operation memory range of the flash memory in multiple rounds based on the checking instruction; the flash memory is a flash memory with bit width higher than a preset value;
[0016] a to-be-checked data compression processing module configured to compress the to-be-checked data read in each round to obtain operation data;
[0017] a CRC operation module configured to perform CRC operation on the operation data to obtain the CRC check code.
[0018] In a third aspect, the application provides a flash memory checking equipment based on CRC check code, which comprises:
[0019] a communication unit / communication interface configured to receive a checking instruction;
[0020] a processing unit / processor configured to read to-be-checked data from the CRC operation memory range of the flash memory in multiple rounds based on the checking instruction; the flash memory is a flash memory with bit width higher than a preset value;
[0021] the to-be-checked data read in each round is compressed to obtain operation data;
[0022] the operation data is subjected to CRC operation to obtain the CRC check code.
[0023] In a fourth aspect, the application provides a computer storage medium, wherein the computer storage medium stores instructions, and when the instructions are executed, the flash memory checking method based on CRC check code is implemented.
[0024] The technical effects achieved by the device scheme provided in the second aspect, the equipment scheme provided in the third aspect, and the computer storage medium scheme provided in the fourth aspect are the same as those of the method scheme provided in the first aspect, and thus are not described herein. BRIEF DESCRIPTION OF DRAWINGS
[0025] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the principles of the application. In the drawings:
[0026] Figure 1 A flowchart of a flash memory verification method based on a CRC check code provided by the present application is shown in the figure.
[0027] Figure 2 A flowchart of reading to-be-verified data provided by the present application is shown in the figure.
[0028] Figure 3 A CRC operation schematic diagram provided by the present application is shown in the figure.
[0029] Figure 4 A structure schematic diagram of a flash memory verification device based on a CRC check code provided by the present application is shown in the figure.
[0030] Figure 5 A structure schematic diagram of a flash memory verification device based on a CRC check code provided by the present application is shown in the figure. DETAILED DESCRIPTION
[0031] In order to clearly describe the technical scheme of the embodiments of the present application, in the embodiments of the present application, the same items or similar items with basically the same functions and effects are distinguished by using the words “first”, “second”, etc. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit the order. Those skilled in the art can understand that the words “first”, “second”, etc. do not limit the number and execution order, and the words “first”, “second”, etc. also do not necessarily mean different.
[0032] It should be noted that the words “exemplary” or “for example” in the present application are used to represent an example, illustration or description. Any embodiment or design scheme described as “exemplary” or “for example” in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words “exemplary” or “for example” are intended to present the relevant concept in a specific manner.
[0033] In the present invention, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.
[0034] Prior art uses parallel computing to generate checksums more quickly, enabling processing of a set of data within a single clock cycle. However, as data width increases, or as circuits use memory, the area required for the checksum calculation circuit and its delay increase linearly. Using parallel CRC to calculate 4N-bit data requires approximately four times the circuit size and delay as calculating N-bit data.
[0035] Therefore, the present invention provides a flash memory verification method based on CRC check code to solve the problems in the prior art. Next, the solution provided by the embodiment of this specification is described in conjunction with the accompanying drawings:
[0036] like Figure 1 As shown, the process may include the following steps:
[0037] Step 110: Receive a verification instruction.
[0038] Step 120: Based on the verification instruction, read the data to be verified from the CRC calculation memory range of the flash memory in multiple rounds; the flash memory has a bit width higher than a preset value.
[0039] The CRC operation memory range can be a pre-set operation range, for example: from 0000H to the target address. CRC can read multiple sets of data from the flash memory in each clock cycle through the bus.
[0040] Specifically, taking the example of using a 128-bit flash to store 32-bit data, the expected calculation result needs to be saved in the last 4 bytes of the corresponding range of memory. Before starting the memory check, you need to set the memory range for the CRC calculation in advance.
[0041] After receiving the check instruction, the CPU stops working, and the CRC check module can read all data in the pre-set CRC operation memory range from address 0; the CRC expected values in different ranges are stored in the last 4 bytes of the corresponding CRC operation memory range.
[0042] Step 130: performing compression processing on the read data in each round to obtain operation data.
[0043] The compression processing can include splitting, shifting, and bitwise XOR operation and the like processing steps. In the implementation of step 130, the read data in each round can be split, shifted, and bitwise XOR operated to obtain a group of operation data with the same width as the polynomial.
[0044] Step 140: performing CRC operation on the operation data to obtain a CRC check code.
[0045] Figure 1 The method in the method, by receiving a check instruction; based on the check instruction, read the to-be-verified data from the CRC operation memory range of the flash memory in multiple rounds; the flash memory is a flash memory with a bit width higher than a preset value; performing compression processing on the read data in each round to obtain operation data; performing CRC operation on the operation data to obtain a CRC check code. The application adopts a high flash memory with a bit width higher than a preset value to store data, can read the to-be-verified data from the CRC operation memory range of the flash memory in multiple rounds, and performs compression processing on the read data in each round before performing the CRC operation, which can reduce the operation logic and improve the operation frequency.
[0046] Based on the method of Figure 1 , the embodiments of the present application also provide some specific implementations of the method, which are described below.
[0047] In step 120, after receiving the check instruction, data needs to be read from the memory with a high bit width, specifically, as shown in Figure 2 , taking the use of 128-bit flash memory to store 32-bit data as an example, after receiving the check instruction, the CPU stops working, and the CRC reads 128-bit data from the flash memory through the bus every clock cycle for operation. The data address is from 0000H to the target address, and the address bit is incremented by 1 every time. The operation range includes all data in the range from 0000H to the target address. The last 4 bytes of the last group of data store the expected operation result, which does not participate in the operation, and the corresponding data bits are filled with 0. After the operation is completed, the operation result is compared, and if they are the same, the process is normally ended, otherwise, the process is abnormally ended.
[0048] The overall CRC check code determination process of the technical solution provided by the application can be seen from Figure 3 for description: Figure 2After the flow execution in the above-mentioned process is completed, taking the CRC-16-CCITT polynomial as an example: the 128-bit data taken out in the first round can be divided into 8 groups of data, which are D0[15:0], D1[15:0], D2[15:0], D3[15:0], D4[15:0], D5[15:0], D6[15:0] and D7[15:0] respectively.
[0049] The above-mentioned data groups are shifted, and the shifting process is as follows:
[0050] DS1[15:0] = {D1[14:0], D1
[15] };
[0051] DS2[15:0] = {D1[13:0], D1[15:14]};
[0052] DS3[15:0] = {D1[12:0], D1[15:13]};
[0053] DS4[15:0] = {D1[11:0], D1[15:12]};
[0054] DS5[15:0] = {D1[10:0], D1[15:11]};
[0055] DS6[15:0] = {D1[9:0], D1[15:10]};
[0056] DS7[15:0] = {D1[8:0], D1[15:9]}.
[0057] According to equation (1):
[0058] E[i] = D0[i] + D1[i] + D2[i] + D3[i] + D4[i] + D5[i] + D6[i] + D7[i] + DS1[i] + DS2[i] + DS3[i] + DS4[i] + DS5[i] + DS6[i] + DS7[i] (i ∈ [31, 0]) (1)
[0059] The pre-processed 16-bit data E[15:0] can be obtained.
[0060] The E[15:0] is further processed as the operation object of the CRC to obtain the CRC check code F[15:0].
[0061] In the verification process, the data read in each round of verification needs to be simply compressed, and the specific steps include:
[0062] The to-be-verified data of multiple addresses read in each round are divided into multiple groups of data with equal bit width;
[0063] The multiple groups of data are subjected to shift processing to obtain shifted data;
[0064] The same bits of the multiple groups of data before shifting and the same bits of the shifted data are subjected to bit-wise XOR processing to complete bit compression and obtain operation data.
[0065] The compression processing process is described by taking the read 128-bit data as an example:
[0066] First, the 128-bit data is divided into 8 groups of 16-bit data (D0-D7) of equal bit width;
[0067] Next, the 8 groups of data are subjected to 1-8-bit shift processing respectively to obtain 8 groups of 16-bit data (DS0-DS7) after shifting;
[0068] Finally, the same bits of the 16 groups of 16-bit data before and after shifting are subjected to XOR processing to obtain the bit-compressed CRC check data (E).
[0069] For example: E[0] = D0[0] + D1[0] + D2[0] + D3[0] + D4[0] + D5[0] + D6[0] + D7[0] + DS1[0] + DS2[0] + DS3[0] + DS4[0] + DS5[0] + DS6[0] + DS7[0].
[0070] The widths of D, E, F and G in the above processing process depend on the width of the CRC polynomial used. When CRC-32 is used, the extracted data is divided into one or more groups of 32-bit data for subsequent operation process.
[0071] In the above steps, the data shifting can avoid the defect that the flipped data after splitting occurs at the same position, so that the data error is not reflected on the parity check code. For example, D1[0] and D2[0] are flipped at the same time, and the value of E[0] does not change. Through shifting, the error can be reflected in E[1], E[2].
[0072] Optionally, the CRC operation on the operation data can include:
[0073] The operation data obtained by compressing the multiple rounds of read check data is subjected to bit-wise XOR processing with the CRC check code result of the previous round to obtain the CRC check code;
[0074] The CRC check code of the last round is the final CRC check code of the current set range data.
[0075] More specifically, for the data taken out in the nth round (n≥2), the pre-processing obtains E(n) [15:0]. It is required to perform bitwise XOR with the check code result of the last round and then perform the CRC operation. That is, first calculate G(n)=E(n)^F(n-1), and then take G(n) as the operation object of the CRC operation to obtain the CRC check code F(n). The calculation result of the last round is the final check code.
[0076] The technical solution provided by the application can store data by using a flash memory with a high bit width, can read and process multiple groups of data in one clock cycle, for example, store 32-bit data by using a 128-bit flash memory. However, the logic required for processing 128-bit data in parallel is large, which limits the clock frequency. Therefore, before performing the CRC operation on the data, the data bit width is compressed by using the parity coding mode. The operation logic can be reduced, and the operation frequency can be improved.
[0077] Based on the same idea, the application further provides a flash memory check device based on a CRC check code, as shown in Figure 4 The device can include the following components:
[0078] The check instruction receiving module 410 is configured to receive a check instruction.
[0079] The to-be-checked data reading module 420 is configured to read to-be-checked data from a CRC operation memory range of a flash memory based on the check instruction; the flash memory is a flash memory with a bit width higher than a preset value.
[0080] The to-be-checked data compression processing module 430 is configured to compress the to-be-checked data read in each round to obtain operation data.
[0081] The CRC operation module 440 is configured to perform a CRC operation on the operation data to obtain a CRC check code.
[0082] Based on the device in Figure 4 The device can further include some specific implementation units:
[0083] Optionally, the to-be-checked data reading module 420 can include the following components:
[0084] The data reading unit is configured to stop the CPU from working after receiving the check instruction, and read all data in a preset CRC operation memory range from address 0 by the CRC check module; the CRC expected value in different ranges is saved in the last 4 bytes of the corresponding CRC operation memory range.
[0085] Optionally, the to-be-checked data compression processing module 430 can include the following components:
[0086] The compression processing unit is configured to split, shift and perform bitwise XOR operation on the to-be-verified data of the plurality of addresses obtained through each round of reading, to obtain a group of operation data with the same width as the polynomial.
[0087] Optionally, the CRC operation module 440 can specifically include:
[0088] The CRC operation unit is configured to perform bitwise XOR operation on the operation data obtained through compression processing of the to-be-verified data read through a plurality of rounds, and the CRC check code result of the previous round, to obtain a CRC check code.
[0089] The final CRC check code determination unit is configured to take the CRC check code of the last round as the final CRC check code of the current set range data.
[0090] Optionally, the data reading unit can be specifically configured to:
[0091] The CRC check module reads data from the flash memory through a bus for operation in each clock cycle;
[0092] The address of the read data is from 0000H to the target address, and the address bit is incremented by 1 each time; the CRC operation memory range includes all data in the range from 0000H to the target address; the last group of data stores the expected operation result in the last 4 bytes, and does not participate in the operation, and the corresponding data bit is filled with 0.
[0093] Optionally, the compression processing unit can be specifically configured to:
[0094] Split the to-be-verified data of the plurality of addresses obtained through each round of reading into a plurality of groups of data with the same bit width;
[0095] Shift the plurality of groups of data to obtain shifted data;
[0096] Perform bitwise XOR operation on the same bits of the plurality of groups of data before shifting and the same bits of the shifted data to complete bit compression, to obtain operation data.
[0097] Optionally, the shifted data is flipped at different positions, and data errors are reflected on the parity check code.
[0098] Based on the same idea, the present specification also provides a flash memory verification device based on a CRC check code. As shown in FIG. Figure 5 The device can include:
[0099] The communication unit / communication interface is configured to receive a verification instruction;
[0100] The processing unit / processor is configured to read to-be-verified data from a CRC operation memory range of a flash memory based on the verification instruction; the flash memory is a flash memory with a bit width higher than a preset value.
[0101] The read data to be verified in each round is compressed to obtain operation data;
[0102] The operation data is subjected to a CRC operation to obtain a CRC check code.
[0103] As shown in Figure 5 , the terminal device can further include a communication line. The communication line can include a path for transmitting information between the components.
[0104] Optionally, as shown in Figure 5 , the terminal device can further include a memory. The memory is used to store computer execution instructions for executing the scheme of the present application, and is controlled by the processor to execute. The processor is used to execute the computer execution instructions stored in the memory, so as to realize the method provided by the embodiment of the present application.
[0105] In a specific implementation, as an embodiment, as shown in Figure 5 , the processor can include one or more CPUs, such as CPU0 and CPU1 in Figure 5 .
[0106] In a specific implementation, as an embodiment, as shown in Figure 5 , the terminal device can include a plurality of processors, such as the processors in Figure 5 . Each of the processors can be a single-core processor or a multi-core processor.
[0107] Based on the same idea, the embodiments of the present application also provide a computer storage medium corresponding to the above-mentioned embodiments, and the computer storage medium stores instructions, and when the instructions are executed, the method in the above-mentioned embodiments is realized.
[0108] The above mainly introduces the scheme provided by the embodiments of the present application from the perspective of the interaction between the modules. It can be understood that each module contains a hardware structure and / or software unit for executing the corresponding functions in order to realize the above functions. Those skilled in the art should easily realize that the units and algorithm steps of each example described in connection with the embodiments disclosed in the present application can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in hardware or computer software driven hardware depends on the specific application and design constraints of the technical scheme. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.
[0109] The functions of the modules in the embodiments of the present application can be divided according to the above method examples. For example, each function module can be divided according to each function, or two or more functions can be integrated into one processing module. The integrated module can be implemented in the form of hardware or in the form of a software function module. It should be noted that the division of the modules in the embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, another division mode can be used.
[0110] The processor in the specification can also have the function of a memory. The memory is used to store computer execution instructions for executing the scheme of the present application, and is controlled by the processor to execute. The processor is used to execute the computer execution instructions stored in the memory, so as to realize the method provided by the embodiments of the present application.
[0111] The memory can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, an optical disk storage (including a compact disk, a laser disk, an optical disk, a digital versatile disk, a Blu-ray disk, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer, but is not limited to this. The memory can exist independently and be connected to the processor through a communication line. The memory can also be integrated with the processor.
[0112] Optionally, the computer execution instructions in the embodiments of the present application can also be referred to as application program codes, which are not specifically limited in the embodiments of the present application.
[0113] Although the present application is described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art with reference to the attached drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. Some measures described in mutually different dependent claims can be combined and produce a good result.
[0114] While the application has been described in connection with specific features thereof, it will be evident that many modifications and variations of the application are possible, and will be evident to those of ordinary skill in the art. Accordingly, it is intended that all such modifications and variations be considered as within the spirit and scope of the application. Other combinations are also possible. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. It will be apparent to those skilled in the art that various modifications and variations can be made to the method of the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application include modifications and variations of the application caused by amateurs in the art during the production of the application claims and their equivalent technologies within the scope of the present application.
Claims
1. A CRC check code based flash memory checking method, characterized in that, The method comprises: receiving a check instruction; based on the check instruction, reading the to-be-checked data from the CRC operation memory range of the flash memory in multiple rounds; the flash memory is a flash memory with a bit width higher than a preset value; performing compression processing on the to-be-checked data read in each round to obtain operation data; performing CRC operation on the operation data to obtain a CRC check code.
2. The CRC check code based flash memory checking method of claim 1, wherein, Specifically, based on the check instruction, the to-be-checked data is read from the CRC operation memory range of the flash memory in multiple rounds, which comprises: after receiving the check instruction, the CPU stops working, and the CRC check module reads all data in the pre-set CRC operation memory range from address 0; the CRC expected value of different ranges is saved in the last 4 bytes of the corresponding CRC operation memory range.
3. The CRC check code based flash memory checking method of claim 1, wherein, Specifically, the to-be-checked data read in each round is compressed to obtain operation data, which comprises: splitting, shifting and performing bitwise XOR operation on the to-be-checked data of multiple addresses obtained in each round to obtain a group of operation data with the same width as the polynomial.
4. The CRC check code based flash memory checking method of claim 3, wherein, Specifically, the CRC operation is performed on the operation data to obtain a CRC check code, which comprises: performing bitwise XOR processing on the operation data obtained by performing compression processing on the to-be-checked data read in multiple rounds and the CRC check code result of the previous round to obtain a CRC check code; the CRC check code of the last round is the final CRC check code of the current set range data.
5. The CRC check code based flash memory checking method of claim 2, wherein, Specifically, the CRC check module reads all data in the pre-set CRC operation memory range from address 0, which comprises: the CRC check module reads data from the flash memory in each clock cycle through the bus for operation; the address of the read data is from 0000H to the target address, and the address bit is incremented by 1 each time; the CRC operation memory range contains all data in the range from 0000H to the target address; the last group of data stores the expected operation result in the last 4 bytes, which does not participate in the operation, and the corresponding data bit is filled with 0.
6. The CRC check code based flash memory checking method of claim 3, wherein, Specifically, the to-be-checked data of multiple addresses obtained in each round is split, shifted and subjected to bitwise XOR operation to obtain a group of operation data with the same width as the polynomial, which comprises: the to-be-checked data of multiple addresses obtained in each round is divided into multiple groups of data with the same bit width; performing shift processing on the multiple groups of data to obtain shifted data; performing bitwise XOR processing on the same bits of the multiple groups of data before shifting and the same bits of the shifted data to complete bit compression and obtain operation data.
7. The CRC check code based flash memory checking method of claim 3, wherein, The shifted data is flipped at different positions, and the data error is reflected on the parity check code.
8. A flash memory verification device based on CRC check code, characterized in that: The device comprises: a check instruction receiving module for receiving a check instruction; a to-be-checked data reading module for reading to-be-checked data from the CRC operation memory range of the flash memory in multiple rounds based on the check instruction; the flash memory is a flash memory with a bit width higher than a preset value; a to-be-checked data compression processing module for performing compression processing on the to-be-checked data read in each round to obtain operation data; a CRC operation module for performing CRC operation on the operation data to obtain a CRC check code.
9. A CRC check code based flash memory checking device, characterized in that the device It comprises: a communication unit / communication interface for receiving a check instruction; a processing unit / processor configured to read, based on the check instruction, to-be-checked data from a plurality of rounds in a CRC operation memory range of a flash memory, the flash memory being a flash memory with a bit width higher than a preset value; performing compression processing on the to-be-checked data read in each round to obtain operation data; performing CRC operation on the operation data to obtain a CRC check code.
10. A computer storage medium, characterized in that, The computer storage medium stores instructions, and when the instructions are executed, the CRC check code-based flash memory check method in any one of claims 1-7 is implemented.