Fault detection method and device for address bus

Abstract

The invention provides a fault detection method and device for an address bus, and belongs to the technical field of electronics. According to the scheme provided by the invention, the bit of the first address of the first register in the functional circuit can be negated to obtain the second address, and the fault of the first signal line in the address bus corresponding to the bit is determined according to the fact that the first data is the same as the second data. Wherein the first data is the data written into the storage position indicated by the first address, and the second data is the data read from the storage position indicated by the second address. On the basis, if the first data is the same as the second data, it is indicated that when the data in the storage position indicated by the second address is read, the data in the storage position indicated by the first address is actually read. Correspondingly, the fault of the first signal line in the address bus can be determined. According to the scheme provided by the invention, the signal line with the fault in the address bus can be detected, so that the fault detection precision is effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and particularly relates to a fault detection method and device of an address bus. BACKGROUND

[0002] In electronic devices such as routers and servers, a central processing unit (CPU) is connected with a programmable logic device through an address bus. In order to ensure reliability, the CPU needs to detect whether the address bus is faulty.

[0003] For fault detection of the address bus, two special readable and writable registers are configured as test registers in the programmable logic device, the same bits of the addresses of the two test registers correspond to opposite levels, and both are exclusive-NOR registers. During fault detection, the CPU can write the same detection data into the two test registers respectively, and then read the data from the two test registers respectively, and perform XOR comparison on the read data. If the result of the XOR comparison is all 0, it can be determined that the address bus is not faulty; if the result of the XOR comparison is not all 0, it can be determined that the address bus is faulty.

[0004] However, since the address bus includes multiple signal lines, the above method can only detect whether the address bus is faulty, and cannot detect the fault of a specific signal line, so the precision of fault detection is low. SUMMARY

[0005] The present application provides a fault detection method and device of an address bus, which can solve the technical problem of low precision of fault detection of the address bus.

[0006] In a first aspect, a fault detection method of an address bus is provided, the address bus being used to connect a control circuit and a functional circuit, the functional circuit including a first register, and an address of the first register being a first address. The method includes: determining a second address according to the first address, and determining that a first signal line is faulty according to first data being the same as second data. The second address is obtained by performing exclusive-NOR on a bit in the first address, the bit corresponding to a first signal line in the address bus. The first data is data written into a storage location indicated by the first address, and the second data is data read from a storage location indicated by the second address.

[0007] Based on the above fault detection method, if the first data is the same as the second data, it indicates that when reading the data in the storage location indicated by the second address, the data in the storage location indicated by the first address is actually read. Correspondingly, it can be determined that the first signal line in the address bus is faulty. Since this method can detect the faulty signal line in the address bus, the accuracy of fault detection is effectively improved.

[0008] Alternatively, according to the first data being the same as the second data, the process of determining the fault of the first signal line can include: writing third data to the storage location indicated by the first address according to the first data being the same as the second data, the third data being different from the first data; and determining the fault of the first signal line according to the third data being the same as the fourth data. The fourth data is the data read from the storage location indicated by the second address after the third data is written.

[0009] It can be understood that if the data stored in the storage location indicated by the second address happens to be the first data, determining the fault of the first signal line according to the first data being the same as the second data may have a certain probability of false detection. By writing third data different from the first data to the storage location indicated by the first address, and reading data from the storage location indicated by the second address again and comparing it with the third data, false detection can be effectively avoided, ensuring the accuracy and reliability of fault detection.

[0010] Alternatively, the functional circuit can further include a second register, the address of the second register being a third address, the third address being different from the first address. The method can further include: determining a fourth address according to the third address, the fourth address being obtained by inverting the bit in the third address corresponding to the first signal line; and determining the fault of the first signal line according to the fifth data being the same as the sixth data. The fifth data is the data written to the storage location indicated by the third address, and the sixth data is the data read from the storage location indicated by the fourth address.

[0011] By configuring two registers with different addresses in the functional circuit, and performing fault detection based on the two registers respectively, the accuracy and reliability of fault detection can be effectively improved. For example, based on the first register, the faults of part of the signal lines in the address bus can be detected, and based on the second register, the faults of another part of the signal lines in the address bus can be detected, thereby ensuring that each signal line in the address bus can be accurately detected.

[0012] Optionally, the process of determining the first signal line fault according to the fifth data being the same as the sixth data can include: writing seventh data to the storage location indicated by the third address according to the fifth data being the same as the sixth data, the seventh data being different from the fifth data; and determining the first signal line fault according to the seventh data being the same as eighth data, the eighth data being data read from the storage location indicated by the fourth address after the seventh data is written.

[0013] It can be understood that if the data stored in the storage location indicated by the fourth address is exactly the fifth data, determining the first signal line fault according to the fifth data being the same as the sixth data can have a certain probability of false detection. By writing the seventh data different from the fifth data to the storage location indicated by the third address, and reading the data from the storage location indicated by the fourth address again and comparing with the seventh data, false detection can be effectively avoided, and the accuracy and reliability of fault detection can be ensured.

[0014] Optionally, the process of determining the first signal line fault can include: if the bit in the third address is 0, determining that the first signal line has a constant 0 fault; and if the bit in the third address is 1, determining that the first signal line has a constant 1 fault.

[0015] If the fourth address is obtained by performing an exclusive-OR operation on the bit in the third address: 0, the corresponding bit in the fourth address is 1. Correspondingly, if the fourth address is accessed by mistake to access the third address, resulting in the fifth data being the same as the sixth data, it can be determined that the first signal line corresponding to the bit in the third address has a constant 0 fault, that is, the first signal line cannot be set to 1, and thus the fourth address cannot be normally accessed. If the fourth address is obtained by performing an exclusive-OR operation on the bit in the third address: 1, the corresponding bit in the fourth address is 0. Correspondingly, if the fourth address is accessed by mistake to access the third address, resulting in the fifth data being the same as the sixth data, it can be determined that the first signal line corresponding to the bit in the third address has a constant 1 fault, that is, the first signal line cannot be set to 0, and thus the fourth address cannot be normally accessed.

[0016] Optionally, the value of each bit in the third address is opposite to the value of the corresponding bit in the first address. That is, the third address and the first address have a bitwise exclusive-OR relationship. For example, one of the first address and the third address can be all 0, and the other can be all 1. In this way, accurate fault detection can be ensured for each signal line in the address bus.

[0017] Optionally, the process of determining the first signal line fault can include: if the bit in the first address is 0, determining that the first signal line has a constant 0 fault; and if the bit in the first address is 1, determining that the first signal line has a constant 1 fault.

[0018] If the second address is obtained by performing the NOT operation on the bit: 0 in the first address, the corresponding bit in the second address is 1. Correspondingly, if the first data is the same as the second data when the second address is accessed by mistake to access the first address, it can be determined that the first signal line corresponding to the bit in the first address has a constant 0 fault, that is, the first signal line cannot be set to 1, so that the second address cannot be normally accessed. If the second address is obtained by performing the NOT operation on the bit: 1 in the first address, the corresponding bit in the second address is 0. Correspondingly, if the first data is the same as the second data when the second address is accessed by mistake to access the first address, it can be determined that the first signal line corresponding to the bit in the first address has a constant 1 fault, that is, the first signal line cannot be set to 0, so that the second address cannot be normally accessed.

[0019] Optionally, the functional circuit can be a programmable logic device or an application specific integrated circuit (ASIC). The programmable logic chip can be a complex programmable logic device (CPLD), a field programmable gate array (FPGA), or a generic array logic (GAL), etc.

[0020] Optionally, the register included in the functional circuit is a register with the same write value and read value; or the register included in the functional circuit is a NOT register; or the register included in the functional circuit for fault detection can be a register with a preset mapping relationship between the write value and the read value. The scheme provided in the present application does not limit the type of the register (i.e., the first register and the second register) for fault detection in the functional circuit, and only needs to ensure that the addresses of the two registers are different. Thus, the performance requirement for the functional circuit is effectively reduced, thereby improving the application flexibility of the fault detection method.

[0021] In a second aspect, a fault detection device for an address bus is provided, which can include at least one module for implementing the fault detection method for the address bus provided in the above aspect.

[0022] In a third aspect, a control chip is provided, which can include a programmable logic circuit and / or program instructions, and the control chip executes the fault detection method for the address bus provided in the above aspect when running. Optionally, the control chip can be a CPU.

[0023] In a fourth aspect, a computer readable storage medium is provided, which stores instructions for implementing the address bus fault detection method according to any one of the preceding aspects.

[0024] In a fifth aspect, a computer program product is provided, which contains instructions for causing a processor to implement the address bus fault detection method according to any one of the preceding aspects.

[0025] In a sixth aspect, an electronic device is provided, which comprises a control circuit and a functional circuit, wherein the control circuit is connected to the functional circuit through an address bus, and the control circuit is configured to implement the address bus fault detection method according to any one of the preceding aspects.

[0026] The electronic device can be a server, a router, a switch or the like.

[0027] In summary, the present application provides an address bus fault detection method and device. The scheme provided by the present application can invert the bit of the first address of the first register in the functional circuit to obtain a second address, and determine that the first signal line in the address bus corresponding to the bit is faulty according to the same first data and second data. The first data is the data written into the storage location indicated by the first address, and the second data is the data read from the storage location indicated by the second address. Based on this, if the first data and the second data are the same, it indicates that when reading the data in the storage location indicated by the second address, the data in the storage location indicated by the first address is actually read. Accordingly, it can be determined that the first signal line in the address bus is faulty. Since the scheme provided by the present application can detect the faulty signal line in the address bus, the accuracy of fault detection is effectively improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0029] Figure 2 is a structural schematic diagram of another electronic device provided by an embodiment of the present application;

[0030] Figure 3 is a flowchart of an address bus fault detection method provided by an embodiment of the present application;

[0031] Figure 4 is a flowchart of another address bus fault detection method provided by an embodiment of the present application;

[0032] Figure 5 is a flowchart of still another address bus fault detection method provided by an embodiment of the present application;

[0033] Figure 6 is a flow chart of another address bus fault detection method provided by an embodiment of the present application;

[0034] Figure 7 is a flow chart of another address bus fault detection method provided by an embodiment of the present application;

[0035] Figure 8 is a structural schematic diagram of an address bus fault detection device provided by an embodiment of the present application;

[0036] Figure 9 is a structural schematic diagram of another electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0037] The address bus fault detection method and device provided by an embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0038] Medical, aviation and automotive fields have increasingly high requirements for the reliability of electronic devices, which requires electronic devices to have the function of automatically diagnosing faults. Referring to Figure 1 , an electronic device (such as a server or a switching device) generally includes a control circuit and a functional circuit. As shown in Figure 2 , the control circuit can be a CPU, a network processing unit (NPU) or a data processing unit (DPU), etc. The functional circuit can be a memory or a non-memory device. For example, referring to Figure 2 , the non-memory device can include a programmable logic chip and / or an ASIC chip, etc. The programmable logic chip can include a CPLD, an FPGA and / or a GAL, etc.

[0039] As shown in Figure 1 and Figure 2 , the bus between the control circuit and the functional circuit generally includes a control bus, an address bus and a data bus. To ensure the reliability of the electronic device, the control circuit needs to be able to accurately detect the faults of the three types of buses. For the control bus and the data bus, the comparison between the written data and the read data can be used to determine whether the data bus and the control bus have faults.

[0040] For the address bus, if the functional circuit is a memory, the control circuit can use a walk algorithm (also known as a three-step method) to detect whether the address bus has a fault. The walk algorithm requires the control circuit to write test data to multiple different addresses of the memory, then read data from each address, and compare the written data with the read data to detect whether the address bus has a fault.

[0041] For the scenario that the functional circuit is a non-memory device, the above walk algorithm is not applicable for detection, because the walk algorithm needs to perform write operation on many addresses (i.e. registers) in the functional circuit during detection. For the non-memory device, the internal registers can be read-only registers, undefined registers, or registers that will be abnormal when writing specific values, etc. If the registers detected by the walk algorithm contain such registers, the write operation cannot be implemented, and the above detection effect cannot be achieved.

[0042] In some embodiments, two special test registers can be configured in the functional circuit, which satisfy the following conditions:

[0043] 1. The same bit of the binary address of the two test registers corresponds to opposite levels. For example, assuming that the address of the first test register is 0x5555, the address of the second test register is 0xaaaa. Wherein, 0x represents hexadecimal, 0x5555 is converted to binary as 01010101 0101 0101, and 0xaaaa is converted to binary as 1010 1010 1010 1010.

[0044] 2. Both test registers are NOT registers, that is, the same bit of the write value and the read value corresponds to opposite levels. For example, write the value 0x5555 to the first test register, when reading the value from the first test register, the functional circuit can perform bitwise NOT operation on all bits of the value, and output the value 0xaaaa to the control circuit.

[0045] When detecting the fault of the address bus, the control circuit can write test data (such as 0x55aa) to the first test register, and then read the data in the first test register to obtain the first reference data. And the control circuit can write the same test data (such as 0x55aa) to the second test register, and read the data in the second test register to obtain the second reference data. Then, the control circuit can perform XOR comparison on the first reference data and the second reference data. If the result of the XOR comparison is all 0, it can be determined that the address bus is not faulty; if the result of the XOR comparison is not all 0, it can be determined that the address bus has a fault.

[0046] Suppose the address bus includes 8 signal lines A0 to A7, and the addresses of the two test registers are 0x00 and 0xff respectively. Since the control circuit writes the same test data 0x55aa to both test registers, it is expected that the data read from the two test registers are both the inverted data 0xaa55. However, if the signal line A0 in the address bus has a short-to-ground fault, the level of the signal line A0 is always low. Accordingly, when the control circuit writes the test data 0x55aa to the test register with the address 0xff (binary 1111 1111), the test data 0x55aa will be wrongly written to the register with the address 0xfe (binary 1111 1110) in the functional circuit. Since the register with the address 0xfe is not an inversion register, the data read from the register by the control circuit is not the inverted data 0xaa55, but the non-inverted test data 0x55aa. When the control circuit writes the test data 0x55aa to the test register with the address 0x00, since the levels of all signal lines in the address bus are always low, the control circuit can correctly write the test data 0x55aa to the test register with the address 0x00. Accordingly, the data read from the test register by the control circuit is the inverted data 0xaa55.

[0047] Based on the above analysis, the control circuit reads two reference data from the two test registers, one reference data is 0x55aa, and the other reference data is 0xaa55. The result of the XOR comparison of the two reference data is all 1, indicating that the address bus has a fault.

[0048] However, the above method can only detect whether the address bus has a fault, but cannot accurately detect a specific signal line in the address bus that has a fault. The detection accuracy of the detection method is low. Moreover, the above method requires the functional circuit to provide test registers with opposite levels corresponding to the same bit of the address, and the two test registers need to be inversion registers, thereby increasing the performance requirements for the functional circuit and reducing the application flexibility. In addition, the above method also has a low probability of failing to detect a fault. For example, when the control circuit accesses the test registers in the functional circuit after the address bus has a fault, it may access an incorrect address. If the register corresponding to the incorrect address is also an inversion register, the control circuit will not be able to detect the fault of the address bus.

[0049] Embodiments of the present application provide a fault detection method for an address bus, which can be applied to scenarios such as those shown in FIGS. 1 to 3, and the method can accurately detect a signal line in the address bus that has a fault. Figure 1 or Figure 2 As shown in FIGS. 4 to 6, the method can accurately detect a signal line in the address bus that has a fault. Figure 1 and Figure 2As shown, the address bus can be used to connect the control circuit and the functional circuit. The functional circuit includes a first register, and the first register has a first address. The fault detection method can be performed by the control circuit. For reference Figure 3 The method comprises:

[0050] Step 101: determining a second address according to the first address.

[0051] In the embodiment of the present application, the first register can be a register in the functional circuit that is specially used for fault detection of the address bus, and the first register can be a readable and writable register. The second address is obtained by inverting a bit in the first address of the first register, and the bit corresponds to a first signal line in the address bus, that is, the second address corresponds to the first signal line.

[0052] It can be understood that the first address of the first register can include a plurality of bits, and the second address can be obtained by inverting one bit (which can be any bit) of the plurality of bits. If a bit in the first address is 0, the value after inversion is 1; if a bit in the first address is 1, the value after inversion is 0. It can also be understood that the values of the other bits in the second address are the same as the values of the corresponding bits in the first address.

[0053] For example, assuming that the address bus includes A0 to A N N+1 signal lines, the first address of the first register can be a binary number of N+1 bits, and the first address A can be represented as {a N ,a N-1 ,…,a1,a0}, N is an integer greater than or equal to 0. Each of a0 to a N is a binary number of 1 bit. The N+1-bit binary number in the first address A corresponds to the N+1 signal lines in the address bus one by one. For example, the bit a i in the first address A can correspond to the i-th signal line A i in the address bus, i is an integer greater than or equal to 0 and not greater than N. Assuming that the second address is obtained by inverting the bit a i in the first address A, the first signal line can be the i-th signal line A i in the address bus.

[0054] Step 102: determining that the first signal line in the address bus is faulty according to the first data and the second data being the same.

[0055] The first data is data written to the storage location indicated by the first address, that is, the first data can be data written to the first register. For example, the control circuit can write the first data to the storage location indicated by the first address before starting the fault detection on the address bus. Alternatively, the first data can also be data previously written to the storage location indicated by the first address, that is, the first data can also be data previously stored in the first register.

[0056] The second data is data read from the storage location indicated by the second address. In the embodiment of the present application, the control circuit can read data from the storage location indicated by the second address after determining the second address according to the first address. If the second data read by the control circuit is different from the first data, it can be determined that the first signal line is not faulty. If the second data read by the control circuit is the same as the first data, it can be determined that the first signal line is faulty.

[0057] It can be understood that if the second data read from the storage location indicated by the second address is the same as the first data, it indicates that the control circuit actually reads the first data in the storage location indicated by the first address when reading data in the storage location indicated by the second address. That is, the control circuit actually accesses the first address when accessing the second address through the address bus. Thus, it can be determined that the first signal line corresponding to the second address is faulty, causing the control circuit to incorrectly access the first address when accessing the second address.

[0058] Optionally, in the embodiment of the present application, the control circuit can determine N+1 first test addresses different from each other according to the first address, and each first test address is obtained by inverting a bit in the first address. For example, the i th first test address in the N+1 first test addresses is obtained by inverting the i th bit a i in the first address, and the i th bit a i in the i th first test address corresponds to the i th signal line in the address bus. Thus, it can be known that the i th bit in the i th first test address is the inverted value of the i th bit a i in the first address, and other bits in the i th first test address are the same as the corresponding bits in the first address. For example, if the i th bit a i in the first address is 0, the inverted value is 1; if the i th bit a i in the first address is 1, the inverted value is 0. For example, referring to Figure 4 , the N+1 first test addresses can be represented as follows:

[0059] The first test address Addr0={a N , aN-1 ,…,a1,~a0}, corresponding to signal line A0;

[0060] The first test address Addr1 = {a N ,a N-1 ,…,~a1,a0}, corresponding to signal line A1;

[0061] …

[0062] The first test address Addri = {a N ,a N-1 ,…,~a i ,…,a1,a0}, corresponding to signal line A i ;

[0063] …

[0064] The first test address AddrN-1={a N ,~a N-1 ,…,a1,a0}, corresponding to signal line A N-1 ;

[0065] The first test address AddrN = {~a N ,~a N-1 ,…,a1,a0}, corresponding to signal line A N .

[0066] The ~a in the first test address above i Indicates bit a i The second address in steps 101 and 102 may be any one of the N+1 first test addresses, and this is not limited in the present embodiment. Optionally, the registers corresponding to the N+1 first test addresses may all be read-only registers. Since there is no need for the functional circuit to have multiple readable and writable registers, the performance requirements for the functional circuit are effectively reduced, thereby effectively improving the flexibility of the fault detection method.

[0067] In the embodiments of this application, Figure 4 As shown, the control circuit can first send a first address A={a N ,a N-1 ,…,a1,a0}, i.e., writing the first data D1 to the first register. The control circuit can then read data from each of the N+1 first test addresses. If the data read from any first test address differs from the first data D1, it can be determined that the signal line corresponding to the first test address is not faulty. If the data read from any first test address is the same as the first data D1, it can be determined that the signal line corresponding to the first test address is faulty.

[0068] For example, assume that the control circuit reads the same data D1 from the i-th first test address Addri = {a N , a N-1 , …, ~a i , a1, a0} as the first data D1, then since the i-th first test address Addri is obtained by inverting the i-th bit a i in the first address, the control circuit can determine that the i-th signal line in the address bus is faulty.

[0069] For example, if the i-th bit a i in the first address is 0 and the i-th signal line A i has a constant 0 fault (i.e., the signal line A i is shorted to ground), then when the control circuit accesses the i-th first test address Addri, the i-th signal line A i cannot be set to 1, so the control circuit will access the first address incorrectly, resulting in the second data read being the same as the first data D1. If the i-th bit a i in the first address is 1 and the i-th signal line A i has a constant 1 fault (i.e., the signal line A i is shorted to power), then when the control circuit accesses the i-th first test address Addri, the i-th signal line A i cannot be set to 0, so the control circuit will access the first address incorrectly, resulting in the second data read being the same as the first data D1.

[0070] Alternatively, in embodiments of the present application, to ensure the reliability of the fault detection, in step 102, if the control circuit detects that the first data and the second data are the same, the control circuit can also write third data that is different from the first data to the storage location indicated by the first address. That is, the control circuit can re-write third data to the first register, the third data being able to overwrite the first data. Then, the control circuit can determine that the first signal line is faulty according to the third data and the fourth data being the same.

[0071] The fourth data is data read from the storage location indicated by the second address after the third data is written. That is, the control circuit can read the data in the storage location indicated by the second address again after writing the third data to the storage location indicated by the first address. If the fourth data read is the same as the third data, it can be determined that the first signal line is faulty.

[0072] It can be understood that the data stored in the storage location indicated by the second address may be exactly the first data. That is, when the control circuit detects whether the first signal line is faulty by comparing whether the first data and the second data are the same, there is a certain probability of false detection. In order to avoid false detection, the control circuit can re-write the third data to the storage location indicated by the first address, and continue to read data from the storage location indicated by the second address. If the fourth data read is still the same as the third data, that is, the data read by the control circuit from the storage location indicated by the second address changes with the data written to the storage location indicated by the first address, the control circuit can determine that the first signal line is faulty.

[0073] Reference Figure 4 The fault detection process of the control circuit on the address bus can include the following steps:

[0074] Step S11, the control circuit calculates N+1 first test addresses: Addr0 to AddrN based on the first address of the first register.

[0075] Step S12, the control circuit writes the first data D1 to the storage location indicated by the first address A={a N ,a N-1 ,…,a1,a0} (i.e. the first register).

[0076] Step S13, the control circuit reads the value of the storage location indicated by each first test address and compares it with the first data D1 respectively.

[0077] For example, the control circuit reads the value of the storage location indicated by the 0th first test address Addr0 and compares it with the first data D1. If they are not the same, it can be determined that the signal line A0 in the address bus is not faulty; if they are the same, the detection of step S14 is continued.

[0078] The control circuit reads the value of the storage location indicated by the 1st first test address Addr1 and compares it with the first data D1. If they are not the same, it can be determined that the signal line A1 in the address bus is not faulty; if they are the same, the detection of step S14 is continued.

[0079] …

[0080] The control circuit reads the value of the storage location indicated by the N-1th first test address AddrN-1 and compares it with the first data D1. If they are not the same, it can be determined that the signal line A N-1 in the address bus is not faulty; if they are the same, the detection of step S14 is continued.

[0081] The control circuit reads the value of the storage location indicated by the Nth first test address AddrN, and compares it with the first data D1. If they are not the same, it can be determined that the signal line A N fault-free; if they are the same, the detection of step S14 continues.

[0082] In step S14, the control circuit writes third data D2 into the storage location indicated by the first address A={a N ,a N-1 ,…,a1,a0}. The third data D2 is different from the first data D1.

[0083] In step S15, the control circuit reads the value of the storage location indicated by the first test address, and compares it with the third data D2. If they are not the same, it is determined that the corresponding signal line is fault-free; if they are the same, it is determined that the corresponding signal line is faulty.

[0084] After writing the third data D2, the control circuit can read the data from the storage location indicated by the first test address again, and compare it with the third data D2. As a possible example, the control circuit can read the data from the storage location indicated by each first test address, and compare it with the third data D2.

[0085] As another possible example, the control circuit can only read the value of the storage location indicated by the target test address, and compare it with the third data D2. The target test address can be the first test address whose read value is the same as the first data D1 in the above step S13. That is, the target test address is the first test address corresponding to the suspected faulty signal line. In step S15, the control circuit can only read the data from the first test address corresponding to the suspected faulty signal line, without reading the data from each first test address, thereby effectively improving the efficiency of fault detection.

[0086] Optionally, in the above step 102, the control circuit can also determine the fault type of the first signal line based on the value of the bit in the first address. The fault type can include: constant 0 fault and constant 1 fault. The constant 0 fault can be caused by a short circuit between the signal line and the ground, and the constant 1 fault can be caused by a short circuit between the signal line and the power supply.

[0087] In the embodiments of the present application, if the bit in the first address is 0, i.e., the second address is obtained by inverting the bit: 0, the control circuit can determine that the first signal line has a constant 0 fault; if the bit in the first address is 1, i.e., the second address is obtained by inverting the bit: 1, the control circuit can determine that the first signal line has a constant 1 fault.

[0088] For a scenario where the control circuit sequentially reads data from the storage locations indicated by the N+1 first test addresses, such as Figure 4 As shown, if the data read from the storage location indicated by the i-th first test address is the same as the first data, and the i-th first test address is the i-th bit a in the first address i =0 and then the control circuit can determine the i-th signal line A in the address bus. i There is a constant 0 fault. If the i-th first test address is the i-th bit a in the first address i =1 and then the control circuit can determine the i-th signal line A in the address bus. i There is a common fault.

[0089] It can be understood that if the i-th first test address is the i-th bit a in the first address i =0, then the i-th bit of the i-th first test address is 1. If the i-th signal line A corresponding to the i-th first test address i If there is a constant 0 fault, when the control circuit accesses the i-th first test address, the i-th signal line A i The first address cannot be set to 1, and the first address is accessed incorrectly, which causes the data read to be the same as the first data D1 (or the third data D2). i =1, then the i-th bit of the i-th first test address is 0. If the i-th signal line A corresponding to the i-th first test address i If there is a constant 1 fault, the control circuit will fail due to the i-th signal line A when accessing the i-th first test address. i The bit cannot be set to 0, and the first address is accessed incorrectly, which causes the read data to be the same as the first data D1 (or the third data D2).

[0090] For example, assuming the first address of the first register is 0x55 (binary 0101 0101), and the bit corresponding to signal line A0 is 1, if the control circuit detects a fault in signal line A0, it can be determined that signal line A0 is a normally 1 fault, i.e., a short circuit between signal line A0 and the power supply. If the bit corresponding to signal line A1 is 0, if the control circuit detects a fault in signal line A1, it can be determined that signal line A1 is a normally 0 fault, i.e., a short circuit between signal line A1 and ground.

[0091] Based on the above analysis, after determining the fault of the signal line corresponding to any first test address, the control circuit can further accurately detect the fault type of the corresponding signal line based on the value of the inverted bit in the first address corresponding to the first test address. Thus, the fault detection accuracy and reliability of the address bus are effectively improved.

[0092] Optionally, the functional circuit can further include a second register, an address of the second register being a third address, the third address being different from the first address. The third address is different from the first address means that at least one bit in the third address is different from the corresponding bit in the first address. For example, part of the bits in the third address are different from the corresponding bits in the first address, and the remaining bits are the same as the corresponding bits in the first address; or each bit in the third address is different from the corresponding bit in the first address. For further reference Figure 3 The method can further include:

[0093] In step 103, a fourth address is determined according to the third address.

[0094] In the embodiments of the present application, the second register can also be a register dedicated to fault detection of the address bus, and the second register can be a readable and writable register. The fourth address is obtained by inverting the bit in the third address corresponding to the first signal line.

[0095] It can be understood that the third address can include a plurality of bits, and the fourth address can be obtained by inverting one bit (which can be any bit) of the plurality of bits. If a bit in the third address is 0, the value after inversion is 1; if a bit in the third address is 1, the value after inversion is 0. It can also be understood that the values of the other bits in the fourth address are the same as the values of the corresponding bits in the third address.

[0096] For example, assuming that the address bus includes A0 to A N N+1 signal lines, the third address of the second register can be a binary number of N+1 bits, and the third address B can be represented as {b N ,b N-1 ,…,b1,b0}. Each of b0 to b N is a binary number of 1 bit. The N+1-bit binary number in the third address B corresponds to the N+1 signal lines in the address bus one by one. For example, the bit b i in the third address B can correspond to the i-th signal line A i in the address bus. Assuming that the fourth address is obtained by inverting the bit b iThe first signal line can be the signal line A in the address bus. i .

[0097] Step 104: Determine that the first signal line in the address bus is faulty based on the fifth data being the same as the sixth data.

[0098] The fifth data is data written to the storage location indicated by the third address, that is, the fifth data may be data written to the second register. For example, after initiating fault detection on the address bus, the control circuit may first write the fifth data to the storage location indicated by the third address. Alternatively, the fifth data may be data pre-written to the storage location indicated by the third address, that is, the fifth data may be data pre-stored in the second register.

[0099] The sixth data is data read from the storage location indicated by the fourth address. In this embodiment of the present application, after the control circuit determines the fourth address based on the third address, it can read data from the storage location indicated by the fourth address. If the sixth data read by the control circuit is different from the fifth data, it can be determined that the first signal line is not faulty. If the sixth data read by the control circuit is the same as the fifth data, it can be determined that the first signal line is faulty.

[0100] It can be understood that if the sixth data read from the storage location indicated by the fourth address is the same as the fifth data, this indicates that when the control circuit read the data from the storage location indicated by the fourth address, it actually read the fifth data from the storage location indicated by the third address. In other words, when the control circuit accessed the fourth address via the address bus, it actually accessed the third address. Therefore, it can be determined that the first signal line corresponding to the fourth address is faulty, causing the control circuit to erroneously access the third address when accessing the fourth address.

[0101] Optionally, in an embodiment of the present application, the control circuit can determine N+1 different second test addresses based on the third address, and each second test address is obtained by inverting a bit in the third address. For example, the i-th second test address in the N+1 second test addresses is the i-th bit b in the third address. i The i-th bit b is obtained by inverting i Corresponding to the i-th signal line in the address bus. It can be seen that the i-th bit in the i-th second test address is the i-th bit b in the third address. i The other bits in the i-th second test address are the same as the corresponding bits in the third address. i is 0, then the value after inverting it is 1; if the i-th bit b in the third addressi If 1, the value after the NOT operation is 0.

[0102] For example, referring to Figure 5 , the N+1 second test addresses can be expressed as follows:

[0103] The second test address Addr0={b N ,b N-1 ,…,b1,~b0} corresponds to the signal line A0.

[0104] The second test address Addr1={b N ,b N-1 ,…,~b1,b0} corresponds to the signal line A1.

[0105] …

[0106] The second test address Addri={b N ,b N-1 ,…,~b i ,…,b1,b0} corresponds to the signal line Ai. i

[0107] …

[0108] The second test address AddrN-1={b N ,~b N-1 ,…,b1,b0} corresponds to the signal line AN-1. N-1

[0109] The second test address AddrN={~b N ,b N-1 ,…,b1,b0} corresponds to the signal line AN. N

[0110] ~b i in the first test address above represents the NOT operation on the bit b i . The fourth address in steps 103 and 104 above can be any one of the N+1 second test addresses, which is not limited in the embodiments of the present application. Optionally, the registers corresponding to the N+1 second test addresses can all be read-only registers. Since there is no need to have multiple readable and writable registers in the functional circuit, the performance requirement for the functional circuit is effectively reduced, and the flexibility of the fault detection method is effectively improved.

[0111] In the embodiments of the present application, as shown in Figure 5 , the control circuit can first send a third address B={b N ,b N-1 ​​​The control circuit can then read data from each of the N+l second test addresses. If the data read from any of the second test addresses is different from the fifth data D3, then the control circuit can determine that the signal line corresponding to the any of the second test addresses is not faulty. If the data read from any of the second test addresses is the same as the fifth data D3, then the control circuit can determine that the signal line corresponding to the any of the second test addresses is faulty.

[0112] For example, assume that the control circuit reads data from the i-th second test address Addri = {b N ,b N-1 ,…,~b i ,…,b1,b0} in the third address. If the data read from the i-th second test address Addri is the same as the fifth data D3, then since the i-th second test address Addri is obtained by inverting the i-th bit b i in the third address, the control circuit can determine that the i-th signal line in the address bus is faulty.

[0113] For example, if the i-th bit b i in the third address is 0, and the i-th signal line A i has a constant 0 fault (i.e., the signal line A i is shorted to ground), then when the control circuit accesses the i-th second test address Addri, the i-th signal line A i cannot be set to 1, and thus the control circuit will access the third address incorrectly, resulting in the sixth data read being the same as the fifth data D3. If the i-th bit b i in the third address is 1, and the i-th signal line A i has a constant 1 fault (i.e., the signal line A i is shorted to power), then when the control circuit accesses the i-th second test address Addri, the i-th signal line A i cannot be set to 0, and thus the control circuit will access the third address incorrectly, resulting in the sixth data read being the same as the fifth data D3.

[0114] Alternatively, in embodiments of the present application, to ensure the reliability of the fault detection, in step 104, if the control circuit detects that the fifth data is the same as the sixth data, the control circuit can also write seventh data to the storage location indicated by the third address, the seventh data being different from the fifth data. That is, the control circuit can re-write the seventh data to the second register, the seventh data being able to overwrite the fifth data. Subsequently, the control circuit can determine that the first signal line is faulty according to the seventh data being the same as the eighth data.

[0115] The eighth data is the data read from the storage location indicated by the fourth address after the seventh data is written. That is, the control circuit can read the data in the storage location indicated by the fourth address again after the seventh data is written to the storage location indicated by the third address. If the eighth data is the same as the seventh data, it can be determined that the first signal line is faulty.

[0116] It can be understood that the data stored in the storage location indicated by the fourth address may be exactly the fifth data. That is, when the control circuit detects whether the first signal line is faulty by comparing whether the sixth data is the same as the fifth data, there is a certain probability of false detection. In order to avoid false detection, the control circuit can re-write the seventh data to the storage location indicated by the third address, and continue to read the data from the storage location indicated by the fourth address. If the eighth data is still the same as the seventh data, that is, the data read by the control circuit from the storage location indicated by the fourth address changes with the data written to the storage location indicated by the third address, the control circuit can determine that the first signal line is faulty.

[0117] Reference Figure 5 The fault detection process of the control circuit on the address bus can include the following steps:

[0118] In step S21, the control circuit calculates N+1 second test addresses Addr0 to AddrN based on the third address of the second register.

[0119] In step S22, the control circuit writes the fifth data D3 to the storage location indicated by the third address B={b N ,b N-1 ,…,b1,b0} (i.e. the second register).

[0120] In step S23, the control circuit reads the value of the storage location indicated by each second test address and compares it with the fifth data D3 respectively.

[0121] For example, the control circuit reads the value of the storage location indicated by the 0th second test address Addr0 and compares it with the fifth data D3. If they are not the same, it can be determined that the signal line A0 in the address bus is not faulty. If they are the same, the detection of step S24 is continued.

[0122] The control circuit reads the value of the storage location indicated by the 1st second test address Addr1 and compares it with the fifth data D3. If they are not the same, it can be determined that the signal line A1 in the address bus is not faulty. If they are the same, the detection of step S24 is continued.

[0123] …

[0124] The control circuit reads the value of the storage location indicated by the Nth second test address AddrN, and compares it with the fifth data D3. If they are not the same, it can be determined that the signal line A in the address bus is faulty. N-1 No fault; if they are the same, the detection of step S24 continues.

[0125] The control circuit reads the value of the storage location indicated by the Nth second test address AddrN, and compares it with the fifth data D3. If they are not the same, it can be determined that the signal line A in the address bus is faulty. N No fault; if they are the same, the detection of step S24 continues.

[0126] In step S24, the control circuit writes the seventh data D4 into the storage location indicated by the third address B = {b N ,b N-1 ,…,b1,b0}, which is different from the fifth data D3.

[0127] In step S25, the control circuit reads the value of the storage location indicated by the second test address, and compares it with the seventh data D4. If they are not the same, it is determined that the corresponding signal line is not faulty; if they are the same, it is determined that the corresponding signal line is faulty.

[0128] After writing the seventh data D4, the control circuit can read the data from the storage location indicated by the second test address again, and compare it with the seventh data D4. As a possible example, the control circuit can read the data from the storage location indicated by each second test address, and compare it with the seventh data D4.

[0129] As another possible example, the control circuit can only read the value of the storage location indicated by the target test address, and compare it with the seventh data D4. The target test address can be the second test address whose read value is the same as the fifth data D3 in the above step S23. That is, the target test address is the second test address corresponding to the suspected faulty signal line. In step S25, the control circuit can only read the data from the second test address corresponding to the suspected faulty signal line, without reading the data from each second test address, thereby effectively improving the efficiency of fault detection.

[0130] Optionally, in the above step 104, the control circuit can also determine the fault type of the first signal line based on the value of the bit in the third address. The fault type can include: constant 0 fault and constant 1 fault. The constant 0 fault can be caused by the short circuit of the signal line to the ground, and the constant 1 fault can be caused by the short circuit of the signal line to the power supply.

[0131] In an embodiment of the present application, if the bit in the third address is 0, that is, the fourth address is obtained by inverting the bit 0 in the third address, then the control circuit can determine that the first signal line has a constant 0 fault; if the bit in the third address is 1, that is, the fourth address is obtained by inverting the bit 1 in the third address, then the control circuit can determine that the first signal line has a constant 1 fault.

[0132] For a scenario where the control circuit sequentially reads data from the storage locations indicated by the N+1 second test addresses, such as Figure 5 As shown, if the data read from the storage location indicated by the i-th second test address is the same as the fifth data, and the i-th second test address is the i-th bit b in the third address i =0 and then the control circuit can determine the i-th signal line A in the address bus. i There is a constant 0 fault. If the i-th second test address is the i-th bit b in the third address i =1 and then the control circuit can determine the i-th signal line A in the address bus. i There is a common fault.

[0133] It can be understood that if the i-th second test address is the i-th bit b in the third address i =0, then the i-th bit of the i-th second test address is 1. If the i-th signal line A corresponding to the i-th second test address i If there is a constant 0 fault, the control circuit will fail due to the i-th signal line A when accessing the i-th second test address. i The ith bit b in the third address is accessed incorrectly, which results in the read data being the same as the fifth data D3 (or seventh data D4). i =1, then the i-th bit of the i-th second test address is 0. If the i-th signal line A corresponding to the i-th second test address i If there is a constant 1 fault, the control circuit will fail due to the i-th signal line A when accessing the i-th second test address. i The bit cannot be set to 0, and the third address is accessed by mistake, which causes the read data to be the same as the fifth data D3 (or the seventh data D4).

[0134] For example, assuming that the third address of the second register is 0xaa (binary number 10101010), the bit corresponding to signal line A0 is 0, if the control circuit detects that signal line A0 is faulty, it can be determined that signal line A0 is a constant 0 fault, i.e., signal line A0 is shorted to ground. The bit corresponding to signal line A1 is 1, if the control circuit detects that signal line A1 is faulty, it can be determined that signal line A1 is a constant 1 fault, i.e., signal line A1 is shorted to power supply.

[0135] Based on the above analysis, after determining the fault of the signal line corresponding to any second test address, the control circuit can also accurately detect the fault type of the corresponding signal line based on the value of the inverted bit in the third address corresponding to the second test address. Thus, the fault detection accuracy and reliability of the address bus are effectively improved.

[0136] Alternatively, the value of each bit in the third address of the second register is opposite to the value of the corresponding bit in the first address of the first register. That is, the third address can be obtained by performing bitwise inversion on the first address. Assuming that the first address A of the first register is represented by a binary number as {a N ,a N-1 ,…,a1,a0}, and the third address B of the second register is represented by a binary number as {b N ,b N-1 ,…,b1,b0}, the addresses of the two registers can satisfy: a N =~b N , a N-1 =~b N -1, …, a1=~b1, a0=~b0. For example, if the first address A of the first register is 0x5555, the third address B of the second register can be 0xaaaa.

[0137] Alternatively, the first address of the first register can be all 0 (for example, it can be 0x00), and the third address of the second register can be all 1 (for example, it can be 0xff). Alternatively, the first address of the first register can be all 1, and the third address of the second register can be all 0.

[0138] It can be understood that, assuming that the i-th bit a i in the first address of the first register is opposite to the value of the i-th bit b i in the third address, and the i-th bit a i in the first address is 0, and the i-th bit b i in the third address is 1. Then for signal line A i in the address bus, there are three detection scenarios as follows:

[0139] Scenario 1: signal line Ai There is a constant 0 fault, then when fault detection is based on the first register (i.e. based on the first address and the second address), the signal line A i has a fault; when fault detection is based on the second register (i.e. based on the third address and the fourth address), the signal line A i is fault-free.

[0140] Scenario 2: signal line A i There is a constant 1 fault, then when fault detection is based on the first register, the signal line A i is fault-free; when fault detection is based on the second register, the signal line A i has a fault.

[0141] Scenario 3: signal line A i is fault-free, then when fault detection is based on the first register, the signal line A i is fault-free; when fault detection is based on the second register, the signal line A i is fault-free.

[0142] That is, for any signal line in the address bus, if the values of the corresponding bit positions of the first address and the third address are opposite to each other, then when the signal line is fault-free, both registers can detect that the signal line is fault-free. When the signal line has a constant 0 or constant 1 fault, one register can detect that the signal line has a fault, and the other register will detect that the signal line is fault-free. Therefore, when a certain signal line is detected to have a fault based on any register, it can be confirmed that the signal line has a fault.

[0143] It can be understood that when a certain signal line has a constant 0 fault, if the bit position corresponding to the signal line in the address of a certain register (such as the first register or the second register) is 0, then the constant 0 fault of the signal line can be detected based on the register. If the bit position corresponding to the signal line in the address of the register is 1, then the signal line will be detected as fault-free based on the register, i.e. the constant 0 fault of the signal line cannot be detected.

[0144] When a certain signal line has a constant 1 fault, if the bit position corresponding to the signal line in the address of a certain register (such as the first register or the second register) is 1, then the constant 1 fault of the signal line can be detected based on the register. If the bit position corresponding to the signal line in the address of the register is 0, then the signal line will be detected as fault-free based on the register, i.e. the constant 1 fault of the signal line cannot be detected.

[0145] Based on the above analysis, it can be further known that if the value of each bit in the third address of the second register is opposite to the value of the corresponding bit in the first address of the first register, it can be ensured that for each signal line in the address bus, it can be detected whether the signal line has a constant 0 or a constant 1 fault based on the method shown in steps 101 to 104. In addition, by designing one of the first address and the third address as all 0 and the other as all 1, it can be ensured that when the plurality of signal lines in the address bus are all grounded or all connected to the power supply, the fault type of each signal line can still be accurately detected.

[0146] It can also be understood that the above is an example in which after the address bus fails, the first data (or also including the third data) can be correctly written to the first register, or the fifth data (or also including the seventh data) can be correctly written to the second register, and the registers indicated by each test address (including the first test address and the second test address) are all read-only registers. That is, the above is an example in which after the address bus fails, at least one of the first register and the second register can normally write data, and the registers indicated by the test address cannot write data. For example, assuming that the first address of the first register is all 0 and the third address of the second register is all 1, when part of the signals in the address bus has a grounding fault, the first register can normally write data; when part of the signals in the address bus has a power supply fault, the second register can normally write data.

[0147] If the register indicated by a certain test address is also a readable and writable register, and after the address bus fails, the control circuit accesses the first address or the third address to write data, and actually accesses the test address, based on the method provided in the embodiment of the application, it can still be detected whether the signal line corresponding to the test address is faulty.

[0148] For example, assuming that the first address of the first register is 0000 0000, the third address of the second register is 1111 1111, the 0th first test address is 0000 0001, the 0th second test address is 1111 1110, and the register indicated by the 0th first test address is a readable and writable register. If there is a constant-1 fault in the signal line A0 in the address bus, when the control circuit writes the first data into the first register, the actual register written is the register indicated by the 0th first test address 0000 0001. Correspondingly, the second data read from the register indicated by the 0th first test address is the same as the first data, so the control circuit can determine that there is a fault in the signal line A0. Moreover, the control circuit can normally write the fifth data into the second register, and the sixth data read from the register indicated by the 0th second test address 1111 1110 is the same as the fifth data, so the control circuit can also determine that there is a fault in the signal line A0.

[0149] Based on the above analysis, if the register indicated by a test address is also a readable and writable register, after a fault occurs in the signal line corresponding to the test address in the address bus, the control circuit can detect the fault in the signal line based on the first register and the second register. In this scenario, the control circuit can no longer need to continue to determine the fault type of the signal line.

[0150] Optionally, in the embodiment of the present application, the register included in the functional circuit for fault detection can be a register whose written value is the same as the read value; or the register included in the functional circuit for fault detection can be a NOT register; or the register included in the functional circuit for fault detection can be a register whose written value and read value have a preset mapping relationship. The preset mapping relationship can be flexibly designed according to the requirements of the application scenario, for example, the mapping relationship can include: when the written value is 0, the read value is 1; when the written value is 1, the read value is 2; when the written value is 2, the read value is 3, and the like. The register included in the functional circuit for fault detection includes at least the first register, or can also include the second register.

[0151] It can be understood that the foregoing is an example in which the first register and the second register are both registers whose written value and read value are the same. For example, after the first data D1 (such as 0x55aa) is written into the first register, when the control circuit reads the data in the first register, the functional circuit can output the first data D1 (such as 0x55aa) back to the control circuit.

[0152] It can also be understood that the method provided by the embodiments of the present application does not limit the type of the register used for fault detection, but only needs to ensure that the register is a readable and writable register. Thus, the performance requirement for the functional circuit is effectively reduced, for example, a custom chip is not needed to implement the fault detection function, thereby effectively improving the application flexibility of the fault detection method.

[0153] The following describes the fault detection method provided by the embodiments of the present application by taking an example of an address bus including a total of 8 (that is, N=7) signal lines A0 to A7 and taking an example of a first address of a first register being 0x00 (binary 0000 0000) and a third address of a second register being 0xff (binary 1111 1111). The fault detection method can include Figure 6 the walk 1 detection shown in FIG. 1, and Figure 7 the walk 0 detection shown in FIG. 2. The walk 1 detection can be used to detect a constant 0 fault of the signal line, and the walk 0 detection can be used to detect a constant 1 fault of the signal line.

[0154] It can be understood that if the i th bit in the first address (or the third address) is 0, the test address obtained by inverting the i th bit can be used to perform walk 1 detection on the i th signal line. If the i th bit in the first address (or the third address) is 1, the test address obtained by inverting the i th bit can be used to perform walk 0 detection on the i th signal line.

[0155] Reference is made to Figure 6 Since the first address of the first register is all 0, the control circuit can first perform walk 1 test on the 8 signal lines A0 to A7 in the address bus, that is, first detect whether the signal lines A0 to A7 have a constant 0 fault of short circuit to ground. As shown in Figure 6 the walk 1 test, the process includes the following steps:

[0156] Step S31, calculating a first test address. The control circuit inverts the binary number 0000 0000 of the first address A=0x0 of the first register by 1 bit each time to obtain a series of first test addresses: 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80.

[0157] Among them, the first test address Addr0={0,0,0,0,0,0,0,1}, that is, 0x1, corresponds to the signal line A0;

[0158] The first test address Addr1={0,0,0,0,0,0,1,0}, that is, 0x2, corresponds to the signal line A1;

[0159] The first test address Addr2={0,0,0,0,0,1,0,0}, i.e. 0x4, corresponds to the signal line A2.

[0160] The first test address Addr3={0,0,0,0,1,0,0,0}, i.e. 0x8, corresponds to the signal line A3.

[0161] The first test address Addr4={0,0,0,1,0,0,0,0}, i.e. 0x10, corresponds to the signal line A4.

[0162] The first test address Addr5={0,0,1,0,0,0,0,0}, i.e. 0x20, corresponds to the signal line A5.

[0163] The first test address Addr6={0,1,0,0,0,0,0,0}, i.e. 0x40, corresponds to the signal line A6.

[0164] The first test address Addr7={1,0,0,0,0,0,0,0}, i.e. 0x80, corresponds to the signal line A7.

[0165] Step S32, write the first data D1=0x5555 to the first address A=0x0 of the first register.

[0166] Step S33, read the value of each first test address and compare it with the first data D1 respectively.

[0167] The control circuit reads the value of the Addr0=0x1 register. If the read value is not 0x5555, it can be determined that the signal line A0 has no constant 0 fault. If the read value is 0x5555, it can be determined that the signal line A0 may have a constant 0 fault. Because if the signal line A0 has a constant 0 fault, the 0x1 (binary 0000 0001) register is expected to be accessed, but the signal line A0 is pulled to low, so the actual register accessed is the register indicated by the error address 0x0 (binary 0000 0000), which is the first register, so the read value should be the first data 0x5555 written in the first register.

[0168] It can be understood that there is a small probability that the value in the register indicated by the first test address 0x1 is also 0x5555. At this time, if the signal line A0 is not faulty, the data read from the register indicated by the first test address 0x1 is also the same as the first data 0x5555. Therefore, if it is judged that the signal line A0 is faulty only according to that the data read from the first test address 0x1 is equal to the first data 0x5555, there may be a false detection. Therefore, the detection of the subsequent step S34 and step S35 can be further added, that is, another different data (for example, 0xaaaa) is written to the first address 0x0 of the first register, the value in the register indicated by the first test address 0x1 is continued to be read, and it is detected whether the read value becomes 0xaaaa. If it becomes, it can be determined that the signal line A0 has a short-to-ground fault, which causes the actual error access to the first register with the address 0x0 when accessing the first test address 0x1.

[0169] The control circuit reads the value of Addr1=0x2, compares it with the first data D1, if they are not the same, it can be determined that the signal line A1 is not faulty; if they are the same, the detection of step S34 is continued;

[0170] The control circuit reads the value of Addr2=0x4, compares it with the first data D1, if they are not the same, it can be determined that the signal line A2 is not faulty; if they are the same, the detection of step S34 is continued;

[0171] The control circuit reads the value of Addr3=0x8, compares it with the first data D1, if they are not the same, it can be determined that the signal line A3 is not faulty; if they are the same, the detection of step S34 is continued;

[0172] The control circuit reads the value of Addr4=0x10, compares it with the first data D1, if they are not the same, it can be determined that the signal line A4 is not faulty; if they are the same, the detection of step S34 is continued;

[0173] The control circuit reads the value of Addr5=0x20, compares it with the first data D1, if they are not the same, it can be determined that the signal line A5 is not faulty; if they are the same, the detection of step S34 is continued;

[0174] The control circuit reads the value of Addr6=0x40, compares it with the first data D1, if they are not the same, it can be determined that the signal line A6 is not faulty; if they are the same, the detection of step S34 is continued;

[0175] The control circuit reads the value of Addr7=0x80, compares it with the first data D1, if they are not the same, it can be determined that the signal line A7 is not faulty; if they are the same, the detection of step S34 is continued;

[0176] Step S34, write the third data D2=0xaaaa to the first address A=0x0 of the first register. The first data D1 and the third data D2 can be any value, but the two must be different.

[0177] Step S35, read the value of the first test address, and compare it with the third data D2 respectively.

[0178] The control circuit reads the value of the register of Addr0=0x1, if the read value is not 0xaaaa, it can be determined that the signal line A0 has no constant 0 fault. If the read value is 0xaaaa, it can be determined that the signal line A0 has a constant 0 fault. Because if the signal line A0 has a constant 0 fault, the expected access is the register of 0x1 (binary 0000 0001), but the signal line A0 is pulled to low, so the actual access is the register indicated by the error address 0x00 (binary 0000 0000), which is the first register, so the read value should be the third data 0xaaaa written in the first register. As can be seen from the above steps S31 to S35, the control circuit writes two different values to the first register, and reads the register indicated by the first test address 0x1 twice, if the read values are equal to the two values written in the first register respectively, the control circuit can confirm that the actual access to the error address 0x0 when accessing 0x1, and further determine that the signal line A0 has a constant 0 fault, that is, the signal line A0 is shorted to ground.

[0179] The control circuit can continue to read the value of Addr1=0x2, and compare it with the third data D2, if they are different, it can be determined that the signal line A1 has no fault; if they are the same, it can be determined that the signal line A1 has a constant 0 fault;

[0180] The control circuit can continue to read the value of Addr2=0x4, and compare it with the third data D2, if they are different, it can be determined that the signal line A2 has no fault; if they are the same, it can be determined that the signal line A2 has a constant 0 fault;

[0181] The control circuit can continue to read the value of Addr3=0x8, and compare it with the third data D2, if they are different, it can be determined that the signal line A3 has no fault; if they are the same, it can be determined that the signal line A3 has a constant 0 fault;

[0182] The control circuit can continue to read the value of Addr4=0x10, and compare it with the third data D2, if they are different, it can be determined that the signal line A4 has no fault; if they are the same, it can be determined that the signal line A4 has a constant 0 fault;

[0183] The control circuit can continue to read the value of Addr5=0x20, compare it with the third data D2, and if they are not the same, it can be determined that the signal line A5 is not faulty; if they are the same, it can be determined that the signal line A5 has a constant 0 fault;

[0184] The control circuit can continue to read the value of Addr6=0x40, compare it with the third data D2, and if they are not the same, it can be determined that the signal line A6 is not faulty; if they are the same, it can be determined that the signal line A6 has a constant 0 fault;

[0185] The control circuit can continue to read the value of Addr7=0x80, compare it with the third data D2, and if they are not the same, it can be determined that the signal line A7 signal line is not faulty; if they are the same, it can be determined that the signal line A7 has a constant 0 fault.

[0186] It can be understood that in the above step S35, the control circuit can read the value of each first test address and compare it with the third data D2. Alternatively, in order to improve the efficiency of fault detection, the control circuit can only read the value of the target test address and compare it with the third data D2. Wherein, the target test address can refer to the first test address whose value is the same as the first data D1 in the above step S33. That is, the target test address is the first test address corresponding to the signal line suspected to have a constant 0 fault.

[0187] After completing the step walk 1 test shown in Figure 6 The control circuit can perform a step walk 0 test based on the second register after the step walk 1 test shown in FIG. 8. Referring to Figure 7 Since the third address of the second register is all 1, the control circuit can perform a step walk 0 test on the 8 signal lines A0 to A7 in the address bus, i.e., detect whether the signal lines A0 to A7 have a constant 1 fault short-circuited to the power supply. As Figure 7 The process of the step walk 0 test includes the following steps:

[0188] Step S41, calculate the second test address. The control circuit takes the binary number 1111 1111 of the third address B=0xff of the second register and flips 1 bit at a time to obtain a series of second test addresses: 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f.

[0189] Among them, the second test address Addr0={1,1,1,1,1,1,1,0}, i.e. 0xfe, corresponds to the signal line A0;

[0190] The second test address Addr1={1,1,1,1,1,1,0,1}, i.e. 0xfd, corresponds to the signal line A1;

[0191] The second test address Addr2 = {1, 1, 1, 1, 1, 0, 1, 1}, i.e. 0xfb, corresponds to the signal line A2;

[0192] The second test address Addr3 = {1, 1, 1, 1, 0, 1, 1, 1}, i.e. 0xf7, corresponds to the signal line A3;

[0193] The second test address Addr4 = {1, 1, 1, 0, 1, 1, 1, 1}, i.e. 0xef, corresponds to the signal line A4;

[0194] The second test address Addr5 = {1, 1, 0, 1, 1, 1, 1, 1}, i.e. 0xdf, corresponds to the signal line A5;

[0195] The second test address Addr6 = {1, 0, 1, 1, 1, 1, 1, 1}, i.e. 0xbf, corresponds to the signal line A6;

[0196] The second test address Addr7 = {0, 1, 1, 1, 1, 1, 1, 1}, i.e. 0x7f, corresponds to the signal line A7.

[0197] Step S42, write the fifth data D3 = 0x5555 to the third address B = 0xff of the second register.

[0198] Step S43, read the value of each second test address and compare it with the fifth data D3 respectively.

[0199] The control circuit reads the value of the register Addr0 = 0xfe, if the read value is not 0x5555, it can be determined that the signal line A0 has no constant 1 fault. If the read value is 0x5555, it can be determined that the signal line A0 may have a constant 1 fault, i.e. the signal line A0 and the power supply are short-circuited. Because if the signal line A0 has a constant 1 fault, the expected access is the register of 0xfe (binary 1111 1110), but the signal line A0 is pulled to high level, so the actual access is the register indicated by the error address 0xff (binary 1111 1111), and the register indicated by this address is the second register, so the read value should be the fifth data 0x5555 written in the second register.

[0200] It can be understood that there is a small probability that the value in the register indicated by the second test address 0xfe is also 0x5555. At this time, if the signal line A0 is not faulty, the data read from the register indicated by the second test address 0xfe is also the same as the fifth data 0x5555. Therefore, if it is judged that the signal line A0 is faulty only according to that the data read from the second test address 0xfe is equal to the fifth data 0x5555, there may be a false detection. Therefore, the detection of the subsequent steps S44 and S45 can be further added, that is, another different data (for example, 0xaaaa) is written to the third address 0xff of the second register, the value in the register indicated by the second test address 0xfe is continued to be read, and it is detected whether the read value becomes 0xaaaa. If it becomes, it can be determined that the signal line A0 has a short-circuit fault with the power supply, resulting in that the actual error access is to the second register with the address 0xff when the second test address 0xfe is accessed.

[0201] The control circuit reads the value of Addr1=0xfd, and compares it with the fifth data D3. If they are not the same, it can be determined that the signal line A1 is not faulty; if they are the same, the detection of step S44 is continued;

[0202] The control circuit reads the value of Addr2=0xfb, and compares it with the fifth data D3. If they are not the same, it can be determined that the signal line A2 is not faulty; if they are the same, the detection of step S44 is continued;

[0203] The control circuit reads the value of Addr3=0xf7, and compares it with the fifth data D3. If they are not the same, it can be determined that the signal line A3 is not faulty; if they are the same, the detection of step S44 is continued;

[0204] The control circuit reads the value of Addr4=0xef, and compares it with the fifth data D3. If they are not the same, it can be determined that the signal line A4 is not faulty; if they are the same, the detection of step S44 is continued;

[0205] The control circuit reads the value of Addr5=0xdf, and compares it with the fifth data D3. If they are not the same, it can be determined that the signal line A5 is not faulty; if they are the same, the detection of step S44 is continued;

[0206] The control circuit reads the value of Addr6=0xbf, and compares it with the fifth data D3. If they are not the same, it can be determined that the signal line A6 is not faulty; if they are the same, the detection of step S44 is continued;

[0207] The control circuit reads the value of Addr7=0x7f, and compares it with the fifth data D3. If they are not the same, it can be determined that the signal line A7 is not faulty; if they are the same, the detection of step S44 is continued;

[0208] Step S44, write the seventh data D4=0xaaaa to the third address B=0xff of the second register. The seventh data D4 and the fifth data D3 can be any value, but the two must be different.

[0209] Step S45, read the value of the second test address, and compare it with the seventh data D4 respectively.

[0210] The control circuit reads the value of the register of Addr0=0xfe, if the read value is not 0xaaaa, it can be determined that the signal line A0 has no constant 1 fault. If the read value is 0xaaaa, it can be determined that the signal line A0 has a constant 1 fault. Because if the signal line A0 has a constant 1 fault, the expected access is the register of 0xfe(binary 1111 1110), but the signal line A0 is pulled to high level, so the actual access is the register indicated by the error address 0xff(binary 1111 1111), and the register indicated by the address is the second register, so the read value should be the seventh data 0xaaaa written in the second register. As can be seen from the above steps S41 to S45, the control circuit writes two different values to the second register, and reads the register indicated by the second test address 0xfe twice, if the read values are equal to the two values written in the second register respectively, the control circuit can confirm that the actual access to the error address 0xff when accessing 0xfe, and further determine that the signal line A0 has a constant 1 fault, that is, the signal line A0 is short-circuited with the power supply.

[0211] The control circuit can continue to read the value of Addr1=0xfd, and compare it with the seventh data D4, if they are different, it can be determined that the signal line A1 has no fault; if they are the same, it can be determined that the signal line A1 has a constant 1 fault;

[0212] The control circuit can continue to read the value of Addr2=0xfb, and compare it with the seventh data D4, if they are different, it can be determined that the signal line A2 has no fault; if they are the same, it can be determined that the signal line A2 has a constant 1 fault;

[0213] The control circuit can continue to read the value of Addr3=0xf7, and compare it with the seventh data D4, if they are different, it can be determined that the signal line A3 has no fault; if they are the same, it can be determined that the signal line A3 has a constant 1 fault;

[0214] The control circuit can continue to read the value of Addr4=0xef, and compare it with the seventh data D4, if they are different, it can be determined that the signal line A4 has no fault; if they are the same, it can be determined that the signal line A4 has a constant 1 fault;

[0215] The control circuit can continue to read the value of Addr5=0xdf and compare it with the seventh data D4. If they are different, it can be determined that the signal line A5 has no fault; if they are the same, it can be determined that the signal line A5 has a normal 1 fault;

[0216] The control circuit can continue to read the value of Addr6=0xbf and compare it with the seventh data D4. If they are different, it can be determined that the signal line A6 has no fault; if they are the same, it can be determined that the signal line A6 has a normal 1 fault;

[0217] The control circuit can continue to read the value of Addr7=0x7f and compare it with the seventh data D4. If they are different, it can be determined that the signal line A7 has no fault; if they are the same, it can be determined that the signal line A7 has a normal 1 fault.

[0218] It will be appreciated that in step S45, the control circuit may read the value of each second test address and compare it with the seventh data D4. Alternatively, to improve fault detection efficiency, the control circuit may only read the value of the target test address and compare it with the seventh data D4. The target test address may be the second test address whose value, read in step S43, is the same as the fifth data D3. In other words, the target test address is the second test address corresponding to the signal line suspected of having a normally-1 fault.

[0219] Optionally, in an embodiment of the present application, the functional circuit may be a memory or a non-memory device. For example, the non-memory device may include a programmable logic chip and an ASIC chip. The programmable logic chip may be a CPLD, an FPGA, or a GAL. In particular, for scenarios where the functional circuit is a memory, the traditional walking algorithm needs to write detection data to multiple addresses in the memory, and the detection data will overwrite the data already stored in the memory. However, the fault detection method provided in the embodiment of the present application only needs to write data to a register dedicated to fault detection, so it will not affect the data already stored in the memory, and can realize online detection of address bus faults. For scenarios where the functional circuit is a non-memory device, the fault detection method provided in the embodiment of the present application can realize fault detection of signal lines in the address bus, effectively improving the accuracy of fault detection. In addition, since there is no need to configure an inverting register in the functional circuit, the performance requirements for the functional circuit are reduced, and the application flexibility of the fault detection method is improved.

[0220] It is understandable that the bits a0 to a in the embodiment of the present application N , and bits b0 to b N , are used to distinguish different bits in the address, and do not necessarily indicate the order of positions in the address. That is, the bits in the first address of the first register can be arranged from a0 to aN The bits in the third address of the second register can be arranged in the order from b0 to b N Similarly, the signal lines A0 to A1 in the address bus are arranged in the same order. N It is used to distinguish different signal lines in the address bus, and does not necessarily indicate the order of arrangement in the address bus. That is, the signal lines in the address bus can be arranged from A0 to A1. N The embodiment of the present application does not limit the order of arrangement of the bits in the register address and the order of arrangement of the signal lines in the address bus. It is only necessary to ensure that the bits in the register address correspond to the signal lines in the address bus in a one-to-one correspondence.

[0221] It can also be understood that the order of the steps of the address bus fault detection method provided in the embodiment of the present application can be appropriately adjusted, and the steps can be increased or decreased accordingly according to the situation. For example, the above steps 103 and 104 can be performed before step 102. That is, the control circuit can first perform fault detection based on the second register, and then perform fault detection based on the first register. Alternatively, it can be understood that the embodiment of the present application does not limit the order in which the control circuit performs the walk 0 test and the walk 1 test. Alternatively, the above steps 103 and 104 can be deleted according to the situation, that is, the control circuit can only perform fault detection based on the first register.

[0222] It is also understood that in the above steps 102 and 104, the control circuit may use a comparison operation to determine whether the two data are identical, or may use a logical operation such as XOR, XOR, addition, or subtraction to determine whether the two data are identical. The present embodiment does not limit the method of data comparison.

[0223] It is also understandable that in the above steps 102 and 104, the control circuit may first write a data into the register and then sequentially read the value of the storage location indicated by each test address. Thereafter, the control circuit may write another data into the register and then sequentially read the value of the storage location indicated by the test address. Alternatively, the control circuit may first write a data into the register and then read the value of the storage location indicated by a test address. Thereafter, the control circuit may write another data into the register and then read the value of the storage location indicated by the test address. Furthermore, the control circuit may repeat the above detection steps for other test addresses until all test addresses are detected.

[0224] To sum up, the embodiment of the present application provides a fault detection method for an address bus. The method can obtain a second address by inverting a bit in a first address of a first register in a functional circuit, and determine that a first signal line in the address bus is faulty according to the fact that a first data and a second data are the same. The first data is data written into a storage location indicated by the first address, and the second data is data read from a storage location indicated by the second address. Based on this, if the first data and the second data are the same, it indicates that when data in the storage location indicated by the second address is read, the data in the storage location indicated by the first address is actually read. Accordingly, it can be determined that the first signal line in the address bus is faulty. Since the method provided by the embodiment of the present application can detect the signal line in the address bus that is faulty, the accuracy of fault detection is effectively improved.

[0225] In addition, in the method provided by the embodiment of the present application, the register (such as the first register and the second register) in the functional circuit for fault detection can not be an inverting register, thereby effectively reducing the performance requirement on the functional circuit and improving the application flexibility of the fault detection method. That is, the application range of the fault detection method can be wider, and it is easier to implement. In addition, since the control circuit can write two different data into the same register and read data from the test address to compare with the written data, the problem of false detection can be effectively avoided, and the accuracy and reliability of fault detection are improved.

[0226] The embodiment of the present application also provides a fault detection device for an address bus. The device can implement the fault detection method for the address bus provided by the method embodiment. The device can be applied to a control circuit in a scenario as shown in Figure 1 or Figure 2 The address bus is used to connect the control circuit and a functional circuit. The functional circuit includes a first register, and the address of the first register is a first address. As shown in Figure 8 The device includes:

[0227] A first determination module 201 is configured to determine a second address according to the first address. The second address is obtained by inverting a bit in the first address, and the bit corresponds to a first signal line in the address bus. The function of the first determination module 201 can be implemented by referring to the related description of steps 101, step S11 and step S31 in the method embodiment.

[0228] The second determining module 202 is configured to determine that the first signal line is faulty according to the first data being the same as the second data. The first data is data written into a storage location indicated by the first address, and the second data is data read from a storage location indicated by the second address. The function of the second determining module 202 can be implemented by referring to the description of steps 102, steps S12 to S13, and steps S32 to S33 in the method embodiments.

[0229] Optionally, the second determining module 202 can be configured to write third data into the storage location indicated by the first address according to the first data being the same as the second data, the third data being different from the first data; and determine that the first signal line is faulty according to the third data being the same as the fourth data. The fourth data is data read from the storage location indicated by the second address after the third data is written. The function of the second determining module 202 can also be implemented by referring to the description of steps S14 to S15, and steps S34 to S35 in the method embodiments.

[0230] Optionally, the functional circuit can further include a second register, an address of the second register being a third address, the third address being different from the first address. The first determining module 201 can be further configured to determine a fourth address according to the third address, the fourth address being obtained by performing a bitwise NOT operation on the third address, and the bit in the third address corresponding to the first signal line. The function of the first determining module 201 can also be implemented by referring to the description of steps 103, step S21, and step S41 in the method embodiments.

[0231] The second determining module 202 is further configured to determine that the first signal line is faulty according to the fifth data being the same as the sixth data. The fifth data is data written into a storage location indicated by the third address, and the sixth data is data read from a storage location indicated by the fourth address. The function of the second determining module 202 can also be implemented by referring to the description of steps 104, steps S22 to S23, and steps S42 to S43 in the method embodiments.

[0232] Optionally, the second determining module 202 can be further configured to write seventh data into the storage location indicated by the third address according to the fifth data being the same as the sixth data, the seventh data being different from the fifth data; and determine that the first signal line is faulty according to the seventh data being the same as the eighth data. The eighth data is data read from the storage location indicated by the fourth address after the seventh data is written. The function of the second determining module 202 can also be implemented by referring to the description of steps S24 to S25, and steps S44 to S45 in the method embodiments.

[0233] Optionally, the second determining module 202 can be configured to determine that the first signal line has a constant-0 fault if the bit in the third address is 0, and determine that the first signal line has a constant-1 fault if the bit in the third address is 1.

[0234] Optionally, each bit in the third address has a value opposite to a corresponding bit in the first address.

[0235] Optionally, the second determining module 202 can be configured to determine that the first signal line has a constant-0 fault if the bit in the first address is 0, and determine that the first signal line has a constant-1 fault if the bit in the first address is 1.

[0236] Optionally, the functional circuit is a programmable logic device or an ASIC.

[0237] Optionally, the register included in the functional circuit is a register with the same write value and read value, or is a NOT register, or is a register with a preset mapping relationship between the write value and the read value.

[0238] In summary, the embodiment of the present application provides a fault detection device for an address bus. The device can perform NOT operation on a bit in a first address of a first register in a functional circuit to obtain a second address, and determine that a first signal line in the address bus is faulty according to the same first data and second data. The first data is data written into a storage location indicated by the first address, and the second data is data read from a storage location indicated by the second address. Based on this, if the first data and the second data are the same, it indicates that the data in the storage location indicated by the second address is actually the data in the storage location indicated by the first address. Accordingly, it can be determined that the first signal line in the address bus is faulty. Since the device provided by the embodiment of the present application can detect the signal line with a fault in the address bus, the precision of fault detection is effectively improved.

[0239] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the address bus fault detection device and each module described above can refer to the corresponding process in the foregoing method embodiments, which will not be described herein.

[0240] It should be understood that the address bus fault detection apparatus provided by the embodiments of the present application can be implemented by an ASIC or a programmable logic device (PLD), and the PLD can be a CPLD, an FPGA, a generic array logic (GAL) or any combination thereof. In addition, the address bus fault detection method provided by the method embodiments can also be implemented by software. When the address bus fault detection method provided by the method embodiments is implemented by software, the address bus fault detection apparatus can include a software module for implementing the method.

[0241] The embodiments of the present application further provide a computer readable storage medium, which stores instructions executed by a processor to implement the address bus fault detection method provided by the method embodiments.

[0242] The embodiments of the present application further provide a computer program product containing instructions, which, when executed on a processor, cause the processor to perform the address bus fault detection method provided by the method embodiments.

[0243] The embodiments of the present application further provide a control chip, which includes a programmable logic circuit and / or program instructions, and the chip performs the address bus fault detection method provided by the method embodiments when running. Optionally, the control chip can be a CPU.

[0244] The embodiments of the present application further provide an electronic device, as shown in Figure 1 The electronic device includes a control circuit and a functional circuit, the control circuit is connected with the functional circuit through an address bus, and the control circuit can be used to implement the address bus fault detection method provided by the method embodiments. For example, the control circuit can include the address bus fault detection apparatus provided by the apparatus embodiments.

[0245] Optionally, the electronic device can be a server or a forwarding device, and the forwarding device can be a router, a switch or a line board unit, etc. Taking the line board unit on the core router of the electronic device as an example, the main function of the line board unit is to realize the data packet forwarding of the router through a forwarding chip, and the CPU on the single board of the line board unit is used to control and manage each functional unit on the board, as shown in Figure 2 The CPU controls and manages each functional circuit through a bus (including an address bus, a data bus and a control bus), and the functional circuit includes a programmable logic chip and / or an ASIC chip, etc.

[0246] If the address bus fails, the register address of the logical chip accessed by the CPU will be incorrect, and then the operation will be performed on the incorrect register address, thereby causing the single board to work abnormally. In the embodiment of the present application, the CPU can perform fault detection on the address bus, and report the detected fault signal line. That is, after the CPU perceives that any signal line in the address bus fails, the CPU can report an alarm, for example, the CPU can report an alarm to a network management. At the same time, the CPU can attempt to recover the system, and if the system cannot be recovered, the CPU can perform service switching on the functional unit, or perform a power-off process and the like, to prevent the service from being affected or the fault from spreading and the like.

[0247] Figure 9 is another structure schematic diagram of an electronic device provided in the embodiment of the present application. Referring to Figure 9 , the electronic device includes a processor 301, a memory 302, a network interface 303 and a bus 304.

[0248] The memory 302 stores a computer program 3021, and the computer program 3021 is used to implement various application functions. The processor 301 is used to execute the computer program 3021 to implement the address bus fault detection method provided in the above method embodiment. For example, the processor 301 is used to execute the computer program 3021 to implement the functions of the modules shown in Figure 8 .

[0249] The processor 301 can be a CPU, and the processor 301 can also be other general-purpose processors, DSPs, ASICs, FPGAs, graphics processing units (GPUs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0250] The memory 302 can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the nonvolatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DRRAM).

[0251] The network interface 303 can be multiple, and the network interface 303 is used to realize the communication connection (which can be wired or wireless) with other devices. Among them, in the embodiment of the present application, the network interface 303 is used to transceive a message. Among them, the other device can be a terminal, a server, a VM, and other network devices.

[0252] The bus 304 is used to connect the processor 301, the memory 302, and the network interface 303. Moreover, the bus 304 can include a power bus, a control bus, and a status signal bus, etc. in addition to the data bus. However, for the purpose of clear illustration, various buses are marked as the bus 304 in the figure.

[0253] In the embodiment of the present application, the terms "first", "second", and "third" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance. The term "at least one" means one or more, and "multiple" means two or more.

[0254] The term "and / or" in the embodiments of the present application is only used to describe the association relationship of the associated objects, and indicates that there can be three relationships, for example, A and / or B can represent three cases of A existing alone, A and B existing simultaneously, and B existing alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects have an "or" relationship.

[0255] The above is only an optional embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of fault detection of an address bus, characterized by, The address bus is used to connect the control circuit and the functional circuit, the functional circuit includes a first register, and an address of the first register is a first address; the method comprises: determining a second address according to the first address, the second address being obtained by performing an inversion on a bit in the first address, the bit corresponding to a first signal line in the address bus; determining that the first signal line is faulty according to first data being the same as second data; wherein the first data is data written into a storage location indicated by the first address, and the second data is data read from a storage location indicated by the second address.

2. The method of claim 1, wherein, The determining that the first signal line is faulty according to the first data being the same as the second data comprises: writing third data into the storage location indicated by the first address according to the first data being the same as the second data, the third data being different from the first data; determining that the first signal line is faulty according to the third data being the same as fourth data; wherein the fourth data is data read from the storage location indicated by the second address after the third data is written.

3. The method according to claim 1 or 2, characterized in that, The functional circuit further includes a second register, an address of the second register being a third address, and the third address being different from the first address; the method further comprises: determining a fourth address according to the third address, the fourth address being obtained by performing an inversion on a bit in the third address, the bit in the third address corresponding to the first signal line; determining that the first signal line is faulty according to fifth data being the same as sixth data; wherein the fifth data is data written into a storage location indicated by the third address, and the sixth data is data read from a storage location indicated by the fourth address.

4. The method of claim 3, wherein, The determining that the first signal line is faulty according to the fifth data being the same as the sixth data comprises: writing seventh data into the storage location indicated by the third address according to the fifth data being the same as the sixth data, the seventh data being different from the fifth data; determining that the first signal line is faulty according to the seventh data being the same as eighth data; wherein the eighth data is data read from the storage location indicated by the fourth address after the seventh data is written.

5. The method according to claim 3 or 4, characterized in that, The determining that the first signal line is faulty comprises: if the bit in the third address is 0, determining that the first signal line has a constant-0 fault; if the bit in the third address is 1, determining that the first signal line has a constant-1 fault.

6. The method according to any one of claims 3 to 5, characterized in that, Each bit in the third address has a value opposite to a corresponding bit in the first address.

7. The method according to any one of claims 1 to 6, characterized in that, The determining that the first signal line is faulty comprises: if the bit in the first address is 0, determining that the first signal line has a constant-0 fault; if the bit in the first address is 1, determining that the first signal line has a constant-1 fault.

8. The method according to any one of claims 1 to 7, characterized in that, The functional circuit is a programmable logic device or an application-specific integrated circuit (ASIC).

9. The method according to any one of claims 1 to 8, characterized in that, The register included in the functional circuit is a register with the same write value and read value; alternatively, the register included in the functional circuit is an inversion register. Alternatively, the register included in the functional circuit is a register having a mapping relationship between a written value and a read value.

10. An address bus fault detection apparatus, characterized by, The application is applied to a control circuit, and the address bus is used for connecting the control circuit and a functional circuit. The device comprises: The first determining module is configured to determine a second address according to the first address, the second address being obtained by performing an inversion on a bit in the first address, the bit corresponding to a first signal line in the address bus; The second determining module is configured to determine that the first signal line is faulty according to the first data being the same as the second data.

11. The apparatus of claim 10, wherein, The first data is data written into a storage location indicated by the first address, and the second data is data read from a storage location indicated by the second address. The second determining module is configured to: write third data into the storage location indicated by the first address according to the first data being the same as the second data, the third data being different from the first data; determine that the first signal line is faulty according to the third data being the same as fourth data; 12. The device according to claim 10 or 11, characterized in that The fourth data is data read from the storage location indicated by the second address after the third data is written. The functional circuit further comprises a second register, the address of the second register being a third address, the third address being different from the first address; The first determining module is further configured to determine a fourth address according to the third address, the fourth address being obtained by performing an inversion on a bit in the third address, the bit in the third address corresponding to the first signal line; The second determining module is further configured to determine that the first signal line is faulty according to the fifth data being the same as the sixth data.

13. The apparatus of claim 12, wherein, The fifth data is data written into a storage location indicated by the third address, and the sixth data is data read from a storage location indicated by the fourth address. The second determining module is configured to: write seventh data into the storage location indicated by the third address according to the fifth data being the same as the sixth data, the seventh data being different from the fifth data; determine that the first signal line is faulty according to the seventh data being the same as eighth data; 14. The apparatus of claim 12 or 13, wherein, The eighth data is data read from the storage location indicated by the fourth address after the seventh data is written. The second determining module is configured to: if the bit in the third address is 0, determine that the first signal line has a constant-0 fault; 15. The apparatus of any one of claims 12 to 14, wherein, if the bit in the third address is 1, determine that the first signal line has a constant-1 fault.

16. The device according to any one of claims 10 to 15, characterized in that The value of each bit in the third address is opposite to the value of a corresponding bit in the first address. The second determining module is configured to: if the bit in the first address is 0, determine that the first signal line has a constant-0 fault; 17. The apparatus of any one of claims 10 to 16, wherein, if the bit in the first address is 1, determine that the first signal line has a constant-1 fault.

18. The apparatus of any one of claims 10 to 17, wherein, The functional circuit is a programmable logic device or an ASIC. The register included in the functional circuit is a register having the same written value and read value; Alternatively, the register included in the functional circuit is a NOT register. Alternatively, the register included in the functional circuit is a register with a mapping relationship between a written value and a read value.

19. A computer-readable storage medium, characterized in that, The computer readable storage medium stores instructions, and the instructions are executed by the processor to implement the method in any one of claims 1 to 9.

20. A computer program product comprising instructions, characterized in that, When the instructions run on the processor, the processor executes the method in any one of claims 1 to 9.

21. A control chip, characterized by The control chip includes a programmable logic circuit and / or program instructions, and the control chip executes the method in any one of claims 1 to 9 when running.

22. An electronic device, comprising: The electronic device includes a control circuit and a functional circuit, the control circuit is connected with the functional circuit through an address bus, and the control circuit is used to implement the method in any one of claims 1 to 9.

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