A matrix accelerator sharing chip system memory and a method for operating the same

Abstract

The application relates to a matrix accelerator sharing a chip system memory and a running method thereof. The matrix accelerator comprises a system memory module, a task management module, a data access module and a matrix operation module. The matrix accelerator directly shares the chip system memory through a double-port SRAM, so that the matrix accelerator can be applied to a small-size and low-power navigation baseband chip. Meanwhile, when the matrix accelerator does not work, the shared memory can still be used as the chip system memory, so that the idle waste of memory resources is avoided. Through a task queue, multiple operation tasks and corresponding task control instructions can be loaded into the matrix accelerator at one time, and an interrupt signal is generated after all operation tasks are completed, so that the interaction between a CPU and the matrix accelerator is completed, the efficiency of the CPU is maximally improved, and the performance of the chip system is significantly improved.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a matrix accelerator with shared chip system memory and its operation method. Background Technology

[0002] Navigation and positioning algorithms heavily utilize vector and matrix operations, such as the commonly used single-point weighted least squares algorithm. Its basic operational units include matrix multiplication, matrix inversion, and matrix addition / subtraction. These basic operational units, combined in a specific order, can complete a weighted least squares operation. Similar operations can be extended to other algorithms such as Kalman filtering. These algorithms are stable and mature, but their computational steps are numerous, and the computation time increases significantly with the matrix dimension. Functionally, they can be completely separated from software, and matrix operations can be accelerated using RTL (Register Transfer Level) to ultimately reduce CPU (Central Processing Unit) load and improve system performance.

[0003] Currently, general-purpose matrix accelerators can independently perform matrix operations, interacting with the outside world only through the bus and interrupts, which facilitates verification and portability. However, each operation (such as matrix multiplication or addition) requires data prefetching and result return. As the matrix dimension increases, the amount of data for matrix operations increases exponentially. Furthermore, existing matrix accelerators use DMA (Direct Memory Access) for data transfer. With increasing matrix dimension, DMA can frequently and persistently occupy the bandwidth of the chip's system bus and system memory, resulting in high system bus load and decreased overall system performance. In addition, matrix operations require the storage of a large number of intermediate variables and results. Therefore, the internal memory capacity of the matrix accelerator needs to be designed according to the maximum possible matrix dimension, which inevitably increases chip area and power consumption. Moreover, when the matrix accelerator is not in operation, the internal memory of the module will be idle. Summary of the Invention

[0004] Therefore, it is necessary to provide a matrix accelerator with shared chip system memory and its operation method to address the above-mentioned technical problems.

[0005] A matrix accelerator sharing chip system memory includes: a system memory module, a task management module, a data access module, and a matrix operation module;

[0006] The system memory module is used to convert part or all of the single-port SRAM (static random access memory) in the chip system memory into dual-port SRAM according to the maximum memory requirements of the matrix accelerator, so that the matrix accelerator can share the chip system memory through the dual-port SRAM.

[0007] The task management module is used to coordinate the CPU to perform computational control and data interaction on the matrix accelerator. It loads computational tasks and task control instructions generated by the CPU based on the computational tasks through the task queue. When the task queue is not empty, it sends the computational tasks and corresponding task control instructions to the data access module. After all computational tasks are completed, it generates an interrupt signal to notify the CPU to complete the computation.

[0008] The data access module is used to send the matrix operation data read from the dual-port SRAM and the synchronously generated operation instructions to the matrix operation module according to the issued operation task and the corresponding task control instructions. It also writes the operation result data sent by the matrix operation module into the dual-port SRAM, and after the operation result data is written, it indicates that the currently issued operation task is completed by pulling up the task completion signal.

[0009] The matrix operation module is used to select the corresponding operators for the input matrix operation data according to the operation operation instructions, and send the operation result data to the data storage and retrieval module after the operation is completed.

[0010] Furthermore, the system memory module also includes a protocol conversion submodule. One end of the dual-port SRAM is connected to the protocol conversion submodule via the MEM bus. The protocol conversion submodule is used to interconnect with the system bus and CPU via the AXI (Advanced Extensible Interface) protocol to ensure seamless connection between the system memory module and the CPU. The other end of the dual-port SRAM is connected to the data access module via the MEM (Memory) bus to enable the matrix accelerator to directly access the dual-port SRAM.

[0011] Furthermore, the task management module also includes a user interface submodule, which consists of an operation start and stop control register, an interrupt enable and clear control register, a status register, and a task queue interface. The user interface submodule is connected to the system bus through the AHB (Advanced High Performance) bus and interconnected with the CPU via the AXI protocol. It is used to complete the operation start and stop control, interrupt enable and clear control, and task queue initialization of the matrix accelerator under the control of the CPU.

[0012] Furthermore, the workflow of the task queue is as follows:

[0013] When the task queue receives a start signal sent by the CPU through the user interface submodule, it loads the computation tasks and corresponding task control instructions initialized by the CPU in the task queue interface into the task queue in ascending address order; the task queue is managed in a first-in, first-out manner.

[0014] When the task queue is not empty, send the computation task at the top of the task queue and its corresponding task control instructions to the data access module.

[0015] When the task queue detects that the data access module pulls a high task completion signal, it determines that the currently issued operation task has been completed, deletes the currently issued operation task from the task queue, and uploads the corresponding task number to the status register of the user interface submodule for the CPU to query the task status information. At the same time, the task queue determines whether the user interface submodule generates an interrupt signal based on whether the interrupt reporting enable in the corresponding task control instruction is high.

[0016] The system checks if the task queue is empty. If it is empty, the matrix operation stops, and an interrupt signal generated by the user interface submodule notifies the CPU to complete the operation. If the task queue is not empty, the system continues to issue operation tasks and corresponding task control instructions according to the task queue order to perform matrix operations until the task queue is empty.

[0017] Furthermore, the task control instruction consists of the task number, interrupt reporting enable, operation type selection, operand matrix X storage address, operand matrix Y storage address, operation result storage address, number of rows in operand matrix X, number of columns in operand matrix X and operand matrix Y, number of columns in operand matrix Y, and instruction activation flag.

[0018] Furthermore, the data access module includes an SRAM read / write control submodule, a matrix operation control submodule, a matrix multiplication / addition operation control submodule, and a matrix inversion operation control submodule;

[0019] The matrix operation control submodule receives the operation tasks and corresponding task control instructions from the task queue, parses the parameters, and sends the parsed operation parameters to the SRAM read / write control submodule, the matrix multiplication / addition operation control submodule, and the matrix inversion operation control submodule, respectively. The matrix operation control submodule also indicates the completion of the currently issued operation task by pulling the task completion signal high after receiving the operation completion signal generated by the SRAM read / write control submodule. The operation parameters include the operation type, the starting address of the matrix data storage, and the matrix dimension parameters.

[0020] The matrix multiplication / addition operation control submodule is used to calculate the starting address of the matrix multiplication / addition operation data, the number of read / write loops, and the increment / decrement of the address in each read / write loop based on the operation parameters. At the same time, it generates the operation instructions corresponding to the matrix multiplication / addition operation and sends them to the matrix operation module.

[0021] The matrix inversion operation control submodule is used to generate the LDL decomposition inversion algorithm control flow based on the operation parameters. In the control flow, the starting address for storing and accessing matrix inversion operation data, the number of read / write loops, and the increment / decrement of the address for each read / write loop are calculated. At the same time, the operation instructions corresponding to the matrix inversion operation are generated and sent to the matrix operation module.

[0022] The SRAM read / write control submodule generates SRAM read / write control signals based on the operation parameters, including the starting address of the matrix operation data, the number of read / write loops, and the increment / decrement of the address in each read / write loop provided by the matrix multiplication / addition operation control submodule and the matrix inversion operation control submodule. Following these signals, a read operation is performed first, reading matrix operation data from the dual-port SRAM and sending it to the matrix operation module. After the operation is completed, a write operation is performed, writing the operation result data sent by the matrix operation module into the dual-port SRAM. Finally, after the last operation result data is written, an operation completion signal is generated and reported to the matrix operation control submodule.

[0023] Furthermore, the matrix operation module includes an operation input / output control submodule, a floating-point multiplication / addition operator, and a floating-point division operator;

[0024] The operation input / output control submodule is used to receive operation instructions and matrix operation data sent by the data access module, select the corresponding operator to perform matrix operation according to the operation instructions, and send the matrix operation data to the corresponding operator. After the operation is completed, the operation result data output by the operator is obtained and sent to the data access module.

[0025] The floating-point multiply / add operator is used to receive matrix operation data sent by the operation input / output control submodule, perform multiplication, addition, and multiply-accumulate operations according to the corresponding operation instructions, and return the operation result data to the operation input / output control submodule.

[0026] The floating-point division operator is used to receive matrix operation data sent by the arithmetic input / output control submodule, perform division and reversal operations according to the corresponding arithmetic operation instructions, and return the operation result data to the arithmetic input / output control submodule.

[0027] A method for operating a matrix accelerator sharing chip system memory, the method comprising the following steps:

[0028] The CPU prepares matrix operation data, initializes the operation task and corresponding task control instructions, and starts the matrix accelerator in the dual-port SRAM of the chip system memory; the matrix accelerator includes a system memory module, a task management module, a data access module, and a matrix operation module.

[0029] After the CPU starts the matrix accelerator, the task queue in the task management module loads the computation tasks and the task control instructions generated by the CPU based on the computation tasks. When the task queue is not empty, the computation tasks and corresponding task control instructions are sent to the data access module. The data access module, based on the sent computation tasks and corresponding task control instructions, sends the matrix operation data read from the dual-port SRAM and the synchronously generated operation instructions to the matrix operation module. The matrix operation module selects the corresponding operators for the input matrix operation data to perform matrix operations according to the operation instructions. After the operation is completed, the data access module writes the operation result data into the dual-port SRAM. After the operation result data is written, the data access module pulls the task completion signal high to indicate that the currently sent computation task is completed.

[0030] The task queue is checked to see if it is empty. If it is not empty, the task queue continues to issue calculation tasks and corresponding task control instructions for matrix calculation until the task queue is empty. If it is empty, it is determined that the matrix accelerator has completed all calculation tasks. The task management module generates an interrupt signal to notify the CPU to complete the calculation, and the CPU obtains the final matrix calculation result from the dual-port SRAM.

[0031] The aforementioned matrix accelerator and its operating method for sharing chip system memory converts part or all of the single-port SRAM in the chip system memory into dual-port SRAM according to the maximum memory requirements of the matrix accelerator. This allows the matrix accelerator to directly share the chip system memory through the dual-port SRAM, eliminating the need to design the internal memory capacity of the matrix accelerator based on the maximum possible matrix dimension. This makes the matrix accelerator suitable for small-size, low-power navigation baseband chips. Furthermore, when the matrix accelerator is not operating, the shared memory can still be used as chip system memory, avoiding idle and wasted memory resources. Additionally, through a task queue, multiple computational tasks and their corresponding task control instructions can be loaded into the matrix accelerator at once. The matrix accelerator can then be controlled to execute the issued computational tasks and corresponding task control instructions sequentially according to the programmed order to perform matrix operations. An interrupt signal is generated upon completion of all computational tasks to complete the interaction between the CPU and the matrix accelerator. This batch processing method significantly reduces the number of interactions between the CPU and the matrix accelerator, avoids prolonged occupation of system bus bandwidth, maximizes CPU efficiency, and significantly improves the performance of the chip system. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of a matrix accelerator with shared chip system memory in one embodiment;

[0033] Figure 2 This is a schematic diagram of the task management module in one embodiment;

[0034] Figure 3 This is a schematic diagram of the task queue and task control instruction encoding format in one embodiment; wherein... Figure 3 (a) is the task queue. Figure 3 (b) is the encoding format for task control instructions;

[0035] Figure 4 This is a schematic diagram of the data access module in one embodiment;

[0036] Figure 5 This is a schematic diagram of the matrix operation module in one embodiment;

[0037] Figure 6 This is a flowchart illustrating the operation method of a matrix accelerator with shared chip system memory in one embodiment;

[0038] Figure 7 This is a schematic diagram of the address interconnection between the P0 and P1 ports of SRAM3 in one embodiment. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0040] In one embodiment, such as Figure 1 As shown, a matrix accelerator with shared chip system memory is provided, including: a system memory module, a task management module, a data access module, and a matrix operation module.

[0041] The system memory module is used to convert part or all of the single-port SRAM in the chip system memory into dual-port SRAM according to the maximum memory requirements of the matrix accelerator, so that the matrix accelerator can share the chip system memory through the dual-port SRAM.

[0042] The task management module is used to coordinate the CPU to perform computational control and data interaction on the matrix accelerator. It loads computational tasks and task control instructions generated by the CPU based on the computational tasks through the task queue. When the task queue is not empty, it sends the computational tasks and corresponding task control instructions to the data access module. After all computational tasks are completed, it generates an interrupt signal to notify the CPU to complete the computation.

[0043] The data access module is used to send the matrix operation data read from the dual-port SRAM and the synchronously generated operation instructions to the matrix operation module according to the issued operation task and the corresponding task control instructions. It also writes the operation result data sent by the matrix operation module into the dual-port SRAM, and after the operation result data is written, it indicates that the currently issued operation task is completed by pulling up the task completion signal.

[0044] The matrix operation module is used to select the corresponding operators for the input matrix operation data according to the operation operation instructions, and send the operation result data to the data storage and retrieval module after the operation is completed.

[0045] Furthermore, the system memory module also includes a protocol conversion submodule. One end of the dual-port SRAM is connected to the protocol conversion submodule via a MEM bus. The protocol conversion submodule is used to interconnect with the system bus and CPU via the AXI protocol, ensuring seamless connection between the system memory module and the CPU. The other end of the dual-port SRAM is connected to the data access module via a MEM bus to enable direct access to the dual-port SRAM by the matrix accelerator. For example... Figure 1 The SRAM3 in the chip is a dual-port SRAM with two independent read / write ports, P0 and P1. Port P0 is connected to the protocol conversion submodule to realize the function of the chip system memory; port P1 is used to connect to the data access module in the matrix accelerator. Through port P1, the matrix accelerator can directly access the SRAM3 memory.

[0046] Furthermore, such as Figure 2 As shown, the task management module also includes a user interface submodule, which includes operation start and stop control registers, interrupt enable and clear control registers, status registers, and a task queue interface (the task queue interface is a set of control registers). The user interface submodule is connected to the system bus via the AHB bus and interconnected with the CPU via the AXI protocol. It is used to complete operations such as operation start and stop control, interrupt enable and clear control, and task queue initialization of the matrix accelerator under the control of the CPU.

[0047] Furthermore, compared to general-purpose matrix accelerators, the task management module of the matrix accelerator in this application adds features such as... Figure 3 The task queue shown in (a) has the following workflow:

[0048] (1) When the task queue receives the start signal sent by the CPU through the user interface submodule, it loads the computation tasks and corresponding task control instructions initialized by the CPU in the task queue interface into the task queue in ascending address order; wherein, the task queue is managed in the form of first-in-first-out (FIFO). For example, the FIFO depth is 32, that is, a maximum of 32 matrix operation tasks can be temporarily stored.

[0049] (2) When the task queue is not empty, send the operation task at the top of the task queue and the corresponding task control instruction to the data access module.

[0050] (3) When the task queue detects that the data access module pulls the task completion signal high, it determines that the currently issued operation task has been completed, deletes the currently issued operation task from the task queue and uploads the corresponding task number to the status register of the user interface submodule for the CPU to query the task status information. At the same time, the task queue determines whether the user interface submodule generates an interrupt signal based on whether the interrupt reporting enable in the corresponding task control instruction is high.

[0051] (4) Check if the task queue is empty. If it is empty, stop the matrix operation and generate an interrupt signal from the user interface submodule to notify the CPU to complete the operation. If it is not empty, repeat steps (1) to (3), that is, continue to issue operation tasks and corresponding task control instructions according to the task queue order to perform matrix operations until the task queue is empty.

[0052] It should be understood that through the task queue, multiple computational tasks and their corresponding task control instructions can be sent to the matrix accelerator at once. The matrix accelerator will execute matrix operations sequentially in the programmed order. After all computational tasks are completed, an interrupt signal is generated to complete the interaction between the CPU and the matrix accelerator. This batch processing method significantly reduces the number of interactions between the CPU and the matrix accelerator, maximizing CPU efficiency.

[0053] Furthermore, the encoding format of task control instructions is as follows: Figure 3 As shown in (b), it consists of task number, interrupt reporting enable, operation type selection, operand matrix X storage address, operand matrix Y storage address, operation result storage address, number of rows of operand matrix X, number of columns of operand matrix X and operand matrix Y, number of columns of operand matrix Y, and instruction activation flag.

[0054] Furthermore, the data access module's function is to calculate the address parameters for reading and writing SRAM within the computational flow based on the issued task control instructions, and then complete the read and write operations on the SRAM. For example... Figure 4As shown, the data access module includes an SRAM read / write control submodule, a matrix operation control submodule, a matrix multiplication / addition operation control submodule, and a matrix inversion operation control submodule.

[0055] The matrix operation control submodule receives operation tasks and corresponding task control instructions from the task queue, parses the parameters, and sends the parsed operation parameters to the SRAM read / write control submodule, matrix multiplication / addition operation control submodule, and matrix inversion operation control submodule, respectively. Upon receiving the operation completion signal generated by the SRAM read / write control submodule, the matrix operation control submodule also indicates the completion of the currently issued operation task by pulling the task completion signal high. Based on this, the task management module updates the task queue, updates the status register, and generates interrupt signals. The operation parameters include the operation type, the starting address for storing matrix data, and the matrix dimension parameters.

[0056] The matrix multiplication / addition operation control submodule is used to calculate the starting address of the matrix multiplication / addition operation data, the number of read / write loops, and the increment / decrement of the address in each read / write loop based on the operation parameters. At the same time, it generates the operation instructions corresponding to the matrix multiplication / addition operation and sends them to the matrix operation module to indicate which operation will be performed on the currently output operation data.

[0057] The matrix inversion operation control submodule is used to generate the LDL decomposition inversion algorithm control flow based on the operation parameters. In the control flow, the starting address for storing and accessing matrix inversion operation data, the number of read / write loops, and the increment / decrement of the address in each read / write loop are calculated. At the same time, the operation instructions corresponding to the matrix inversion operation are generated and sent to the matrix operation module, indicating whether the currently output operation data will be multiplied and accumulated or differentiated.

[0058] The SRAM read / write control submodule generates SRAM read / write control signals based on the operation parameters, including the starting address of the matrix operation data, the number of read / write loops, and the increment / decrement of the address in each read / write loop provided by the matrix multiplication / addition operation control submodule and the matrix inversion operation control submodule. Following these signals, a read operation is performed first, reading matrix operation data from the dual-port SRAM and sending it to the matrix operation module. After the operation is completed, a write operation is performed, writing the operation result data sent by the matrix operation module into the dual-port SRAM. Finally, after the last operation result data is written, an operation completion signal is generated and reported to the matrix operation control submodule.

[0059] Furthermore, the matrix operation module's function is to select the corresponding operators for the input matrix operation data according to the operation instructions, and complete the specific calculations, such as... Figure 5As shown, the matrix operation module includes an operation input / output control submodule, a floating-point multiplication / addition operator, and a floating-point division operator.

[0060] The operation input / output control submodule is used to receive operation instructions and matrix operation data sent by the data access module, select the corresponding operator to perform matrix operation according to the operation instructions, and send the matrix operation data to the corresponding operator. After the operation is completed, the operation result data output by the operator is obtained and sent to the data access module.

[0061] The floating-point multiply / add operator is used to receive matrix operation data sent by the operation input / output control submodule, perform multiplication, addition, and multiply-accumulate operations according to the corresponding operation instructions, and return the operation result data to the operation input / output control submodule.

[0062] The floating-point division operator is used to receive matrix operation data sent by the arithmetic input / output control submodule, perform division and reversal operations according to the corresponding arithmetic operation instructions, and return the operation result data to the arithmetic input / output control submodule.

[0063] In one embodiment, such as Figure 6 As shown, a method for operating a matrix accelerator with shared chip system memory is provided, including the following steps:

[0064] First, the CPU uses the dual-port SRAM (such as...) in the chip's system memory. Figure 1The system prepares matrix operation data, initializes operation tasks and corresponding task control instructions, and starts the matrix accelerator in the SRAM (3) of the CPU. The matrix accelerator includes a system memory module, a task management module, a data access module, and a matrix operation module. After the CPU starts the matrix accelerator, the task queue in the task management module loads the operation tasks and the task control instructions generated by the CPU based on the operation tasks. When the task queue is not empty, the operation tasks and corresponding task control instructions are sent to the data access module. The data access module, based on the sent operation tasks and corresponding task control instructions, sends the matrix operation data read from the dual-port SRAM and the synchronously generated operation instructions to the matrix operation module. The matrix operation module selects the corresponding operators for the input matrix operation data to perform matrix operations according to the operation instructions. After the operation is completed, the operation result data is written to the dual-port SRAM through the data access module. After the operation result data is written, the task completion signal is pulled high through the data access module to indicate that the currently sent operation task is completed. The task queue is checked to see if it is empty. If it is not empty, the task queue continues to issue calculation tasks and corresponding task control instructions for matrix calculation until the task queue is empty. If it is empty, it is determined that the matrix accelerator has completed all calculation tasks. The task management module generates an interrupt signal to notify the CPU to complete the calculation, and the CPU obtains the final matrix calculation result from the dual-port SRAM.

[0065] It should be understood that the aforementioned matrix accelerator and its operating method for sharing chip system memory converts part or all of the single-port SRAM in the chip system memory into dual-port SRAM according to the maximum memory requirements of the matrix accelerator. This allows the matrix accelerator to directly share the chip system memory through the dual-port SRAM, eliminating the need to design the internal memory capacity of the matrix accelerator based on the maximum possible matrix dimension. This makes the matrix accelerator suitable for small-size, low-power navigation baseband chips. Furthermore, when the matrix accelerator is not operating, the shared memory can still be used as chip system memory, avoiding the waste of idle memory resources. Additionally, through a task queue, multiple computational tasks and their corresponding task control instructions can be loaded into the matrix accelerator at once. The matrix accelerator can be controlled to execute the issued computational tasks and corresponding task control instructions sequentially according to the programmed order to perform matrix operations. An interrupt signal is generated after all computational tasks are completed to complete the interaction between the CPU and the matrix accelerator. This batch processing method significantly reduces the number of interactions between the CPU and the matrix accelerator, avoids prolonged occupation of system bus bandwidth, maximizes CPU efficiency, and significantly improves the performance of the chip system.

[0066] Furthermore, taking the matrix operation D=A*B+C as an example, the method provided in this application is as follows: Figure 1The operation flow of a matrix accelerator with shared chip system memory is explained.

[0067] Table 1. Address mapping relationship between P0 port and P1 port of SRAM3

[0068]

[0069] Specifically, Figure 1 The total storage capacity of SRAM3 is 1MB, and the data bit width is 64 bits. The address interconnection relationship between ports P0 and P1 is as follows: Figure 7 As shown. The SRAM3's system address space in the chip is 0x300000~0x3fffff. Figure 7 The address mapping relationship between port P0 and port P1 under the interconnection method shown is shown in Table 1.

[0070] Assuming the matrices involved in the operation are A (20×40), B (40×40), and C (20×40), the output matrix is ​​D (20×40), and the matrix elements are 64-bit double-precision floating-point numbers. The operation process includes:

[0071] 1. The CPU prepares matrix operation data in the system memory SRAM3.

[0072] The CPU places matrix A at memory address 0x00300000 through port P0, storing it sequentially in row order, with 8 bytes for each element, for a total data length of 20*40*8 bytes.

[0073] The CPU places matrix B at memory address 0x00310000 through port P0, storing the elements in row order, with each element stored in 8 bytes, for a total data length of 40*40*8 bytes.

[0074] The CPU places matrix C at memory address 0x00320000 through port P0, storing the elements in row order, with 8 bytes for each element, for a total data length of 20*40*8 bytes.

[0075] The physical path of the data flow is: CPU → System Bus → Protocol Conversion Submodule → SRAM3 P0 Port → SRAM3 Storage Unit.

[0076] 2. The CPU initializes computation tasks and task control instructions through the task queue interface.

[0077] (1) Task 1 (Complete C_tmp=A*B).

[0078] Task ID: 1 indicates that the current task ID is 1.

[0079] Interrupt reporting enable: 0, indicating that task number 1 will complete without generating an interrupt.

[0080] Operation type selection: 0x03 indicates that multiplication operation is selected.

[0081] Operand matrix X is stored at address 0x00000000, which represents the starting address of port P1 stored in matrix A.

[0082] The operand matrix Y is stored at address 0x00002000, which represents the starting address of port P1 stored in matrix B.

[0083] The storage address of the operation result is 0x00006000, which represents the starting address of port P1 where the operation result matrix C_tmp is stored.

[0084] The number of rows in operand matrix X is 20, representing the row dimension of matrix A.

[0085] The ratio of the number of columns in operand matrix X to the number of rows in operand matrix Y is 40, representing the column dimension of matrix A and the row dimension of matrix B.

[0086] The number of columns in operand matrix Y is 40, representing the column dimension of matrix B.

[0087] Instruction activation flag: 1.

[0088] (2) Task 2 (Complete D=C_tmp+C).

[0089] Task number: 2, indicating that the current task number is 2.

[0090] Interrupt reporting enable: 1, indicating that task number 2 has completed and generated an interrupt.

[0091] Operation type selection: 0x00 indicates that addition operation is selected.

[0092] Operand matrix X is stored at address 0x00006000, which represents the starting address of port P1 stored in matrix C_tmp.

[0093] The operand matrix Y is stored at address 0x00004000, which represents the starting address of port P1 stored in matrix C.

[0094] The storage address of the operation result is 0x00008000, which represents the starting address of port P1 where the operation result matrix D is stored.

[0095] The number of rows in operand matrix X is 20, representing the row dimension of matrix C_tmp.

[0096] Number of columns in operand matrix X / Number of rows in operand matrix Y: Invalid, can be left blank.

[0097] The number of columns in operand matrix Y is 40, representing the column dimension of matrix C.

[0098] Instruction activation flag: 1.

[0099] 3. CPU Startup Matrix Accelerator.

[0100] Write 1 to the operation start register of the user interface submodule and load task control instructions into the task queue.

[0101] 4. Matrix operations.

[0102] (1) The task queue is not empty, so task 1 is issued.

[0103] The data access module retrieves the first row elements of matrix A sequentially from addresses 0x00000000, 0x00000001, ..., 0x00000027 via port P1.

[0104] The data access module retrieves the first column elements of matrix B sequentially from addresses 0x00002000, 0x00002028, ..., 0x00002618 via port P1.

[0105] The matrix operation module performs a multiplication and accumulation operation on the first row of matrix A and the first column of matrix B to calculate the first row and first column element of matrix C_tmp, and saves the result to port address 0x00006000 on port P1.

[0106] Repeat the above three steps until the element of the 20th row and 40th column of matrix C_tmp is calculated and written to port address 0x0000631f of P1.

[0107] (2) Once task 1 is completed, the task queue discards the task control instructions for task 1. Check that the task queue is not yet empty, and continue to issue task 2.

[0108] The data access module retrieves the first row element of matrix C_tmp sequentially from addresses 0x00006000, 0x00006001, ..., 0x00006027 via port P1.

[0109] The data access module retrieves the first row element of matrix C sequentially from addresses 0x00004000, 0x00004001, ..., 0x00004027 via port P1.

[0110] The matrix operation module performs addition operations on the first row of the obtained matrix C_tmp and the first row elements of matrix C in sequence to calculate the first row elements of matrix D. The results are then saved sequentially to port addresses 0x00008000, 0x00008001, ..., 0x00008027 on port P1.

[0111] Repeat the above three steps until the elements of the 20th row of matrix D are calculated and written sequentially into port address P1 0x000082f8, 0x000082f9, ..., 0x0000831f.

[0112] The physical path for data reading is: SRAM3 storage cell → SRAM3 P1 port → data access module.

[0113] The physical path for data storage is: data access module → P1 port of SRAM3 → storage cell of SRAM3.

[0114] 5. The matrix accelerator calculation is complete.

[0115] Calculation task 2 is complete, the task queue has been cleared, this calculation is complete, the matrix accelerator generates an interrupt signal to notify the CPU that the calculation is complete.

[0116] 6. The CPU obtains the calculation results in the system memory SRAM3.

[0117] The CPU accesses system memory address 0x00340000 to obtain the final calculated result matrix D. Accessing system memory address 0x00330000 can also obtain the intermediate result, namely the calculation result of A*B.

[0118] The physical path of the data flow is: SRAM3 storage cell → SRAM3 P0 port → protocol conversion submodule → system bus → CPU.

[0119] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0120] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A matrix accelerator sharing a system memory of a chip, characterized in that, The matrix accelerator comprises a system memory module, a task management module, a data access module and a matrix operation module; The system memory module is configured to convert part or all of the single-port SRAM in the chip system memory into double-port SRAM according to the maximum memory requirement of the matrix accelerator, so that the matrix accelerator shares the chip system memory through the double-port SRAM; when the matrix accelerator is not working, the shared memory is still used as the chip system memory; The task management module is configured to coordinate the operation control and data interaction of the CPU on the matrix accelerator, load the operation task and the task control instruction generated by the CPU based on the operation task through the task queue, and deliver the operation task and the corresponding task control instruction to the data access module when the task queue is not empty, and generate an interrupt signal to inform the CPU of the completion of the operation when all the operation tasks are completed; The data access module is configured to send the matrix operation data read from the double-port SRAM and the operation operation instruction synchronously generated to the matrix operation module according to the delivered operation task and the corresponding task control instruction, write the operation result data sent by the matrix operation module into the double-port SRAM, and pull up the task completion signal to indicate that the current delivered operation task is completed after the operation result data is written into the double-port SRAM; The matrix operation module is configured to select the corresponding operation sub-module for the input matrix operation data according to the operation operation instruction to perform matrix operation, and send the operation result data to the data access module after the operation is completed; The data access module comprises an SRAM read / write control sub-module, a matrix operation control sub-module, a matrix multiplication / addition operation control sub-module and a matrix inversion operation control sub-module; The matrix operation control sub-module is configured to receive the operation task and the corresponding task control instruction delivered by the task queue to perform parameter analysis, and send the analyzed operation parameters to the SRAM read / write control sub-module, the matrix multiplication / addition operation control sub-module and the matrix inversion operation control sub-module respectively; the matrix operation control sub-module is further configured to pull up the task completion signal to indicate that the current delivered operation task is completed after receiving the operation completion signal generated by the SRAM read / write control sub-module; the operation parameters comprise an operation type, a matrix data storage starting address and a matrix dimension parameter; The matrix multiplication / addition operation control sub-module is configured to calculate the access starting address, the read / write cycle number and the increment / decrement amplitude of the address of each read / write cycle of the matrix multiplication / addition operation data based on the operation parameters, generate the operation operation instruction corresponding to the matrix multiplication / addition operation and send the operation operation instruction to the matrix operation module; The matrix inversion operation control sub-module is configured to generate an LDL decomposition inversion algorithm control flow based on the operation parameters, calculate the access starting address, the read / write cycle number and the increment / decrement amplitude of the address of each read / write cycle of the matrix inversion operation data in the control flow, generate the operation operation instruction corresponding to the matrix inversion operation and send the operation operation instruction to the matrix operation module. The SRAM read-write control submodule is configured to generate an SRAM read-write control signal based on the operation parameters and the access start address, the read / write cycle number, and the increment / decrement amplitude of the address of each read / write cycle of the matrix operation data provided by the matrix multiplication / addition operation control submodule and the matrix inversion operation control submodule, perform a read operation to read the matrix operation data from the dual-port SRAM and send the matrix operation data to the matrix operation module according to the SRAM read-write control signal, perform a write operation to write the operation result data sent by the matrix operation module into the dual-port SRAM after the operation is completed, and generate an operation completion signal and report the operation completion signal to the matrix operation control submodule after the last operation result data is written.

2. The matrix accelerator sharing the system memory of a chip according to claim 1, characterized in that, The system memory module further comprises a protocol conversion submodule, one end of the dual-port SRAM is connected to the protocol conversion submodule through a MEM bus, and the protocol conversion submodule is configured to interconnect the system bus and the CPU through an AXI protocol to ensure seamless connection between the system memory module and the CPU; and the other end of the dual-port SRAM is connected to the data access module through the MEM bus to realize direct access of the matrix accelerator to the dual-port SRAM.

3. The matrix accelerator sharing on-chip system memory of claim 1, wherein, The task management module further comprises a user interface submodule, the user interface submodule is composed of an operation start and stop control register, an interrupt enable and clear control register, a status register, and a task queue interface, the user interface submodule is connected to the system bus through an AHB bus and interconnected to the CPU through the AXI protocol, and is configured to complete operation start and stop control of the matrix accelerator, interrupt enable and clear control, and task queue initialization under the control of the CPU.

4. The matrix accelerator sharing on-chip system memory according to claim 3, wherein, The working process of the task queue is as follows: When the task queue receives a start signal sent by the CPU through the user interface submodule, the operation task and the corresponding task control instruction initialized by the CPU in the task queue interface are loaded into the task queue in the order of address increment; wherein, the task queue is managed in a first-in-first-out manner; When the task queue is not empty, the operation task and the corresponding task control instruction located at the first position in the task queue are sent to the data access module; When the task queue detects that the data access module pulls up the task completion signal, it is determined that the current dispatched operation task is completed, the current dispatched operation task is deleted in the task queue, and the corresponding task number is uploaded to the status register of the user interface submodule for the CPU to query the task state information, and at the same time, the user interface submodule generates an interrupt signal according to whether the interrupt reporting enable in the current corresponding task control instruction is high; It is detected whether the task queue is empty, if empty, the matrix operation is stopped, the interrupt signal generated by the user interface submodule notifies the CPU that the operation is completed, if not empty, the operation task and the corresponding task control instruction are continuously dispatched according to the task queue sorting to perform the matrix operation until the task queue is empty.

5. The matrix accelerator sharing the system memory of a chip according to claim 4, characterized in that, The task control instruction is composed of a task number, an interruption report enabling, an operation type selection, an operand matrix X storage address, an operand matrix Y storage address, an operation result storage address, a number of rows of the operand matrix X, a number of columns of the operand matrix X and a number of rows of the operand matrix Y, a number of columns of the operand matrix Y, and an instruction validity identifier.

6. The matrix accelerator sharing on-chip system memory of claim 1, wherein, The matrix operation module comprises an operation input / output control submodule, a floating point multiplication / addition operator, and a floating point division operator. The operation input / output control submodule is configured to receive the operation operation instruction and the matrix operation data sent by the data access module, select the corresponding operator to perform the matrix operation according to the operation operation instruction, and send the matrix operation data to the corresponding operator, obtain the operation result data output by the operator after the operation is completed, and send the operation result data to the data access module. The floating point multiplication / addition operator is configured to receive the matrix operation data sent by the operation input / output control submodule, complete multiplication, addition, and multiplication-accumulation operations according to the corresponding operation operation instruction, and return the operation result data to the operation input / output control submodule. The floating point division operator is configured to receive the matrix operation data sent by the operation input / output control submodule, complete division and reciprocal operations according to the corresponding operation operation instruction, and return the operation result data to the operation input / output control submodule.

7. A method of operating a matrix accelerator sharing a system memory of a chip according to any one of claims 1 to 6, characterized in that, The method comprises the following steps: The CPU prepares matrix operation data in a double-port SRAM of a chip system memory, initializes an operation task and a corresponding task control instruction, and starts a matrix accelerator; wherein the matrix accelerator comprises a system memory module, a task management module, a data access module, and a matrix operation module. After the CPU starts the matrix accelerator, the task queue in the task management module loads the operation task and the task control instruction generated by the CPU based on the operation task, and when the task queue is not empty, the operation task and the corresponding task control instruction are issued to the data access module, the data access module sends the matrix operation data read from the double-port SRAM and the operation operation instruction generated synchronously to the matrix operation module according to the issued operation task and the corresponding task control instruction, the matrix operation module selects the corresponding operator to perform the matrix operation for the input matrix operation data according to the operation operation instruction, and after the operation is completed, the operation result data is written into the double-port SRAM through the data access module, and after the writing of the operation result data is completed, the task completion signal is pulled high through the data access module to indicate that the current issued operation task is completed. It is detected whether the task queue is empty, if not, the operation task and the corresponding task control instruction are continuously issued by the task queue for matrix operation until the task queue is empty; if empty, it is determined that the matrix accelerator completes all operation tasks, an interruption signal is generated by the task management module to notify the CPU that the operation is completed, and the CPU obtains the final matrix operation result from the double-port SRAM.

Images