Pixel circuit, display device and electronic device

Abstract

The invention relates to a pixel circuit, a display device and an electronic device. The pixel circuit includes: a light emitting element; a driving transistor configured to apply a driving current to the light emitting element; a storage capacitor including a first electrode connected to a gate electrode of the driving transistor, and a second electrode; and a boost capacitor including a first electrode receiving a gate control signal and a second electrode connected to the gate electrode of the driving transistor. The gate control signal changes from a first level to a second level at a start point of a boost period in a non-emission period, and changes from the second level to the first level at an end point of the boost period.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a pixel circuit, a display device including the pixel circuit, and an electronic device including the display device. More particularly, the present disclosure relates to a pixel circuit for preventing deterioration of a driving transistor and a display device including the pixel circuit. BACKGROUND

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel includes gate lines, data lines, emission lines, and pixel circuits. The display panel driver includes a gate driver for providing a gate signal to the gate lines, a data driver for providing a data voltage to the data lines, an emission driver for providing an emission signal to the emission lines, and a driving controller for controlling the gate driver, the data driver, and the emission driver.

[0003] The pixel circuit can include a light emitting element and a driving transistor. The driving transistor can be turned on based on a voltage of a gate electrode of the driving transistor to apply a driving current to the light emitting element. The light emitting element can emit light based on the driving current. As the driving transistor is turned on and used, the driving transistor can deteriorate.

[0004] Even in a non-emission period in which the driving current does not flow to the light emitting element and the light emitting element does not emit light, the driving transistor can be turned on based on the voltage of the gate electrode of the driving transistor, and thus the driving transistor can deteriorate.

[0005] DISCLOSURE

[0006] An embodiment of the present disclosure provides a pixel circuit for preventing deterioration of a driving transistor.

[0007] An embodiment of the present disclosure provides a display device including the pixel circuit.

[0008] In one or more embodiments of the present disclosure, a pixel circuit includes a light emitting element, a driving transistor configured to apply a driving current to the light emitting element, a storage capacitor including a first electrode connected to a gate electrode of the driving transistor and a second electrode, and a boost capacitor including a first electrode receiving a gate control signal and a second electrode connected to the gate electrode of the driving transistor. The gate control signal changes from a first level to a second level at a start point of a boost period in a non-emission period, and changes from the second level to the first level at an end point of the boost period.

[0009] In one or more embodiments, when the gate control signal changes from the first level to the second level, the voltage of the gate electrode of the driving transistor can change by an amount of a boost voltage corresponding to a difference between the first level and the second level, and the driving transistor can be turned off based on a threshold voltage of the driving transistor.

[0010] In one or more embodiments, the voltage of the gate electrode of the driving transistor can change by the amount of the boost voltage when the gate control signal changes from the first level to the second level or from the second level to the first level.

[0011] In one or more embodiments, the voltage of the gate electrode of the driving transistor immediately before the starting point of the boost period can be equal to the voltage of the gate electrode of the driving transistor immediately after the ending point of the boost period.

[0012] In one or more embodiments, the first level can be lower than the second level when the driving transistor is a P-type transistor.

[0013] In one or more embodiments, the voltage of the gate electrode of the driving transistor can increase by the amount of the boost voltage when the gate control signal changes from the first level to the second level.

[0014] In one or more embodiments, the voltage of the gate electrode of the driving transistor can decrease by the amount of the boost voltage when the gate control signal changes from the second level to the first level.

[0015] In one or more embodiments, the driving transistor can include a gate electrode connected to the gate node, a first electrode connected to the first node, and a second electrode connected to the second node, the storage capacitor can include a first electrode connected to the gate node and a second electrode configured to receive the first driving voltage, the second electrode of the boost capacitor is connected to the gate node, and the light emitting element can include an anode electrode and a cathode electrode configured to receive the second driving voltage.

[0016] In one or more embodiments, the pixel circuit further includes: a data write transistor including a gate electrode configured to receive a data write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the first node; a compensation transistor including a gate electrode configured to receive the data write gate signal, a first electrode connected to the second node, and a second electrode connected to the gate node; a data initialization transistor including a gate electrode configured to receive a data initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the gate node; a first emission transistor including a gate electrode configured to receive an emission signal, a first electrode configured to receive the first driving voltage, and a second electrode connected to the first node; a second emission transistor including a gate electrode configured to receive the emission signal, a first electrode connected to the second node, and a second electrode connected to the anode electrode; and an anode initialization transistor including a gate electrode configured to receive an anode initialization gate signal, a first electrode configured to receive the initialization voltage, and a second electrode connected to the anode electrode.

[0017] In one or more embodiments, the non-emission period can not include the on-voltage period of the emission signal, and the emission period can include the on-voltage period of the emission signal.

[0018] In one or more embodiments, the non-emission period and the non-boost period in the emission period can include the on-voltage period of the data write gate signal, the on-voltage period of the data initialization gate signal, the on-voltage period of the emission signal, and the on-voltage period of the anode initialization gate signal.

[0019] In one or more embodiments, when the driving transistor is an N-type transistor, the first level can be higher than the second level.

[0020] In one or more embodiments, when the gate control signal changes from the first level to the second level, the voltage of the gate electrode of the driving transistor can decrease by an amount of the boost voltage.

[0021] In one or more embodiments, when the gate control signal changes from the second level to the first level, the voltage of the gate electrode of the driving transistor can increase by an amount of the boost voltage.

[0022] In one or more embodiments, the driving transistor can include a gate electrode connected to the gate node, a first electrode connected to the first node, a second electrode connected to the second node, and a back gate electrode connected to the second node, the storage capacitor can include a first electrode connected to the gate node and a second electrode connected to the second node, the second electrode of the boost capacitor is connected to the gate node, and the light emitting element can include an anode electrode and a cathode electrode configured to receive the second driving voltage.

[0023] In one or more embodiments, the pixel circuit further includes: a data write transistor including a gate electrode configured to receive a data write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the gate node; a reference voltage transistor including a gate electrode configured to receive a reference voltage gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the gate node; an anode initialization transistor including a gate electrode configured to receive an anode initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the anode electrode; an emission transistor including a gate electrode configured to receive an emission gate signal, a first electrode configured to receive a first driving voltage, and a second electrode connected to the first node; and a holding capacitor including a first electrode configured to receive the first driving voltage and a second electrode connected to the second node.

[0024] In one or more embodiments, the emission period can include the on-voltage period of the emission gate signal.

[0025] In one or more embodiments, the non-boost period in the non-emission period can include a turn-on voltage period of the data write gate signal, a turn-on voltage period of the reference voltage gate signal, a turn-on voltage period of the anode initialization gate signal, and a turn-on voltage period of the emission gate signal.

[0026] In one or more embodiments of a display device according to the inventive concept, a display device includes a display panel including a pixel circuit, and a display panel driver configured to drive the display panel. The pixel circuit includes a light emitting element, a driving transistor configured to apply a driving current to the light emitting element, a storage capacitor including a first electrode connected to a gate electrode of the driving transistor and a second electrode, and a boost capacitor including a first electrode configured to receive a gate control signal and a second electrode connected to the gate electrode of the driving transistor. The gate control signal changes from a first level to a second level at a start point of a boost period in a non-emission period, and changes from the second level to the first level at an end point of the boost period.

[0027] In one or more embodiments, when the gate control signal changes from the first level to the second level, a voltage of the gate electrode of the driving transistor can change by an amount of a boost voltage corresponding to a difference between the first level and the second level, and the driving transistor is turned off based on a threshold voltage of the driving transistor.

[0028] In one or more embodiments, an electronic device includes a display device including a display panel including a pixel circuit, and a display panel driver configured to drive the display panel, wherein the pixel circuit includes a light emitting element, a driving transistor configured to apply a driving current to the light emitting element, a storage capacitor including a first electrode connected to a gate electrode of the driving transistor and a second electrode, and a boost capacitor including a first electrode configured to receive a gate control signal and a second electrode connected to the gate electrode of the driving transistor, wherein the gate control signal changes from a first level to a second level at a start point of a boost period in a non-emission period, and changes from the second level to the first level at an end point of the boost period, and wherein, when the driving transistor is a P-type transistor, the first level is lower than the second level.

[0029] The electronic device includes a cellular phone, a video phone, a smart pad, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop computer, or a head-mounted display (HMD) device.

[0030] According to a pixel circuit and a display device including the pixel circuit, the pixel circuit may include a boost capacitor including a first electrode configured to receive a gate control signal and a second electrode connected to the gate electrode of a drive transistor. The voltage of the gate electrode of the drive transistor may be changed based on the gate control signal during a boost period in a non-emission period, and the drive transistor may be turned off during the boost period. Therefore, degradation of the drive transistor can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] FIG. 1 is a block diagram illustrating a display device according to one or more embodiments of the present disclosure;

[0033] FIG. 2 It shows FIG. 1 A circuit diagram of an example of a pixel circuit;

[0034] FIG. 3 It shows FIG. 2 A timing diagram of a gate signal, an emission signal, and a gate control signal of a pixel circuit;

[0035] FIG. 4A It shows FIG. 2 The pixel circuit in FIG. 3 a circuit diagram for operating during a first time period;

[0036] FIG. 4B It shows FIG. 2 The pixel circuit in FIG. 3 a circuit diagram for operating during a second time period;

[0037] FIG. 4C It shows FIG. 2 The pixel circuit in FIG. 3 A circuit diagram of the operation during the transmission cycle;

[0038] FIG. 4D It shows FIG. 2 The pixel circuit in FIG. 3 A circuit diagram of operation at the starting point of a boost cycle;

[0039] FIG. 4E It shows FIG. 2 The pixel circuit in FIG. 3 A circuit diagram of operation at the end point of a boost cycle;

[0040] FIG. 5 It shows FIG. 1 A circuit diagram of an example of a pixel circuit;

[0041] FIG. 6 is a timing chart showing gate signals and gate control signals of the pixel circuit of FIG. 5

[0042] FIG. 7A is a circuit diagram showing the pixel circuit of FIG. 5 operating in a first time period of FIG. 6

[0043] FIG. 7B FIG. 5 is a circuit diagram showing the pixel circuit of FIG. 6 operating in a second time period of

[0044] FIG. 7C FIG. 5 is a circuit diagram showing the pixel circuit of FIG. 6 operating in a third time period of

[0045] FIG. 7D FIG. 5 is a circuit diagram showing the pixel circuit of FIG. 6 operating in a fourth time period of

[0046] FIG. 7E FIG. 5 is a circuit diagram showing the pixel circuit of FIG. 6 operating in an emission period of

[0047] FIG. 7F FIG. 5 is a circuit diagram showing the pixel circuit of FIG. 6 operating at a starting point of a boost period of

[0048] FIG. 7G FIG. 5 is a circuit diagram showing the pixel circuit of FIG. 6 operating at an ending point of a boost period of

[0049] FIG. 8 is a block diagram showing an electronic device; and

[0050] FIG. 9 is a diagram showing an embodiment in which the electronic device of FIG. 8 is implemented as a smart phone. DETAILED DESCRIPTION

[0051] Hereinafter, the present disclosure will be described in greater detail with reference to the accompanying drawings.

[0052] ​​​​​​​​In view of the entire disclosure, those of ordinary skill in the art will appreciate that each suitable feature of various embodiments of the present disclosure can be combined, in part or in whole, with each other, unless otherwise stated or implied, and can be technically interlocked and operated in various suitable ways, and each embodiment can be implemented independently of each other or in combination with each other in any suitable manner.

[0053] FIG. 1 is a block diagram illustrating a display device 10 according to one or more embodiments of the present disclosure.

[0054] Referring to FIG. 1 , the display device 10 can include a display panel 100 and a display panel driver. The display panel driver can include a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0055] For example, the driving controller 200 and the data driver 500 can be integrally formed. For example, the driving controller 200, the gamma reference voltage generator 400, and the data driver 500 can be integrally formed. For example, the driving controller 200, the gate driver 300, the gamma reference voltage generator 400, and the data driver 500 can be integrally formed. For example, the driving controller 200, the gate driver 300, the gamma reference voltage generator 400, the data driver 500, and the emission driver 600 can be integrally formed. In one or more embodiments, a driving module in which at least the driving controller 200 and the data driver 500 are integrally formed can be referred to as a timing controller embedded data driver (TED).

[0056] The display panel 100 can include a display area for displaying an image and a peripheral area disposed adjacent to the display area.

[0057] For example, the display panel 100 can be an organic light emitting diode (OLED) display panel including an organic light emitting diode (OLED). For another example, the display panel 100 can be a quantum dot organic light emitting diode display panel including an organic light emitting diode (OLED) and a quantum dot (QD) color filter. For another example, the display panel 100 can be a quantum dot nano light emitting diode display panel including a nano light emitting diode and a quantum dot color filter. For another example, the display panel 100 can be a liquid crystal display panel including a liquid crystal layer.

[0058] The display panel 100 can include gate lines GL, data lines DL, emission lines EML, and pixel circuits P electrically connected to the gate lines GL, the data lines DL, and the emission lines EML, respectively. The gate lines GL can extend in a first direction, the data lines DL can extend in a second direction crossing the first direction, and the emission lines EML can extend in the first direction.

[0059] The driving controller 200 can receive input image data IMG and input control signals CONT from an external device. For example, the input image data IMG can include red image data, green image data, and blue image data. The input image data IMG can include white image data. The input image data IMG can include magenta image data, yellow image data, and cyan image data. The input control signals CONT can include a main clock signal and a data enable signal. The input control signals CONT can further include a vertical synchronization signal and a horizontal synchronization signal.

[0060] The driving controller 200 can generate first control signals CONT1, second control signals CONT2, third control signals CONT3, fourth control signals CONT4, and data signals DATA based on the input image data IMG and the input control signals CONT.

[0061] The driving controller 200 can generate first control signals CONT1 for controlling operations of the gate driver 300 based on the input control signals CONT, and output the first control signals CONT1 to the gate driver 300. The first control signals CONT1 can include a vertical start signal and a gate clock signal.

[0062] The driving controller 200 can generate second control signals CONT2 for controlling operations of the data driver 500 based on the input control signals CONT, and output the second control signals CONT2 to the data driver 500. The second control signals CONT2 can include a horizontal start signal and a load signal.

[0063] The driving controller 200 can generate data signals DATA based on the input image data IMG. The driving controller 200 can output the data signals DATA to the data driver 500.

[0064] The driving controller 200 can generate third control signals CONT3 for controlling operations of the gamma reference voltage generator 400 based on the input control signals CONT, and output the third control signals CONT3 to the gamma reference voltage generator 400.

[0065] The driving controller 200 can generate a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and output the fourth control signal CONT4 to the emission driver 600.

[0066] The gate driver 300 can generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 can output the gate signal to the gate line GL.

[0067] In one or more embodiments, the gate driver 300 can be integrated in a peripheral area of the display panel 100.

[0068] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 can provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF can have a value corresponding to each data signal DATA.

[0069] For example, the gamma reference voltage generator 400 can be provided in the driving controller 200, or can be provided in the data driver 500.

[0070] The data driver 500 can receive the second control signal CONT2 and the data signal DATA from the driving controller 200, and receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can convert the data signal DATA into a data voltage having an analog type using the gamma reference voltage VGREF. The data driver 500 can output the data voltage to the data line DL.

[0071] The emission driver 600 can generate an emission signal for driving the emission line EML in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 can output the emission signal to the emission line EML.

[0072] In one or more embodiments, the emission driver 600 can be integrated into a peripheral area of the display panel 100. In one or more embodiments, the emission driver 600 can be mounted in a peripheral area of the display panel 100.

[0073] In FIG. 1In the middle, in order to facilitate the description, the gate driver 300 can be disposed at the first side of the display panel 100, and the emission driver 600 can be disposed at the second side of the display panel 100. Although it is shown, the present disclosure is not limited thereto. For example, both the gate driver 300 and the emission driver 600 can be disposed at the first side of the display panel 100. For example, both the gate driver 300 and the emission driver 600 can be disposed at both sides of the display panel 100. For example, the gate driver 300 and the emission driver 600 can be integrally formed.

[0074] FIG. 2 is a circuit diagram illustrating an example of the pixel circuit P. FIG. 1

[0075] Referring to FIG. 2 According to one or more embodiments of the present disclosure, the pixel circuit P can include the light emitting element EE, the driving transistor T1, the storage capacitor CST, and the boost capacitor CB. The pixel circuit P can further include the data write transistor T2, the compensation transistor T3, the data initialization transistor T4, the first emission transistor T5, the second emission transistor T6, and the anode initialization transistor T7. In one or more embodiments, the driving transistor T1, the data write transistor T2, the compensation transistor T3, the data initialization transistor T4, the first emission transistor T5, the second emission transistor T6, and the anode initialization transistor T7 can be P-type transistors. When a voltage of a gate electrode of the P-type transistor has a low level, the P-type transistor can be turned on. When the voltage of the gate electrode of the P-type transistor has a high level, the P-type transistor can be turned off.

[0076] The driving transistor T1 can include a gate electrode connected to the gate node NG, a first electrode connected to the first node N1, and a second electrode connected to the second node N2.

[0077] The data write transistor T2 can include a gate electrode receiving a data write gate signal GW, a first electrode receiving a data voltage VDATA, and a second electrode connected to the first node N1.

[0078] The compensation transistor T3 can include a gate electrode receiving the data write gate signal GW, a first electrode connected to the second node N2, and a second electrode connected to the gate node NG.

[0079] The data initialization transistor T4 can include a gate electrode receiving a data initialization gate signal GI, a first electrode receiving an initialization voltage VINT, and a second electrode connected to the gate node NG.

[0080] The first emission transistor T5 can include a gate electrode receiving an emission signal EM, a first electrode receiving a first driving voltage VDD, and a second electrode connected to the first node N1.​

[0081] The second transistor T6 can include a gate electrode receiving the emission signal EM, a first electrode connected to the second node N2, and a second electrode connected to the anode electrode of the light emitting element EE.

[0082] The anode initialization transistor T7 can include a gate electrode receiving the anode initialization gate signal GB, a first electrode receiving the initialization voltage VINT, and a second electrode connected to the anode electrode of the light emitting element EE.

[0083] The storage capacitor CST can include a first electrode connected to the gate node NG and a second electrode receiving the first driving voltage VDD.

[0084] The boost capacitor CB can include a first electrode receiving the gate control signal GTF and a second electrode connected to the gate node NG.

[0085] The light emitting element EE can include an anode electrode and a cathode electrode receiving the second driving voltage VSS. For example, the light emitting element EE can be a micro light emitting diode (Micro LED), an organic light emitting diode (OLED), a nano light emitting diode (nano-LED), a quantum dot (QD) light emitting diode, an inorganic light emitting diode, or any other suitable light emitting element.

[0086] The configuration of the pixel circuit P according to one or more embodiments of the disclosure is not limited to the example shown in FIG. 2 . FIG. 2 is an example for describing a pixel circuit P including a driving transistor T1 that is a P-type transistor. Accordingly, the configuration of the pixel circuit P according to one or more embodiments of the disclosure can have any configuration in which the driving transistor T1 is a P-type transistor.

[0087] FIG. 3 is a timing diagram of the gate signals GW, GI, GB, the emission signal EM, and the gate control signal GTF of the pixel circuit P of FIG. 2 .

[0088] Referring to FIG. 2 and FIG. 3 , a frame period FP for the pixel circuit P can include an emission period EP and a non-emission period NEP. The non-emission period NEP can include a portion of a non-boost period NBP and a boost period BP. The non-boost period NBP can include a first time period TP1 and a second time period TP2.

[0089] The emission period EP can include a turn-on voltage period of the emission signal EM, and the non-emission period NEP can not include the turn-on voltage period of the emission signal EM. The emission signal EM can have a low level in the emission period EP, and can have a high level in the non-emission period NEP. The emission period EP can be a period in which the drive current ID flows to the light emitting element EE and the light emitting element EE emits light based on the drive current ID, and the non-emission period NEP can be a period in which the drive current ID does not flow to the light emitting element EE and the light emitting element EE does not emit light based on the drive current ID.

[0090] The gate control signal GTF can have a first level L1 in the non-boost period NBP, can change from the first level L1 to a second level L2 at a start point BP_S of the boost period BP, can have the second level L2 in the boost period BP, and can change from the second level L2 to the first level L1 at an end point BP_E of the boost period BP. When the drive transistor T1 is a P-type transistor, the first level L1 can be lower than the second level L2. A voltage corresponding to a difference between the first level L1 and the second level L2 can be referred to as a boost voltage VB. Here, the boost voltage VB can be determined based on a voltage distribution of capacitors (e.g., a storage capacitor CST, a boost capacitor CB, and a parasitic capacitor) connected to the gate node NG. The non-boost period NBP can be a period in which a voltage of a gate electrode of the drive transistor T1 is not boosted, and the boost period BP can be a period in which the voltage of the gate electrode of the drive transistor T1 is boosted by the boost voltage VB.

[0091] The non-boost period NBP can include a turn-on voltage period of the data write gate signal GW, a turn-on voltage period of the data initialization gate signal GI, a turn-on voltage period of the emission signal EM, and a turn-on voltage period of the anode initialization gate signal GB.

[0092] The first time period TP1 can include a turn-on voltage period of the data initialization gate signal GI. The data initialization gate signal GI can have a low level in the first time period TP1, and can have a high level in the frame period FP except for the first time period TP1.

[0093] The second time period TP2 can include a turn-on voltage period of the data write gate signal GW and a turn-on voltage period of the anode initialization gate signal GB. The data write gate signal GW and the anode initialization gate signal GB can have a low level in the second time period TP2, and can have a high level in the frame period FP except for the second time period TP2.

[0094] In one or more embodiments, when the light emitting element EE is a micro light emitting diode, the emission signal EM can include a turn-on voltage period that does not overlap each other for each of a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0095] FIG. 4A is a circuit diagram illustrating operation of the pixel circuit P in a first time period TP1 of FIG. 2 FIG. 3 is a circuit diagram illustrating operation of the pixel circuit P in a second time period TP2 of

[0096] Referring to FIG. 2 to FIG. 4A , the data initialization transistor T4 can be turned on in response to the data initialization gate signal GI having a low level. The data initialization transistor T4 can apply the initialization voltage VINT to the gate electrode of the driving transistor T1. Accordingly, the voltage of the gate electrode of the driving transistor T1 can be initialized with the initialization voltage VINT.

[0097] FIG. 4B is a circuit diagram illustrating operation of the pixel circuit P in a second time period TP2 of FIG. 2 FIG. 3 is a circuit diagram illustrating operation of the pixel circuit P in a second time period TP2 of

[0098] Referring to FIG. 2 to FIG. 4B , the data write transistor T2 can be turned on in response to the data write gate signal GW having a low level, and the compensation transistor T3 can be turned on in response to the data write gate signal GW having a low level.

[0099] The data voltage VDATA can be applied to the second node N2 through the data write transistor T2 and the driving transistor T1. The compensation transistor T3 can diode-connect the driving transistor T1 to compensate for a threshold voltage (VTH) of the driving transistor T1, and can apply a voltage obtained by adding the threshold voltage (VTH) of the driving transistor T1 to the data voltage VDATA to the gate electrode of the driving transistor T1. That is, the voltage of the gate electrode of the driving transistor T1 can be VDATA+VTH. The storage capacitor CST can store the voltage of the gate electrode of the driving transistor T1.

[0100] The anode initialization transistor T7 can be turned on in response to the anode initialization gate signal GB having a low level. The anode initialization transistor T7 can apply the initialization voltage VINT to the anode electrode of the light emitting element EE. Accordingly, the voltage of the anode electrode of the light emitting element EE can be initialized with the initialization voltage VINT.

[0101] FIG. 4C is a circuit diagram illustrating operation of the pixel circuit P in a second time period TP2 of FIG. 2 FIG. 3 is a circuit diagram illustrating operation of the pixel circuit P in a second time period TP2 of

[0102] Referring to​​​FIG. 2 to FIG. 4C The first emission transistor T5 can turn on in response to the emission signal EM having a low level, and the second emission transistor T6 can turn on in response to the emission signal EM having a low level.

[0103] The drive current ID can flow in the order of the first emission transistor T5, the drive transistor T1, and the second emission transistor T6, and can be applied to the light emitting element EE. The light emitting element EE can emit light based on the drive current ID. The intensity of the drive current ID can be determined based on the level of the data voltage VDATA. The luminance of the light emitting element EE can be determined based on the intensity of the drive current ID.

[0104] FIG. 4D is a circuit diagram illustrating that the pixel circuit P of FIG. 2 operates at the start point BP_S of the boost period BP of FIG. 3 . FIG. 4E is a circuit diagram illustrating that the pixel circuit P of FIG. 2 operates at the end point BP_E of the boost period BP of FIG. 3 .

[0105] Referring to FIG. 2 to FIG. 4E , the drive transistor T1 can turn on based on the voltage of the gate electrode of the drive transistor T1 even in a non-emission period NEP in which the drive current ID does not flow to the light emitting element EE and thus the light emitting element EE does not emit light. This is because the storage capacitor CST stores the voltage corresponding to the data voltage VDATA. The drive transistor T1 can further deteriorate when the drive transistor T1 maintains the on state. Accordingly, the non-emission period NEP includes the boost period BP, and thus deterioration of the drive transistor T1 can be prevented.

[0106] When the gate control signal GTF changes from the first level L1 to the second level L2 at the start point BP_S of the boost period BP, the voltage of the gate electrode of the drive transistor T1 can increase by the amount of the boost voltage VB through the boost capacitor CB. That is, the voltage of the gate electrode of the drive transistor T1 can increase from VNG to VNG+VB. When the voltage of the gate electrode of the drive transistor T1 increases by the amount of the boost voltage VB, the drive transistor T1 can be turned off according to the voltage of the gate electrode of the drive transistor T1. When the voltage of the gate electrode of the drive transistor T1 is greater than the threshold voltage (VTH) of the drive transistor T1, the drive transistor T1 can be turned off. In order for the drive transistor T1 to be turned off, the size of the boost voltage VB can be large enough.

[0107] In the boost period BP, the gate control signal GTF can hold the second level L2. Because the gate control signal GTF holds the second level L2, the drive transistor T1 can hold the off state, and deterioration of the drive transistor T1 can be prevented.

[0108] When the gate control signal GTF changes from the second level L2 to the first level L1 at the end point BP E of the boost period BP, the voltage of the gate electrode of the drive transistor T1 can be reduced by the amount of the boost voltage VB by the boost capacitor CB. That is, the voltage of the gate electrode of the drive transistor T1 can be reduced from VNG+VB to VNG. When the voltage of the gate electrode of the drive transistor T1 is reduced by the amount of the boost voltage VB, the drive transistor T1 can be turned on.

[0109] Because the voltage of the gate electrode of the drive transistor T1 before (e.g., immediately before) the start point BP S of the boost period BP is VNG, and the voltage of the gate electrode of the drive transistor T1 after (e.g., immediately after) the end point BP E of the boost period BP is VNG, the voltage of the gate electrode of the drive transistor T1 before (e.g., immediately before) the start point BP S of the boost period BP can be equal to the voltage of the gate electrode of the drive transistor T1 after (e.g., immediately after) the end point BP E of the boost period BP. Thus, even if the frame period FP includes the boost period BP, the voltage of the gate electrode of the drive transistor T1 can be the same based on before and after the boost period BP.

[0110] Thus, the pixel circuit P can include a boost capacitor CB including a first electrode that receives the gate control signal GTF and a second electrode connected to the gate electrode of the drive transistor T1. The voltage of the gate electrode of the drive transistor T1 can change based on the gate control signal GTF included in the boost period BP included in the non-emission period NEP, and the drive transistor T1 can be off in the boost period BP. Thus, deterioration of the drive transistor T1 can be prevented.

[0111] FIG. 5 is a circuit diagram illustrating an example of the pixel circuit Pa of FIG. 1 .

[0112] Referring to FIG. 5According to one or more embodiments of the present disclosure, the pixel circuit Pa can include a light emitting element EE', a driving transistor T1', a storage capacitor CST', and a boost capacitor CB'. The pixel circuit Pa can further include a data write transistor T2', a reference voltage transistor T3', an anode initialization transistor T4', an emission transistor T5', and a holding capacitor CH'. In one or more embodiments, the driving transistor T1', the data write transistor T2', the reference voltage transistor T3', the anode initialization transistor T4', and the emission transistor T5' can be N-type transistors. When a voltage of a gate electrode of the N-type transistor has a high level, the N-type transistor can be turned on. When the voltage of the gate electrode of the N-type transistor has a low level, the N-type transistor can be turned off.

[0113] The driving transistor T1' can include a gate electrode connected to the gate node NG', a first electrode connected to the first node N1', a second electrode connected to the second node N2', and a back gate electrode connected to the second node N2'.

[0114] The data write transistor T2' can include a gate electrode receiving a data write gate signal GW', a first electrode receiving a data voltage VDATA', and a second electrode connected to the gate node NG'.

[0115] The reference voltage transistor T3' can include a gate electrode receiving a reference voltage gate signal GR', a first electrode receiving a reference voltage VREF', and a second electrode connected to the gate node NG'.

[0116] The anode initialization transistor T4' can include a gate electrode receiving an anode initialization gate signal GB', a first electrode receiving an initialization voltage VINT', and a second electrode connected to an anode electrode of the light emitting element EE'.

[0117] The emission transistor T5' can include a gate electrode receiving an emission gate signal GE', a first electrode receiving a first driving voltage VDD', and a second electrode connected to the first node N1'.

[0118] The storage capacitor CST' can include a first electrode connected to the gate node NG' and a second electrode connected to the second node N2'.

[0119] The boost capacitor CB' can include a first electrode receiving a gate control signal GTF' and a second electrode connected to the gate node NG'.

[0120] The holding capacitor CH' can include a first electrode receiving the first driving voltage VDD' and a second electrode connected to the second node N2'.

[0121] Because the back-gate electrode of the drive transistor T1' and the sustain capacitor CH' are connected to the second node N2', the voltage of the back-gate electrode of the drive transistor T1' can be controlled. Accordingly, the body effect in which the threshold voltage of the drive transistor T1' changes can be reduced or minimized. That is, the threshold voltage compensation capability of the pixel circuit Pa can be improved.

[0122] The light emitting element EE' can include an anode electrode and a cathode electrode that receives the second drive voltage VSS'. For example, the light emitting element EE' can be a micro light emitting diode (Micro LED), an organic light emitting diode (OLED), a nano light emitting diode (nano-LED), a quantum dot (QD) light emitting diode, an inorganic light emitting diode, or any other suitable light emitting element.

[0123] The configuration of the pixel circuit Pa according to one or more embodiments of the disclosure is not limited to FIG. 5 the example shown in FIG. 1. FIG. 5 is an example for describing the pixel circuit Pa including the drive transistor T1' that is an N-type transistor. The configuration of the pixel circuit Pa according to one or more embodiments of the disclosure can have any configuration in which the drive transistor T1' is an N-type transistor.

[0124] FIG. 6 is a timing chart showing the gate signals GW', GR', GB', GE', and the gate control signal GTF' of the pixel circuit Pa of FIG. 5 FIG. 1.

[0125] Referring to FIG. 5 and FIG. 6 , referring also to FIG. 7E , the frame period FP' for the pixel circuit Pa can include an emission period EP' and a non-emission period NEP'. The non-emission period NEP' can include a portion of a non-boost period NBP' and a boost period BP'. The non-boost period NBP' can include a first time period TP1', a second time period TP2', a third time period TP3', and a fourth time period TP4'.

[0126] The emission period EP' can include a conduction voltage period in which the emission gate signal GE' is emitted. The emission gate signal GE' can have a high level in the emission period EP'. The emission period EP' can be a period in which the drive current ID' flows to the light emitting element EE' and the light emitting element EE' emits light based on the drive current ID', and the non-emission period NEP' can be a period in which the drive current ID' does not flow to the light emitting element EE' and the light emitting element EE' does not emit light based on the drive current ID'.

[0127] The gate control signal GTF' can have a first level L1' in the non-boost period NBP', can change from the first level L1' to a second level L2' at a start point BP_S' of the boost period BP', can have the second level L2' in the boost period BP', and can change from the second level L2' to the first level L1' at an end point BP_E' of the boost period BP'. When the driving transistor T1' is an N-type transistor, the first level L1' can be higher than the second level L2'. A difference between the first level L1' and the second level L2' can be referred to as a boost voltage VB'. The non-boost period NBP' can be a period in which a voltage of a gate electrode of the driving transistor T1' is not boosted, and the boost period BP' can be a period in which the voltage of the gate electrode of the driving transistor T1' is boosted by the boost voltage VB'.

[0128] The non-boost period NBP' can include a turn-on voltage period of the data write gate signal GW', a turn-on voltage period of the reference voltage gate signal GR', a turn-on voltage period of the anode initialization gate signal GB', and a turn-on voltage period of the emission gate signal GE'.

[0129] The first time period TP1' can overlap with the second time period TP2' and the third time period TP3'. The first time period TP1' can include a turn-on voltage period of the reference voltage gate signal GR'. The reference voltage gate signal GR' can have a high level in the first time period TP1' and can have a low level in the frame period FP' except for the first time period TP1'.

[0130] The second time period TP2' can include a turn-on voltage period of the anode initialization gate signal GB'. The anode initialization gate signal GB' can have a high level in the second time period TP2' and can have a low level in the frame period FP' except for the second time period TP2'.

[0131] The third time period TP3' can include a turn-on voltage period of the emission gate signal GE'. The emission gate signal GE' can have a high level in the third time period TP3' and can have a low level in the frame period FP' except for the third time period TP3'.

[0132] The fourth time period TP4' can include a turn-on voltage period of the data write gate signal GW'. The data write gate signal GW' can have a high level in the fourth time period TP4' and can have a low level in the frame period FP' except for the fourth time period TP4'.

[0133] FIG. 7A is a pixel circuit Pa FIG. 5 is a pixel circuit Pa FIG. 6a circuit diagram showing operation of the pixel circuit Pa of FIG. 1 in a first time period TP1.

[0134] Referring to FIG. 2, FIG. 5 to FIG. 7A The reference voltage transistor T3' can be turned on in response to the reference voltage gate signal GR' having a high level, and the anode initialization transistor T4' can be turned on in response to the anode initialization gate signal GB' having a high level. The reference voltage transistor T3' can apply the reference voltage VREF' to the gate electrode of the driving transistor T1', and the anode initialization transistor T4' can apply the initialization voltage VINT' to the anode electrode of the light emitting element EE'. Accordingly, the voltage of the second electrode of the driving transistor T1' can be VINT'.

[0135] FIG. 7B a circuit diagram showing operation of the pixel circuit Pa of FIG. 1 in a second time period TP2. FIG. 5 FIG. 6 a circuit diagram showing operation of the pixel circuit Pa of FIG. 1 in a third time period TP3.

[0136] Referring to FIG. 3, FIG. 5 to FIG. 7B The reference voltage transistor T3' can be turned on in response to the reference voltage gate signal GR' having a high level, and the anode initialization transistor T4' can be turned on in response to the anode initialization gate signal GB' having a high level. The reference voltage transistor T3' can apply the reference voltage VREF' to the gate electrode of the driving transistor T1', and the anode initialization transistor T4' can apply the initialization voltage VINT' to the anode electrode of the light emitting element EE'. Accordingly, the voltage of the second electrode of the driving transistor T1' can be VINT'.

[0137] FIG. 7C a circuit diagram showing operation of the pixel circuit Pa of FIG. 1 in a second time period TP2. FIG. 5 FIG. 6 a circuit diagram showing operation of the pixel circuit Pa of FIG. 1 in a third time period TP3.

[0138] Referring to FIG. 4, FIG. 5 to FIG. 7C The reference voltage transistor T3' can be turned on in response to the reference voltage gate signal GR' having a high level, and the anode initialization transistor T4' can be turned on in response to the anode initialization gate signal GB' having a high level. The reference voltage transistor T3' can apply the reference voltage VREF' to the gate electrode of the driving transistor T1', and the anode initialization transistor T4' can apply the initialization voltage VINT' to the anode electrode of the light emitting element EE'. Accordingly, the voltage of the second electrode of the driving transistor T1' can be VINT'.

[0139] FIG. 7D a circuit diagram showing operation of the pixel circuit Pa of FIG. 1 in a second time period TP2. FIG. 5 ​​The pixel circuit Pa is FIG. 6 1 '.

[0140] refer to FIG. 5 to FIG. 7D , the data write transistor T2 ′ may be turned on in response to the data write gate signal GW′ having a high level.

[0141] The data writing transistor T2 ′ may apply the data voltage VDATA′ to the gate electrode of the driving transistor T1 ′.

[0142] FIG. 7E It shows FIG. 5 The pixel circuit Pa is FIG. 6 Circuit diagram of the operation during the emission period EP'.

[0143] refer to FIG. 5 to FIG. 7E , the emission transistor T5′ may be turned on in response to the emission gate signal GE′ having a high level.

[0144] The driving current ID' may flow in the order of the emission transistor T5' and the driving transistor T1' and may be applied to the light-emitting element EE'. The light-emitting element EE' may emit light based on the driving current ID'. The intensity of the driving current ID' may be determined based on the level of the data voltage VDATA'. The brightness of the light-emitting element EE' may be determined based on the intensity of the driving current ID'.

[0145] FIG. 7F It shows FIG. 5 The pixel circuit Pa is FIG. 6 A circuit diagram showing the operation at the starting point BP_S' of the boost period BP'. FIG. 7G It shows FIG. 5 The pixel circuit Pa is FIG. 6 1 , which is a circuit diagram of the circuit operating at the end point BP_E' of the boost period BP'.

[0146] refer to FIG. 5 to FIG. 7F Even during the non-emission period NEP', when the drive current ID' does not flow to the light-emitting element EE' and the light-emitting element EE' does not emit light, the drive transistor T1' can be turned on based on the voltage of the gate electrode of the drive transistor T1'. This is because the storage capacitor CST' stores the voltage corresponding to the data voltage VDATA'. While the drive transistor T1 remains turned on, the drive transistor T1 may further degrade. Therefore, the non-emission period NEP' includes the voltage boost period BP', thereby preventing degradation of the drive transistor T1'.

[0147] When the gate control signal GTF' changes from the first level L1' to the second level L2' at the start point BP_S' of the boost period BP', the voltage of the gate electrode of the drive transistor T1' can be reduced by the amount of the boost voltage VB' through the boost capacitor CB'. That is, the voltage of the gate electrode of the drive transistor T1' can be reduced from VNG' to VNG'-VB'. When the voltage of the gate electrode of the drive transistor T1' is reduced by the amount of the boost voltage VB', the drive transistor T1' can be turned off. To turn off the drive transistor T1', the size of the boost voltage VB' can be large enough.

[0148] In the boost period BP', the gate control signal GTF' can maintain the second level L2'. Because the gate control signal GTF' maintains the second level L2', the drive transistor T1' can maintain the off state, and deterioration of the drive transistor T1' can be prevented.

[0149] When the gate control signal GTF' changes from the second level L2' to the first level L1' at the end point BP_E' of the boost period BP', the voltage of the gate electrode of the drive transistor T1' can be increased by the amount of the boost voltage VB' through the boost capacitor CB'. That is, the voltage of the gate electrode of the drive transistor T1' can be increased from VNG'-VB' to VNG'. When the voltage of the gate electrode of the drive transistor T1' is increased by the amount of the boost voltage VB', the drive transistor T1' can be turned on.

[0150] Because the voltage of the gate electrode of the drive transistor T1' before (e.g., immediately before) the start point BP_S' of the boost period BP' is VNG' and the voltage of the gate electrode of the drive transistor T1' after (e.g., immediately after) the end point BP_E' of the boost period BP' is VNG', the voltage of the gate electrode of the drive transistor T1' before (e.g., immediately before) the start point BP_S' of the boost period BP' can be equal to the voltage of the gate electrode of the drive transistor T1' after (e.g., immediately after) the end point BP_E' of the boost period BP'. Thus, even if the frame period FP' includes the boost period BP', the voltage of the gate electrode of the drive transistor T1' can be the same based on before and after the boost period BP'.

[0151] As such, the pixel circuit Pa can include a boost capacitor CB' including a first electrode receiving the gate control signal GTF' and a second electrode connected to the gate electrode of the driving transistor T1'. The voltage of the gate electrode of the driving transistor T1' can be changed based on the gate control signal GTF' in the boost period BP' included in the non-emission period NEP', and the driving transistor T1' can be turned off in the boost period BP'. Accordingly, deterioration of the driving transistor T1' can be prevented.

[0152] FIG. 8 is a block diagram illustrating an electronic device 1000. FIG. 9 is a block diagram illustrating an electronic device 1000. FIG. 8 is a diagram of an embodiment in which the electronic device 1000 is implemented as a smart phone.

[0153] Referring to FIG. 8 and FIG. 9 , the electronic device 1000 can include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 can be the display device 10 of FIG. 1 . In addition, the electronic device 1000 can further include a plurality of ports for communication with a video card, a sound card, a memory card, a universal serial bus (USB) device, and / or other electronic devices, etc.

[0154] In one or more embodiments, as shown in FIG. 9 , the electronic device 1000 can be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart pad, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop computer, and a head-mounted display (HMD) device, etc.

[0155] The processor 1010 can perform various computing functions. The processor 1010 can be a microprocessor, a central processing unit (CPU), and / or an application processor (AP), etc. The processor 1010 can be coupled to other components via an address bus, a control bus, and / or a data bus, etc. In addition, the processor 1010 can be coupled to an extension bus, such as a peripheral component interconnect (PCI) bus.

[0156] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 can include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and / or a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and / or a mobile DRAM device.

[0157] The storage device 1030 can include a solid state drive (SSD) device, a hard disk drive (HDD) device, and / or a compact disc read only memory (CD-ROM) device, etc.

[0158] The I / O device 1040 can include an input device such as a keyboard, a keypad, a mouse device, a touchpad, and / or a touchscreen, and an output device such as a printer and a speaker. In one or more embodiments, the I / O device 1040 can include the display device 1060.

[0159] The power supply 1050 can provide power for the operation of the electronic device 1000.

[0160] The display device 1060 can be connected to other components through a bus or other communication link.

[0161] The present disclosure can be applied to any display device including a touch panel and any electronic device. For example, the present disclosure can be applied to a mobile phone, a smart phone, a digital television (TV), a 3D TV, a personal computer (PC) such as a tablet computer or a laptop computer, a home appliance, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.

[0162] The foregoing is a summary of the present disclosure and is not to be construed as limiting the disclosure. Although several embodiments of the disclosure have been described, it will be apparent to those skilled in the art that many modifications are possible without materially departing from the novel teachings and advantages of the disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims and their equivalents. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures. Thus, although specific embodiments of the disclosure have been described, it will be apparent to those skilled in the art that modifications are possible without materially departing from the novel teachings and advantages of the disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims and their equivalents. The disclosure is defined by the claims and their equivalents, and the equivalents of the claims are intended to include any alterations of the embodiments described herein that are within the scope of the present disclosure.

Claims

1. A pixel circuit, wherein, The pixel circuit includes: a light emitting element; a drive transistor configured to apply a drive current to the light emitting element; a storage capacitor including a first electrode connected to a gate electrode of the drive transistor, and a second electrode; and a boost capacitor including a first electrode configured to receive a gate control signal, and a second electrode connected to the gate electrode of the drive transistor, wherein the gate control signal changes from a first level to a second level at a start point of a boost period in a non-emission period, and changes from the second level to the first level at an end point of the boost period.

2. The pixel circuit of claim 1, wherein, When the gate control signal changes from the first level to the second level, a voltage of the gate electrode of the drive transistor changes by an amount of a boost voltage corresponding to a difference between the first level and the second level, and the drive transistor is turned off based on a threshold voltage of the drive transistor.

3. The pixel circuit of claim 2, wherein, When the gate control signal changes from the first level to the second level or from the second level to the first level, the voltage of the gate electrode of the drive transistor changes by the amount of the boost voltage.

4. The pixel circuit of claim 3, wherein, A voltage of the gate electrode of the drive transistor immediately before the start point of the boost period is equal to a voltage of the gate electrode of the drive transistor immediately after the end point of the boost period.

5. The pixel circuit of claim 3, wherein, When the drive transistor is a P-type transistor, the first level is lower than the second level.

6. The pixel circuit of claim 5, wherein, When the gate control signal changes from the first level to the second level, the voltage of the gate electrode of the drive transistor increases by the amount of the boost voltage.

7. The pixel circuit of claim 6, wherein, When the gate control signal changes from the second level to the first level, the voltage of the gate electrode of the drive transistor decreases by the amount of the boost voltage.

8. The pixel circuit according to claim 5, wherein: The drive transistor includes the gate electrode connected to a gate node, a first electrode connected to a first node, and a second electrode connected to a second node, wherein the storage capacitor includes the first electrode connected to the gate node, and the second electrode configured to receive a first drive voltage, wherein the second electrode of the boost capacitor is connected to the gate node, and wherein the light emitting element includes an anode electrode and a cathode electrode configured to receive a second drive voltage.

9. The pixel circuit of claim 8, wherein, The pixel circuit further includes: a data write transistor including a gate electrode configured to receive a data write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the first node; a compensation transistor including a gate electrode configured to receive the data write gate signal, a first electrode connected to the second node, and a second electrode connected to the gate node; a data initialization transistor including a gate electrode configured to receive a data initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the gate node; a first emission transistor including a gate electrode configured to receive an emission signal, a first electrode configured to receive the first drive voltage, and a second electrode connected to the first node; a second emission transistor including a gate electrode configured to receive the emission signal, a first electrode connected to the second node, and a second electrode connected to the anode electrode; and an anode initialization transistor including a gate electrode configured to receive an anode initialization gate signal, a first electrode configured to receive the initialization voltage, and a second electrode connected to the anode electrode.

10. The pixel circuit of claim 9, wherein, The non-emission period does not include a turn-on voltage period of the emission signal, and an emission period includes the turn-on voltage period of the emission signal.

11. The pixel circuit of claim 9, wherein, The non-emission period and non-boost period of the emission period include a turn-on voltage period of the data write gate signal, a turn-on voltage period of the data initialization gate signal, a turn-on voltage period of the emission signal, and a turn-on voltage period of the anode initialization gate signal.

12. The pixel circuit of claim 3, wherein, When the drive transistor is an N-type transistor, the first level is higher than the second level.

13. The pixel circuit of claim 12, wherein, When the gate control signal changes from the first level to the second level, the voltage of the gate electrode of the drive transistor decreases by the amount of the boost voltage.

14. The pixel circuit of claim 13, wherein, When the gate control signal changes from the second level to the first level, the voltage of the gate electrode of the drive transistor increases by the amount of the boost voltage.

15. The pixel circuit of claim 12, wherein, The drive transistor includes the gate electrode connected to a gate node, the first electrode connected to a first node, the second electrode connected to a second node, and a back gate electrode connected to the second node, wherein the storage capacitor includes the first electrode connected to the gate node and the second electrode connected to the second node, wherein the second electrode of the boost capacitor is connected to the gate node, and wherein the light emitting element includes an anode electrode and a cathode electrode configured to receive a second drive voltage.

16. The pixel circuit of claim 15, wherein, The pixel circuit further includes: a data write transistor including a gate electrode configured to receive a data write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the gate node; a reference voltage transistor including a gate electrode configured to receive a reference voltage gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the gate node; an anode initialization transistor including a gate electrode configured to receive an anode initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the anode electrode; an emission transistor including a gate electrode configured to receive an emission gate signal, a first electrode configured to receive a first drive voltage, and a second electrode connected to the first node; and a holding capacitor including a first electrode configured to receive the first drive voltage and a second electrode connected to the second node.

17. The pixel circuit of claim 16, wherein, The emission period includes a turn-on voltage period of the emission gate signal.

18. The pixel circuit of claim 16, wherein, The non-boost period in the non-emission period includes a turn-on voltage period of the data write gate signal, a turn-on voltage period of the reference voltage gate signal, a turn-on voltage period of the anode initialization gate signal, and a turn-on voltage period of the emission gate signal.

19. A display device, wherein, The display device includes: a display panel including a pixel circuit; and a display panel driver configured to drive the display panel, wherein the pixel circuit includes: a light emitting element; a drive transistor configured to apply a drive current to the light emitting element; a storage capacitor including a first electrode connected to a gate electrode of the drive transistor, and a second electrode; and a boost capacitor including a first electrode configured to receive a gate control signal, and a second electrode connected to the gate electrode of the drive transistor, and wherein the gate control signal changes from a first level to a second level at a start point of a boost period in a non-emission period, and changes from the second level to the first level at an end point of the boost period.

20. The display device of claim 19, wherein, When the gate control signal changes from the first level to the second level, a voltage of the gate electrode of the drive transistor changes by an amount of a boost voltage corresponding to a difference between the first level and the second level, and the drive transistor is turned off based on a threshold voltage of the drive transistor. 21.An electronic device comprising a display device, wherein, The display device includes: a display panel including a pixel circuit; and a display panel driver configured to drive the display panel, wherein the pixel circuit includes: a light emitting element; a drive transistor configured to apply a drive current to the light emitting element; a storage capacitor including a first electrode connected to a gate electrode of the drive transistor, and a second electrode; and a boost capacitor including a first electrode configured to receive a gate control signal, and a second electrode connected to the gate electrode of the drive transistor, wherein the gate control signal changes from a first level to a second level at a start point of a boost period in a non-emission period, and changes from the second level to the first level at an end point of the boost period, and wherein, when the drive transistor is a P-type transistor, the first level is lower than the second level. 22.The electronic device of claim 21, wherein, The electronic device includes a cellular phone, a video phone, a smart pad, a smart watch, a tablet personal computer, a car navigation system, a computer monitor, a laptop computer, or a head-mounted display device.

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