Floating gate charge sharing type storage and calculation integrated unit and use method thereof

Abstract

The invention discloses a floating gate charge sharing type storage and calculation integrated unit and a use method thereof, and belongs to the technical field of semiconductors. By utilizing the erasable storage weight brought by the floating gate structure and utilizing the charge coupling mechanism to judge the weight, the memory can be used as a memory and can also be used as a memory, and the memory has the characteristics of small size, high dynamic range, high calculation accuracy and non-volatile property; the storage and calculation integrated unit can also form a common floating gate structure so as to further reduce the equivalent area of devices in the array.

Description

TECHNICAL FIELD

[0001] The application provides a floating gate charge sharing type memory-computing integrated unit and a use method thereof, and belongs to the technical field of semiconductors. BACKGROUND

[0002] The feature of the separation of storage and computing in the Von Neumann architecture has helped the independent high-speed iterative development of memory and processors in the past few decades, but brings many limitations when processing neural network algorithms today, among which the most severe is the large language model. The core weight matrix only performs one calculation after a large-scale data transfer, resulting in a delay and power consumption of memory access far greater than that of calculation. In addition, the bandwidth between the memory and the processor is limited, and as the size of the neural network continues to expand, the amount of data grows exponentially, and the limited memory access bandwidth also becomes the main factor limiting the speed of network reasoning. Due to the separation of storage and computing, frequent data transmission will cause a large amount of energy consumption, and when implementing neural network algorithms using the Von Neumann architecture, many operation units will be in an idle state, resulting in a low energy efficiency utilization of computing resources. At the same time, neural network computing requires a large number of matrix vector multiplication calculations, and traditional digital multipliers processing such calculations require tens of thousands of transistors, greatly affecting the integration and energy efficiency ratio of the traditional scheme when processing such algorithms.

[0003] In order to overcome this limitation, people have proposed a memory-computing integrated scheme, which directly utilizes storage units for data processing by integrating storage functions and computing functions in the same chip or tightly coupled chip set. The feature of this scheme is that it can store neural network weights in a memory-computing integrated array composed of memory-computing integrated units, and can apply an excitation vector to the array to complete matrix vector multiplication calculation locally, effectively solving the hardware acceleration bottleneck of neural networks.

[0004] The existing computing and storage integrated solutions mostly use current domain readout, because the existing mainstream storage media, such as RRAM, FLASH and MRAM, all use the size of current to represent the weight, the accumulation in the formula can be simply obtained through the principle of Kirchhoff's law of current, and the current has strong anti-interference ability, good linearity, and is easy to realize signal amplification and processing; therefore, it can be considered that the current domain readout is a simpler and more convenient way for storage media to realize storage and computing; the Chinese patent with publication number CN118629456A discloses a three-transistor memory with a buried gate and a composite medium gate structure, a readout and write-in method and a storage and computing array, a three-transistor structure is formed by adding a buried gate structure on the basis of the existing composite medium gate double-transistor photosensitive detector, the buried gate structure is used to control the writing and erasing of the weight to the storage device, and the storage and readout of the charge information are realized by using the principle of charge coupling, thereby inheriting the characteristics of small size, high dynamic range and strong weight retention of the composite medium gate double-transistor photosensitive detector; however, the solution adopts the current domain readout mode, and a certain bias current needs to be continuously provided to maintain the readout, which will cause additional power consumption; in addition, non-ideal effects such as IR-Drop caused by parasitic resistance and temperature drift caused by changes in carrier mobility will reduce the accuracy of the final simulation result.

[0005] In addition, in the existing charge sharing type storage and computing solution, a capacitor is usually arranged outside the SRAM unit to convert the output voltage of the SRAM into a charge sharing output, so as to realize the charge sharing type SRAM analog domain storage and computing; however, there is a matching difference between the capacitors outside different SRAM units, which will cause uneven charge distribution and affect the calculation accuracy; in addition, the SRAM unit is composed of at least six tubes, and a capacitor unit needs to be added to convert the output into charge, so that the entire unit becomes more bloated, and the SRAM is a volatile device, so that the data stored therein will be lost when the power is cut off, thereby causing the calculation task to be interrupted, and frequent restart and reinitialization are required, which affects the performance of the device.

[0006] Therefore, the solution is not suitable for some application scenarios that require non-volatile deployment, and there is a lack of a non-volatile, high-density charge readout type storage and computing integrated unit and storage and computing integrated solution at the present stage. SUMMARY

[0007] In order to solve the existing problems, the present application provides a floating gate charge sharing type storage and computing integrated unit and a use method, which are used to realize charge domain readout, save array power consumption, avoid non-ideal effects caused by current readout such as IR-Drop and temperature drift, and improve the accuracy of array inference.

[0008] The first object of the present application is to provide a floating gate charge sharing type memory and calculation integrated unit, which comprises a substrate, a weight storage tube and a charge coupling tube.

[0009] Optionally, the substrate serves as the base of the memory and calculation integrated unit.

[0010] Optionally, a weight storage gate structure is arranged on the substrate, which comprises, from bottom to top, a bottom dielectric layer, a first floating gate, a first top dielectric layer and a first control gate. An excitation drain is arranged in the substrate, and the excitation drain and the weight storage gate structure jointly form the weight storage tube.

[0011] Optionally, a charge coupling gate structure is arranged on the substrate, which comprises, from bottom to top, a bottom dielectric layer, a second floating gate, a second top dielectric layer and a second control gate. A through hole exists on the second control gate and the second top dielectric layer, and an insulating sidewall is arranged around the through hole, and a metal is filled in the through hole to directly contact the floating gate. The charge coupling gate structure and the substrate jointly form the charge coupling tube, and the charge coupling tube does not have a source and a drain in the substrate.

[0012] Optionally, the bottom dielectric layer, the first top dielectric layer, the second top dielectric layer and the insulating sidewall around the through hole are one of silicon dioxide and silicon nitride or a combination thereof; and the first floating gate, the first control gate, the second floating gate and the second control gate are polycrystalline silicon.

[0013] The second object of the present application is to provide a use method of the floating gate charge sharing type memory and calculation integrated unit, which comprises the following steps: applying a positive high voltage to the first control gate applying voltages to the excitation drain and the substrate to form a positive bias between the first control gate and the substrate, and the voltages of the excitation drain and the substrate do not need to be the same, at this time, a strong electric field exists between the first floating gate and the substrate, and electrons in the substrate enter the first floating gate through a tunneling mechanism, thereby increasing the threshold voltage of the weight storage tube; applying a negative high voltage to the first control gate applying voltages to the excitation drain and the substrate to form a negative bias between the first control gate and the substrate, and the voltages of the excitation drain and the substrate do not need to be the same, at this time, a strong electric field exists between the first floating gate and the substrate, and electrons in the first floating gate enter the substrate through a tunneling mechanism, thereby decreasing the threshold voltage of the weight storage tube; applying a voltage to the second control gate applying a fixed positive voltage to the first control gate of the selected memory and calculation integrated unit As excitation, if the threshold voltage of the weight storage tube is greater than Vth0 due to the previous programming operation, the weight storage tube cannot be opened, and if the threshold of the memory and calculation integrated unit is less than Vth1 due to the previous erasing operation, the weight storage tube can be opened. ​​The substrate and the excitation drain are first applied for 10 ms, and then switched to a negative bias At this time, a depletion region appears in the substrate under the charge-coupled tube due to the bias of the gate liner, and since the depletion region has just been formed, it has not yet had time to generate electrons through recombination. If the weight storage tube can be opened, the depletion region in the substrate under the charge-coupled tube can quickly replenish electrons through the excitation drain, at which time the potential in the second floating gate is:

[0014] wherein is the second floating gate-bottom layer dielectric layer-substrate capacitance, is the second top layer dielectric layer capacitance, is the surface potential of the substrate of the charge-coupled tube, and the value is approximately:

[0015] wherein, is the Fermi potential of the semiconductor; If the weight storage tube cannot be opened, the depletion region in the substrate under the charge-coupled tube is in a hollow state, and the surface potential of the substrate is , the potential in the second floating gate is , so the weight of the storage and calculation integrated unit can be determined by the size of the second floating gate potential.

[0016] A third object of the present application is to provide a scheme for forming a storage and calculation integrated array with a floating gate charge sharing type storage and calculation integrated unit, in which the charge-coupled tubes of two storage and calculation integrated devices in adjacent rows are adjacent, they share the same substrate, and are separated by shallow trench isolation between the shared substrates, share a second floating gate, a second top layer dielectric layer, a second control gate, an excitation drain, and a floating gate via structure to save area; the write drains of all storage and calculation integrated units in the array are connected to their substrates through metal lines; the floating gates of storage and calculation integrated units in the same column are connected to form an FGL, and the first control gates of storage and calculation integrated units in the same row are connected to form a word line WL.

[0017] A fourth object of the present application is to provide a use method of a floating gate charge sharing type storage and calculation integrated array, in which during inference calculation, different WLs are respectively applied with a voltage of 0 or Vw according to actual conditions, and the FGL potential on a certain column is:

[0018] wherein is the number of storage and calculation integrated units in a column, is the substrate surface potential of the th storage and calculation integrated unit in the column, and the FGL potential is the multiplication and accumulation result of the weight of the storage and calculation integrated units in the column and the applied excitation vector.

[0019] The beneficial effects of the present invention are: The present application provides a floating gate charge-sharing storage and computing integrated unit and a method for using the same. The method utilizes a floating gate structure to use a tunneling mechanism to change the charge amount and thereby change the characteristics of the transistor threshold voltage for weight storage. The tube is connected to a transistor capacitor, and the external potential can form a potential in the capacitor that is directly related to the size of the weight. The floating gate of the transistor capacitor has a through hole, and its potential can be read out through the floating gate using a charge coupling mechanism to complete the weight judgment. The structural device can be used as both a memory and a storage and computing device. Compared with the classic current domain storage and computing integrated solution, the storage and computing integrated unit that reads the potential through the floating gate has the characteristics of small size, low power consumption, high dynamic range, high calculation accuracy, and non-volatility. The storage and computing integrated unit can also constitute a common floating gate structure to further reduce the equivalent area of ​​the device in the array. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 This is a cross-sectional view of a floating gate charge-sharing storage and computing integrated unit provided in the first embodiment of the present invention; Figure 2 This is a schematic diagram of a floating gate charge sharing storage and computing integrated unit provided in the first embodiment of the present invention; Figure 3 This is a diagram of an array structure composed of floating gate charge sharing storage and computing integrated units provided by the second embodiment of the present invention; Figure 4 This is a cross-sectional view of a common excitation drain and common charge-coupled gate structure in the WL direction in an array composed of four floating gate charge-sharing storage and computing integrated units described in the second embodiment of the present invention; Figure 5 This is a schematic diagram of the structure in the WBL direction of an array composed of floating gate charge sharing type integrated storage and computing units described in the second embodiment of the present invention; Figure 6 1. A cross-sectional view and a top view of an array structure composed of column substrate-isolated floating gate charge-sharing storage and computing units described in the third embodiment of the present invention; Figure 7 This is a schematic diagram of the connection of an array composed of column substrate-isolated floating gate charge-sharing storage and computing units described in the third embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purposes, technical solutions and advantages of the embodiments of the present application more obvious, the various embodiments according to the present application will be described in detail below with reference to the drawings, in which the same reference signs are used to represent substantially the same steps and elements in the description and the drawings, and repeated explanations of these steps and elements will be omitted.

[0023] It should be understood that the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments described in the present application without creative labor should fall within the protection scope of the present application. Moreover, in order to make the description more concise and brief, the detailed description of the functions and structures well known in the art will be omitted.

[0024] Three preferred embodiments of the memory device and the manufacturing method of the device according to the present application will be described in detail below with reference to the drawings. The embodiments described in the present application are only examples but not limitations, the steps and devices in each embodiment in the present application are not limited to be implemented in only one embodiment, and those skilled in the art can combine and integrate some steps and devices from the separately described various embodiments to achieve the effects of the present application according to the concept of the present application, and some variations, modifications, changes, additions and sub-combinations of these embodiments form embodiments included in the present application, which will not be described one by one here.

[0025] Embodiment one The present embodiment provides a floating gate charge sharing type memory and computing integrated unit and a use method, the structure of the unit is shown in Figure 1 , which comprises a substrate, a weight storage tube and a charge coupling tube, the substrate is a P-type base shared by two transistors in the memory and computing integrated unit; the weight storage tube comprises an excitation drain and a weight storage gate structure, the excitation drain is arranged in the substrate and is N-type doped, and the weight storage gate structure comprises a bottom dielectric layer, a first floating gate, a first top dielectric layer and a first control gate from bottom to top; the charge coupling tube comprises a charge coupling tube, and the charge coupling tube structure comprises a bottom dielectric layer, a second floating gate, a second top dielectric layer and a second control gate from bottom to top, a via hole is arranged on the second top dielectric layer and the second gate, the periphery of the via hole is an insulating side wall, and the middle is filled with metal to directly contact the floating gate.

[0026] Figure 2 It is a corresponding floating gate charge sharing type memory and computing integrated unit schematic diagram, the weight storage tube is a floating gate transistor pattern in Figure 2 , since the charge coupling tube does not have a source and a drain in the substrate, and its main function is to perform charge coupling, it is a capacitor pattern in Figure 2 , and the surface of the substrate of the charge coupling tube is Figure 2The X node in the figure is a node, the capacitance pattern under the X node is essentially a depletion region capacitance formed after a gate insulating bias is applied between the second control gate and the substrate, the two capacitances above the X node represent the bottom dielectric layer capacitance and the second top dielectric layer capacitance in turn, and the Y node is a floating gate node connected by a via structure.

[0027] To map the neural network weight of the device, the device needs to be programmed and erased, and the weight of the floating gate charge sharing type storage and calculation integrated unit is stored in the first floating gate, which is specifically physically manifested as the number of electrons in the first floating gate; When the device needs to be programmed, a positive high voltage 5V is applied to the first control gate, 0V is applied to the second control gate, and -5V is applied to the excitation drain and the substrate, at this time, the first floating gate has a strong electric field from the first floating gate to the substrate, and the electrons in the substrate enter the first floating gate through the FN tunneling mechanism under the action of the strong electric field, and the number of electrons in the first floating gate increases, so that the potential in the first floating gate is lower under the same first control gate voltage, thereby making the inversion degree of the weight storage tube lower, which is equivalent to increasing the threshold voltage of the device; When the device needs to be erased, a negative high voltage -10V is applied to the first control gate, and 0V is applied to the excitation drain, the second control gate and the substrate, at this time, the first floating gate has a strong electric field from the substrate to the first floating gate, and the electrons in the first floating gate enter the substrate through the FN tunneling mechanism under the action of the strong field, and the number of electrons in the first floating gate decreases, so that the potential of the first floating gate is higher under the same first control gate, thereby making the inversion degree of the weight storage tube higher, which is equivalent to reducing the threshold voltage of the device.

[0028] When the device is read out, 0V is applied to the second control gate, and 3V is applied to the first control gate of the unit to be read out as a logic 1 excitation. In the programming and erasing process of the device, if the threshold voltage of the device is less than 3V, it is considered that the weight 1 is written, and at this time, the weight storage tube of the unit is turned on; if the threshold voltage of the device is greater than 3V, it is considered that the weight 0 is written, and the weight storage tube is not turned on. For example, in the case where the threshold voltage is greater than 3V (i.e. weight 0 is written), even if 3V excitation is applied to the first control gate, it will not be turned on; and if the excitation is 0V (logic 0), even if the threshold voltage is less than 3V (weight 1 is written), it will not be turned on. After the excitation is applied, the substrate and the excitation drain of the storage and calculation unit are switched from 0V to -3V at the same time, and in this transient state, the depletion region under the charge coupled tube is just formed, and the electrons are not generated through recombination in time, and the device is in an empty well state.

[0029] If the weight storage tube can be turned on, the device will provide electrons from the excitation drain (at this time, -3V) until the surface inversion. The second floating gate of the charge coupled tube will be coupled to a certain negative potential; If the weight storage tube cannot be turned on, the device will remain in a depleted state, and at this time, the substrate surface potential coupled to the second floating gate of the charge coupled tube is higher.

[0030] From the above, it can be seen that if the device stores a weight of 1 (the threshold voltage of the weight storage tube is low) and is given an excitation of 1 (a positive voltage is applied to the first control gate), the potential on the second floating gate of the unit will decrease. By measuring the potential on the second floating gate, the weight previously written into the device can be determined, and the weight and the excitation also complete a 1-bit multiplication operation.

[0031] Example 2 This embodiment provides a floating gate charge sharing storage and computing integrated array and a method of using the array. Figure 3 As shown, the first control gates of the storage and calculation cells in the same row are connected to form a word line (shown as WL in the figure), and the second control gates of the entire array are connected. Figure 3 Marked with H in the figure, since the potential of the second control gate is always the same and is always 0 voltage in each mode, the entire array can be connected and grounded; the excitation drains of the storage and calculation units in the same column are connected to form the write bit line (shown as WBL in the figure), and the substrate of the entire array is Figure 3 Marked with P in the figure, since the electric potential of the substrate is always the same and the array does not completely isolate the substrates of different units, the substrates of the entire array need to be connected; the floating gates of the storage and computing units in the same column are led out by through holes and connected to form a floating gate line (shown as FGL in the figure).

[0032] In actual manufacturing, considering the reduction of device size, the two devices can share the excitation drain or the second floating gate and the second control gate. Figure 4 This shows a method for connecting floating gate-sharing devices in the same column. Unit 1 shares the second floating gate and the second control gate with units 2, 3, and 4, respectively. Shallow trench isolation is used in the substrate to isolate the substrate depletion regions of different devices, ensuring that each does not affect the substrate surface potential multiplication results. Units 2 and 3 share the excitation drain. This connection method saves unit area without affecting actual functionality. The array structure formed by this connection method is shown in [1]. Figure 5 .

[0033] Next, we introduce the methods of programming specific cells, erasing the entire chip, reading specific cell weights, and array reasoning.

[0034] When programming a specific cell, -5V needs to be applied to the substrate of the entire array and 0V to the second control gate of the entire array. In addition, 5V is applied to the WL corresponding to the selected cell, while 0V is applied to the WL corresponding to the unselected cells. -5V is applied to the WBL corresponding to the selected cell, while 0V is applied to the WBL corresponding to the unselected cells. At this time, the first control gate of the selected cell is applied with 5V, the substrate and the stimulating drain are applied with -5V, and the gate of the weight storage tube is applied with 10V, which is enough to cause FN tunneling to write electrons into the first floating gate; For the cell with selected WL and unselected WBL, at this time, the first control gate is applied with 5V, the substrate is applied with -5V, and the stimulating drain is applied with 0V, and the substrate surface of the device is clamped at 0V, and the gate bias is only 5V, which is not enough to cause FN tunneling; For the cell with selected WBL and unselected WL, at this time, the first control gate is applied with 0V, the substrate and the stimulating drain are applied with -5V, and the gate bias is 5V, which is not enough to cause FN tunneling.

[0035] The erase operation is a global operation, the second control gate of the entire array is applied with 0V, the substrate is applied with 0V, the WL is applied with -10V, and the stimulating drain is applied with 0V, at this time, the gate bias of the weight storage tube of the entire array cell reaches -10V, which can cause FN tunneling to erase the electrons in the first floating gate.

[0036] Before the weight of a specific cell is read out, the reference potential of each FGL needs to be adjusted: the second control gate of the entire array is applied with 0V, the first control gate of the entire array is applied with 0V, and the write drain and the substrate of the entire array are switched together from 0V to -5V, after the switching is completed, the potential of each FGL in the array is detected, and the potential is adjusted to zero as the reference when all cells are not turned on. After that, the read operation is performed on the specific cell, similarly to determining the reference potential, the second control gate of the entire array is applied with 0V, and the WL of the selected cell is applied with 3V, and the WL of the unselected cell is applied with 0V, then the write drain and the substrate of the entire array are switched together from 0V to -5V, if the weight of the device is 0 (the threshold voltage is greater than 3V), the weight storage tube is not turned on, and the depletion region remains depleted, the potential of the FGL corresponding to the selected cell does not change; if the weight of the device is 1 (the threshold voltage is less than 3V), the weight storage tube is turned on, and the depletion region is filled with electrons from the stimulating drain in an instant, and the potential of the second floating gate of the charge-coupled tube is lowered by a fixed value , a potential drop of a fixed value occurs on the corresponding FGL potential, so the weight of the selected device can be determined by the potential of the FGL.

[0037] When reasoning for the entire array, similarly to the weight readout of a single cell, the second control gate of the entire array is applied with 0V, and the corresponding stimulating WL is applied with 3V, the unselected WL is applied with 0V, and the write drain and the substrate of the entire array are switched together from 0V to -5V, at this time, the weight of the weight storage tube and the voltage on the WL of the entire array are multiplied, and are reflected on the substrate surface potential below the cell charge-coupled tube, and the potential on the FGL is finally lowered to , The number of cells with 1 for both excitation and weight on the column is counted, and the matrix vector multiplication calculation is completed.

[0038] Embodiment Three This embodiment provides a substrate-isolated floating gate charge sharing type memory-computing integrated array and its use method. The structure of the substrate-isolated floating gate charge sharing type memory-computing integrated cell in the array is as shown in the figure Figure 6 The substrate is completely isolated between columns in the array using an insulating medium layer, so that different substrate voltages can be applied between different columns without short circuiting. The structure of the array is as shown in the figure Figure 7 The excitation drain of the memory-computing integrated cell in the same column in the array can be directly connected to the substrate of the column as the WBL, the second floating gate of the cell in the same column is connected through the via and forms the FGL, the first floating gate of the cell in the same row is directly connected to form the WL, and the second control gate of the entire array can be connected and grounded.

[0039] Next, the methods of programming specific cells in the array, erasing the entire chip, reading out the weights of specific cells, and array inference are introduced.

[0040] When programming specific cells, 5V is applied to the WL corresponding to the selected cell, and 0V is applied to the WL corresponding to the non-selected cell. -5V is applied to the WBL corresponding to the selected cell, and 0V is applied to the WBL corresponding to the non-selected cell.

[0041] At this time, 5V is applied to the first control gate of the selected cell, the substrate and the excitation drain are connected to -5V, and the gate-substrate bias of the weight storage tube reaches 10V, which is sufficient to cause FN tunneling to write electrons into the first floating gate.

[0042] For cells with selected WL and non-selected WBL, at this time, 5V is applied to the first control gate, the substrate is 0V, the excitation drain is connected to 0V, and the gate-substrate bias is only 5V, which is not sufficient to cause FN tunneling; For cells with selected WBL and non-selected WL, at this time, 0V is applied to the first control gate, the substrate and the excitation drain are -5V, and the gate-substrate bias is 5V, which is not sufficient to cause FN tunneling.

[0043] The erase operation is a global operation, with -10V applied to the WL and 0V applied to the WBL. At this time, the gate-substrate bias of the weight storage tube of the cells in the entire array reaches -10V, which can cause FN tunneling to erase the electrons in the first floating gate.

[0044] Before the weight of a certain cell is read out, the reference potential of each FGL needs to be adjusted: 0V is applied to the WL of the whole array, the WBL of the whole array is switched from 0V to -5V, and after the switching is completed, the potential of each FGL in the array is detected, and the potential is adjusted to zero as the reference when all cells are not turned on. After that, the readout operation can be performed on the certain cell, and similarly to determining the reference potential, 3V is applied to the WL of the selected cell and 0V is applied to the WL of the unselected cell, and then the WBL of the whole array is switched from 0V to -5V. If the weight of the device is 0 (the threshold voltage is greater than 3V), the weight storage tube is not turned on, and the depletion region still remains in the depletion state, and the potential of the FGL corresponding to the selected cell does not change; if the weight of the device is 1 (the threshold voltage is less than 3V), the weight storage tube is turned on, and the depletion region is filled with electrons from the stimulating drain in an instant, and the potential of the second floating gate of the charge-coupled tube is lowered by a fixed value A potential drop of a fixed value can occur on the corresponding FGL potential, so the weight of the selected device can be determined by the potential of the FGL.

[0045] When reasoning for the whole array, similarly to the weight readout of a single cell, 0V is applied to the second control gate of the whole array, and 3V is applied to the WL corresponding to the stimulating, and 0V is applied to the WL of the unselected, and the WBL is switched from 0V to -5V at the same time. At this time, the weight in the weight storage tube and the voltage on the WL of the whole array all realize multiplication, and are reflected on the potential of the substrate surface below the charge-coupled tube of the cell. The potential on the FGL is lowered to , The number of cells in this column is the number of cells with stimulating and weight both being 1. Thus, the matrix vector multiplication calculation of the array is completed.

[0046] The benefit of the substrate isolation is that the potential of the stimulating drain and the substrate of the storage and calculation cell can always be the same in different modes without additional area, which reduces the control difficulty of the array.

[0047] As described above, the above specific embodiments described in the present application are only examples and not limitations, and those skilled in the art can combine and combine some steps and devices from the above separately described various embodiments according to the concept of the present application to achieve the effect of the present application. The embodiments thus combined are also included in the present application, and such combination is not described here.

[0048] Note that the advantages, advantages, effects, etc. mentioned in the present application are only examples and not limitations, and these advantages, advantages, effects, etc. cannot be considered as the must-have of each embodiment of the present application. In addition, the above specific details of the application are only for the purpose of example and for the purpose of understanding, and not for the purpose of limitation, and the above details do not limit the application to the must-use of the above specific details.

[0049] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present invention are intended to be illustrative examples only and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems may be connected, arranged, or configured in any manner. Words such as "include," "comprise," "have," and the like are open-ended words, meaning "including but not limited to," and may be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or" and may be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and may be used interchangeably therewith.

[0050] The step flow charts and the above method descriptions in the present invention are intended to be illustrative examples only and are not intended to require or imply that the steps of the various embodiments must be performed in the order given. As will be appreciated by those skilled in the art, the order of the steps in the above embodiments can be performed in any order. Words such as "thereafter," "then," "next," and the like are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods. In addition, any reference to an element in the singular, such as using the articles "a," "an," or "the," is not to be construed as limiting the element to the singular.

[0051] In addition, the steps and devices in the various embodiments of this document are not limited to being implemented in a certain embodiment. In fact, based on the concept of the present invention, relevant partial steps and partial devices in the various embodiments of this document can be combined to conceive new embodiments, and these new embodiments are also included in the scope of the present invention.

[0052] The methods herein include one or more actions for implementing the methods described. The methods and / or actions may be interchangeable with one another without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and / or use of the specific actions may be modified without departing from the scope of the claims.

[0053] The above description of the invented aspects is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present invention. Therefore, the present invention is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features of the invention herein.

[0054] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0055] The above merely describes preferred embodiments of the present application, and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A floating gate charge sharing type compute-in-memory cell, characterized in that, The memory-computing integrated unit comprises a substrate, a weight storage tube and a charge-coupled tube; The substrate serves as the base of the memory-computing integrated unit and is provided with an excitation drain therein; The weight storage tube comprises an excitation drain and a weight storage gate structure, and the weight storage gate structure comprises, from bottom to top, a bottom dielectric layer, a first floating gate, a first top dielectric layer and a first control gate; The charge-coupled tube comprises a substrate and a charge-coupled gate structure, and the charge-coupled gate structure comprises, from bottom to top, a bottom dielectric layer, a second floating gate, a second top dielectric layer and a second control gate; a floating gate via is provided on the second control gate and the second top dielectric layer, an insulating sidewall is provided around the floating gate via, and a metal is filled in the floating gate via to directly contact the floating gate; the charge-coupled tube is not provided with a source and a drain in the substrate; The floating gate via is directly connected to the second floating gate, and the calculation of the weight stored in the memory-computing integrated unit is realized through the second floating gate. 2.The all-memory computing cell of claim 1, wherein, The bottom dielectric layer, the first top dielectric layer, the second top dielectric layer and the insulating sidewall around the via are one of silicon dioxide and silicon nitride or a combination thereof; The first floating gate, the first control gate, the second floating gate and the second control gate are polycrystalline silicon; and the via is one of titanium silicide, titanium nitride and tungsten or a combination thereof.

3. A method for using a floating gate charge sharing storage and computing integrated unit, characterized in that: The method is realized based on the memory-computing integrated unit of claim 1 and claim 2; and the method realizes the programming operation, the erasing operation and the readout operation of the memory-computing integrated unit by applying voltages to the control gates of the weight storage tube and the charge-coupled tube, respectively.

4. The method of claim 3, wherein, The method comprises: Weight programming: applying positive voltage to the first control gate Applying voltage to the stimulating drain and the substrate, so that the control gate and the substrate form a positive bias, under the action of the electric field between the first floating gate and the substrate, the electrons of the substrate enter the first floating gate through the tunneling mechanism, and then increase the threshold voltage of the weight storage tube, realizing the programming operation; Weight Erase: Apply negative voltage to first control gate , and apply voltage to the stimulating drain and the substrate, so that a negative bias is formed between the first control gate and the substrate, and under the action of the electric field between the first floating gate and the substrate, the electrons in the first floating gate enter the substrate through the tunneling mechanism, thereby reducing the threshold voltage of the weight storage tube, and realizing the erase operation; Weight readout: apply voltage to second control gate Apply fixed positive voltage to first control gate of the weight storage cell to be read out As an incentive, if the threshold voltage of the weight storage cell is greater than The weight storage cell cannot open; if the threshold voltage of the weight storage cell is less than The weight storage cell opens normally.

5. The method of claim 4, wherein, The weight readout comprises: The substrate and the excitation drain are first applied for 10 ms, and then switched to a negative voltage A depletion region appears in the substrate below the dynode due to the gate insulator bias, and no electrons are generated; If the weight storage tube is open, the depletion region in the substrate below the charge-coupled tube is supplemented with electrons through the excitation drain, and at this time, the potential in the second floating gate is: wherein, is the second floating gate-bottom layer dielectric layer-substrate capacitance, is the second top layer dielectric layer capacitance, is the surface potential of the charge coupled diode substrate, expressed as: wherein the Fermi potential of the semiconductor; If the weight storage tube cannot be opened, the depletion region in the substrate under the charge-coupled tube is in a hollow state, and the substrate surface potential of the charge-coupled tube is , the potential in the second floating gate , the weight of the storage and calculation integrated unit is judged by the size of the second floating gate potential, and the readout operation is realized.

6. A floating gate charge sharing type storage and computing integrated unit array, characterized in that: The array is realized based on the memory-computing integrated unit of claim 1 and claim 2; The array of the storage-computation integrated unit is An array of Rows Columns, two adjacent storage-computation integrated devices in the same row form a group, share a substrate, a second floating gate, a second top dielectric layer, a second control gate, and a floating gate via structure; the shared substrates are separated by shallow trench isolation; two adjacent groups of storage-computation integrated devices share an excitation drain; and the weight storage tubes of the storage-computation integrated devices in the same row are an integral whole; The first control gates of the memory-computing integrated devices in the same row are connected to form a word line WL; the excitation drains and the substrates of the memory-computing integrated devices in the same column are connected through a metal line to form a WBL line; and the second floating gates of the memory-computing integrated devices in the same column are connected to form an FGL.

7. A substrate-isolated floating-gate charge-sharing type compute-in-memory cell array, comprising: The substrate-isolated array is realized based on the memory-computing integrated unit of claim 1 and claim 2; The array of the storage-computation integrated unit is An array of Rows Columns, two adjacent storage-computation integrated devices in the same row form a group, share a substrate, a second floating gate, a second top dielectric layer, a second control gate, and a floating gate via structure; the shared substrates are separated by shallow trench isolation; two adjacent groups of storage-computation integrated devices share an excitation drain; and the weight storage tubes of the storage-computation integrated devices in the same row are an integral whole; The memory-computing integrated devices in the same column in the substrate-isolated array are isolated from each other by an insulating layer, so as to ensure that the substrates of different columns apply different voltages without short circuiting; the excitation drains and the substrates of the memory-computing integrated devices in the same column are connected through a metal line to form a WBL; the floating gates of the memory-computing integrated devices in the same column are connected to form an FGL; and the first control gates of the memory-computing integrated devices in the same row are connected to form a word line WL.

8. A method for using a floating gate charge sharing storage and computing integrated cell array, characterized in that: The method is realized based on the array of claim 6 and claim 7; The method respectively applies 0 or voltage excitation to different word lines WL according to an excitation vector when performing calculation, so that the weight storage tube is turned off or turned on, and the potential of the substrate surface under the charge coupling tube of different calculation and storage integrated units in the array is jointly modulated by the voltage on the first control gate and the stored weight value in the weight storage tube. The potential of the FGL on a certain column is: wherein, is the number of columns of the memory-computing integrated cells, is the substrate surface potential of the memory-computing integrated cell in the column, is the substrate surface potential of the memory-computing integrated cell in the column, and FGL is the multiplication-accumulation result of the column weight of the memory-computing integrated cell and the applied excitation vector.

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