Managing program disturb in storage device

Abstract

Example apparatus and methods for managing program disturb in flash memory are disclosed. In one example, a memory device may include a string including a first select gate transistor, a second select gate transistor, and a memory cell therebetween. The peripheral circuit is configured to apply a first voltage to the first select gate transistor during a program operation of the first memory cell. A first memory cell is coupled to a first word line closest to the first select gate transistor among word lines coupled to the memory cell. The peripheral circuit is further configured to apply a second voltage to the first select gate transistor during a program operation of the second memory cell. The second memory cell is coupled to a second word line farther from the first select gate transistor than the first word line. The second voltage is higher than the first voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of semiconductor technology, and more specifically, to systems and methods for managing program disturb in storage devices. BACKGROUND

[0002] Flash memory is a low cost, high density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as program (write) and erase operations, to change the threshold voltage of each storage cell to a corresponding level. For NAND flash memory, erase operations can be performed at a block level, program operations can be performed at a page level, and read operations can be performed at a page level. SUMMARY

[0003] The present disclosure relates to storage devices, storage systems, and methods for managing program disturb in flash memory. In an example, a storage device can include a storage array and a peripheral circuit. The storage array can include a storage string including a first select gate transistor, a second select gate transistor, and a storage cell located between the first select gate transistor and the second select gate transistor. The peripheral circuit is configured to apply a first voltage to a select line coupled to the first select gate transistor during a first program operation of a first storage cell. The first storage cell is coupled to a first word line that is closest to the first select gate transistor among word lines coupled to the storage cell. The peripheral circuit is further configured to apply a second voltage to the select line coupled to the first select gate transistor during a second program operation of a second storage cell. The second storage cell is coupled to a second word line that is farther from the first select gate transistor than the first word line. The second voltage is higher than the first voltage.

[0004] While generally described as software that processes and transforms respective data embodied on tangible media, some or all of the aspects can alternatively be computer implemented methods or further included in respective systems or other apparatuses configured to perform the described functions. The details of these and other aspects and embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 An example of a schematic diagram of a storage device including a peripheral circuit is shown in accordance with some aspects of the present disclosure.

[0006] Figure 2 An example of a schematic diagram of a storage cell array is shown in accordance with some aspects of the present disclosure.

[0007] Figure 3An example cross-sectional side view of an array of memory cells including a string of memory cells is shown in accordance with some aspects of the present disclosure.

[0008] Figure 4 An example memory cell stack including a stack of multiple layers of memory cells is shown in accordance with some aspects of the present disclosure.

[0009] Figure 5 Some example peripheral circuitry is shown in accordance with some aspects of the present disclosure.

[0010] Figure 6A An example of voltages of components in a memory block during programming of the memory block is shown in accordance with some aspects of the present disclosure.

[0011] Figure 6B Another example of voltages of components in a memory block during programming of the memory block is shown in accordance with some aspects of the present disclosure.

[0012] Figure 7A Another example of voltages of components in a memory block during programming of the memory block is shown in accordance with some aspects of the present disclosure.

[0013] Figure 7B Another example of voltages of components in a memory block during programming of the memory block is shown in accordance with some aspects of the present disclosure.

[0014] Figure 8A Another example of voltages of components in a memory block during programming of the memory block is shown in accordance with some aspects of the present disclosure.

[0015] Figure 8B Another example of voltages of components in a memory block during programming of the memory block is shown in accordance with some aspects of the present disclosure.

[0016] Figure 9 An example flowchart of a method for reducing program disturbance in a memory device is shown in accordance with some aspects of the present disclosure.

[0017] Figure 10 A block diagram of an example system having a memory device is shown in accordance with some aspects of the present disclosure.

[0018] Figure 11A A diagram of a memory card having a memory device is shown in accordance with some aspects of the present disclosure.

[0019] Figure 11B A diagram of a solid state drive (SSD) having a memory device is shown in accordance with some aspects of the present disclosure.

[0020] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0021] The present specification relates to a memory device, a memory system, and a method for managing program disturbance in NAND flash memory. The memory device may include one or more memory blocks. Each memory block may include multiple memory strings. Each memory string may have a top select gate (TSG) transistor, a bottom select gate (BSG) transistor, and a memory cell located between the TSG transistor and the BSG transistor. The TSG transistors of two or more memory strings may be coupled to the same TSG select line. During a programming operation of a selected memory cell in a selected memory string, the memory device may apply a programming voltage to a word line coupled to the selected memory cell and apply a pass voltage to a word line coupled to memory cells in the selected memory string that are not selected for programming. In addition, during a programming operation of a selected memory cell in a selected memory string, the memory device may turn on the TSG transistor of the selected memory string and turn off the TSG transistor of the deselected memory string coupled to the same TSG select line as the selected memory string.

[0022] Program disturb may occur during a programming operation, which may affect the reliability and integrity of a memory device. For example, a TSG transistor in a deselected memory string may be erroneously turned on due to factors such as the coupling effect of an elevated word line voltage. Consequently, memory cells in the deselected memory string that were not intended to be programmed may be erroneously programmed due to program disturb.

[0023] In some cases, program disturb may be more significant when programming memory cells coupled to word lines closer to the TSG transistor of a selected memory string. For example, when a programming voltage is applied to a word line closer to the TSG transistor of a selected memory string, the TSG transistor of a deselected memory string is more likely to be erroneously turned on. In some embodiments, to mitigate program disturb, the memory device may apply a lower voltage to the TSG select line when programming memory cells coupled to the two word lines closest to the TSG transistor. When programming memory cells coupled to the remaining word lines, the memory device may apply a higher voltage to the TSG select line.

[0024] Figure 1 An example of a schematic circuit diagram of a memory device 100 including peripheral circuits according to some aspects of the present disclosure is shown. The memory device 100 may include a memory cell array 101 and a peripheral circuit 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array and further include one or more memory blocks 104. The memory cells 106 are provided in the form of an array of memory strings 108, 128, each memory string being formed on a substrate ( Figure 1extend vertically above (not shown). In some embodiments, each memory string 108, 128 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 can hold a continuous analog value, such as a voltage or charge depending on the number of electrons trapped within a storage layer of the memory cell 106. The logical state (i.e., data) of each memory cell 106 in the block 104 can be determined based on a threshold voltage Vth of the memory cell 106. Each memory cell 106 can be a floating gate type memory cell including a floating gate transistor, or a charge trap type memory cell including a charge trap transistor. th

[0025] In some embodiments, each memory cell 106 is a single-level cell (SLC) having two possible memory states that can store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 106 is a multi-level cell (MLC) capable of storing more than one bit of data in more than two memory states. For example, an MLC can store two bits per cell, three bits per cell (also referred to as triple-level cell (TLC)), or four bits per cell (also referred to as quad-level cell (QLC)). Each MLC can be programmed to support a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to one of three possible program levels by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

[0026] As Figure 1 ​As shown, each memory string 108, 128 can include a source select gate (SSG, also known as a bottom select gate, BSG) 110, 130 at its source terminal and a drain select gate (DSG, also known as a top select gate, TSG) 112, 122 at its drain terminal. The SSG 110, 130 and the DSG 112, 122 can be configured to activate a selected memory string 108, 128 (column of the array) during read and program operations. In some embodiments, the sources of the memory strings 108, 128 in the same block 104 are coupled via the same source line 114. In other words, according to some embodiments, the memory strings 108, 128 in the same block 104 have an array common source (ACS). According to some embodiments, the DSG 112, 122 of each memory string 108, 128 is coupled to a corresponding bit line 116, 126, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 108, 128 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of transistors having the DSG 112, 122) or a deselect voltage (e.g., 0V) to the corresponding DSG 112, 122 via one or more DSG lines 113, and / or by applying a select voltage (e.g., higher than the threshold voltage of transistors having the SSG 110, 130) or a deselect voltage (e.g., 0V) to the corresponding SSG 110, 130 via one or more SSG lines 115.

[0027] like Figure 1 As shown, the memory strings 108, 128 can be organized into a plurality of blocks 104, each of which can have a common source line 114 coupled to an ACS. In some embodiments, each block 104 can be used as a basic data unit for an erase operation, so that the memory cells 106 on the same block 104 are erased simultaneously. To erase the memory cells 106 in a selected block 104, the source lines 114 coupled to the selected block 104 and unselected blocks in the same plane can be biased with an erase voltage. For example, the erase voltage can be a high positive voltage (e.g., 20V or higher). In some embodiments, the erase operation can be performed at the half-block level, the quarter-block level, or a level having any suitable number of blocks or portions of a block.

[0028] The memory cells 106 of an adjacent memory string 108 can be coupled by a word line 118. The word line 118 can select which row of memory cells 106 is affected by read and program operations. In some implementations, the memory cells 106 are SLC, and each word line 118 is coupled to a page of memory cells 106, which is the basic unit of data for program operations. If the memory cells 106 are MLC that store two bits of data per cell, then each word line 118 can correspond to two pages. If the memory cells 106 are TLC, then each word line 118 can correspond to three pages. If the memory cells 106 are QLC, then each word line 118 can correspond to four pages. The size of a page in bits is associated with the number of memory strings 108, 128 that a word line 118 in a block 104 is coupled to. Each word line 118 can include a gate line that is coupled to a plurality of control gates (gate electrodes) of a plurality of memory cells 106 in a corresponding page. Figure 1 The example word lines shown include WL0, WL1, WL2, WL3, WL4, and WL5 between one or more DSG lines 113 and one or more SSG lines 115. In some implementations, the word lines can also include dummy word lines that are coupled to dummy memory cells.

[0029] The peripheral circuitry 102 can be coupled to the memory cell array 101 by the bit lines 116, the word lines 118, the source lines 114, the SSG lines 115, and the DSG lines 113. The peripheral circuitry 102 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array 101 by applying voltage and / or current signals to and sensing voltage and / or current signals from each target memory cell 106 via the bit lines 116, the word lines 118, the source lines 114, the SSG lines 115, and the DSG lines 113. The peripheral circuitry 102 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0030] Figure 2 An example of a schematic diagram of a memory cell array 101 according to some aspects of the present disclosure is shown. In some implementations, the TSG 112 of the memory string 108 (first memory string) and the TSG 122 of the memory string 128 (second memory string) are coupled to the same TSG line 113. Further, the TSG 212 of the third memory string 208 (third memory string) can be coupled to another TSG line 213 (not shown in FIG. 1). The first memory string 108 and the third memory string 208 can be coupled to the same bit line 116, and the second memory string can be coupled to a different bit line 126. Figure 1

[0031] ​In some embodiments, the following voltages can be applied to program a selected storage cell 220 in the first storage string 108. First, the storage device can apply a select voltage to the BSG line 115. The BSG transistors of the first storage string 108, the second storage string 128, and the third storage string 208 are turned on. Second, the storage device can apply a select voltage to the TSG line 113 and a deselect voltage to the TSG line 213. Third, the storage device can apply a ground voltage to the bit line 116 to maintain a low voltage in the channel of the transistor with the TSG 112. As such, the transistor with the TSG 112 is turned on and the first select storage string 108 is selected for programming. In addition, the storage device can apply an inhibit voltage (e.g., V cc ) to increase the voltage in the channel of the transistor with the TSG 122. The difference between the inhibit voltage and the select voltage applied to the TSG 122 through the TSG line 113 is less than or equal to the threshold voltage of the transistor with the TSG 122. As a result, the transistor with the TSG 122 is turned off and the second storage string 128 is deselected from being used for programming. Fourth, the storage device can apply a program voltage V pgm to the word line (e.g., WLm) coupled to the selected storage cell 220 and a pass voltage V pass to the other word lines (e.g., WL0-WL5, WLn, and other word lines not shown in Figure 2 ). It should be noted that the voltages can be applied simultaneously or in any possible order and do not have to follow the order described above.

[0032] Program disturb can occur during a program operation, which can affect the reliability and integrity of the storage device. For example, a storage cell in the second storage string 128 or the third storage string 208 that is not intended to be programmed can be erroneously programmed due to program disturb. In some embodiments, the voltage in the channel of the second storage string 128 can rise due to the coupling effect of the increased voltage of the word lines (e.g., WL0-WLn). The increased voltage in the channel of the second storage string 128 can cause the voltage of the TSG line 113 to increase, which can turn on the transistor with the TSG 122 in the second storage string 128. As a result, the channel of the second storage string 122 can have a current leakage through the bit line 126. The current leakage in the bit line 126 can cause the voltage in the channel of the second storage string 128 to decrease. As a result, the storage cell 230 in the second storage string 128 can be programmed by the program voltage V pgm applied to WLm, which causes the problem of program disturb.

[0033] In some implementations, programming disturbance can be more significant when programming storage cells coupled to word lines closer to transistors with TSGs 112, 122 (e.g., WL0 and WL1) than when programming storage cells coupled to word lines further away from transistors with TSGs 112, 122 (e.g., WL2-WLn). For example, due to the coupling effect of the increased voltage of the word lines WL0-WLn, the transistors with TSGs 122 in the second storage string 128 are more likely to be turned on erroneously. In some implementations, to mitigate programming disturbance, the storage device can apply a lower voltage to the TSG line 113 when programming storage cells coupled to word lines closer to transistors with TSGs 112, 122 (e.g., WL0 and WL1) and can apply a normal voltage to the TSG line 113 when programming storage cells coupled to other word lines (e.g., WL2-WLn).

[0034] Figure 3 An example is shown of a cross-sectional side view of a storage cell array 101 including a storage string 108, in accordance with some aspects of the present disclosure. As shown, the storage string 108 can extend vertically through a storage stack 304 above a substrate 302. The substrate 302 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. Figure 2

[0035] The storage stack 304 can include pairs of interleaved gate conductive layers 306 and gate-to-gate dielectric layers 308. The number of pairs of interleaved gate conductive layers 306 and gate-to-gate dielectric layers 308 in the storage stack 304 can determine the number of storage cells 106 in the storage cell array 101. The gate conductive layers 306 can include a conductive material, including but not limited to one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, or silicide. In some implementations, each gate conductive layer 306 includes a metal layer, such as a tungsten layer. In some implementations, each gate conductive layer 306 includes a doped polysilicon layer. Each gate conductive layer 306 can include a control gate around a storage cell 106, a DSG 112, or a SSG 110, and can extend laterally like a DSG line 113 at the top of the storage stack 304, a SSG line 115 at the bottom of the storage stack 304, or a word line 118 between the DSG line 113 and the SSG line 115.

[0036] Figure 4 An example storage cell stack 400 is shown including multiple storage cell tiers, in accordance with some aspects of the present disclosure. Figure 4 ​Three example tiers of memory cells are shown in FIG. 4 from the top of the stack 400 to the bottom, i.e., tier 2, tier 1, and tier 0. An example of the stack 400 is Figure 1 The tier 2 is above the tier 1 (e.g., second tier), and the tier 1 is above the tier 0, as shown in the block 104 of FIG. 1. Figure 4 Adjacent tiers in FIG. 4 are connected using inter-tier plugs (IDPs) 402. Figure 4 The IDP DMY tier 1 in FIG. 4 represents dummy word lines in the tier 1 and the tier 2 that are adjacent to the IDP connecting the tier 1 and the tier 2. Figure 4 The IDP DMY tier 0 in FIG. 4 represents dummy word lines in the tier 0 and the tier 1 that are adjacent to the IDP connecting the tier 0 and the tier 1. In some embodiments, programming operations in the stack 400 of memory cells can be performed from the top to the bottom. That is, the memory cells coupled to word lines further away from the substrate 302 are programmed before the memory cells coupled to word lines closer to the substrate 302. When the memory cells in the tier 1 are being programmed, the memory cells in the tier 2 have already been programmed, and the memory cells in the tier 0 have not yet been programmed. In other embodiments, programming operations in the stack 400 of memory cells can be performed from the bottom to the top. That is, the memory cells coupled to word lines closer to the substrate 302 are programmed before the memory cells coupled to word lines further away from the substrate 302. When the memory cells in the tier 1 are being programmed, the memory cells in the tier 0 have already been programmed, and the memory cells in the tier 2 have not yet been programmed.

[0037] Figure 5 Some example peripheral circuits according to some aspects of the present disclosure are shown. The example peripheral circuits include a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, registers 514, an interface 516, and a data bus. In some examples, additional peripheral circuits not shown in FIG. 5 can also be included. Figure 5

[0038] ​The page buffer / sense amplifier 504 can be configured to read data from and program (write) data to the memory cell array 101 according to control signals from the control logic unit 512. In an example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into a page in the memory cell array 101. In another example, the page buffer / sense amplifier 504 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 106 coupled to a selected word line 118. In yet another example, the page buffer / sense amplifier 504 can also sense low power signals from the bit lines 116 representing data bits stored in the memory cells 106 and amplify small voltage swings to identifiable logic levels in read operations. The column decoder / bit line driver 506 can be configured to be controlled by the control logic unit 512 and select one or more memory strings 108 by applying bit line voltages generated from the voltage generator 510.

[0039] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and select / deselect blocks 104 of the memory cell array 101 and select / deselect word lines 118 of the blocks 104. The row decoder / word line driver 508 can also be configured to drive the word lines 118 using word line voltages generated from the voltage generator 510. In some implementations, the row decoder / word line driver 508 can also select / deselect and drive the SSG lines 115 and the DSG lines 113. As described in detail below, the row decoder / word line driver 508 is configured to apply a program voltage to a selected word line 118 in a program operation to the memory cells 106 coupled to the selected word line 118.

[0040] The voltage generator 510 can be configured to be controlled by the control logic unit 512 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be provided to the memory cell array 101.

[0041] The control logic unit 512 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 514 can be coupled to the control logic unit 512 and include state registers, command registers, and address registers for storing state information, command operation codes (OP codes), and command addresses for controlling the operation of each of the peripheral circuits.

[0042] Interface 516 can be coupled to control logic 512 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic 512 and to buffer and relay status information received from control logic 512 to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via a data bus and act as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory cell array 101.

[0043] Figure 6A An example of voltages of components in a memory cell array during programming of a memory block in the memory cell array is shown in accordance with some aspects of the present disclosure. In some implementations, selected word line 602 represents a word line selected for a program operation (e.g., WLm in Figure 2 Figure 2 Figure 2 Figure 2 Figure 1 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 1

[0044] In some implementations, a program operation can include a channel preparation phase 620, a channel boosting phase 622, a program pulse phase 624, a first recovery phase 626, and a second recovery phase 628. For example, Figure 6A ​​​​​​​​​​​The voltages shown in may represent the voltages during the programming pulses in the later portion of an Incremental Step Pulse Programming (ISPP) scheme. For example, for an ISPP scheme with 16 programming pulses, you may use Figure 6A The programming operation using the last 10 pulses is performed at the voltage shown. Since the last 10 pulses have a higher voltage than the first 6 pulses and may cause greater interference during the programming operation, the channel preparation phase 620 may include a channel precharge operation. The channel precharge operation may be performed on the memory string selected for programming (e.g., Figure 2 The first memory string 108 in the channel and the memory strings not selected for programming (eg, Figure 2 618 is used to precharge the channel of the second memory string 128 and the third memory string 208 in the memory block 104. In some embodiments, the programming operation in the memory block 104 is performed from top to bottom. In the top-to-bottom programming operation, the voltage of ACS 618 is used to precharge the channel by controlling the voltage of BSG 614.

[0045] In some embodiments, a channel precharge operation is performed at the beginning of the channel preparation phase 620 (i.e., before t0). To perform the channel precharge operation, the voltage of the ACS 618 is increased from V1 (e.g., 0V) to V5 (e.g., 2V). Additionally, a voltage V6 (e.g., 5V) can be applied to the bsg 614 to turn on the transistors coupled to the bsg 614 so as to connect the memory strings (e.g., Figure 2 The channels of the memory strings 108, 128, 208 in the memory are connected to the ACS 618. After the precharge operation is performed, the voltage of the bsg 614 decreases from V6 to V1 and remains at V1 until the end of the second recovery phase 628. The voltage of the ACS 618 may remain at V5 until the end of the second recovery phase 628.

[0046] In some embodiments, after the channel precharge operation (i.e., after t0) and during the channel preparation phase 620, the voltage of tsg(select) 606 is increased from V1 to V4 (e.g., 3V, so that the voltage of tsg(select) 606 is greater than the threshold voltage of the TSG transistor) and remains at V4 until the end of the second recovery phase 628. In other embodiments, such as Figure 6AAs shown, the voltage of tsg(select) 606 can be increased to V4 in a two-step approach. First, starting at t0 during the channel preparation phase 620, the voltage of tsg(select) 606 can be increased from V1 to a voltage between V1 and V4 (i.e., V4-deltaV). Second, starting from the channel boosting phase 622, the voltage of tsg(select) 606 can be increased from V4-deltaV to V4. In some embodiments, the two-step approach can help reduce program disturb in memory strings that are not selected for programming.

[0047] In some embodiments, the voltage of tsg(unselected) 610 remains at V1 from the beginning of the channel preparation phase 620 to the end of the second recovery phase 628 .

[0048] In some embodiments, from the start of the channel boosting phase 622 (i.e., t1), the voltage of the selected word line 602 is increased from V1 to V2 (e.g., 6.5V). From the start of the programming pulse phase 624 (i.e., t2), the voltage of the selected word line 602 is increased from V2 to V pgm (For example, between 10V and 20V). From the start of the first recovery phase 626, the voltage of the selected word line 602 is increased from V pgm During the second recovery phase 628, the voltage of the selected word line 602 may be maintained at V3. After the second recovery phase 628, the voltage of the selected word line 602 may be reduced from V3 to the power supply voltage V cc (e.g., 2V). In some embodiments, when a particular voltage is applied to a line at a particular time, it may take some time before the voltage of the line ramps up to the particular voltage due to a loading effect associated with the line. For example, when V2 is applied to the selected word line 602 at t1, it may take some time for the voltage of the selected word line 602 to increase from V1 to V2, as shown in FIG. Figure 6A In other embodiments, the voltage of the line can immediately reach the applied voltage.

[0049] In some embodiments, from the beginning of the channel boosting phase 622 (ie, t1), the voltage of the unselected word line 604 increases from V1 to the pass voltage V pass1 (eg, 5V). The voltage of the unselected word line 604 may be maintained at V pass1 Until the second recovery phase 628 ends, and can be reduced to V after the second recovery phase 628 cc .

[0050] In some embodiments, from the beginning of the channel boosting phase 622 (ie, t1), the voltage of the dummy word line 612 increases from V1 to the pass voltage V pass2 (eg, 5V). The voltage of the dummy word line 612 is maintained at Vpass2 until the end of the second recovery phase 628, and can be reduced to V cc .

[0051] In some embodiments, starting from the channel preparation phase 620, the voltage to inhibit the BL in the BL 616 is increased from VI to V7 (e.g., 2V). The difference between the voltage of the tsg(select) 606 (i.e., V4) and V7 is less than or equal to the threshold voltage of the TSG transistor coupled to the tsg(select) 606 during the program pulse phase 620. The voltage to program the BL in the BL 616 remains at VI from the start of the channel preparation phase 620 to the end of the second recovery phase 628. From the start of the channel boosting phase 622 (ti), the voltage to 3BL in the BL 616 can be increased from VI to an intermediate voltage between VI and V7.

[0052] Figure 6B An example of voltages of components in a memory cell array during programming of a memory block in the memory cell array is shown in accordance with some aspects of the present disclosure. The voltage conditions of most of the components of the memory block (e.g., select word line 602, unselect word line 604, tsg(unselect) 610, dummy word line 612, bsg 614, BL 616, and ACS 618) are the same as those in Figure 6A , except for tsg(select) 606, 608. As shown with reference to Figure 2 To mitigate programming disturbance, the memory device can apply a lower voltage to tsg(select) 606 when programming memory cells coupled to word lines closer to the TSG transistor (e.g., WL0 and WL1), and a higher voltage to tsg(select) 606 when programming memory cells coupled to other word lines (e.g., WL2-WLn), as shown with reference to

[0053] In some embodiments, during a programming operation for programming a memory cell coupled to one of word lines WL2-WLn, after a channel precharge operation (i.e., after t0) and during a channel preparation phase 620, the voltage of tsg(select) 608 is increased from V1 to V4 (e.g., 3V, such that the voltage of tsg(select) 608 is higher than the threshold voltage of the TSG transistor coupled to tsg(select) 708). The voltage of tsg(select) 608 can be maintained at V4 until the end of the second recovery phase 628. In other embodiments, the voltage of tsg(select) 608 can be increased to V4 in a two-step approach. First, starting at t0 during the channel preparation phase 620, the voltage of tsg(select) 608 can be increased from V1 to a voltage between V1 and V4 (i.e., V4-deltaV). Second, after t0 during the channel preparation phase 620 and before the program pulse phase 624 begins, the voltage of tsg(select) 608 may be increased from V4-deltaV to V4.

[0054] In some embodiments, during a programming operation for programming a memory cell coupled to WL0 or WL1, after a channel precharge operation (i.e., after t0) and during a channel preparation phase 620, the voltage of tsg(select) 606 is increased from V1 to V9 (e.g., 2.5-2.9V, such that the voltage of tsg(select) 606 remains above the threshold voltage of the TSG transistor coupled to the tsg(select) line). The voltage of tsg(select) 606 can remain at V9 until the end of the second recovery phase 628. V9 is lower than V4. In other embodiments, the voltage of tsg(select) 606 can be increased to V9 in a two-step approach. First, starting at t0 during the channel preparation phase 620, the voltage of tsg(select) 606 can be increased from V1 to a voltage between V1 and V9 (i.e., V9-deltaV). Second, after t0 during the channel preparation phase 620 and before the program pulse phase 624 begins, the voltage of tsg(select) 608 may be increased from V9-deltaV to V9.

[0055] In some embodiments, the voltage of tsg(select) 606 when programming storage cells coupled to WL0 can be the same as the voltage of tsg(select) 606 when programming storage cells coupled to WL1. In other embodiments, the voltage of tsg(select) 606 when programming storage cells coupled to WL0 is lower than the voltage of tsg(select) 606 when programming storage cells coupled to WL1. For example, in a program operation programming storage cells coupled to WL0, the voltage of tsg(select) 606 increases from VI to V9 after the channel pre-charge operation (i.e., after to) and before the program pulse phase 624. In a program operation programming storage cells coupled to WL1, the voltage of tsg(select) 606 increases from VI to V4 after the channel pre-charge operation (i.e., after to) and before the program pulse phase 624. In some embodiments, the voltage of tsg(select) 606 when programming storage cells coupled to WL0 is lower than the voltage of tsg(select) 606 when programming storage cells coupled to WL1. For example, in a program operation programming storage cells coupled to WL0, the voltage of tsg(select) 606 increases from VI to V9 after the channel pre-charge operation (i.e., after to) and before the program pulse phase 624. In a program operation programming storage cells coupled to WL1, the voltage of tsg(select) 606 increases from VI to V 10 . 10 higher than V9 and lower than V4.

[0056] In some embodiments, the word lines are divided into two groups using a predetermined threshold. The first group of word lines is closer to the TSG transistor than the second group of word lines. For example, the predetermined threshold can be set to 2. The first group of word lines can include WL0 and WL1, and the second group of word lines can include WL2-WLn. When programming storage cells coupled to WL0 and WL1, the voltage applied to tsg(select) 606 can be the lower voltage V9. When programming storage cells coupled to WL2-WLn, the voltage applied to tsg(select) 608 can be the higher voltage V4. As another example, the predetermined threshold can be set to 3. The first group of word lines can include WL0, WL1, and WL2, and the second group of word lines can include WL3-WLn. When programming storage cells coupled to WL0, WL1, and WL2, the voltage applied to tsg(select) 606 can be the lower voltage V9. When programming storage cells coupled to WL3-WLn, the voltage applied to tsg(select) 608 can be the higher voltage V4. It should be noted that the word lines can be grouped based on other suitable predetermined thresholds.

[0057] Figure 7A Another example of voltages of components in a storage cell array during programming of a storage block in the storage cell array according to some aspects of the present disclosure is shown. In some embodiments, a program operation can include a channel preparation phase 720, a channel boost phase 722, a program pulse phase 724, a first recovery phase 726, and a second recovery phase 728. Similar to the example shown in FIG. 6, the channel preparation phase 720 can include a channel pre-charge operation 712 and a channel pre-charge verify operation 714. The channel boost phase 722 can include a channel boost operation 716 and a channel boost verify operation 718. The program pulse phase 724 can include a program pulse operation 726 and a program pulse verify operation 728. The first recovery phase 726 can include a first recovery operation 730 and a first recovery verify operation 732. The second recovery phase 728 can include a second recovery operation 734 and a second recovery verify operation 736. Figure 6A , Figure 7AThe voltages shown in may represent voltages during programming pulses in a later portion of the ISPP scheme (eg, the last 10 pulses of an ISPP scheme having 16 programming pulses).The channel preparation phase 720 may also include a channel precharge operation. Figure 6A shows the voltages for programming operation from top to bottom, with Figure 6A Different, in Figure 7A In the programming operation from bottom to top, the voltage of BL 716 is used to precharge the channel by controlling the voltages of tsg(select) 706 and tsg(unselect) 710.

[0058] like Figure 7A As shown, the voltage during the channel preparation phase 720 may be different from Figure 6A Specifically, the voltages of tsg(select) 706, tsg(unselect) 710, bsg 714, and BL 716 may be different from Figure 6A To perform the channel precharge operation, the voltage of BL 716 is increased from V1 to V7 from the beginning of the channel preparation phase 720. In addition, voltage V6 may be applied to tsg(select) 706 and tsg(unselect) 710 at the beginning of the channel preparation phase 720. In this way, by turning on the transistors coupled to tsg(select) 706 and tsg(unselect) 710, the memory string (e.g., Figure 2 The channels of the memory strings 108, 128, 208 in FIG. 1 are connected to corresponding bit lines (eg, Figure 2 After the precharge operation is performed and before t0, the voltage of tsg(select) 706 and tsg(unselect) 710 decreases to V1.

[0059] From the start of the channel preparation phase 720 to the end of the second recovery phase 728 , the voltage of the bsg 714 may be maintained at V1 .

[0060] Figure 7B 1 shows another example of voltages of components in a memory block during programming of the memory block according to some aspects of the present disclosure. The voltage conditions of most components of the memory block (e.g., selected word line 702, unselected word line 704, tsg (unselected) 710, dummy word line 712, bsg 714, BL 716, and ACS 718) are the same as Figure 7A Same as those in , except for tsg (select) 706, 708 after t0. Figure 2As explained, to mitigate programming disturbance, the storage device can apply a lower voltage to tsg(select) 706 when programming storage cells coupled to word lines closer to the TSG transistor (e.g., WL0 and WL1), and a higher voltage to tsg(select) 708 when programming storage cells coupled to other word lines (e.g., WL2-WLn).

[0061] In some embodiments, in a program operation to program storage cells coupled to WL2-WLn, the voltage of tsg(select) 708 is increased from VI to V4 (e.g., 3V, such that the voltage of tsg(select) 708 is higher than the threshold voltage of the TSG transistor coupled to tsg(select) 708) after the channel pre-charge operation (i.e., after to) and during the channel preparation phase 720. The voltage of tsg(select) 708 can remain at V4 until the end of the second recovery phase 728. In other embodiments, the voltage of tsg(select) 708 can be increased to V4 in a two-step approach. First, from to during the channel preparation phase 720, the voltage of tsg(select) 708 can be increased from VI to a voltage between VI and V4 (i.e., V4-deltaV). Second, after to during the channel preparation phase 720 and before the start of the program pulse phase 724, the voltage of tsg(select) 708 can be increased from V4-deltaV to V4.

[0062] In some embodiments, in a program operation to program storage cells coupled to WL0 or WL1, the voltage of tsg(select) 706 is increased from VI to V9 (e.g., 2.5-2.9V, such that the voltage of tsg(select) 706 is still higher than the threshold voltage of the TSG transistor coupled to tsg(select) 706) after the channel pre-charge operation (i.e., after to) and during the channel preparation phase 720. V9 is lower than V4. The voltage of tsg(select) 706 can remain at V9 until the end of the second recovery phase 728. In other embodiments, the voltage of tsg(select) 706 can be increased to V9 in a two-step approach. First, from to during the channel preparation phase 720, the voltage of tsg(select) 706 can be increased from VI to a voltage between VI and V9 (i.e., V9-deltaV). Second, after to during the channel preparation phase 720 and before the start of the program pulse phase 724, the voltage of tsg(select) 708 can be increased from V9-deltaV to V9.

[0063] In some embodiments, the voltage of tsg(select) 706 when programming memory cells coupled to WL0 can be the same as the voltage of tsg(select) 706 when programming memory cells coupled to WL1. In other embodiments, the voltage of tsg(select) 706 when programming memory cells coupled to WL0 is lower than the voltage of tsg(select) 706 when programming memory cells coupled to WL1. For example, in a programming operation to program memory cells coupled to WL0, the voltage of tsg(select) 706 increases from V1 to V9 after a channel precharge operation (i.e., after t0) and before a programming pulse phase 724. In a programming operation to program memory cells coupled to WL1, the voltage of tsg(select) 706 increases from V1 to V9 after a channel precharge operation (i.e., after t0) and before a programming pulse phase 724. 10 . V 10 Higher than V9 and lower than V4.

[0064] In some embodiments, a predetermined threshold is used to divide the word lines into two groups. The first group of word lines is closer to the TSG transistor than the second group of word lines. For example, the predetermined threshold can be set to 2. The first group of word lines can include WL0 and WL1, and the second group of word lines can include WL2-WLn. When programming memory cells coupled to WL0 and WL1, the voltage applied to tsg (select) 706 can be a lower voltage V9. When programming memory cells coupled to WL2-WLn, the voltage applied to tsg (select) 708 can be a higher voltage V4. For another example, the predetermined threshold can be set to 3. The first group of word lines can include WL0, WL1, and WL2, and the second group of word lines can include WL3-WLn. When programming memory cells coupled to WL0, WL1, and WL2, the voltage applied to tsg (select) 706 can be a lower voltage V9. When programming memory cells coupled to WL3-WLn, the voltage applied to tsg(select) 708 may be the higher voltage V4. It should be noted that word lines may be grouped based on other suitable predetermined thresholds.

[0065] Figure 8A Another example of voltages of components in a memory cell array during programming of a memory block in the memory cell array according to some aspects of the present disclosure is shown. In some embodiments, a programming operation may include a channel preparation phase 820, a channel boosting phase 822, a programming pulse phase 824, a first recovery phase 826, and a second recovery phase 828. Figure 6A different, Figure 8A The voltages shown in may represent the voltages during the programming pulses in the earlier part of the ISPP scheme. For example, for an ISPP scheme with 16 programming pulses,Figure 8A The programming operation using the first 6 pulses is performed with the voltages shown. Since the first 6 pulses have lower voltages than the last 10 pulses, the disturbance during the programming operation is less severe, and the channel pre-charge operation can not be performed during the channel preparation phase 820. In some embodiments, since the channel pre-charge operation is not performed, Figure 8A The voltages shown in FIG. 8B can be applied to a programming operation that takes a top-to-bottom order and a programming operation that takes a bottom-to-top order.

[0066] As Figure 8A shown, the voltage conditions for most of the components of the memory block (e.g., selected word line 802, unselected word line 804, tsg(unselected) 810, dummy word line 812, BL 816, and ACS 818) are the same as those in Figure 6A , except for tsg(selected) 806 and bsg 814.

[0067] In some embodiments, the voltage of tsg(selected) 806 increases from VI to V4 from the start of the channel preparation phase 820. In other embodiments, the voltage of tsg(selected) 806 increases from VI to V4 in a two-step approach. For example, the voltage of tsg(selected) 806 first increases from VI to V4-deltaV from the start of the channel preparation phase 820, and then increases from V4-deltaV to V4 before the start of the programming pulse phase 824.

[0068] In some embodiments, the voltage of bsg 814 remains at VI from the start of the channel preparation phase 820 to the end of the second recovery phase 828.

[0069] Figure 8B Another example of voltages of components in a memory block during programming of the memory block is shown in accordance with some aspects of the disclosure. The voltage conditions for most of the components of the memory block (e.g., selected word line 802, unselected word line 804, tsg(unselected) 810, dummy word line 812, bsg 814, BL 816, and ACS 818) are the same as those in Figure 8A , except for tsg(selected) 806, 808. As explained with reference to Figure 2 to mitigate programming disturbance, the memory device can apply a lower voltage to tsg(selected) 806 when programming memory cells coupled to word lines (e.g., WL0 and WL1) that are closer to the TSG transistor, and a higher voltage to tsg(selected) 808 when programming memory cells coupled to other word lines (e.g., WL2-WLn).

[0070] In some embodiments, in a program operation to program a storage cell coupled to WL2-WLn, from the beginning of the channel preparation phase 820, the voltage of tsg(select) 808 is increased from VI to V4 and held at V4 until the end of the second recovery phase 828. In other embodiments, the voltage of tsg(select) 808 can be increased to V4 in a two-step approach. First, from the beginning of the channel preparation phase 820, the voltage of tsg(select) 808 can be increased from VI to a voltage between VI and V4 (i.e., V4-deltaV). Second, after the channel preparation phase 820 and before the beginning of the program pulse phase 824, the voltage of tsg(select) 808 can be increased from V4-deltaV to V4.

[0071] In some embodiments, in a program operation to program a storage cell coupled to WL0 or WL1, from the beginning of the channel preparation phase 820, the voltage of tsg(select) 806 is increased from VI to V9 and held at V9 until the end of the second recovery phase 828. V9 is lower than V4. In other embodiments, the voltage of tsg(select) 806 can be increased to V9 in a two-step approach. First, from the beginning of the channel preparation phase 820, the voltage of tsg(select) 806 can be increased from VI to a voltage between VI and V9 (i.e., V9-deltaV). Second, after the channel preparation phase 820 and before the beginning of the program pulse phase 824, the voltage of tsg(select) 806 can be increased from V9-deltaV to V9.

[0072] In some embodiments, the voltage of tsg(select) 806 when programming a storage cell coupled to WL0 can be the same as the voltage of tsg(select) 806 when programming a storage cell coupled to WL1. In other embodiments, the voltage of tsg(select) 806 when programming a storage cell coupled to WL0 is lower than the voltage of tsg(select) 806 when programming a storage cell coupled to WL1. For example, in a program operation to program a storage cell coupled to WL0, after the channel pre-charge operation (i.e., after to) and before the program pulse phase 824, the voltage of tsg(select) 806 is increased from VI to V9. In a program operation to program a storage cell coupled to WL1, after the channel pre-charge operation (i.e., after to) and before the program pulse phase 824, the voltage of tsg(select) 806 is increased from VI to V 10 . 10 which is higher than V9 and lower than V4.

[0073] In some embodiments, the word lines are divided into two groups using a predetermined threshold. The first group of word lines is closer to the TSG transistor than the second group of word lines. For example, the predetermined threshold can be set to 2. The first group of word lines can include WL0 and WL1, and the second group of word lines can include WL2-WLn. When programming the memory cells coupled to WL0 and WL1, the voltage applied to tsg(select) 806 can be the lower voltage V9. When programming the memory cells coupled to WL2-WLn, the voltage applied to tsg(select) 808 can be the higher voltage V4. As another example, the predetermined threshold can be set to 3. The first group of word lines can include WL0, WL1, and WL2, and the second group of word lines can include WL3-WLn. When programming the memory cells coupled to WL0, WL1, and WL2, the voltage applied to tsg(select) 806 can be the lower voltage V9. When programming the memory cells coupled to WL3-WLn, the voltage applied to tsg(select) 808 can be the higher voltage V4. It should be noted that the word lines can be grouped based on other suitable predetermined thresholds.

[0074] Figure 9 An example of a flowchart of a method for managing program disturbance in a storage device is shown in accordance with some aspects of the present disclosure. The storage device can include a storage array including a first memory string. The memory string can include a top select gate (TSG) transistor, a bottom select gate (BSG) transistor, and a memory cell located between the TSG transistor and the BSG transistor. The memory cell is coupled to a word line.

[0075] At 902, a first voltage (e.g., V9 in FIG. 9) is applied to a select line coupled to a TSG during a first program operation of a first memory cell coupled to a first word line (e.g., WL0 in FIG. 9) closest to the TSG transistor. Figure 2 At 904, a second voltage (e.g., V4 in FIG. 9) is applied to the select line coupled to the TSG during a second program operation of a second memory cell coupled to a second word line (e.g., WL1 in FIG. 9) second closest to the TSG transistor. Figure 6B In some embodiments, the first program operation can include a channel preparation phase, a channel boosting phase, a program pulse phase, a first recovery phase, and a second recovery phase. The first voltage can be applied after a channel pre-charge operation during the channel preparation phase until the end of the second recovery phase.

[0076] At 904, a second voltage (e.g., V4 in FIG. 9) is applied to the select line coupled to the TSG during a second program operation of a second memory cell coupled to a second word line (e.g., WL1 in FIG. 9) second closest to the TSG transistor. Figure 2 At 904, a second voltage (e.g., V4 in FIG. 9) is applied to the select line coupled to the TSG during a second program operation of a second memory cell coupled to a second word line (e.g., WL1 in FIG. 9) second closest to the TSG transistor. Figure 6BV9) in FIG. 9. The second voltage is higher than or equal to the first voltage. In some embodiments, the second programming operation can include a channel preparation phase, a channel boosting phase, a program pulse phase, a first recovery phase, and a second recovery phase. The second voltage can be applied after a channel pre-charge operation during the channel preparation phase until the end of the second recovery phase.

[0077] At 906, a third voltage (e.g., V4 in FIG. 9) is applied to a select line coupled to a TSG during a third programming operation of a third storage cell coupled to a third word line (e.g., Figure 2 WL2-WLn in FIG. 9) further away from the TSG than the first word line and the second word line. The third voltage is higher than the first voltage and the second voltage. In some embodiments, the third programming operation can include a channel preparation phase, a channel boosting phase, a program pulse phase, a first recovery phase, and a second recovery phase. The third voltage can be applied after a channel pre-charge operation during the channel preparation phase until the end of the second recovery phase. Figure 6B

[0078] Figure 10 A block diagram illustrating an example system 1000 having a storage device in accordance with some aspects of the present disclosure is shown. The system 1000 can be a mobile phone, a desktop computer, a notebook computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown, the system 1000 can include a host 1008 and a storage system 1002 having one or more storage devices 1004 and a memory controller 1006. The host 1008 can be a processor of an electronic device, such as a central processing unit (CPU) or a system on chip (SoC), such as an application processor (AP). The host 1008 can be configured to send data to or receive data from the storage device 1004. Figure 10

[0079] ​​The storage device 1004 can be any storage device disclosed in the present disclosure. According to some embodiments, a memory controller 1006 is coupled to the storage device 1004 and the host 1008 and configured to control the storage device 104. The memory controller 1006 can manage data stored in the storage device 1004 and communicate with the host 1008. In some embodiments, the memory controller 1006 is designed for operation in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB), a flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1006 is designed for operation in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 1006 can be configured to control operations of the storage device 1004, such as read, erase, and program operations. The memory controller 1006 can also be configured to manage various functions with respect to data stored or to be stored in the storage device 1004, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 1006 is also configured to process error correction codes (ECC) for data read from or written to the storage device 1004. Any other suitable functions can also be performed by the memory controller 1006, such as formatting the storage device 1004.

[0080] The memory controller 1006 can communicate with external devices (e.g., the host 1008) according to a particular communication protocol. For example, the memory controller 1006 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0081] The memory controller 1006 and the one or more storage devices 1004 can be integrated into various types of storage devices. For example, the memory controller 1006 and the one or more storage devices 1004 can be packaged in a universal flash storage (UFS) package or an eMMC package. In the case of a UFS package, the memory controller 1006 and the one or more storage devices 1004 can be packaged in a single package with a UFS interface. Figure 11AIn one example shown, the memory controller 1006 and the single storage device 1004 can be integrated into a memory card 1102. The memory card 1102 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 1102 can also include a memory card connector 1104 that couples the memory card 1102 with a host (e.g., the host 1008 in Figure 10 FIG. 6A). In another example shown, the memory controller 1006 and the multiple storage devices 1004 can be integrated into an SSD 1106. The SSD 1106 can also include an SSD connector 1108 that couples the SSD 1106 with a host (e.g., the host 1008 in Figure 11B FIG. 6A). In some implementations, the storage capacity and / or operating speed of the SSD 1106 is greater than the storage capacity and / or operating speed of the memory card 1102. Figure 10

[0082] Certain aspects of the subject matter described herein can be implemented as a storage device. The storage device includes an array of storage cells and a peripheral circuit coupled to the storage array. The storage array can include a first string of storage cells (e.g., the string 108 in Figure 2 FIG. 6A). The first string of storage cells can include a first select gate transistor (e.g., a top select gate transistor), a second select gate transistor (e.g., a bottom select gate transistor), and a storage cell between the first select gate transistor and the second select gate transistor. The peripheral circuit is configured to apply a first voltage (e.g., V9 in Figure 6B FIG. 6A) to a select line coupled to the first select gate transistor during a first program operation of a first storage cell of the storage cells. The first storage cell is coupled to a first word line (e.g., WL0 in Figure 2 FIG. 6A) that is closest to the first select gate transistor among word lines coupled to the storage cells. The peripheral circuit is also configured to apply a second voltage (e.g., V4 in Figure 6B FIG. 6A) to the select line coupled to the first select gate transistor during a second program operation of a second storage cell of the storage cells. The second storage cell is coupled to a second word line (e.g., one of WL2-WLn in Figure 2 FIG. 6A). The second word line is farther from the first select gate transistor than the first word line. The second voltage is higher than the first voltage.

[0083] The storage device can include one or more of the following features.

[0084] ​In some embodiments, the peripheral circuit is further configured to apply a third voltage (e.g., V9 in Figure 6B ) to the select line coupled to the first select gate transistor during a third programming operation of a third storage cell of the storage cells. The third storage cell is coupled to a third word line (e.g., WL1 in Figure 2 ). The third word line is closer to the first select gate transistor than the second word line. The third voltage is higher than or equal to the first voltage and lower than the second voltage.

[0085] In some embodiments, the third word line is the second closest word line to the first select gate transistor after the first word line.

[0086] In some embodiments, the peripheral circuit is further configured to apply the second voltage to the select line coupled to the first select gate transistor during a fourth programming operation of a fourth storage cell of the storage cells. The fourth storage cell is coupled to a fourth word line (e.g., one of WL2-WLn in Figure 2 ) different from the first word line and the third word line.

[0087] In some embodiments, the peripheral circuit is further configured to apply a fourth voltage (e.g., V9-deltaV in Figure 6B ) to the select line coupled to the first select gate transistor during a first time period (e.g., channel preparation phase 620 in Figure 6B ) of the first programming operation. The fourth voltage is lower than the first voltage. The peripheral circuit is further configured to apply the first voltage to the select line coupled to the first select gate transistor during a second time period (e.g., channel boost phase 622, program pulse phase 624, first recovery phase 626, and second recovery phase 628 in Figure 6B ) of the first programming operation. The second time period follows the first time period.

[0088] In some embodiments, the second time period includes a third time period (e.g., channel boost phase 622 in Figure 6B ), a fourth time period following the third time period (e.g., program pulse phase 624 in Figure 6B ), and a fifth time period following the fourth time period (e.g., first recovery phase 626 and second recovery phase 628 in Figure 6B ). The peripheral circuit is further configured to apply a fifth voltage (e.g., V2 in Figure 6B ) to the first word line during the third time period, a program voltage (e.g., V Figure 6B in pgm ) to the first word line during the fourth time period, and a sixth voltage (e.g., V3 in Figure 6B ) to the first word line during the fifth time period. The fifth voltage and the sixth voltage are higher than the first voltage and lower than the program voltage.

[0089] In some embodiments, the peripheral circuit is further configured to apply a pass voltage to the second word line during the second time period.

[0090] In some embodiments, the peripheral circuit is configured to program the storage cells coupled to the first word line before programming the storage cells coupled to the second word line.

[0091] In some embodiments, the peripheral circuit is configured to program the storage cells coupled to the first word line after programming the storage cells coupled to the second word line.

[0092] In some embodiments, the peripheral circuit is further configured to apply a seventh voltage (e.g., V7 in Figure 2 ) to a bit line coupled to a second storage string (e.g., storage string 128 in Figure 6B ) of the storage array during the first programming operation. The seventh voltage is higher than or equal to a difference between the first voltage and a predetermined threshold voltage of a first select gate transistor (e.g., a top select gate transistor) in the second storage string.

[0093] Certain aspects of the subject matter described herein can be implemented as a method of operating a storage device. The storage device includes an array of storage cells, the array of storage cells including a first storage string (e.g., storage string 108 in Figure 2 ). The first storage string can include a first select gate transistor (e.g., a top select gate transistor), a second select gate transistor (e.g., a bottom select gate transistor), and a storage cell located between the first select gate transistor and the second select gate transistor. The method includes applying a first voltage (e.g., V9 in Figure 6B ) to a select line coupled to the first select gate transistor during a first programming operation of a first storage cell of the storage cells. The first storage cell is coupled to a first word line (e.g., WL0 in Figure 2 ) that is closest to the first select gate transistor among word lines coupled to the storage cells. The method further includes applying a second voltage (e.g., V4 in Figure 6B ) to the select line coupled to the first select gate transistor during a second programming operation of a second storage cell of the storage cells. The second storage cell is coupled to a second word line (e.g., one of WL2-WLn in Figure 2 ). The second word line is farther from the first select gate transistor than the first word line. The second voltage is higher than the first voltage.

[0094] The method of performing a programming operation by a storage device can include one or more of the following features.

[0095] In some embodiments, the method further includes applying a third voltage (e.g., V9 in Figure 6B ) to the select line coupled to the first select gate transistor during a third programming operation of a third storage cell in the storage cells. The third storage cell is coupled to a third word line (e.g., WL1 in Figure 2 ). The third word line is closer to the first select gate transistor than the second word line. The third voltage is higher than or equal to the first voltage and lower than the second voltage.

[0096] In some embodiments, the third word line is a second closest word line to the first select gate transistor after the first word line.

[0097] In some embodiments, the method includes applying the second voltage to the select line coupled to the first select gate transistor during a fourth programming operation of a fourth storage cell in the storage cells. The fourth storage cell is coupled to a fourth word line (e.g., one of WL2-WLn in Figure 2 ) different from the first word line and the third word line.

[0098] In some embodiments, the method further includes applying a fourth voltage (e.g., V9-deltaV in Figure 6B ) to the select line coupled to the first select gate transistor during a first time period (e.g., channel preparation phase 620 in Figure 6B ) of the first programming operation. The fourth voltage is lower than the first voltage. The method further includes applying the first voltage to the select line coupled to the first select gate transistor during a second time period (e.g., by channel boost phase 622, program pulse phase 624, first recovery phase 626, and second recovery phase 628 in Figure 6B ) of the first programming operation. The second time period follows the first time period.

[0099] In some embodiments, the second time period includes a third time period (e.g., channel boost phase 622 in Figure 6B ), a fourth time period following the third time period (e.g., program pulse phase 624 in Figure 6B ), and a fifth time period following the fourth time period (e.g., first recovery phase 626 and second recovery phase 628 in Figure 6B ). The peripheral circuit is further configured to apply a fifth voltage (e.g., V2 in Figure 6B ) to the first word line during the third time period, a program voltage (e.g., V Figure 6B in pgm ) to the first word line during the fourth time period, and a sixth voltage (e.g., V3 in Figure 6B ) to the first word line during the fifth time period. The fifth voltage and the sixth voltage are higher than the first voltage and lower than the program voltage.

[0100] In some embodiments, the method further includes applying a pass voltage to the second word line during the second time period.

[0101] In some embodiments, the method further includes applying a seventh voltage (e.g., V7 of Figure 2 ) to a bit line coupled to a second memory string (e.g., memory string 128 of Figure 6B ) of the memory array during the first program operation. The seventh voltage is higher than or equal to a difference between the first voltage and a predetermined threshold voltage of a first select gate transistor (e.g., a top select gate transistor) in the second memory string.

[0102] Certain aspects of the subject matter described herein can be implemented as a memory system. The memory system includes a memory device and a controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells and a peripheral circuit coupled to the memory array. The memory array can include a memory string (e.g., memory string 108 of Figure 2 ). The memory string can include a first select gate transistor (e.g., a top select gate transistor), a second select gate transistor (e.g., a bottom select gate transistor), and a memory cell between the first select gate transistor and the second select gate transistor. The peripheral circuit is configured to apply a first voltage (e.g., V9 of Figure 6B ) to a select line coupled to the first select gate transistor during a first program operation of a first memory cell of the memory cells. The first memory cell is coupled to a first word line (e.g., WL0 of Figure 2 ) that is closest to the first select gate transistor among word lines coupled to the memory cells. The peripheral circuit is further configured to apply a second voltage (e.g., V4 of Figure 6B ) to the select line coupled to the first select gate transistor during a second program operation of a second memory cell of the memory cells. The second memory cell is coupled to a second word line (e.g., one of WL2-WLn of Figure 2 ). The second word line is farther from the first select gate transistor than the first word line. The second voltage is higher than the first voltage.

[0103] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to a particular embodiment. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any sub-combination. Furthermore, although previously described features may be described as working in certain combinations and even initially claimed as such, in some cases one or more features in the claimed combination may be deleted from that combination, and the claimed combination may be directed to a sub-combination or a variant of a sub-combination.

[0104] As used in this disclosure, the terms "a" or "the" are used to include one or more than one, unless the context clearly indicates otherwise. Unless otherwise specified, the term "or" is used to refer to a non-exclusive "or". The expression "at least one of A and B" has the same meaning as "A, B, or A and B". In addition, the words or terms used in this disclosure and not otherwise defined are for descriptive purposes only and not for limiting purposes. The use of any section headings is to aid reading of the document and should not be construed as limiting; information related to the section heading may appear within or outside that particular section.

[0105] As used in this disclosure, the terms "about" or "approximately" can allow for a degree of variability in values ​​or ranges, such as within 10%, within 5%, or within 1% of a stated value or stated range limit.

[0106] As used in this disclosure, the term "substantially" refers to a majority or majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0107] Values stated in ranges format should be interpreted in a flexible manner to include both values explicitly recited as the limits of the range but also to include values implicitly lying within the range. For example, a range of "0.1 % to about 5%" or "0.1 % to 5%" should be interpreted to include not only the explicitly recited values of about 0.1 % to about 5%, but also values such as 1 %, 2%, 3%, and 4%, and sub-ranges within the indicated range (e.g., 0.1 % to 0.5%, 1.1 % to 2.2%, 3.3% to 4.4%). Unless otherwise indicated, the expression "X to Y" has the same meaning as "about X to about Y." Likewise, unless otherwise indicated, the expression "X, Y, or Z" has the same meaning as "about X, about Y, or about Z."

[0108] Particular embodiments of the subject matter have been described. Other embodiments, alterations, and permutations of the described embodiments are within the scope of the appended claims, as will be apparent to those skilled in the art. While operations are depicted in the drawings or claims in a particular order, this should not be understood as requiring or implying that such operations be performed in the particular order shown or in sequential order, or that all operations be performed, to achieve desirable results. In certain circumstances, multitasking or parallel processing (or multitasking and parallel processing) can be advantageous and can be employed within the scope of the disclosure, depending on the circumstances.

[0109] Moreover, the separation or integration of various system modules and components in the previously described embodiments should not be understood as requiring or implying that such separation or integration in all embodiments, and that the described components and systems can generally be separated or integrated together in the same way or in a different way.

[0110] Accordingly, the previously described example embodiments do not define or limit the disclosure. Other changes, modifications, and alterations are also possible. The disclosure is not limited to the described embodiments, but rather, there are many possible variations.

Claims

1. A memory device comprising: a memory array comprising a first string of memory, wherein the first string of memory comprises a first select gate transistor, a second select gate transistor, and a memory cell between the first select gate transistor and the second select gate transistor; and peripheral circuitry coupled to the memory array, wherein the peripheral circuitry is configured to: apply a first voltage to a select line coupled to the first select gate transistor during a first program operation of a first memory cell of the memory cells, wherein the first memory cell is coupled to a first word line that is closest to the first select gate transistor among word lines coupled to the memory cells; and apply a second voltage to the select line coupled to the first select gate transistor during a second program operation of a second memory cell of the memory cells, wherein the second memory cell is coupled to a second word line that is farther from the first select gate transistor than the first word line, and wherein the second voltage is higher than the first voltage.

2. The memory device of claim 1, wherein, the peripheral circuitry is further configured to: apply a third voltage to the select line coupled to the first select gate transistor during a third program operation of a third memory cell of the memory cells, wherein the third memory cell is coupled to a third word line that is closer to the first select gate transistor than the second word line, and wherein the third voltage is higher than or equal to the first voltage and lower than the second voltage.

3. The memory device of claim 2, wherein, the third word line is a second closest word line to the first select gate transistor after the first word line.

4. The memory device of claim 2, wherein, the peripheral circuitry is further configured to: apply the second voltage to the select line coupled to the first select gate transistor during a fourth program operation of a fourth memory cell of the memory cells, wherein the fourth memory cell is coupled to a fourth word line that is different from the first word line and the third word line.

5. The memory device of claim 1, wherein, the peripheral circuitry is further configured to: apply a fourth voltage to the select line coupled to the first select gate transistor during a first time period of the first program operation, wherein the fourth voltage is lower than the first voltage; and apply the first voltage to the select line coupled to the first select gate transistor during a second time period of the first program operation, wherein the second time period is after the first time period.

6. The memory device of claim 5, wherein, the second time period comprises a third time period, a fourth time period after the third time period, and a fifth time period after the fourth time period, and wherein the peripheral circuitry is further configured to: apply a fifth voltage to the first word line during the third time period; apply a program voltage to the first word line during the fourth time period; and apply a sixth voltage to the first word line during the fifth time period, wherein the fifth voltage and the sixth voltage are higher than the first voltage and lower than the program voltage.

7. The memory device of claim 6, wherein, the peripheral circuitry is further configured to: apply a pass voltage to the second word line during the second time period.

8. The memory device of any one of claims 1-7, wherein, The peripheral circuit is configured to program the storage cells coupled to the first word line before programming the storage cells coupled to the second word line.

9. The memory device of any one of claims 1-7, wherein, The peripheral circuit is configured to program the storage cells coupled to the first word line after programming the storage cells coupled to the second word line.

10. The memory device of any one of claims 1-7, wherein, The peripheral circuit is further configured to: apply a seventh voltage to a bit line coupled to a second storage string of the storage array during the first programming operation, wherein the seventh voltage is higher than or equal to a difference between the first voltage and a predetermined threshold voltage of a first select gate transistor in the second storage string.

11. The memory device of any one of claims 1-7, wherein, The storage array includes one or more storage cell tiers, wherein a first tier of the one or more storage cell tiers is adjacent to a second tier of the one or more storage cell tiers, wherein a word line coupled to a storage cell in the first tier closest to the second tier is a dummy word line, and wherein a word line coupled to a storage cell in the second tier closest to the first tier is a dummy word line.

12. A method for operating a storage device, wherein, The method includes: applying a first voltage to a select line coupled to a first select gate transistor during a first programming operation of a first storage cell of the storage cell, wherein the storage device includes a storage array, wherein the storage array includes a storage string including the first select gate transistor, a second select gate transistor, and a storage cell between the first select gate transistor and the second select gate transistor, wherein a first word line coupled to the first storage cell of the storage cell is closest to the first select gate transistor among word lines coupled to the storage cell; and applying a second voltage to the select line coupled to the first select gate transistor during a second programming operation of a second storage cell of the storage cell, wherein the second storage cell is coupled to a second word line farther from the first select gate transistor than the first word line, and wherein the second voltage is higher than the first voltage.

13. The method of claim 12, further comprising: applying a third voltage to the select line coupled to the first select gate transistor during a third programming operation of a third storage cell of the storage cell, wherein the third storage cell is coupled to a third word line closer to the first select gate transistor than the second word line, and wherein the third voltage is higher than or equal to the first voltage and lower than the second voltage.

14. The method of claim 13, wherein, The third word line is a second closest word line to the first select gate transistor after the first word line.

15. The method of claim 13, further comprising: applying the second voltage to the select line coupled to the first select gate transistor during a fourth programming operation of a fourth storage cell of the storage cell, wherein the fourth storage cell is coupled to a fourth word line different from the first word line and the third word line.

16. The method of claim 12, further comprising: applying a fourth voltage to the select line coupled to the first select gate transistor during a first time period of the first program operation, wherein the fourth voltage is lower than the first voltage; and applying the first voltage to the select line coupled to the first select gate transistor during a second time period of the first program operation, wherein the second time period is after the first time period.

17. The method of claim 16, wherein, the second time period includes a third time period, a fourth time period after the third time period, and a fifth time period after the fourth time period, wherein the method further comprises: applying a fifth voltage to the first word line during the third time period; applying a program voltage to the first word line during the fourth time period; and applying a sixth voltage to the first word line during the fifth time period, wherein the fifth voltage and the sixth voltage are higher than the first voltage and lower than the program voltage.

18. The method of claim 17, further comprising: applying a pass voltage to the second word line during the second time period.

19. The method of any one of claims 12-18, further comprising: applying a seventh voltage to a bit line coupled to a second storage string of the storage array during the first program operation, wherein the seventh voltage is higher than or equal to a difference between the first voltage and a predetermined threshold voltage of a first select gate transistor in the second storage string.

20. A storage system, comprising: a storage device, the storage device comprising: an array of storage cells, the array of storage cells comprising storage strings, wherein the storage strings comprise a first select gate transistor, a second select gate transistor, and a storage cell between the first select gate transistor and the second select gate transistor; and peripheral circuitry coupled to the array of storage cells and configured to: apply a first voltage to a select line coupled to the first select gate transistor during a first program operation of a first storage cell of the storage cells, wherein the first storage cell is coupled to a first word line closest to the first select gate transistor among word lines coupled to the storage cells; and apply a second voltage to the select line coupled to the first select gate transistor during a second program operation of a second storage cell of the storage cells, wherein the second storage cell is coupled to a second word line farther from the first select gate transistor than the first word line, and wherein the second voltage is higher than the first voltage; and a controller coupled to the storage device and configured to control the storage device.

21. The storage system of claim 20, wherein, the peripheral circuitry is configured to: apply a third voltage to the select line coupled to the first select gate transistor during a third program operation of a third storage cell of the storage cells, wherein the third storage cell is coupled to a third word line closer to the first select gate transistor than the second word line, and wherein the third voltage is higher than or equal to the first voltage and lower than the second voltage.

22. The storage system of claim 21, wherein, The third word line is a second closest word line to the first select gate transistor after the first word line.

23. The storage system of claim 21 or 22, wherein, The peripheral circuit is configured to: apply the second voltage to the select line coupled to the first select gate transistor during a fourth programming operation of a fourth storage unit of the storage units, wherein the fourth storage unit is coupled to a fourth word line different from the first word line and the third word line.

Images