Semiconductor device and method of manufacturing ets or core particles with dual-sided bridged

Abstract

A semiconductor device has a double-sided bridged die. The bridging die has a first contact pad on a first surface of the bridging die and a second contact pad on a second surface of the bridging die opposite the first surface. The bridging die is disposed over the carrier. A first conductive layer is formed on a carrier. A first insulating layer is formed over the first conductive layer and the bridging die. An opening is formed through the first insulating layer to expose the first conductive layer. A second conductive layer is formed over the first insulating layer. A second conductive layer electrically couples the first conductive layer to a first contact pad of the bridging die. The carrier is removed. The first semiconductor die is electrically coupled to the first conductive layer and the second contact pad bridging the die.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods of fabricating embedded trace substrates (ETSs) or chiplets with double-sided bridge dies. BACKGROUND

[0002] Semiconductor devices are common in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight to electricity and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, entertainment and consumer products. Semiconductor devices are also found in military applications, aerospace, automotive, industrial controls and office equipment.

[0003] Semiconductor device manufacturers continually strive to make smaller semiconductor devices to satisfy the demands of electronic device manufacturers and, in turn, consumers. At the same time, device manufacturers need increasingly complex semiconductor devices. Bridge dies can be embedded within a semiconductor substrate to provide tighter interconnect pitch and higher total bandwidth than can be provided by the substrate itself. However, even bridge dies have limitations, and creating bridge dies with tighter pitch can only get device manufacturers so far. Thus, there is a need for a semiconductor device and a method of fabricating an ETS or chiplet with double-sided bridge dies. BRIEF DESCRIPTION OF DRAWINGS

[0004] Figures la-lc A semiconductor wafer with multiple double-sided bridge dies separated by scribe lanes is shown;

[0005] Figures 2a-2o Forming a chiplet with double-sided bridge dies is shown;

[0006] Figures 3a-3f An alternative embodiment is shown; and

[0007] Figure 4a And 4b An electronic device with a chiplet is shown. DETAILED DESCRIPTION

[0008] In the following description of drawings in reference to the various figures, the application is described in one or more embodiments in which like numbers represent the same or similar elements. Although the application is described in the best mode contemplated, it is to be understood that the application is capable of numerous rearrangements and / or substitutions of parts and elements, as will be appreciated by those skilled in the art. Such embodiments are also contemplated as within the scope of the application as defined by the appended claims and equivalents thereof. Features shown in the drawings are not necessarily to scale. Elements with the same reference numbers in different figures have the same or similar functionality and description. The terms "semiconductor die" and "die" are used synonymously herein and refer to both the singular and plural forms of the word, and thus can refer to both a single semiconductor device and multiple semiconductor devices.

[0009] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming a plurality of semiconductor dies on a surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. The active electrical components such as transistors and diodes have a "current flow" ability. The passive electrical components such as capacitors, inductors, and resistors create a relationship between voltage and current necessary to perform circuit functions.

[0010] Back-end manufacturing refers to the process of cutting or singulating the finished wafer into individual semiconductor dies and packaging the semiconductor dies to form a semiconductor device. To singulate the wafer, the wafer is marked and broken along non-functional areas called streets or scribe lines. The singulation process creates individual semiconductor dies from the finished wafer. Thereafter, the individual semiconductor dies are mounted to a packaging substrate in a package on package (PoP) configuration. The packaging substrate includes pins or contact pads for electrical interconnection with other system components. Electrical connections between the semiconductor dies and the packaging substrate are created by wire bonds. A encapsulant or other molding compound is deposited over the package to provide physical support and electrical isolation.

[0011] Figure laA semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material used for structural support. A plurality of bridge dies 104 are formed on the wafer 100, separated by non-active inter-die wafer area or streets 106. The streets 106 provide a cutting area to singulate the semiconductor wafer 100 into individual bridge dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0012] Figure lb A cross-sectional view of a portion of the semiconductor wafer 100 is shown. Each bridge die 104 has two opposing and substantially identical surfaces 108 and 110, optionally containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die, and electrically interconnected according to the electrical design and function of the die. For example, the circuitry can include one or more transistors, diodes, and other circuit elements formed within the surface 108 or 110 to implement analog circuitry or digital circuitry, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a memory, or other signal processing circuitry. The bridge die 104 can also contain IPD for RF signal processing, such as inductors, capacitors, and resistors.

[0013] In other embodiments, the bridge die 104 does not contain active or passive components other than a conductive layer 112 formed over the surface 108 and a conductive layer 114 formed over the surface 110. The conductive layers 112 and 114 are formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating, sputtering, or other suitable metal deposition process. The conductive layers 112 and 114 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive material. The conductive layers 112 and 114 can be deposited and patterned in the same processing step, or one conductive layer can be formed and patterned before flipping the wafer 100 and forming and patterning the other conductive layer.

[0014] The conductive layer 112 is patterned to include contact pads 112a and conductive traces 112b. The conductive layer 114 includes contact pads 114a and conductive traces 114b. To operate as a bridge die, the bridge die 104 includes contact pads near both opposing edges of the bridge die. Each contact pad 112a or 114a is paired with a contact pad on the opposite edge of the bridge die 104 by a conductive trace 112b or 114b. When the bridge die 104 is incorporated into a semiconductor package (e.g., a die-stacked or system-in-a-package), two other semiconductor dies will be disposed over the opposing edges of the bridge die 104. Each stacked semiconductor die will be connected to one side of the bridge die 104 using the contact pads 112a and 114a, and then the bridge die will interconnect the two stacked semiconductor dies to each other through the conductive traces 112b and 114b. The bridge die 104 is a double-sided bridge die because it has conductive traces 112 and 114 on both opposing surfaces of the bridge die. A passivation or solder resist layer 116 is formed over the surfaces 108 and 110 to protect the conductive layers 112 and 114. Openings are formed through the solder resist layer 116 to expose the contact pads 112a and 114a.

[0015] In Figure lc the semiconductor wafer 100 is singulated into individual bridge dies 104 through the scribe lanes 106 using a saw blade or laser cutting tool 118. The individual bridge dies 104 can be inspected and electrically tested to identify known good dies or units after singulation.

[0016] Figures 2a-2o A process of forming die-stacked or other types of semiconductor packages having bridge dies 104 is shown. Figure 2a A copper clad laminate (CCL) 120 panel is shown. The CCL 120 includes a core 122 formed of a laminate or other type of printed circuit board (PCB) or substrate material having two opposing surfaces completely covered in copper or other conductive layer 124. In other embodiments, any type of temporary carrier or substrate can be used in place of the CCL 120.

[0017] While only the formation of a single unit is shown, the CCL 120 is typically provided large enough to form hundreds of units together before singulation near the end of the process. Each of the following manufacturing steps that occur on both sides of the CCL 120 can be performed simultaneously on both sides, or can be formed on one side at a time with the CCL flipped from one side to the other between each step. In another embodiment, the steps shown are performed on one side of the CCL 120 only, with each step being re-performed on the opposite surface of the CCL after flipping the CCL and repositioning it. There are also embodiments, especially where another type of carrier is used, where the processing once occurred on only a single side of the carrier.

[0018] In Figure 2b , a photoresist layer 130 is formed over the conductive layer 124. An opening 132 is formed through the photoresist layer 130. The opening 132 exposes the conductive layer 124 for deposition of a conductive material to form a contact pad 136 directly on Figure 2c the conductive layer. In Figure 2d , the photoresist layer 130 is removed, leaving the contact pad 136 extending over the conductive layer 124. In some embodiments, the contact pad 136 is part of a conductive layer that also includes conductive traces for fan-in or fan-out. The term "conductive layer" can refer to the contact pad 136 as a group with or without conductive traces.

[0019] Figure 2d A bridge die 104 is shown disposed onto the CCL 120 after the photoresist layer 130 is removed. In Figure 2e , the bridge die 104 is disposed on both opposing surfaces of the CCL 120. A pick-and-place operation is used to dispose the bridge die 104 directly on the conductive layer 124 between the contact pads 136. The bridge die 104 is shown as symmetrical, so either surface of the bridge die can be oriented toward the CCL 120. The surface 108 has been arbitrarily designated as the inside of the bridge die, facing the CCL 120. The bridge die 104 will not necessarily be symmetrical in all embodiments.

[0020] In Figure 2f , an insulating layer 140 is formed to cover each side of the CCL 120 over the bridge die 104. The insulating layer 140 comprises one or more layers of silicon dioxide (Si02), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta205), aluminum oxide (AI2O3), solder resist, polyimide (PI), photosensitive polyimide (PSPI), benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layer 140 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Any of the insulating, passivation, or dielectric layers mentioned above or below can be formed using any of the materials or methods described for the insulating layer 140. In one embodiment, the insulating layer 140 is a sheet of prepreg applied using lamination.

[0021] In Figure 2g1. In the embodiment of the present invention, an opening 142 is formed through insulating layer 140 to expose contact pad 136 for subsequent electrical interconnection. Opening 142 is formed by laser direct ablation (LDA) using laser 144, by mechanical etching, by chemical etching, or by another suitable method. Opening 142 also exposes contact pad 114b of bridge die 104. In other embodiments, insulating layer 140 is formed using film-assisted molding or another method without covering bridge die 104.

[0022] exist Figure 2h , conductive layer 150 is formed over insulating layer 140. Conductive layer 150 is formed using any of the materials and methods described above for conductive layers 112 and 114. Conductive layer 150 fills openings 142 to provide conductive vias for vertical interconnection through insulating layer 140. Conductive layer 150 also includes conductive traces for horizontal interconnection across the surface of insulating layer 140. Specifically, conductive layer 150 includes conductive traces and conductive vias to electrically connect some of contact pads 136 to contact pads 114a of bridge die 104. Other portions of conductive layer 150 provide only vertical interconnection and contact pads for subsequent electrical interconnection, or alternatively provide conductive traces for fan-in or fan-out electrical connections, without connecting to bridge die 104.

[0023] exist Figure 2i , additional insulating layer 154 and conductive layer 156 are formed over insulating layer 140 and conductive layer 150. Insulating layer 154 is formed of similar materials and methods as described above for insulating layer 140. Conductive layer 156 is formed of similar materials and methods as described above for conductive layer 150. Conductive layer 156 is patterned to include conductive vias through insulating layer 154 to physically and electrically contact conductive layer 150 and, if desired, include conductive traces to fan-in or fan-out electrical connections. Although two redistribution layers (RDLs) are shown formed over CCL 120, any number of insulating and conductive layers may be interleaved over the CCL to achieve desired signal routing.

[0024] exist Figure 2j In FIG, a solder resist layer 160 is formed over the insulating layer 154 and the conductive layer 156. The solder resist layer 160 can generally be formed using any of the materials and methods discussed above for the insulating layer. Figure 2k 1 , solder resist layer 160 has openings 162 formed therethrough to expose contact pads of conductive layer 156. Openings 162 may be formed by laser ablation, chemical etching, photolithography, or another suitable method.

[0025] exist Figure 21In the middle, the CCL 120 is deconstructed by separating the conductive layer 124 from the core 122. The conductive layer 124 can be separated from the core 122 by mechanical peeling, thermal release, or another suitable means. Each side (top and bottom) of the CCL 120 becomes an independent embedded trace substrate (ETS) 166. From here on, each side of the CCL 120 as constructed above is treated as its own panel or ETS 166, respectively.

[0026] In the middle, the CCL 120 is deconstructed by separating the conductive layer 124 from the core 122. The conductive layer 124 can be separated from the core 122 by mechanical peeling, thermal release, or another suitable means. Each side (top and bottom) of the CCL 120 becomes an independent embedded trace substrate (ETS) 166. From here on, each side of the CCL 120 as constructed above is treated as its own panel or ETS 166, respectively. Figure 2m In the middle, the ETS 166 is oriented with the conductive layer 124 exposed for removal. Removal of the conductive layer 124 is shown as being accomplished by a grinder 168, but in other embodiments chemical etching, laser ablation, or another suitable method is used. Removal of the conductive layer 124 exposes the contact pads 136 and the contact pads 112a that bridge the core 104.

[0027] Figure 2n In the middle, the ETS 166 is oriented with the conductive layer 124 exposed for removal. Removal of the conductive layer 124 is shown as being accomplished by a grinder 168, but in other embodiments chemical etching, laser ablation, or another suitable method is used. Removal of the conductive layer 124 exposes the contact pads 136 and the contact pads 112a that bridge the core 104. Figure 2n In the middle, the ETS 166 is oriented with the conductive layer 124 exposed for removal. Removal of the conductive layer 124 is shown as being accomplished by a grinder 168, but in other embodiments chemical etching, laser ablation, or another suitable method is used. Removal of the conductive layer 124 exposes the contact pads 136 and the contact pads 112a that bridge the core 104.

[0028] Figure 2o As one basic example of forming a die with the ETS 166, in the middle, a pair of semiconductor dies 170 are mounted to the contact pads 136 and the contact pads 112a of the bridge core 104. The semiconductor dies 170 are formed from semiconductor wafers similar to the wafer 100. The semiconductor dies 170 are used for their active functions implemented using transistors, diodes, and other circuit elements formed in or on the semiconductor dies. Solder bumps 172 are reflowed between the semiconductor dies 170 and the contact pads 136 and 112a to mechanically and electrically connect the semiconductor dies to the contact pads. In some embodiments, underfill is used between the semiconductor dies 170 and the underlying substrate.

[0029] A sealant can also be deposited to cover the semiconductor dies 170, or to co- planarize the top surface with the semiconductor dies. The sealant material can be deposited using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or another suitable applicator. The sealant can be a liquid or particulate polymer composite, such as an epoxy, epoxy acrylate, or polymer, with or without added fillers.

[0030] ​​Each semiconductor die 170 is mounted over one of the two opposite sides of the bridge die 104 on which the contact pads 112a are formed, and the semiconductor dies are connected to each other through the bridge die. The semiconductor dies 170 can each be disposed directly over one side of the bridge die 104, or slightly outside the footprint of the bridge die where short interconnects are still possible. Because the bridge die 104 is double-sided, the semiconductor dies 170 are coupled to each other not only through the conductive layers 112 on the top side of the bridge die (as shown by signal paths 176a), but also through the conductive layers 114 on the bottom side of the bridge die in series with the conductive layers 150 (as shown by signal paths 176b). Having signal paths on both sides of the bridge die 104 allows for a reduction in total pitch compared to a bridge die having conductive traces on only one side, thereby reducing manufacturing complexity and cost. The double-sided feature of the bridge die 104 can be used to double the total number of conductive signal paths at the same pitch as prior art, to relax the line pitch while maintaining the same number of conductive signal paths, or to provide both benefits to a lesser extent.

[0031] A conductive bump material is deposited over the conductive layer 156 in the opening 162 using an evaporation, electrochemical plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is joined to the conductive layer 156 using a suitable attachment or joining process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 178. In one embodiment, the bumps 178 are formed over under bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesion layer.

[0032] The bumps 178 can also be compression bonded or thermocompression bonded to the conductive layer 156. The bumps 178 represent one type of interconnect structure that can be formed over the conductive layer 156. The interconnect structure can also use a wire bond, a conductive paste, a columnar bump, a micro bump, or other electrical interconnect. In some embodiments, the bumps 178 are formed by the ETS 166 manufacturer before the semiconductor package or dielet begins to be formed using the ETS. The bumps 172 on the semiconductor dies 170 can be formed in the same manner and using the same materials as the bumps 178.

[0033] Figure 2o A completed dielet 180 is shown ready for integration into a larger device or semiconductor package. In most embodiments, a large ETS 166 is used to form multiple dielets 180 together. In the completed dielet 180, the semiconductor dies 170 are connected to each other through the bridge die 104, and the bridge die is connected to the ETS 166 through the conductive layers 112 and 114. The dielet 180 is ready for integration into a larger device or semiconductor package. Figure 2oThe ETS 166 is singulated from the CCL 120 by cutting through the ETS and any encapsulant or underfill (if used) to separate the ETS and the package from each other, resulting in Figure 2o a plurality of structures shown in FIG. 1 separated from each other.

[0034] Figures 3a-3f An alternative process flow is shown. In Figure 3a the conductive layer 124 is removed at the location where the bridge die 104 will be disposed. Removing the conductive layer 124 under the bridge die 104 leaves an opening 182, allowing the bridge die to be disposed lower, and thereby reducing the overall thickness of the ETS and the die being formed.

[0035] In Figure 3b the adhesive 184 is disposed or dispensed directly onto the die 122. In one embodiment, the adhesive 184 is applied as a thin film. In other embodiments, the adhesive 184 is dispensed as a liquid, gel, or other semi-liquid. In practice, the adhesive 184 ends up thinner than the conductive layer 124, even though the two layers are not drawn at significantly different thicknesses. In other embodiments, the adhesive 184 can completely fill the footprint of the opening 182, or a gap can be left between the adhesive 184 and the conductive layer 124.

[0036] In Figure 3c the bridge die 104 is disposed on the adhesive 184. In some embodiments, the adhesive 184 has a smaller footprint than the bridge die 104. The adhesive 184 attaches the bridge die 104 to the core 122. As disclosed above, the insulating layer 140, the conductive layer 150, the insulating layer 154, the conductive layer 156, and the solder mask layer 160 are formed over the bridge die 104.

[0037] Figure 3d Jumping ahead to the step of just removing the die 122, exposing the adhesive 184 and the remaining portion of the conductive layer 124. In Figure 3e the adhesive 184 is removed by thermal release, UV release, mechanical peeling, or another suitable process. In other embodiments, the adhesive 184 is removed along with the die 122. In Figure 3f the conductive layer 124 is removed using a mill or other device as shown above to complete the ETS 190. The ETS 190 uses a double-sided bridge die 104 with parallel conductive paths on its top and bottom surfaces, as shown above, and has all of its benefits. Furthermore, removing a portion of the conductive layer 124 before disposing the bridge die 104 onto the CCL 120 results in the ETS 190 being thinner than the ETS 166. As with the ETS 166, the ETS 190 can be used to form any type of die or semiconductor package.

[0038] Figure 4a and 4b Integration of the semiconductor package (e.g., the die 180) described above into a larger electronic device 300 is shown. Figure 4a A partial cross-section of the die 180 mounted to a printed circuit board (PCB) or other substrate 302 that is part of the electronic device 300 is shown. The solder bumps 178 are reflowed onto a conductive layer 304 of the PCB 302 to physically attach and electrically connect the die to the PCB. In other embodiments, a thermal compression or another suitable attachment and connection method is used. In some embodiments, an adhesive or underfill layer is used between the die 180 and the PCB 302. The semiconductor die 170 is electrically coupled to the conductive layer 304 by the ETS 166. The ETS 166 also includes a double-sided bridge die 104 that electrically couples the two semiconductor dies 170 to each other.

[0039] Figure 4b An electronic device 300 with a chip carrier substrate or PCB 302 is shown, with multiple semiconductor packages disposed on a surface of the PCB 302, including the die 180. Depending on the application, the electronic device 300 can have one type of semiconductor package or multiple types of semiconductor packages. In other embodiments, the die 180 is incorporated as only a part of another larger semiconductor package (e.g., a system-in-a-package) before being incorporated into the larger electronic device 300.

[0040] The electronic device 300 can be a stand-alone system that uses the semiconductor package to perform one or more electrical functions. Alternatively, the electronic device 300 can be a subcomponent of a larger system. For example, the electronic device 300 can be part of a tablet computer, a cellular telephone, a digital camera, a communication system, or other electronic device. Alternatively, the electronic device 300 can be a graphics card, a network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for products to be marketable. Distances between semiconductor devices can be reduced to achieve higher densities. The PCB 302 can have a more irregular shape to conveniently fit into a more ergonomic and smaller device housing.

[0041] In Figure 4bIn particular, the PCB 302 provides a general substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 304 are formed on or within the surface of the PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces 304 provide electrical communication between each semiconductor package, mounted components, and other external system components. The traces 304 also provide power and ground connections to each semiconductor package.

[0042] In some embodiments, the semiconductor device has two levels of packaging. The first level of packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device can have only a first level of packaging, in which the die is mechanically and electrically disposed directly on the PCB.

[0043] For illustrative purposes, several types of first level packaging are shown on the PCB 302, including wire bond packages 346 and flip chip 348. In addition, several types of second level packaging are shown disposed on the PCB 302, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, land grid array (LGA) 356, multi-chip module (MCM) or SIP module 358, quad flat no-lead package (QFN) 360, quad flat package 362, and embedded wafer level ball grid array (eWLB) 364. In one embodiment, the eWLB 364 is a fan-out wafer level package (Fo-WLP) or a fan-in wafer level package (Fi-WLP).

[0044] Depending on system requirements, any combination of semiconductor packages configured with first and second level packaging styles, and any combination of other electrical components can be connected to the PCB 302. In some embodiments, the electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because the semiconductor packages include complex functionality, less expensive components and streamlined manufacturing processes can be used to manufacture the electronic device. The resulting device is less likely to fail and is less expensive to manufacture, resulting in lower costs to the consumer.

[0045] While one or more embodiments of the application have been illustrated and described, as noted above, one skilled in the art will readily devise numerous other variations of these embodiments that, without departing from the scope of the application as set forth in the appended claims.

Claims

1. A method of manufacturing a semiconductor device, comprising: providing a double-sided bridge die including a first contact pad on a first surface of the bridge die and a second contact pad on a second surface of the bridge die opposite the first surface; disposing the bridge die over a carrier; forming a first conductive layer on the carrier; forming a first insulating layer over the first conductive layer and the bridge die; forming an opening through the first insulating layer to expose the first conductive layer; forming a second conductive layer over the first insulating layer, wherein the second conductive layer electrically couples the first conductive layer to the first contact pad of the bridge die; removing the carrier; and mounting a first semiconductor die electrically coupled to the first conductive layer and the second contact pad of the bridge die.

2. The method of claim 1, further comprising forming a second insulating layer over the first insulating layer and the second conductive layer.

3. The method of claim 2, further comprising forming a third conductive layer over the second insulating layer, wherein the third conductive layer includes a conductive via extending through the second insulating layer to contact the second conductive layer.

4. The method of claim 1, wherein the carrier is a copper clad laminate (CCL).

5. The method of claim 4, wherein removing the carrier includes: separating a core of the CCL from a copper layer of the CCL; and removing the copper layer from the first insulating layer, the first conductive layer, and the bridge die after separating the core from the copper layer.

6. The method of claim 1, further comprising mounting a second semiconductor die electrically coupled to the first semiconductor die through the first contact pad and the second contact pad in parallel.

7. A method of manufacturing a semiconductor device, comprising: providing a double-sided bridge die including a first contact pad on a first surface of the bridge die and a second contact pad on a second surface of the bridge die; disposing the bridge die over a carrier; forming a first conductive layer over the carrier; forming a second conductive layer, wherein the second conductive layer electrically couples the conductive layer to the first contact pad of the bridge die; and removing the carrier to expose the first conductive layer and the second contact pad of the bridge die.

8. The method of claim 7, wherein the carrier is a copper clad laminate (CCL).

9. The method of claim 8, wherein removing the carrier includes: separating a core of the CCL from a copper layer of the CCL; and removing the copper layer from the first conductive layer and the bridge die after separating the core from the copper layer.

10. The method of claim 7, further comprising forming the bridge die to include: a third contact pad on the first surface of the bridge die; a first conductive trace extending from the first contact pad to the third contact pad on the first surface of the bridge die; a fourth contact pad on the second surface of the bridge die; and a second conductive trace extending from the second contact pad to the fourth contact pad on the second surface of the bridge die.

11. A semiconductor device, comprising: a double-sided bridge die including a first contact pad on a first surface of the bridge die and a second contact pad on a second surface of the bridge die; a first conductive layer formed adjacent the bridge die; and a second conductive layer formed over the first conductive layer, wherein the second conductive layer electrically couples the first conductive layer to the first contact pad of the bridge die. ​ ​ ​ ​ a second conductive layer electrically coupling the first contact pad to the first conductive layer; and a semiconductor die disposed above the bridge die and electrically coupled to the first contact pad through the first conductive layer and the second conductive layer.

12. The semiconductor device of claim 11, further comprising an insulating layer formed above the bridge die and the first conductive layer and below the second conductive layer.

13. The semiconductor device of claim 11, wherein, The bridge die comprises: a third contact pad on a first surface of the bridge die; a first conductive trace extending from the first contact pad to the third contact pad on the first surface of the bridge die; a fourth contact pad on a second surface of the bridge die; and a second conductive trace extending from the second contact pad to the fourth contact pad on the second surface of the bridge die.

14. The semiconductor device of claim 13, wherein, The second conductive layer electrically couples the third contact pad to the first conductive layer.

15. The semiconductor device of claim 14, further comprising: a first semiconductor die; and a second semiconductor die, wherein the second semiconductor die is coupled to the first semiconductor die through the parallel first conductive trace and the second conductive trace.

Images