Multi-chip flip chip ball grid array packaging method and packaging structure

Abstract

The invention provides a multi-chip flip chip ball grid array packaging method and a packaging structure, which are used for solving the technical problems that the coplanarity of multiple chips is poor and the edges of the chips are easy to damage in the packaging of a large-size multi-chip module (MCM) flip chip ball grid array (FCBGA). According to the invention, the plurality of chips on the substrate in the MCM structure are additionally provided with the reinforcing structures formed by curing the colloid or the plastic packaging material, and the reinforcing structures fill the gaps among the chips and wrap the edges of the chips. The surface of the chip and the surface of the reinforcing structure are ground by using a grinding process to form a flat surface, and the surfaces of all the chips are exposed to facilitate heat dissipation through the radiator. According to the invention, the coplanarity of the surface of the multi-chip structure can be effectively improved, the edges of the chips can be effectively protected, and the warping of the packaging structure can be well controlled.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging manufacturing, and in particular to a multi-chip flip chip ball grid array packaging method and packaging structure. BACKGROUND

[0002] In the field of semiconductor manufacturing, as Moore's Law approaches the physical limit, advanced wafer process nodes face the dual challenges of exponential growth in process complexity and dramatic increase in single-chip manufacturing costs. The huge cost pressure has driven the explosive development of Chiplet technology. Chiplet integrates different functional chips (such as computing cores, memory units, and IO modules) into a whole through heterogeneous integration, which can significantly reduce manufacturing costs while achieving equivalent computing power, and has become a core path to break through the physical and economic bottlenecks of advanced processes.

[0003] Multi-Chip Module (MCM) architecture, as one of the typical carriers of Chiplet technology, can realize high-density interconnection of multiple chips through large-size packaging substrates. Such substrates usually use ABF (a kind of build-up film) and other materials. When the size of the substrate is expanded to 50mm x 50mm or more, the application of MCM multi-chip integration will present a large chip area / packaging area ratio, which will lead to the risk of warping and stress caused by the mismatch of the coefficient of thermal expansion (CTE) between materials. SUMMARY

[0004] Embodiments of the present application provide a multi-chip flip chip ball grid array packaging method and packaging structure, which are used to solve the technical problems of poor coplanarity of multiple chips and easy damage of chip edges in large-size multi-chip module MCM flip chip ball grid array FCBGA packaging.

[0005] Based on an aspect of the embodiments of the present disclosure, the present disclosure provides a multi-chip flip chip ball grid array packaging method, which packages multiple chips on the same substrate based on flip chip ball grid array packaging FCBGA technology, comprising: According to the layout of the multiple chips on the substrate, fill the gap between the chips with a colloid and wrap the edges of the chips, and solidify the multiple chips periphery to form a reinforcing structure; Use a grinding process to form a flat surface on the surface of the multiple chips and the reinforcing structure and expose the surface of the multiple chips.

[0006] Further, the method further comprises adding a stiffener ring on the substrate.

[0007] Further, the method for filling the gap between the chips with the glue and wrapping the chip edges, and curing the glue around the periphery of the chips to form a reinforcing structure comprises: After the multi-chip is mounted using the surface mount SMT technology and the flip chip assembly FCA technology, the bottom of the chip is first filled with the underfill glue (UF glue) and then cured; The cofferdam structure is made using the cofferdam glue (DAM glue) around the periphery of the chip, and the cofferdam is filled with the fill glue (Fill glue) and then cured to form a reinforcing structure; The curing steps of the underfill glue, the cofferdam glue, and the fill glue are performed separately or together.

[0008] Further, the method for filling the gap between the chips with the glue and wrapping the chip edges, and curing the glue around the periphery of the chips to form a reinforcing structure comprises: After the multi-chip is mounted using the surface mount SMT technology and the flip chip assembly FCA technology, the bottom of the chip is first filled with the underfill glue (UF1 glue), and then the cofferdam structure is made using the cofferdam glue (DAM glue) and then cured; The cofferdam structure is filled with the second underfill glue (UF2) and then cured to form a reinforcing structure; The curing steps of the first underfill glue, the cofferdam glue, and the second underfill glue are performed separately or together.

[0009] Further, the method for filling the gap between the chips with the glue and wrapping the chip edges, and curing the glue around the periphery of the chips to form a reinforcing structure comprises: After the multi-chip is mounted using the surface mount SMT technology and the flip chip assembly FCA technology, the cofferdam structure is added using the cofferdam glue, and the cofferdam structure is cured; The bottom of the chip and the cofferdam are filled with the underfill glue, the underfill glue fills the gap between the chips and wraps the chip edges, and then cured to form a reinforcing structure; The curing steps of the cofferdam glue and the underfill glue are performed separately or together.

[0010] Further, the method for filling the gap between the chips with the glue and wrapping the chip edges, and curing the glue around the periphery of the chips to form a reinforcing structure comprises: After the multi-chip is mounted using the surface mount SMT technology and the flip chip assembly FCA technology, the bottom of the chip is filled with the underfill glue and then cured; The multi-chip is encapsulated on the packaging substrate using the encapsulation material, the encapsulation material wraps the chip, and the encapsulation material is cured to form a reinforcing structure.

[0011] Further, the method of filling the gap between the chips with the glue and wrapping the chip edges, and then curing the glue around the periphery of the chips to form the reinforcing structure comprises: After the multi-chip flip-chip assembly is completed using the surface mount technology (SMT) and the flip-chip assembly technology (FCA), the multi-chip is encapsulated using an encapsulation material on the packaging substrate, the encapsulation material fills the bottom of the chip and wraps the chip, and after curing, a reinforcing structure is formed.

[0012] Further, the method first encapsulates the multi-chip on a first substrate using a fan-out packaging technology and performs wafer-level cutting of the fan-out packaging particles, and then encapsulates the fan-out packaging particles on a second substrate using the FCBGA technology. The process of encapsulating the multi-chip on the first substrate using the fan-out packaging technology and performing wafer-level cutting of the fan-out packaging particles comprises: A redistribution layer (RDL) is made on the first substrate, the multi-chip is mounted on the first substrate using the flip-chip assembly technology (FCA), and the bottom of the chip is filled with the underfill glue. The multi-chip on the first substrate is encapsulated using a wafer-level encapsulation process, the gap between the chips is filled with the encapsulation material during the encapsulation process, the chip edges are wrapped with the encapsulation material, and a reinforcing structure is formed by curing around the periphery of the multi-chip. A wafer-level back-grinding process is used to thin the back of the chip, so that the surface of the multi-chip and the surface of the reinforcing structure form a flat surface, and then a controllable chip connection (C4) ball planting is performed. The wafer-level cutting of the fan-out packaging particles is performed.

[0013] Further, the edge structure of the reinforcing structure is designed as a side bevel structure, a side bevel structure, or a side right angle structure, the layout of the reinforcing structure is adapted to different surface chip position layouts on the substrate, and the intersection angle of two edges of the reinforcing structure is a right angle or a round angle.

[0014] Based on another aspect of the embodiments of the present disclosure, the present disclosure further provides a multi-chip flip-chip ball grid array packaging structure, which comprises a substrate, a plurality of chips encapsulated on the substrate, and a reinforcing structure. The plurality of chips are encapsulated on the same substrate using the flip-chip ball grid array packaging technology (FCBGA). The reinforcing structure is a reinforcing structure formed after the glue or the encapsulation material is cured, the glue or the encapsulation material of the reinforcing structure fills the gap between the chips and wraps the chip edges. The surface of the plurality of chips and the surface of the reinforcing structure are a flat surface formed after polishing using a polishing process, and the surface of the plurality of chips is exposed.

[0015] The technical scheme provided by the embodiment of the present specification can include the following beneficial effects: The present disclosure adds a reinforcing structure formed by curing and molding of a colloid or plastic sealing material to multiple chips on a substrate in an MCM structure, the reinforcing structure fills the gaps between the chips and wraps the chip edges, a flat surface is formed by polishing the chip surface and the reinforcing structure surface using a polishing process, and the surfaces of all the chips are exposed to facilitate heat dissipation through a heat sink. The present application can effectively improve the coplanarity of the surface of the multi-chip structure, effectively protect the chip edges, and has a good control effect on the warping of the packaging structure.

[0016] The present application is suitable for chip packaging and manufacturing in high-performance computing, data centers and other fields with high requirements for high-power chip heat dissipation and reliability in large-size MCM structure FCBGA packaging scenarios.

[0017] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 Packaging schematic diagram of Cavity / Hat structure with closed cavity; Figure 2 Packaging schematic diagram of Stiffener Ring reinforcing ring structure; Figure 3 System-level heat sink assembly schematic diagram under the conditions of good and poor coplanarity of multiple chips; Figure 4 Example diagram for improving the height difference of chip coplanarity caused by package warping by increasing the pressing force of the system-level heat sink fixture during installation; Figure 5 Method flow schematic diagram for packaging multiple chips based on MCM-FCBGA technology provided by an embodiment of the present disclosure; Figure 6 Packaging process and packaging side cross-sectional example diagram for forming a reinforcing structure for multiple chips on a substrate using a first kind of dike filling scheme in an embodiment of the present disclosure; Figure 7 Packaging process and packaging side cross-sectional example diagram for forming a reinforcing structure for multiple chips on a substrate using a second kind of dike filling scheme in an embodiment of the present disclosure; Figure 8 Packaging process and packaging side cross-sectional example diagram for forming a reinforcing structure for multiple chips on a substrate using a third kind of dike filling scheme in an embodiment of the present disclosure; Figure 9Fig. 1 is a cross-sectional view of a packaging process and a packaging side surface of a package for forming a reinforcing structure for a plurality of chips on a substrate according to a first plastic packaging scheme according to an embodiment of the present disclosure; Figure 10 Fig. 2 is a cross-sectional view of a packaging process and a packaging side surface of a package for forming a reinforcing structure for a plurality of chips on a substrate according to a second plastic packaging scheme according to an embodiment of the present disclosure; Figure 11 Fig. 3 is a cross-sectional view of a packaging process and a packaging side surface of a package for forming a reinforcing structure for a plurality of chips on a substrate according to a third plastic packaging scheme according to an embodiment of the present disclosure; Figure 12 Fig. 4 is a schematic view of an edge structure design of a reinforcing structure according to an embodiment of the present disclosure; Figure 13 Fig. 5 is a top view of a schematic view of a plurality of reinforcing structure layout designs according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The following will describe exemplary embodiments in detail, and when the following description refers to the accompanying drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure, but are exemplary embodiments of devices and methods consistent with some aspects of the present disclosure.

[0020] The terms used in the present disclosure are merely for the purpose of describing particular embodiments and are not intended to limit the present disclosure. As used in the present disclosure, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0021] It should be understood that the terms "first", "second", "third", etc. can be used in the present disclosure to describe various information or structural modules, and the purpose is to make the scheme more clearly described, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number, order or position of the indicated technical features. Therefore, the features defined as "first", "second", "third", etc. can be explicitly or implicitly included one or more features. In the description of the present disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more; "if" can be interpreted as "when" or "when" or "in response to determining".

[0022] In the present disclosure, "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents that the associated objects before and after are in an "or" relationship.

[0023] When using MCM-FCBGA technology for multi-chip packaging, the warpage of the package will affect the coplanarity (the degree of being in the same plane) of the BGA solder interface at the bottom of the package, which will bring greater challenges to the subsequent soldering and assembly of the package on the PCB board level Surface Mount Technology (SMT). Industry standards such as JEDEC SPP-024A and JEITA ED-7306 have strict requirements for the warpage of the package and the coplanarity of the BGA interface. However, there is no standard to explicitly require the coplanarity of the chip side in MCM multi-chip die packaging. The warpage of the package will also cause coplanarity problems on the surface of the multi-chip structure, affecting the interface thermal resistance between the heat sink and the multi-chip.

[0024] To cope with the increasingly serious warpage and coplanarity problems of general large-size multi-chip MCM-FCBGA packaging, technicians in the field usually use closed cavity structures and reinforcement ring structures, but both have their own defects.

[0025] Figure 1 A schematic diagram of a package using a Cavity / Hat structure. The Cavity / Hat reinforcement structure adds a metal cover plate on the top layer of the chip to form a cavity structure. This type of metal reinforcement structure usually has a size similar to that of the package substrate, and relies on the high modulus of the metal material to control the warpage of the package. The warpage can generally be controlled and adjusted by increasing the thickness of the structure, increasing the width of the metal structure and substrate bonding interface, or replacing the metal or adhesive material. The upper surface of this type of structure can provide a flat surface for the assembly of a system-level heat sink, but its main problem is that there is a high thermal resistance between the chip surface and the metal cover interface. Even if a thermal interface material has been placed between the chip surface and the metal cover, it is still difficult to meet the growing heat dissipation needs of high-power chips. In recent years, packaging factories have been developing indium sheets as TIM1 materials, but they are mainly used in single-chip FCBGA packaging, and the holes and indium running problems related to the indium sheet process still pose a risk to product heat dissipation and reliability. The application of indium sheets in multi-chip MCM packaging will be even more difficult to control.

[0026] Figure 2An example of a package using a Stiffener Ring structure. The Stiffener Ring structure is usually of similar size to the package substrate, and is arranged in a strip around the package. The structure can also expose the chip surface, which is conducive to heat dissipation of the chip. Warpage can be controlled by increasing the thickness of the structure, increasing the width of the adhesive interface between the metal structure and the substrate, or changing the material of the metal and the adhesive. The main problem with this structure is that the Stiffener Ring structure is only arranged on the outside of the package, and its control of the warpage of the entire package is usually weaker than that of a Cavity / Hat structure of the same size, especially for the warpage and coplanarity control of the MCM multi-chip area. Poor multi-chip coplanarity will affect the assembly of the system heat sink and the control of the interface thermal resistance. To address this defect, one solution is to Figure 3 An example, Figure 3 (A) in the above is a schematic diagram of the assembly of a system-level heat sink / fan when the multi-chip coplanarity is good, Figure 3 (B) in the above is a schematic diagram of compensating for the difference in multi-chip coplanarity by the thickness of the TIM (thermal interface material) when the system-level heat sink is installed, but this method will cause differences in the thermal resistance of different chip heat dissipation paths.

[0027] Figure 4 An example of improving the height difference of the chip coplanarity caused by the warpage of the package by increasing the pressing force when the system-level heat sink / fan fastener is installed. Figure 4 (A) in the above is a schematic diagram of improving the warpage of the package by increasing the pressing force of the fastener of the system-level heat sink when the multi-chip coplanarity is good, Figure 4 (B) in the above is a schematic diagram of possibly causing damage to the corners or edges of some chips due to excessive force when the system-level heat sink is installed by increasing the static pressing force of the fastener, thereby causing chip failure.

[0028] Based on the above analysis and research, when using the flip-chip ball grid array packaging (FCBGA) technology on a large-size package substrate in a multi-chip module (MCM) architecture (i.e., MCM-FCBGA), to solve the technical problems of multi-chip coplanarity and chip edge damage, an improved technical solution for multi-chip flip-chip ball grid array packaging is proposed, which is described in detail below in conjunction with specific embodiments.

[0029] Figure 5 A method flowchart for packaging multi-chips based on the MCM-FCBGA technology according to an embodiment of the present disclosure is provided. The method is based on the MCM-FCBGA packaging structure, and exposes the chip surface. The method is different from the conventional multi-chip FCBGA packaging method, and the main difference includes: B01, filling the gap between the chips with a glue and wrapping the edges of the chips, and curing the glue to form a reinforcement structure around the periphery of the chips; In this step, the purpose of wrapping the edges of the chips with glue is to form a reinforcement structure to protect the edges of the chips, and the reinforcement structure also has the function of controlling warping, and in addition, it can avoid damage to the edges or corners of the chips when the heat sink is installed, which can cause the edges or corners of the chips to be damaged and broken, thereby damaging the chips.

[0030] In this step, the gap between the plurality of chips on the substrate is filled with glue, and the plurality of chips mounted on the substrate using the FCBGA process are bonded together by the adhesive effect of the glue and cured to form a whole (including the chips and the reinforcement structure). The purpose of this is to use the high modulus of the glue to provide overall protection for the plurality of chips, and in addition, it has the effect of suppressing the warping deformation of the chips and the substrate due to the mismatch of the coefficient of thermal expansion (CTE).

[0031] This step summarizes various implementation schemes, including but not limited to the coffered DAM filling scheme and the plastic encapsulation Molding scheme, and each scheme has a plurality of sub-schemes, such as the Underfill&DAM&Fill sub-scheme, the Underfill1&DAM&Underfill2 sub-scheme, etc. Each sub-scheme has differences in process and flow, but the purpose is the same.

[0032] B02, using a grinding process to form a flat surface on the surface of the plurality of chips and the reinforcement structure and expose the surface of the plurality of chips.

[0033] If the coplanarity deviation between the surfaces of the plurality of chips is too large, the contact between some of the chips and the heat sink will be poor, the thermal resistance will increase significantly, and the temperature of the chips may be too high due to poor heat dissipation, which may exceed the safety temperature threshold of the chips, thereby causing solder fatigue and shortening the service life. In order to improve the coplanarity (the degree of being on the same level) of the surfaces of the plurality of chips (the back surface of the chip that does not contact the substrate) packaged together, a grinding process is used in this step to mechanically grind the overall surface formed by the plurality of chips and the reinforcement structure, so as to form a flat surface on the overall surface. By improving the coplanarity of the chips, the thermal resistance difference between different chips and the heat dissipation system can be reduced, the heat dissipation efficiency can be improved, and the service life of the chips can be prolonged.

[0034] In an embodiment of the present disclosure, in order to control the warping degree of the entire package, a reinforcing ring is also added along the periphery of the packaging substrate, and the reinforcing ring can be arranged in a strip shape. Adding a reinforcing ring structure to the substrate while exposing the surface of the chip is beneficial to the heat dissipation of the chip.

[0035] In an embodiment of the present disclosure, a system-level heat sink is added to the plurality of chips, and the system-level heat sink is in contact with the surfaces of the plurality of chips on the substrate at the same time, which can reduce the cost and improve the overall heat dissipation efficiency. The surfaces of the plurality of chips in contact with the heat sink can be coated with a thermal interface material to increase the heat conduction efficiency.

[0036] The following describes in detail a plurality of methods for bonding and curing the plurality of chips on the substrate into one body by using a colloid through a plurality of embodiments.

[0037] Figure 6 The following describes in detail a plurality of methods for bonding and curing the plurality of chips on the substrate into one body by using a colloid through a plurality of embodiments. Figure 6 The example scheme is referred to as the Underfill & DAM & Fill scheme. It should be noted that the packaging process in the subsequent embodiments, including this embodiment, includes a plurality of processes, and the order of a plurality of processes for achieving the purpose of the present application can be different. The present disclosure will focus on the steps directly related to the present application. Any simple adjustment of the steps, simple change of the structure shape (for example, change of the shape of the dam and the shape of the colloid), and equivalent replacement of the technical features (for example, use of different colloid with similar properties) made by the person skilled in the art under the guidance of the present disclosure should be attributed to the protection scope of the present application.

[0038] S601, chip processing and sawing DPS; The chip processing and sawing (DPS) step is mainly used for processing and cutting the chips after the chip manufacturing is completed. The processing steps can include a thinning processing step. Thinning processing is to reduce the thickness of the original wafer by grinding, which can improve the heat dissipation performance of the chip, reduce the packaging volume, and enhance the mechanical properties of the chip. Cutting refers to cutting the thinned wafer into a single chip for subsequent packaging.

[0039] As an example of (A) in the above Figure 6 In the example of (A) in the above

[0040] S602, using surface mounting SMT technology and flip chip assembly FCA technology to mount the plurality of chips.

[0041] This step uses Surface Mount Technology (SMT) and Flip Chip Assembly (FCA) technology to mount multiple chips on the substrate. Mounting is the accurate mounting of a single or multiple chips on a packaging substrate or other carrier, preparing for subsequent electrical connection and packaging. Multi-chip on-chip refers to the integration of multiple chips in the same package to improve system performance and reduce size.

[0042] S603, fill the bottom of the chip with underfill UF glue and cure; The underfill process is mainly used in flip chip packaging. In flip chip, the chip is connected to the substrate through solder balls, and there is a certain gap between the chip and the substrate. The underfill process is to inject underfill glue into the gap to fill the space between the chip and the substrate.

[0043] The curing process is the process of changing the gel material from a flowable state to a solid state. In the field of electronic packaging, many materials such as underfill glue, potting glue, etc. need to be cured to play their final performance. The curing method is various, the common ones are heating curing, through raising the temperature to make the curing agent in the material initiate chemical reaction, promote the material crosslinking curing; there is also ultraviolet curing, using ultraviolet irradiation of materials containing photosensitizer, initiating photochemical reaction to achieve curing.

[0044] S604, use dam glue to make dam structure around the chip; This step uses the dam and fill process to form a dam structure around the designated protection area (the area where multiple chips are located) on the substrate using DAM glue, which encloses the area to be protected, providing boundary constraints for subsequent filling with fill glue (Fill glue) or underfill glue (Underfill), preventing the filling material from overflowing, such as Figure 6 (A) in the example. When the DAM glue is combined with the Fill / Underfill glue, its rigid boundary can limit the flow range of the filling material, and can avoid additional warping caused by uneven filling.

[0045] The dam structure can use epoxy resin + high-hardness filler (such as silica), and the elastic modulus after curing can reach 5-10 GPa, and the coefficient of thermal expansion (CTE) can be controlled at 10-15 ppm / ℃, close to the packaging substrate (such as ABF material), which can reduce the interface stress. The dam structure uses the characteristics of high modulus material to suppress the warping deformation of the chip and the substrate caused by the mismatch of the coefficient of thermal expansion (CTE), especially effective for the problem of upwarping in the middle of the chip and sagging at the edge in large-size MCM packaging.

[0046] S605, filling the gap between the chips inside the cofferdam with fill adhesive and wrapping the chip edges, and then curing to form a reinforced structure; This step fills the gap between the chips inside the DAM cofferdam with Fill adhesive and wraps the chip edges, and then cures to form a reinforced structure with the cofferdam adhesive and the fill adhesive, which protects the chips. The shrinkage stress of the Fill adhesive during curing can be constrained by the DAM cofferdam, and its high modulus can "flatten" the warping of the chips, especially the middle part of the package.

[0047] Fill process is usually used in some cases where specific areas need to be sealed, protected or enhanced in structure. Fill adhesive can use epoxy resin as matrix and add high filling amount (volume ratio 60%-80%) of inorganic filler, which has low shrinkage rate (≤0.1%) and high flatness after curing. Liquid fillers with good flowability can be used to fill complex gaps.

[0048] Preferably, high thermal conductivity fillers (such as alumina, boron nitride) can be added to the Fill adhesive. After adding high thermal conductivity fillers, the thermal conductivity of the adhesive can reach 2-5 W / (m・K), which can assist in lateral heat dissipation of the chip and reduce thermal resistance.

[0049] Preferably, the curing of the cofferdam adhesive in step S604 and the curing of the fill adhesive in step S605 can be combined. The specific process is as follows: after the cofferdam structure is made with DAM adhesive, the Fill adhesive needs to be filled into the dam body of the cofferdam structure when the DAM adhesive is not completely cured (still slightly sticky), the flow range of the Fill filling adhesive is limited by the surface tension of the DAM adhesive, and after the Fill adhesive is filled, the reinforced structure formed by the DAM adhesive and the Fill adhesive is cured as a whole.

[0050] If the DAM adhesive and the fill adhesive are cured separately (first cure DAM adhesive and then cure Fill adhesive), the surface of the DAM adhesive will lose adhesion, which may cause delamination at the interface between the Fill adhesive and the DAM adhesive. In addition, it will also increase the number of heating / cooling cycles and prolong the production cycle, and multiple thermal stresses may cause increased warping of the substrate.

[0051] To achieve co-curing, compatible adhesive materials should be selected when selecting DAM adhesive and Fill adhesive, which will bring better results. For example, both adhesives choose epoxy-based fluid as the core, only the filler content (DAM adhesive is higher to ensure structural support; Fill adhesive is lower to ensure flowability) and viscosity are different, and there is no chemical reaction conflict, and the cross-linked adhesive can be completed in the same curing cycle.

[0052] For example, Figure 6Example of (B) in FIG. 2. As can be seen from the figure, there is a height difference between the surfaces of chip A and chip B. When filling the dam with glue, the glue level should at least reach or be higher than the surface of the lowest chip among the multiple chips.

[0053] S606, using a grinding process to make the surfaces of the multiple chips and the surface of the reinforcing structure into a flat surface; As Figure 6 Example of (C) in FIG. 3. This step is to grind the surface of the reinforcing structure formed by the multiple chips and the glue into a flat surface using a grinding process, so that the surface of each chip is completely exposed, thereby enhancing the heat dissipation efficiency of the chips. The height of the grinding can be adjusted according to design requirements to optimize the heat sink assembly and reduce the thermal resistance.

[0054] S607, adding a reinforcing ring structure and curing.

[0055] As Figure 6 Example of (D) in FIG. 4. In order to control the warpage of the entire package, a reinforcing ring (Stiffener Ring) structure can be added along the edges of the package substrate. The reinforcing ring can be arranged in a strip shape.

[0056] The scheme of this embodiment is to add a dam structure and fill it with glue to form a physical reinforcing structure that wraps around the chips after curing, thereby achieving the purpose of protecting the chips and controlling warpage. The reinforcing structure can surround the MCM multi-chip area inside the package. The width, thickness and position of the reinforcing structure can be flexibly adjusted according to the arrangement position of the multiple chips on the surface of the package substrate. The edge (outer edge of the dam) of the reinforcing structure can be vertical as shown in Figure 12 or have a certain inclination. The upper surface of the entire reinforcing structure (including the back of the multiple chips) maintains good flatness. The introduction of the reinforcing structure will help to improve the coplanarity of the surface of the multi-chip structure and provide protection for the chips to prevent damage to the edges of the chips.

[0057] Figure 7 Example of the package process and cross-sectional view of the package side for forming a reinforcing structure for multiple chips on a substrate using the second dam filling scheme in an embodiment of the present disclosure. Figure 7 The scheme of the example is referred to as the Underfill1&DAM&Underfill2 scheme.

[0058] S701, chip processing and cutting DPS; This step is the same as the S601 step in the previous embodiment, which is used for the DPS chip processing and cutting process of the chips, and will not be described here.

[0059] S702, using surface mounting SMT technology and flip chip assembly FCA technology to mount the multiple chips; This step is the same as step S602 in the previous embodiment, which is used to use SMT and FCA technology to Figure 7 The exemplary multi-chips (including at least chip A and chip B) are integrated on the same packaging substrate, which will not be described in detail here.

[0060] S703, first fill the bottom of the chip with bottom filler UF1, then add a cofferdam structure, and then cure; like Figure 7 In the example (A), in this step, the bottom of the chip is first filled with underfill (UF) glue, namely UF1 glue, and then DAM glue is applied to form a DAM cofferdam structure set on the surface of the substrate. Finally, the DAM glue and UF1 glue are heated and cured together.

[0061] S704, filling the inside of the cofferdam structure with bottom filling glue UF2, and then curing it to form a reinforcement structure; like Figure 7 In the example (B) above, UF2 glue is used to fill the gaps between the multiple chips within the DAM cofferdam and wrap around the chip edges. The UF2 glue and DAM glue are then cured to form a reinforcement structure, which is bonded to the multiple chips to form a single unit. The shrinkage stress of the UF2 glue during curing is restrained by the DAM cofferdam, and its high modulus helps control warpage in the middle of the package.

[0062] In this embodiment, the type of colloid filled in the cofferdam structure is different from the fill glue in the previous embodiment. Instead, bottom filling glue is used. This allows the bottom filling glue of the chip to have similar properties to the filling glue in the cofferdam structure, reducing the risk of cracking and delamination at the material interface.

[0063] Preferably, the composition of the UF2 colloid used for the cofferdam filling in this step can be the same as the composition of the UF1 colloid used in step S703. If the UF2 and UF1 colloids are made of the same material, the material properties of the reinforcement structure around the chip can be nearly consistent with those of the UF1 colloid, thereby reducing the risk of cracking and delamination at the material interface.

[0064] Preferably, in another embodiment of the present disclosure, the curing steps of UF1 glue, DAM glue and UF2 glue can be combined into one curing step to reduce the number of temperature stress loading times and simplify the production steps.

[0065] S705, using a grinding process to form a flat surface on the surfaces of the multiple chips and the surface of the reinforcement structure; like Figure 7An example of (C) in the above embodiment, the step uses a grinding process to make the surfaces of the multiple chips and the surface of the reinforcing structure into a flat surface, for example, the original surface height of chip A is higher than the surface of chip B, after grinding, the surfaces of chip A, chip B and the reinforcing structure are all in the same plane and the chip surfaces are exposed, which facilitates full contact with the heat sink / heat sink, reduces thermal resistance and improves heat dissipation efficiency.

[0066] S706, add reinforcing ring structure and solidify.

[0067] As Figure 7 An example of (D) in the above embodiment, please refer to the description of step S607, which will not be repeated here. It should be noted that the step of adding a reinforcing ring is an optional step. The reinforcing ring, in combination with the reinforcing structure formed by the colloid in the present disclosure, can bring better technical effect of controlling the warping of the packaging structure.

[0068] The physical reinforcing structure formed by the cofferdam filling technology in this embodiment includes two parts of DAM and UF2. The composition and properties of the colloid UF1 filled at the bottom of the chip and the colloid UF2 filled in the cofferdam are similar, which can reduce the risk of material interface cracking and delamination of the two colloid used in succession, making the reinforcing structure more solid and stable. Through the technical scheme of this embodiment, the chip surface can maintain good coplanarity, and the reinforcing structure can protect and control the warping of the chip, thereby improving the chip heat dissipation efficiency and prolonging the service life of the chip.

[0069] Figure 8 This is an example of a cross-sectional view of a packaging process and a packaging side surface for forming a reinforcing structure for multiple chips on a substrate using a third cofferdam filling scheme in an embodiment of the present disclosure. Figure 8 The example scheme is referred to as DAM & Underfill scheme.

[0070] S801, chip processing and cutting DPS; This step is described in the foregoing embodiment S601, which will not be repeated here.

[0071] S802, use surface mounting SMT technology and flip chip assembly FCA technology to mount multiple chips on the chip; This step is described in the foregoing embodiment S602, which will not be repeated here.

[0072] S803, add cofferdam structure, and solidify the cofferdam structure; As Figure 8An example of (A) in FIG. 8, after the chips (at least including chip A and chip B) are mounted on the substrate using FCA technology, the step of bottom filling of the chips is not performed, and a DAM dam structure is first prepared on the surface of the substrate by dispensing DAM glue, and then the glue of the DAM dam structure is heated and cured.

[0073] S804, filling the bottom of the chip and the inside of the dam with bottom filling glue, and then curing to form a reinforcing structure; As Figure 8 An example of (B) in FIG. 8, the step of filling the bottom of multiple chips and filling the inside space of the dam with bottom filling glue (UF glue) is performed at one time, and then the UF glue and the DAM glue are cured to form a reinforcing structure that fills the gap between the chips and wraps the edges of the chips.

[0074] Preferably, in another embodiment of the present disclosure, the curing steps of the dam glue in S803 and the bottom filling UF glue in S804 can be combined together for curing, so as to reduce the number of temperature stress loads and simplify the production steps.

[0075] S805, using a polishing process to form a flat surface on the surfaces of the multiple chips and the reinforcing structure; As Figure 8 An example of (C) in FIG. 8, the step of using a polishing process to form a flat surface on the surfaces of the multiple chips and the reinforcing structure, for details, please refer to the corresponding steps of the previous embodiments, which will not be repeated here.

[0076] S806, adding a reinforcing ring structure and curing.

[0077] As Figure 8 An example of (D) in FIG. 8, a reinforcing ring is added to the edge of the substrate, for details, please refer to the corresponding steps of the previous embodiments, which will not be repeated here.

[0078] The physical reinforcing structure in this embodiment includes two parts of DAM and UF, that is, after the DAM is formed, the UF glue is used to complete the bottom filling of the multiple chips and the forming of the reinforcing structure at one time. This scheme simplifies the complexity of the process and has strong compatibility with the existing production process. The reinforcing structure can surround the MCM multi-chip area in the package, and the width, thickness and position of the structure can be flexibly adjusted according to the multi-chip arrangement position on the surface of the package substrate. The outer edge of the reinforcing structure can be vertical as shown in Figure 12 , or have a certain inclination. The upper surface of the entire reinforcing structure (including the multiple chips) maintains good flatness, which will help to improve the coplanarity of the surface of the multi-chip structure and improve other aforementioned technical problems such as the vulnerability of the edges of the chips.

[0079] Figure 9This is an exemplary diagram of a packaging process and a cross-sectional side view of a package side that uses the first plastic packaging solution to form a reinforcement structure for multiple chips on a substrate in an embodiment of the present disclosure. Figure 9 The example solution is referred to as the FCBGA single-die molding solution.

[0080] S901, chip processing and cutting DPS; Please refer to the description of step S601 in the aforementioned embodiment for this step, which will not be repeated here.

[0081] S902, using surface mount technology (SMT) and flip chip assembly (FCA) technology to place multiple chips on the core, fill the bottom of the chip with underfill glue and cure it; like Figure 9 In the example of (A), after multiple chips are mounted on the core using SMT and FCA technology, the bottom of multiple chips are filled with underfill glue UF glue.

[0082] S903 , using a plastic encapsulation material to encapsulate the plurality of chips on the packaging substrate, the plastic encapsulation material wrapping the chips, and the plastic encapsulation material solidifies to form a reinforcement structure.

[0083] like Figure 9 In the example of step (B), multiple chips (including at least Chip A and Chip B) mounted on the package substrate are encapsulated using a molding material (typically a thermosetting plastic such as epoxy resin, silicone resin, or phenolic resin). During the encapsulation process, the molding material is melted to form a colloid. Then, using injection molding equipment, the colloid is injected into a mold cavity designed based on the layout of the multiple chips on the substrate. The molding material fills the gaps between the chips and wraps around their periphery and top surfaces. Then, under certain temperature and time conditions, the injected molding material undergoes a cross-linking reaction, transforming from a molten state to a solid state and curing. After curing, the molding material forms a reinforced structure. The curing temperature and time depend on the properties of the molding material, and are generally maintained at the desired temperature by a heating device on the mold.

[0084] S904, using a grinding process to form a flat surface on the surfaces of the multiple chips and the surface of the reinforcement structure; like Figure 9 In the example of (C), this step uses a grinding process to polish the reinforcement structure and the chip surface, so that the multiple chip surfaces and the reinforcement structure surfaces finally form a flat surface.

[0085] S905, adding a reinforcing ring structure and curing.

[0086] like Figure 9 In the example of (D), a reinforcement ring is added to the edge of the substrate. For detailed description, please refer to the corresponding steps of the aforementioned embodiment, which will not be repeated here.

[0087] The scheme replaces the molding process of the physical strengthening structure from the dam filling point gluing process to the plastic sealing Molding process. The plastic sealing material is more cost-effective, and has higher modulus in terms of material performance, and has lower thermal expansion coefficient than DAM glue and filling glue (UF glue and Fill glue), which helps to achieve better packaging warping performance. The plastic sealing structure can surround the MCM multi-chip area in the package. The width, thickness and position of the strengthening structure can be flexibly adjusted through the design of the plastic sealing mold according to the multi-chip arrangement position on the surface of the packaging substrate. The edge of the strengthening structure can be vertical as shown in Figure 12 The upper surface of the entire strengthening structure (including the multi-chip) maintains good flatness, which will help to improve the coplanarity of the surface of the multi-chip structure and play a role in protecting the edges of the chips.

[0088] Figure 10 The following is an example of a cross-sectional view of the process of forming a strengthening structure for multiple chips on a substrate and the packaging side surface according to the second plastic sealing scheme in an embodiment of the present disclosure. Figure 10 The example scheme is referred to as the FCBGA single Molding Underfill (MUF) scheme.

[0089] S1001, chip processing and cutting DPS; This step is described in the foregoing embodiment of step S601, which will not be repeated here.

[0090] S1002, using surface mounting SMT technology and flip chip assembly FCA technology to mount multiple chips on the chip; As shown in (A) of Figure 10 After using SMT and FCA technology to mount multiple chips on the chip, this step does not perform point gluing filling at the bottom of the chip.

[0091] S1003, using plastic sealing material to plastic seal multiple chips on the packaging substrate, the plastic sealing material fills the bottom of the chip and wraps the chip, and after curing, a strengthening structure is formed; As shown in Figure 10An example of (B) in the above embodiment, in this step, the multiple chips (at least including chip A and chip B) mounted on the substrate are molded on the packaging substrate using a molding material (usually a thermosetting plastic such as epoxy resin, silicone resin, phenolic resin, etc.), and in the molding process, the molding material needs to be melted to form a colloid, and then the colloid state molding material is injected into the mold cavity using an injection molding device and filled into the gap between the bottom of the chip and the substrate. The mold cavity is designed according to the layout of the multiple chips on the substrate, and the molding material will fill the gap between the bottom of the chip and the chip and wrap the periphery and upper surface of the chip. Then, under certain temperature and time conditions, the injected molding material undergoes cross-linking reaction to change from molten state to solid state, realizing solidification.

[0092] S1004, using a grinding process to form a flat surface on the surface of the multiple chips and the surface of the reinforcing structure; As Figure 10 An example of (C) in the above embodiment, in this step, the reinforcing structure and the chip surface are polished using a grinding process, so that the surface of the multiple chips and the surface of the reinforcing structure finally form a flat surface.

[0093] S1005, adding a reinforcing ring structure and solidifying.

[0094] As Figure 10 An example of (D) in the above embodiment, a reinforcing ring is added at the edge of the substrate, and the specific description is as follows. The corresponding steps of the foregoing embodiments are not repeated here.

[0095] Compared with the FCBGA single Molding scheme, the bottom filling UF dispensing process is also replaced by the Molding process. In the molding process, the molding material is used to replace the bottom filling adhesive to fill the gap between the chip and the substrate. The reinforcing structure formed by molding surrounds the MCM multi-chip area in the package. This scheme can simplify the packaging process and reduce the packaging cost. The width, thickness and position of the reinforcing structure formed by molding can be flexibly adjusted through the design of the molding mold according to the multi-chip arrangement position on the surface of the packaging substrate. The edge of the molding structure can be vertical as shown in Figure 12 , or have a certain inclination. The upper surface of the entire reinforcing structure (including multiple chips) maintains good flatness, which will help to improve the coplanarity of the surface of the multi-chip structure and play a role in protecting the edges of the chips.

[0096] Figure 11 The packaging process and the cross-sectional view of the packaging side of the third molding scheme for forming a reinforcing structure for multiple chips on a substrate in an embodiment of the present disclosure are shown in the following figures. Figure 11The example solution is referred to as the Fan out FCBGA solution. Multiple types of chip dies can be included on a wafer, and in this embodiment, wafer level fan out packaging is first performed and wafer level molding and dicing is performed, and then the diced fan out packaging particles are packaged.

[0097] S1101, fabricate an RDL on the first substrate, and flip multiple chips on the RDL, and fill the chip bottom with underfill glue.

[0098] As an example of (A) in FIG. 1, Figure 11 In this step, the pad layout and pitch of the multiple chips (at least including chip A and chip B) are adjusted based on a redistribution layer (RDL) process, the multiple chips are mounted on the first substrate using flip chip assembly FCA technology, and the chip bottom is filled with underfill glue (UF glue).

[0099] The RDL process can coat an insulating material on the surface of the chip, define a wiring pattern using photolithography technology, and fill metal through a metal deposition process to form a conductive circuit. The RDL process not only improves packaging density and enhances electrical performance, but also provides a foundation for advanced packaging technologies such as multi-chip integration and 3D packaging, effectively improving the overall performance and adaptability of chip packaging.

[0100] S1102, perform wafer level molding to form a reinforcing structure; As an example of (A) in FIG. 1, Figure 11 In this step, the multiple chips on the first substrate are molded at the wafer level using molding material, and in the molding process, the gap between the chips is filled with molding material and the entire chip is wrapped, and the molding material and the underfill glue are solidified around the multiple chips to form a reinforcing structure.

[0101] S1103, perform wafer level backgrinding using a grinding process to form a flat surface on the surface of the multiple chips and the surface of the reinforcing structure, and then perform C4 ball planting; As an example of (B) in FIG. 1, Figure 11 In this step, the wafer after molding is ground at the wafer level using a grinding process to thin the back, so that the surface of all the chips on the wafer and the surface of the reinforcing structure become a flat surface.

[0102] In the chip manufacturing packaging process, the controlled collapse chip connection (C4) process includes two closely related important links of C4 bumping and C4 bonding. C4 bumping refers to the process of making bumps on the pads of the chip. These bumps are usually composed of solder (such as tin-lead alloy, lead-free solder, etc.), and C4 bumping provides a physical medium for the connection between the chip and the substrate, enabling the chip to achieve electrical connection with external circuits.

[0103] S1104, wafer-level fan-out package particles are cut; Wafer sawing is a key link in the chip manufacturing process. After completing all the manufacturing processes of the chips on the wafer, a large number of functional complete but not yet separated chips are arranged on the wafer. This step cuts the fan-out package particles after wafer-level packaging through wafer sawing, cutting out independent fan-out package particles.

[0104] S1105, using surface mount SMT technology and flip chip assembly FCA technology to mount the fan-out package particles on the second substrate; As an example in (C) of the embodiment in Figure 11 This step mounts the cut fan-out package particles on the second substrate. In this step, the C4 bonding step is performed, which is a process step of connecting the chip and the substrate using the bumps made by C4 bumping. In this process, the chip with bumps is accurately placed on the corresponding pad position of the substrate, and the solder of the bump is melted by heating. Under the action of surface tension, the melted solder forms a good metallurgical bond between the chip and the substrate pad, thereby achieving reliable electrical and mechanical connection.

[0105] S1106, filling the bottom of the fan-out package particles with bottom filling glue and curing; S1107, adding a reinforcing ring structure and curing.

[0106] As an example in (D) of the embodiment in Figure 11 A reinforcing ring is added to the edge of the second substrate. For specific instructions, please refer to the corresponding steps of the aforementioned embodiments, which will not be repeated here.

[0107] This embodiment requires fanning out multiple dies, followed by underfill and encapsulation at the wafer level. This solution improves packaging efficiency. The encapsulation process uses wafer-level molds, eliminating the need for separate mold adaptations for each different packaging structure, reducing mold costs. The top surface of the entire reinforced structure (including multiple chips) maintains excellent flatness, which helps improve the coplanarity of the multi-chip structure's surface. The reinforced structure also protects the chips.

[0108] Figure 12 This is a schematic diagram of the edge structure design of the reinforcement structure provided by an embodiment of the present disclosure. The edge of the reinforcement structure can be designed to match the application characteristics of the product and also requires the support of the plastic packaging mold structure.

[0109] use Figure 12 The chamfered side structure shown in example (a) can mitigate the stress levels acting on the upper edge of the reinforcement structure during heat sink installation, preventing issues such as edge chipping and cracking. The chamfered design alone can also limit the lateral dimensions of the reinforcement structure, preventing it from extending too wide and impacting the placement of other components on the substrate surface.

[0110] use Figure 12 The side bevel design (b) mitigates stress at the interface between the reinforcement structure and the substrate, preventing delamination and cracking. Furthermore, this bevel exhibits a concave curve when using the DAM&Fill solution.

[0111] use Figure 12 The right-angle side structure design of (c) has a simpler plastic encapsulation mold structure and is also convenient for controlling the width of the compression reinforcement structure to avoid interfering with the assembly of other surface components.

[0112] Figure 13 This is a top view of an example diagram of various reinforcement structure layout designs used in one embodiment of the present disclosure. The reinforcement structure layout can take various forms, such as rectangle, square, triangle, polygon (regular or irregular), circle, and so on. The intersection angle between two sides of the reinforcement structure can be right angle or rounded. The different reinforcement structure forms are primarily adapted to different surface chip layouts on the substrate. Figure 13 The number of chips shown is for illustration only. In practice, one or more chips of the same or different sizes may be arranged in parallel or staggered. The present invention does not impose any limitation on the actual layout.

[0113] The above-described embodiments of the application have been described in connection with what are presently considered to be the most practical and preferred embodiments, and the best modes contemplated by the inventors of carrying out the application. Of course, the application is not limited to the embodiments, but is intended to cover any modifications or equivalents included within the spirit and scope of the application. It is intended that each of the claims is to be interpreted to embrace all such modifications and equivalents.

[0114] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the present description shall include all such modifications and variations as come within the scope of the concepts described. It is intended that the specification and examples be considered as exemplary only, with the true scope of the application being indicated only by the following claims.

[0115] The above description is intended to be illustrative and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the application should, therefore, be determined not with reference to the above description, but instead with reference to the appended claims, along with their full scope of equivalents.

Claims

1. A multi-chip flip chip ball grid array packaging method, which is based on a flip chip ball grid array packaging (FCBGA) technique for packaging a plurality of chips on a single substrate, characterized by, The method comprises: ​ filling the gap between the chips and wrapping the chip edges with a gel, and curing the gel around the periphery of the chips to form a reinforcing structure; using a polishing process to form a flat surface on the surface of the chips and the reinforcing structure and expose the surface of the chips.

2. The method of claim 1, wherein, The method further comprises: adding a reinforcing ring on the substrate.

3. The method according to claim 1 or 2, characterized in that, The method of filling the gap between the chips and wrapping the chip edges with a gel, and curing the gel around the periphery of the chips to form a reinforcing structure comprises: After the multi-chip is mounted using surface mount technology (SMT) and flip chip assembly technology (FCA), first fill the bottom of the chip with underfilling glue and then cure it; Use cofferdam glue to make cofferdam structure on the periphery of the chip, and then fill the cofferdam with filling glue and cure it to form a reinforcing structure; The curing steps of the underfilling glue, cofferdam glue and filling glue are carried out separately or together.

4. The method of claim 1 or 2, wherein, The method of filling the gap between the chips and wrapping the chip edges with a gel, and curing the gel around the periphery of the chips to form a reinforcing structure comprises: After the multi-chip is mounted using surface mount technology (SMT) and flip chip assembly technology (FCA), first fill the bottom of the chip with first underfilling glue, then make cofferdam structure with cofferdam glue and cure it; Fill the cofferdam structure with second underfilling glue and cure it to form a reinforcing structure; The curing steps of the first underfilling glue, cofferdam glue and second underfilling glue are carried out separately or together.

5. The method of claim 1 or 2, wherein, The method of filling the gap between the chips and wrapping the chip edges with a gel, and curing the gel around the periphery of the chips to form a reinforcing structure comprises: After the multi-chip is mounted using surface mount technology (SMT) and flip chip assembly technology (FCA), first add cofferdam structure with cofferdam glue and cure it; Fill the bottom of the chip and the cofferdam with underfilling glue, which fills the gap between the chips and wraps the chip edges, and then cure it to form a reinforcing structure; The curing steps of the cofferdam glue and underfilling glue are carried out separately or together.

6. The method of claim 1 or 2, wherein, The method of filling the gap between the chips and wrapping the chip edges with a gel, and curing the gel around the periphery of the chips to form a reinforcing structure comprises: After the multi-chip is mounted using surface mount technology (SMT) and flip chip assembly technology (FCA), fill the bottom of the chip with underfilling glue and cure it; Use plastic packaging material to package the multi-chip on the packaging substrate, and the plastic packaging material wraps the chip. After curing, a reinforcing structure is formed.

7. The method of claim 1 or 2, wherein, The method of filling the gap between the chips and wrapping the chip edges with a gel, and curing the gel around the periphery of the chips to form a reinforcing structure comprises: After the multi-chip is mounted using surface mount technology (SMT) and flip chip assembly technology (FCA), use plastic packaging material to package the multi-chip on the packaging substrate, and the plastic packaging material fills the bottom of the chip and wraps the chip. After curing, a reinforcing structure is formed.

8. The method of claim 1 or 2, wherein: first, the multi-chip is packaged on a first substrate using fan-out packaging technology and the wafer-level fan-out packaging die is cut, and then the fan-out packaging die is packaged on a second substrate using FCBGA technology; The process of packaging the plurality of chips to the first substrate by using fan-out packaging technology and cutting the wafer-level fan-out packaging die includes: Fabricating a redistribution layer (RDL) on the first substrate, mounting the plurality of chips on the first substrate by using flip chip assembly (FCA) technology, and filling the bottom of the chips by using underfilling glue; Wafer-level plastic packaging of the plurality of chips on the first substrate by using plastic packaging material, filling the gap between the chips and wrapping the edges of the chips by using the plastic packaging material during the plastic packaging process, and solidifying the plastic packaging material around the edges of the plurality of chips to form a reinforcing structure; Wafer-level backside thinning by using a grinding process to form a flat surface on the surfaces of the plurality of chips and the reinforcing structure, and then performing controlled collapse chip connection (C4) ball planting; Cutting the wafer-level fan-out packaging die.

9. The method of claim 1, wherein: the edge structure of the reinforcing structure is designed in a side bevel type, a side bevel angle type, or a side right angle type, and the layout of the reinforcing structure is adapted to different surface chip position layouts on the substrate; the intersection angle of two edges of the reinforcing structure is a right angle or a round angle.

10. A multi-chip flip chip ball grid array packaging structure, characterized in that: The packaging structure includes a substrate, a plurality of chips packaged on the substrate, and a reinforcing structure. The plurality of chips are packaged on the same substrate by using flip chip ball grid array (FCBGA) packaging technology. The reinforcing structure is a reinforcing structure formed after the solidification of glue or plastic packaging material, and the glue or plastic packaging material of the reinforcing structure fills the gap between the chips and wraps the edges of the chips. The surfaces of the plurality of chips and the surface of the reinforcing structure are a flat surface formed after polishing by using a grinding process, and the surfaces of the plurality of chips are exposed.

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