Charge pump circuit and charge pump system

Abstract

The invention provides a charge pump circuit and a charge pump system, and relates to the technical field of semiconductors. The charge pump circuit comprises a switch unit which comprises a first switch tube, a second switch tube and control ends which are respectively connected with the first switch tube and the second switch tube; a clock unit including a clock generator outputting a reverse clock signal; the capacitor unit comprises a first capacitor and a second capacitor, one end of the first capacitor is connected with the first switch tube, the other end of the first capacitor is coupled with one of the reverse clock signals, one end of the second capacitor is connected with the second switch tube, and the other end of the second capacitor is coupled with the other one of the reverse clock signals; the first capacitor is used for stabilizing the voltage of the first connection point, and the second capacitor is used for stabilizing the voltage of the second connection point. According to the technical scheme, the influence of the substrate bias effect of the switching tube on the threshold voltage of the switching tube can be reduced, and then the influence of voltage fluctuation on the signal line on the conduction characteristics of the first switching tube and the second switching tube is reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a charge pump circuit and a charge pump system. BACKGROUND

[0002] The charge pump is a device for providing voltages required for read, program and erase operations of a non-volatile memory, but the MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) transistor in the current charge pump has a substrate bias effect, resulting in defects such as low transmission efficiency and insufficient voltage resistance of the charge pump.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The purpose of the present disclosure is to provide a charge pump circuit and a charge pump system, which at least partially overcome the problems of low transmission efficiency and insufficient voltage resistance of the charge pump caused by the substrate bias effect of the MOS transistor in the related art.

[0005] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0006] According to one aspect of the present disclosure, a charge pump circuit is provided, comprising: a switching unit comprising a first switching transistor and a second switching transistor, and a control end connected by the first switching transistor and the second switching transistor respectively, the first switching transistor and the second switching transistor being PMOS transistors, or the first switching transistor and the second switching transistor being NMOS transistors; a clock unit comprising a clock generator outputting a reverse clock signal; a capacitor unit comprising a first capacitor and a second capacitor, one end of the first capacitor being connected with the first switching transistor, the other end of the first capacitor being coupled with one of the reverse clock signals, one end of the second capacitor being connected with the second switching transistor, the other end of the second capacitor being coupled with the other of the reverse clock signals, the first capacitor and the first switching transistor having a first connection point therebetween, the first capacitor being used for voltage stabilization of the first connection point, the second capacitor and the second switching transistor having a second connection point therebetween, the second capacitor being used for voltage stabilization of the second connection point.

[0007] In one embodiment of the present disclosure, the control end includes a first control end and a second control end; the capacitor unit further includes a third capacitor and a fourth capacitor, one end of the third capacitor is connected to the first control end, the other end of the third capacitor is coupled to one of the inverted clock signals, one end of the fourth capacitor is connected to the second control end, and the other end of the fourth capacitor is coupled to another of the inverted clock signals.

[0008] In one embodiment of the present disclosure, the control end includes a first control end and a second control end; the capacitor unit further includes a third capacitor and a fourth capacitor, one end of the third capacitor is connected to the first control end, the other end of the third capacitor is coupled to one of the inverted clock signals, one end of the fourth capacitor is connected to the second control end, and the other end of the fourth capacitor is coupled to another of the inverted clock signals.

[0009] In one embodiment of the present disclosure, the other end of the first clamping circuit is connected to the first control end, and the other end of the second clamping circuit is connected to the second control end.

[0010] In one embodiment of the present disclosure, the switch unit further includes a third switch tube and a fourth switch tube, the gate of the first switch tube is connected to the first connection point; the gate of the second switch tube is connected to the second connection point; the source of the first switch tube, the drain of the third switch tube, and the gate of the fourth switch tube are connected to the first control end; the source of the second switch tube, the drain of the fourth switch tube, and the gate of the third switch tube are connected to the second control end.

[0011] In one embodiment of the present disclosure, the switch unit further includes a third switch tube and a fourth switch tube, the gate of the first switch tube is connected to the first connection point; the gate of the second switch tube is connected to the second connection point; the source of the first switch tube, the drain of the third switch tube, and the gate of the fourth switch tube are connected to the first control end; the source of the second switch tube, the drain of the fourth switch tube, and the gate of the third switch tube are connected to the second control end.

[0012] In one embodiment of the present disclosure, the third switch tube and the fourth switch tube are PMOS tubes.

[0013] In one embodiment of the present disclosure, the inverted clock signal includes a first clock signal and a second clock signal, the first capacitor is connected to the first clock signal, the second capacitor is connected to the second clock signal, when the first clock signal is low, the first switch tube is turned on, the first clamping circuit is used for upward clamping the voltage of the first connection point, when the second clock signal is high, the second switch tube is turned off, and the second clamping circuit is used for downward clamping the voltage of the second connection point.

[0014] In one embodiment of the present disclosure, the inverted clock signal comprises a first clock signal and a second clock signal, the first capacitor is connected to the second clock signal, the second capacitor is connected to the first clock signal, when the second clock signal is high, the first switch is off, the first clamping circuit is used for clamping the voltage at the first connection point downward, when the first clock signal is low, the second switch is on, and the second clamping circuit is used for clamping the voltage at the second connection point upward.

[0015] In one embodiment of the present disclosure, the first clamping circuit or the second clamping circuit comprises a first diode and a second diode connected in parallel, and the first diode and the second diode are reversely arranged.

[0016] According to another aspect of the present disclosure, a charge pump system is provided, comprising at least two charge pump circuits as described in the above embodiments, and the at least two charge pump circuits are cascaded in sequence.

[0017] In one embodiment of the present disclosure, the at least two charge pump circuits comprise a first stage charge pump and at least one cascaded secondary charge pump, wherein the first switch and the second switch in the first stage charge pump are PMOS or NMOS, and the first switch and the second switch in the secondary charge pump are PMOS.

[0018] In one embodiment of the present disclosure, the at least two charge pump circuits comprise adjacent first and second charge pumps, in the first charge pump, one end of a first capacitor is connected to a first switch, the other end of the first capacitor is coupled to one of inverted clock signals, one end of a second capacitor is connected to a second switch, and the other end of the second capacitor is coupled to the other inverted clock signal; in the second charge pump, one end of the first capacitor is connected to the first switch, the other end of the first capacitor is coupled to the other inverted clock signal, one end of the second capacitor is connected to the second switch, and the other end of the second capacitor is coupled to one of the inverted clock signals.

[0019] The charge pump scheme provided by the embodiments of the present disclosure can reduce the influence of the substrate bias effect of the switch tube on the on / off state of the switch tube, and also facilitate alleviating the voltage fluctuation on the signal line caused by the charge transmission in the charge pump circuit, thereby facilitating improving the transmission efficiency and voltage resistance of the charge pump circuit.

[0020] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained according to these drawings without creative labor for those skilled in the art.

[0022] Figure 1 A circuit schematic diagram of a charge pump system in an embodiment of the present disclosure is shown;

[0023] Figure 2 A schematic diagram of a charge pump circuit in an embodiment of the present disclosure is shown;

[0024] Figure 3 A schematic diagram of another charge pump circuit in an embodiment of the present disclosure is shown;

[0025] Figure 4 A schematic diagram of still another charge pump circuit in an embodiment of the present disclosure is shown;

[0026] Figure 5 A schematic diagram of a clamping circuit in an embodiment of the present disclosure is shown;

[0027] Figure 6 A schematic block diagram of another charge pump system in an embodiment of the present disclosure is shown;

[0028] Figure 7A circuit diagram of another charge pump system according to an embodiment of the present disclosure is shown;

[0029] Figure 8 A structural block diagram of a memory in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0031] In addition, the accompanying drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0032] The substrate bias effect refers to the phenomenon that the source potential of the MOS tube is greater than the substrate potential (V S >V B ), more holes in the surface layer below the gate will be absorbed into the substrate, leaving more immobile negative ions, causing the depletion layer to widen and the turn-on threshold voltage V TH Increase.

[0033] A deep N-well NMOS transistor refers to an NMOS transistor (N-channel Metal-Oxide-Semiconductor) with a deep N-well layer added between the P-well and the P-substrate. Since a P-well is provided in the deep N-well and the P-well has a free potential, by connecting a high potential to the P-well, the deep N-well NMOS transistor can connect the substrate P-well to the drain to increase the substrate voltage, thereby reducing the substrate bias effect and lowering the turn-on threshold voltage V TH .like Figure 1 As shown, the charge pump circuit A and the charge pump circuit B are two adjacent charge pumps in the charge pump system, wherein V n is the input voltage of the charge pump circuit A, V n+1 is the output voltage of charge pump circuit A and the input voltage of charge pump circuit B, V n+2The output voltage of the charge pump circuit B, the switch tube N0 and the switch tube N1 in the charge pump circuit A, the switch tube N2 and the switch tube N3 in the charge pump circuit B are deep N well NMOS tubes, the switch tube P0, the switch tube P1, the switch tube P2 and the switch tube P3 are low-voltage PMOS tubes (P-channel Metal-Oxide-Semiconductor), CLK and CLKB are reverse clock signals, the charge pump is a doubler positive voltage charge pump, and the charge pump has high transmission efficiency and low backflow.

[0034] Since the deep N well MOS tube has defects of large process difficulty and high cost of the deep N well layer, if the ordinary NMOS tube is simply used for replacement, the substrate bias effect of the NMOS tube will cause problems of poor conduction characteristics of the charge pump and high working difficulty of the multi-stage charge pump, and therefore, a scheme is urgently needed, which does not use the deep N well NMOS tube but still enables the charge pump to have the advantages of high efficiency and low backflow.

[0035] As shown in FIG. 1, the charge pump circuit according to one embodiment of the present disclosure includes a switch unit, a clock unit and a capacitor unit. Figure 2

[0036] In some embodiments, the switch unit includes a first switch tube 102 and a second switch tube 104, and control ends of the first switch tube 102 and the second switch tube 104 are connected, respectively. The first switch tube 102 and the second switch tube 104 are PMOS tubes, or the first switch tube 102 and the second switch tube 104 are NMOS tubes.

[0037] In some embodiments, in the multi-stage charge pump, if the charge pump circuit is in the first-stage charge pump circuit, the first switch tube 102 and the second switch tube 104 are PMOS tubes or the first switch tube 102 and the second switch tube 104 are NMOS tubes, and if the charge pump circuit is in the next stage, the first switch tube 102 and the second switch tube 104 are both PMOS tubes. The two switch tubes control the flow of charges, and the transmission and storage of charges are realized by adjusting the conduction state thereof.

[0038] In some embodiments, the clock unit includes a clock generator outputting reverse clock signals, and the reverse clock signals include a first clock signal CLKB and a second clock signal CLK.

[0039] The clock unit includes a clock generator outputting reverse clock signals, and is configured to generate timing signals to control the operation of the first switch tube 102 and the second switch tube 104. Through accurate clock control, the coordinated work of each part of the charge pump circuit can be ensured, and the transmission efficiency and stability can be improved.

[0040] ​In some embodiments, the capacitor unit includes a first capacitor 106 and a second capacitor 108, one end of the first capacitor 106 is connected to the first switch tube 102, the other end of the first capacitor 106 is coupled to one of the inverted clock signals, one end of the second capacitor 108 is connected to the second switch tube 104, the other end of the second capacitor 108 is coupled to the other inverted clock signal, the first capacitor 106 and the first switch tube 102 have a first connection point 110, the first capacitor 106 is used to stabilize the voltage of the first connection point 110, the second capacitor 108 and the second switch tube 104 have a second connection point 112, and the second capacitor 108 is used to stabilize the voltage of the second connection point 112.

[0041] In some embodiments, the first capacitor 106 and the second capacitor 108 are both voltage stabilizing capacitors, the first capacitor 106 is connected to the first switch tube 102 and has a first connection point 110, the second capacitor 108 is connected to the second switch tube 104 and has a second connection point 112, and the voltage of the first connection point 110 and the second connection point 112 is stabilized within a certain range, so as to prevent the voltage fluctuation at the first connection point 110 and the second connection point 112 from affecting the conduction performance of the first switch tube 102 and the second switch tube 104 when the voltage fluctuation is too large.

[0042] In this embodiment, in the charge pump circuit without using high-cost deep N-well NMOS tube, the first connection point is connected to the gate of the first switch tube, and the second connection point is connected to the gate of the second switch tube, if the voltage fluctuation of the first connection point and the second connection point exceeds a certain range, it may cause the electric field between the gate and the source of the switch tube to be affected, thereby affecting the on / off state of the first switch tube and the second switch tube, and thus affecting the conduction performance of the switch tube. By setting voltage stabilizing capacitors, i.e. the first capacitor and the second capacitor, between the switch tube and the corresponding clock generator, the first capacitor is used to stabilize the voltage of the first connection point, i.e. to stabilize the voltage of the gate of the first switch tube, and the second capacitor is used to stabilize the voltage of the second connection point, i.e. to stabilize the voltage of the gate of the second switch tube, on the one hand, it can reduce the influence of the substrate bias effect of the switch tube on the on / off state of the switch tube, on the other hand, it can reduce the influence of the voltage fluctuation on the signal line during the charge transfer on the conduction characteristics of the first switch tube and the second switch tube, thereby improving the transfer efficiency and voltage resistance of the charge pump circuit.

[0043] As shown in FIG. 1, Figure 3 In one embodiment of the present disclosure, the charge pump circuit further includes a clamping unit including a first clamping circuit 114 and a second clamping circuit 116, one end of the first clamping circuit 114 is connected to the first connection point 110 for clamping the voltage of the first connection point 110, and one end of the second clamping circuit 116 is connected to the second connection point 112 for clamping the voltage of the second connection point 112.

[0044] In some embodiments, the first clamping circuit 114 is used to clamp the voltage at the first connection point 110 , ie, the gate of the first switch 102 , and the second clamping circuit 116 is used to clamp the voltage at the second connection point 112 , ie, the gate of the second switch 104 .

[0045] In this embodiment, by connecting the first clamping circuit and the second clamping circuit to different connection points respectively, the first clamping circuit and the second clamping circuit respectively limit the voltage range of the first connection point and the second connection point, and the different connection points can be clamped independently to achieve control and protection of the gate voltage of the first switching tube and the second switching tube. Combined with the voltage stabilization processing of the first connection point by the first capacitor and the voltage stabilization processing of the second connection point by the second capacitor, the stability and reliability of the conduction performance of the first switching tube and the second switching tube can be further guaranteed.

[0046] In some embodiments, in a charge pump circuit, since the voltage boosting process is often accompanied by charge transfer and accumulation, it is easy to cause voltage withstand problems. By setting a clamping unit, it is also possible to prevent the voltage in the charge pump circuit from being too high and causing voltage withstand problems.

[0047] like Figure 4 As shown, in one embodiment of the present disclosure, the control end includes a first control end and a second control end; the capacitor unit also includes a third capacitor and a fourth capacitor, one end of the third capacitor is connected to the first control end, and the other end of the third capacitor is coupled to one of the reverse clock signals, one end of the fourth capacitor is connected to the second control end, and the other end of the fourth capacitor is coupled to the other of the reverse clock signals.

[0048] In one embodiment of the present disclosure, the reverse clock signal includes a first clock signal and a second clock signal, the first capacitor and the third capacitor are respectively connected to the first clock signal, and the second capacitor and the fourth capacitor are respectively connected to the second clock signal.

[0049] In one embodiment of the present disclosure, the third capacitor and the fourth capacitor are capacitors used in the boost main path, the first capacitor and the second capacitor are capacitors used to control the gate of the switching tube, and the voltages of the first control terminal and the second control terminal are affected by the charge of the main path and jitter occurs. Although the clock signals connected to the first capacitor and the third capacitor are signals of the same phase, by using different clock generators to generate the same clock signal, and coupling them to the first connection point and the first control terminal respectively, the gate control of the first switching tube and the boost control of the charge pump can be separated, so that the voltage of the first connection point is not interfered with by the voltage of the jittering first control terminal, thereby ensuring the reliability of the on-off control of the first switching tube.

[0050] In some embodiments, the second clock signal inputted by the second capacitor and the fourth capacitor is a same-phase signal, and the same clock signal is generated by using different clock generators and coupled to the second connection point and the second control end respectively, so that the gate control of the second switch tube and the voltage boosting control of the charge pump are separated, the voltage of the second connection point is not interfered by the voltage of the second control end with jitter, and the reliability of the on-off control of the second switch tube is ensured.

[0051] In one embodiment of the present disclosure, since the first capacitor and the second capacitor are used for voltage stabilization, a large-capacity capacitor is not required, that is, the capacity of the first capacitor is smaller than that of the third capacitor or the fourth capacitor, and the capacity of the second capacitor is smaller than that of the third capacitor or the fourth capacitor. Since the capacitor is a device occupying a larger area in the circuit board, in a charge pump circuit using an ordinary switch tube, by using the first capacitor and the second capacitor with small capacity, the charge pump circuit can have a lower manufacturing cost while the increase of the area occupied by the charge pump circuit in the circuit board is smaller.

[0052] In this embodiment, the third capacitor and the fourth capacitor are storage capacitors in the charge pump circuit, and the charging and discharging process of the third capacitor and the fourth capacitor realizes the voltage boosting operation of the output voltage of the charge pump circuit relative to the input voltage.

[0053] In one embodiment of the present disclosure, the other end of the first clamping circuit is connected to the first control end, and the other end of the second clamping circuit is connected to the second control end.

[0054] In some embodiments, one end of the first clamping circuit is connected to the first connection point, the other end of the first clamping circuit is connected to the first control end, one end of the second clamping circuit is connected to the second connection point, and the other end of the second clamping circuit is connected to the second control end. Based on the conduction characteristics of the clamping circuit, when the first capacitor discharges, the charge flows from the first connection point to the first control end, and the charge flowing to the first control end can be used for charging the third capacitor. When the second capacitor discharges, the charge flows from the second connection point to the second control end, and the charge flowing to the second control end can be used for charging the fourth capacitor.

[0055] In this embodiment, by connecting the first connection point and the first control end to the two ends of the first clamping circuit respectively and connecting the second connection point and the second control end to the two ends of the second clamping circuit respectively, the clamping circuit is beneficial to reducing the loss of charge in the circuit.

[0056] In one embodiment of the present disclosure, the switching unit further includes a third switching tube and a fourth switching tube, the gate of the first switching tube is connected to the first connection point; the gate of the second switching tube is connected to the second connection point; the source of the first switching tube, the drain of the third switching tube, and the gate of the fourth switching tube are connected to the first control end; the source of the second switching tube, the drain of the fourth switching tube, and the gate of the third switching tube are connected to the second control end.

[0057] In one embodiment of the present disclosure, it also includes an input end and an output end, the drain of the first switch tube and the drain of the second switch tube are connected to the input end; the source of the third switch tube and the source of the fourth switch tube are connected to the output end.

[0058] The input end is the voltage input end of the charge pump, and the output end is the voltage output end of the charge pump.

[0059] In some embodiments, in a first-stage charge pump circuit, the switching unit includes a first switching tube, a second switching tube, a third switching tube, and a fourth switching tube, and charge transfer and accumulation are achieved by controlling the on / off state of the switching tube, wherein the gate of the first switching tube is connected to the first connection point and coupled to the first capacitor, the source of the first switching tube is connected to the first control terminal, and the drain of the first switching tube is connected to the voltage input terminal, the gate of the second switching tube is connected to the second connection point and coupled to the second capacitor, the source of the second switching tube is connected to the second control terminal, and the drain of the second switching tube is connected to the voltage input terminal, the gate of the third switching tube is connected to the second control terminal and coupled to the fourth capacitor, the source of the third switching tube is connected to the voltage output terminal, and the drain of the third switching tube is connected to the first control terminal, the gate of the fourth switching tube is connected to the first control terminal and coupled to the third capacitor, the source of the fourth switching tube is connected to the voltage output terminal, and the drain of the fourth switching tube is connected to the second control terminal.

[0060] In one embodiment of the present disclosure, the third switch tube and the fourth switch tube are PMOS tubes.

[0061] In this embodiment, the voltages at the first connection point and the second connection point are clamped by the synergistic effect of the voltage-stabilizing capacitor and the clamping circuit in the charge pump circuit. When an ordinary PMOS tube is used in the charge pump circuit, efficient voltage multiplication and stable output can also be achieved.

[0062] In one embodiment of the present disclosure, the reverse clock signal includes a first clock signal and a second clock signal. The first capacitor is connected to the first clock signal, and the second capacitor is connected to the second clock signal. When the first clock signal is at a low level, the first switch tube is turned on, and the first clamping circuit is used to clamp the voltage of the first connection point upward. When the second clock signal is at a high level, the second switch tube is turned off, and the second clamping circuit is used to clamp the voltage of the second connection point downward.

[0063] Among them, in the first-stage charge pump circuit, the first capacitor and the third capacitor are connected to the first clock signal, and the second capacitor and the fourth capacitor are connected to the second clock signal. The first clock signal is sent by two clock generators, and the second clock signal is sent by two clock generators, so as to realize the separate control of the gate of the switching tube and the boost main path.

[0064] In some embodiments, as Figure 4 As shown, the first to fourth switch transistors are all PMOS transistors, the first clock signal CLKB is connected to the first capacitor C1 and the third capacitor C3, and the second clock signal CLK is connected to the second capacitor C2 and the fourth capacitor C4. When the first clock signal CLKB is at a low level and the second clock signal CLK is at a high level, the first switch transistor MP1 and the fourth switch transistor MP4 are turned on, and the second switch transistor MP2 and the third switch transistor MP3 are turned off. At this time, the voltage of the first control terminal 118 is V n , the voltage of the second control terminal 120 is V n +V DD , where V DD The voltage value is a high level, and the charge of the first control terminal 118 is discharged to the first connection point 110 through the first clamping circuit 114, thereby preventing the first switch tube MP1 from being unable to be turned off due to the voltage of the first connection point 110 being too low, and preventing the second switch tube MP2 from being unable to be turned on due to the voltage of the second connection point 112 being too high.

[0065] In one embodiment of the present disclosure, the reverse clock signal includes a first clock signal and a second clock signal, the first capacitor is connected to the second clock signal, and the second capacitor is connected to the first clock signal. When the second clock signal is at a high level, the first switch tube is cut off, and the first clamping circuit is used to clamp the voltage of the first connection point downward. When the first clock signal is at a low level, the second switch tube is turned on, and the second clamping circuit is used to clamp the voltage of the second connection point upward.

[0066] In some embodiments, as Figure 4 As shown, the first to fourth switch tubes are all PMOS tubes. When the first clock signal CLKB is at a high level and the second clock signal CLK is at a low level, the first switch tube MP1 and the fourth switch tube MP4 are turned off, and the second switch tube MP2 and the third switch tube MP3 are turned on. At this time, the voltage of the first connection point 110 is pulled high, and the voltage of the second control terminal 120 is V n , the charge at the first connection point 110 is discharged to the first control terminal 118, preventing the voltage at the first connection point 110 from being too high and causing the switch tube MP1 to be unable to turn on, and the charge at the first connection point 110 discharged by the first clamping circuit 114 can be transmitted to the first control terminal 118 without charge loss.

[0067] like Figure 5As shown, in one embodiment of the present disclosure, the first clamping circuit or the second clamping circuit includes: a first diode D1 and a second diode D2 connected in parallel, and the first diode D1 and the second diode D2 are arranged in opposite directions.

[0068] For the first clamping circuit, the connection point is the first connection point and the control end is the first control end; for the second clamping circuit, the connection point is the second connection point and the control end is the second control end.

[0069] In addition, a circuit structure constructed by an operational amplifier can be used to achieve a precise clamping effect, or the characteristics of a Zener diode can be used to clamp the signal.

[0070] In this embodiment, the clamping circuit utilizes the characteristics of diodes to achieve a signal clamping effect. When the input signal exceeds the diode's cutoff voltage, the diode begins to conduct. When the voltage at the connection point is higher than the voltage at the control terminal, the first diode D1 conducts. When the voltage at the control terminal is higher than the voltage at the connection point, the second diode D2 conducts. This prevents the voltage difference between the connection point and the control terminal from being too large, thereby ensuring the stability of the voltage at the connection point and the control terminal.

[0071] A charge pump system according to an embodiment of the present disclosure includes: at least two charge pump circuits as described in the above embodiments, wherein the at least two charge pump circuits are cascaded in sequence.

[0072] like Figure 6 As shown, the charge pump system has a positive voltage input port VIN, a positive voltage output port VOUT, and multiple charge pump circuits (including charge pump circuit 1, charge pump circuit 2 to charge pump circuit N) cascade-coupled between the positive voltage input port VIN and the positive voltage output port VOUT.

[0073] In this embodiment, in the charge pump circuit of each stage, the first connection point is connected to the gate of the first switching tube, and the second connection point is connected to the gate of the second switching tube. If the voltage fluctuation of the first connection point and the second connection point exceeds a certain range, it may cause the electric field between the gate and the source of the switching tube to be affected, thereby affecting the on / off state of the first switching tube and the second switching tube.

[0074] In some embodiments, by setting a voltage-stabilizing capacitor between the switching tube and the corresponding clock generator, that is, a first capacitor and a second capacitor, the first capacitor is used to stabilize the voltage of the first connection point, that is, to stabilize the gate voltage of the first switching tube, and the second capacitor is used to stabilize the voltage of the second connection point, that is, to stabilize the gate voltage of the second switching tube. On the one hand, it can reduce the influence of the substrate bias effect of the switching tube on the on / off state of the switching tube. On the other hand, it is also beneficial to slow down the voltage fluctuation on the signal line caused by the charge transfer in the charge pump circuit, thereby helping to improve the transmission efficiency and voltage resistance of the charge pump circuit.

[0075] In one embodiment of the present disclosure, the at least two charge pump circuits include a first stage charge pump and at least one cascaded secondary charge pump, wherein the first switch tube and the second switch tube in the first stage charge pump are PMOS tubes or NMOS tubes, and the first switch tube and the second switch tube in the secondary charge pump are PMOS tubes.

[0076] In one embodiment of the present disclosure, the at least two charge pump circuits include adjacent first and second charge pump circuits, in the first charge pump circuit, one end of a first capacitor is connected with a first switch tube, the other end of the first capacitor is coupled with one of the inverted clock signals, one end of a second capacitor is connected with a second switch tube, and the other end of the second capacitor is coupled with the other inverted clock signal; in the second charge pump circuit, one end of the first capacitor is connected with the first switch tube, the other end of the first capacitor is coupled with the other inverted clock signal, one end of the second capacitor is connected with the second switch tube, and the other end of the second capacitor is coupled with one of the inverted clock signals.

[0077] Figure 7 Two connected charge pump circuits in a charge pump system with multiple stage charge pumps are shown as follows, Figure 7 As shown, the charge pump system includes a first charge pump circuit 702 and a second charge pump circuit 704, wherein V n is the input voltage of the first charge pump circuit 702, n+1 is the output voltage of the first charge pump circuit 702 and the input voltage of the second charge pump circuit 704, n+2 is the output voltage of the second charge pump circuit 704.

[0078] In some embodiments, in the first charge pump circuit 702, one end of the first capacitor C1-1 is connected with the first switch tube MP1, the other end of the first capacitor C1-1 is coupled with the first clock signal CLKB, one end of the second capacitor C2-1 is connected with the second switch tube MP2, the other end of the second capacitor C2-1 is coupled with the second clock signal CLK, there is a first connection point na3g between the first capacitor C1-1 and the first switch tube MP1, the first capacitor C1-1 is used for voltage stabilization of the first connection point na3g, there is a second connection point na4g between the second capacitor C2-1 and the second switch tube MP2, the second capacitor C2-1 is used for voltage stabilization of the second connection point na4g, one end of the third capacitor C3-1 is connected with the first control end na3, the other end of the third capacitor C3-1 is coupled with the first clock signal CLKB, one end of the fourth capacitor C4-1 is connected with the second control end na4, the other end of the fourth capacitor C4-1 is coupled with the second clock signal CLK, the gate of the first switch tube MP1 is connected with the first connection point na3g, the gate of the second switch tube MP2 is connected with the second connection point na4g, the source of the first switch tube MP1, the drain of the third switch tube MP3 and the gate of the fourth switch tube MP4 are connected with the first control end na3, the source of the second switch tube MP2, the drain of the fourth switch tube MP4 and the gate of the third switch tube MP3 are connected with the second control end na4. The first clamping circuit CLAMP1 is arranged between the first connection point na3g and the first control end na3, and the second clamping circuit CLAMP2 is arranged between the second connection point na4g and the second control end na4.

[0079] In some embodiments, in the second charge pump circuit 704, one end of the first capacitor C1-2 is connected with the first switch tube MP5, the other end of the first capacitor C1-2 is coupled with the second clock signal CLK, one end of the second capacitor C2-2 is connected with the second switch tube MP6, the other end of the second capacitor C2-2 is coupled with the first clock signal CLKB, there is a first connection point na5g between the first capacitor C1-2 and the first switch tube MP5, the first capacitor C1-2 is used for voltage stabilization of the first connection point na5g, there is a second connection point na6g between the second capacitor C2-2 and the second switch tube MP6, the second capacitor C2-2 is used for voltage stabilization of the second connection point na6g, one end of the third capacitor C3-2 is connected with the first control end na5, the other end of the third capacitor C3-2 is coupled with the second clock signal CLK, one end of the fourth capacitor C4-2 is connected with the second control end na6, the other end of the fourth capacitor C4-2 is coupled with the first clock signal CLKB, the gate of the first switch tube MP5 is connected with the first connection point na5g, the gate of the second switch tube MP6 is connected with the second connection point na6g, the source of the first switch tube MP5, the drain of the third switch tube MP7 and the gate of the fourth switch tube MP8 are connected with the first control end na5, the source of the second switch tube MP6, the drain of the fourth switch tube MP8 and the gate of the third switch tube MP7 are connected with the second control end na6, the first clamping circuit CLAMP3 is arranged between the first connection point na5g and the first control end na5, and the second clamping circuit CLAMP4 is arranged between the second connection point na6g and the second control end na6.

[0080] When the first clock signal CLKB is low, MP4 and MP6 are turned on, the voltage of the second control end na4 connected with MP4 is pulled up, and the charge flows from MP4 to MP6 through the node V n+1 In the process, the voltage of the first connection point na3g and the first control end na3 is clamped by the first clamping circuit CLAMP1 to prevent the voltage difference between the first connection point na3g and the first control end na3 from being too large. In addition, since the gate of MP5 has no path, the voltage is not strong in determinacy. The voltage of the first connection point na5g is pulled up by the first clamping circuit CLAMP3 to prevent the voltage of the first connection point na5g from being too low and MP5 from being turned on to flow back.

[0081] In one embodiment of the present disclosure, in a charge pump system with a multi-stage charge pump circuit, a plurality of first capacitors in the multi-stage charge pump circuit are connected to the same clock generator, a plurality of second capacitors are connected to the same clock generator, a plurality of third capacitors are connected to the same clock generator, and a plurality of fourth capacitors are connected to the same clock generator.

[0082] In the first charge pump circuit, the first capacitor and the third capacitor are connected to clock signals of the same phase, the second capacitor and the fourth capacitor are connected to clock signals of the same phase, the clock signals of the second capacitor and the fourth capacitor are output by two clock generators, and the clock signals of the first capacitor and the third capacitor are output by two clock generators, that is, four clock generators are arranged in the first charge pump circuit, and in the charge pump system with multiple charge pump circuits, the four clock generators are respectively coupled to each charge pump circuit to input corresponding clock signals to the multiple charge pump circuits.

[0083] Figure 8 A functional block diagram of the memory 80 according to one embodiment of the present disclosure is shown.

[0084] As shown in Figure 8 The memory 80 is, for example, a non-volatile memory such as a flash memory. The memory 80 includes a controller 802, a charge pump circuit 804, a memory cell array 806, a row selector 808, and a column selector 810. The memory cell array 806 includes a plurality of memory cells, which are addressed by word lines and bit lines. The row selector 808 is configured to select a target word line according to an address. The column selector 810 is configured to select a target bit line according to an address. The controller is configured to control operations such as read, write, and erase operations for the memory cell array 806. The charge pump circuit 804 is configured to provide operating voltages for the above-mentioned operations, and the charge pump circuit 804 can be any of the charge pump circuits described in the above embodiments. When the memory 80 is a NAND flash memory, the charge pump circuit 804 can provide a program voltage provided to a target word line in a write operation, and can also provide a pass voltage provided to a non-target word line in a verify operation, both of which are positive voltages, and the program voltage is greater than the pass voltage. When the memory 80 is a NOR flash memory, the charge pump circuit 804 can provide a negative high voltage provided to a target word line in an erase operation, and can also provide a negative low voltage provided to a non-target word line in a verify operation.

[0085] In the charge pump circuit and the memory in the present disclosure, by arranging a capacitor for voltage stabilization and a clamping circuit in the charge pump circuit, the influence of the substrate bias effect of the switch tube on the threshold voltage of the switch tube is reduced while the manufacturing cost is reduced, and the influence of the voltage fluctuation on the signal line on the conduction characteristics of the first switch tube and the second switch tube during the charge transfer process is prevented, thereby facilitating the improvement of the transfer efficiency and the voltage resistance of the charge pump circuit.

[0086] It should be noted that the above-described diagrams are only schematic illustrations of processes included in the method according to the exemplary embodiments of the present disclosure, and are not intended for limiting purposes. It is easily understood that the processes shown in the above-described diagrams do not indicate or limit the time sequence of the processes. In addition, it is also easily understood that the processes can be executed synchronously or asynchronously, for example, in a plurality of modules.

[0087] Those skilled in the art can understand that various aspects of the present disclosure can be implemented as a system, a method or a program product. Therefore, various aspects of the present disclosure can be embodied in the form of a complete hardware, a complete software (including firmware, microcode, etc.), or a combination of hardware and software aspects, which can be collectively referred to as "circuitry", "module" or "system" herein.

[0088] In the present disclosure, the terms "first", "second", "third" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance; the term "multiple" refers to two or more, unless otherwise explicitly limited. The terms "mounting", "connecting", "connecting", "fixing" and the like should be interpreted broadly, for example, "connecting" can be fixed connection, or detachable connection, or integrally connected; "connected" can be directly connected, or indirectly connected through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0089] In the description of the present disclosure, it should be understood that the terms "upper", "lower", "left", "right", "front", "back" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or units referred to must have a particular direction, be constructed and operated in a particular orientation, therefore, cannot be understood as a limitation on the present disclosure.

[0090] In the description of the present disclosure, the description of the terms "one embodiment", "some embodiments", "a specific embodiment" and the like means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0091] The above merely provides preferred embodiments of the present disclosure but is not intended to limit the present disclosure. The present disclosure can have various modifications and variations. Any modified, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the specification and practicing the present disclosure. The present disclosure is intended to cover any variations, uses, or adaptive changes of the present disclosure following the general principles of the present disclosure and including common knowledge or conventional technical means in the technical field of the present disclosure not disclosed by the present disclosure. The specification and embodiments are merely regarded as exemplary, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A charge pump circuit, characterized by, The application relates to a charge pump circuit. The switch unit comprises a first switch tube and a second switch tube, and the first switch tube and the second switch tube are respectively connected to control ends; the first switch tube and the second switch tube are PMOS tubes, or the first switch tube and the second switch tube are NMOS tubes. The clock unit comprises a clock generator outputting reverse clock signals. The capacitor unit comprises a first capacitor and a second capacitor; one end of the first capacitor is connected to the first switch tube; the other end of the first capacitor is coupled to one of the reverse clock signals; one end of the second capacitor is connected to the second switch tube; the other end of the second capacitor is coupled to the other reverse clock signal; the first capacitor and the first switch tube have a first connection point; the first capacitor is used for stabilizing voltage of the first connection point; the second capacitor and the second switch tube have a second connection point; and the second capacitor is used for stabilizing voltage of the second connection point.

2. The charge pump circuit of claim 1, wherein, The application further relates to a charge pump circuit. The clamp unit comprises a first clamp circuit and a second clamp circuit; one end of the first clamp circuit is connected to the first connection point and used for clamping voltage of the first connection point; one end of the second clamp circuit is connected to the second connection point and used for clamping voltage of the second connection point.

3. The charge pump circuit according to claim 2, wherein The control ends comprise a first control end and a second control end; The capacitor unit further comprises a third capacitor and a fourth capacitor; one end of the third capacitor is connected to the first control end; the other end of the third capacitor is coupled to one of the reverse clock signals; one end of the fourth capacitor is connected to the second control end; and the other end of the fourth capacitor is coupled to the other reverse clock signal.

4. The charge pump circuit according to claim 3, wherein The other end of the first clamp circuit is connected to the first control end; and the other end of the second clamp circuit is connected to the second control end.

5. The charge pump circuit of claim 3, wherein, The switch unit further comprises a third switch tube and a fourth switch tube; The gate of the first switch tube is connected to the first connection point; The gate of the second switch tube is connected to the second connection point; The source of the first switch tube, the drain of the third switch tube and the gate of the fourth switch tube are connected to the first control end; The source of the second switch tube, the drain of the fourth switch tube and the gate of the third switch tube are connected to the second control end.

6. The charge pump circuit of claim 5, wherein, The charge pump circuit further comprises an input end and an output end; The drain of the first switch tube and the drain of the second switch tube are connected to the input end; The source of the third switch tube and the source of the fourth switch tube are connected to the output end.

7. The charge pump circuit according to claim 5, wherein The third switch tube and the fourth switch tube are PMOS tubes.

8. The charge pump circuit of claim 2, wherein, The reverse clock signals comprise a first clock signal and a second clock signal; the first capacitor is connected to the first clock signal; and the second capacitor is connected to the second clock signal. The first switch is turned on when the first clock signal is low, and the first clamping circuit is used to clamp the voltage of the first connection point upward, The second switch is turned off when the second clock signal is high, and the second clamping circuit is used to clamp the voltage of the second connection point downward.

9. The charge pump circuit of claim 2, wherein, The reverse clock signal includes a first clock signal and a second clock signal, the first capacitor is connected to the second clock signal, and the second capacitor is connected to the first clock signal, The first switch is turned off when the second clock signal is high, and the first clamping circuit is used to clamp the voltage of the first connection point downward, The second switch is turned on when the first clock signal is low, and the second clamping circuit is used to clamp the voltage of the second connection point upward.

10. The charge pump circuit of any one of claims 2 to 9, wherein, The first clamping circuit or the second clamping circuit includes: A first diode and a second diode are connected in parallel, and the first diode and the second diode are reversely arranged.

11. A charge pump system, characterized by, It includes: At least two charge pump circuits as claimed in any one of claims 1 to 10, and at least two charge pump circuits are connected in series.

12. The charge pump system of claim 11, wherein, At least two charge pump circuits include a first charge pump and at least one cascaded secondary charge pump, Wherein, the first switch and the second switch in the first charge pump are PMOS or NMOS, and the first switch and the second switch in the secondary charge pump are PMOS.

13. The charge pump system of claim 11, wherein, At least two charge pump circuits include adjacent first and second charge pumps, In the first charge pump, one end of a first capacitor is connected to a first switch, the other end of the first capacitor is coupled to one of the reverse clock signals, one end of a second capacitor is connected to a second switch, and the other end of the second capacitor is coupled to the other of the reverse clock signals; In the second charge pump, one end of the first capacitor is connected to the first switch, the other end of the first capacitor is coupled to the other of the reverse clock signals, one end of the second capacitor is connected to the second switch, and the other end of the second capacitor is coupled to one of the reverse clock signals.

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