Three-phase converter control method, system, medium and equipment

Abstract

The invention relates to the technical field of converters, in particular to a three-phase converter control method and system, a medium and equipment. The method comprises the steps that a main processor transmits sampling original data of a three-phase converter to a first storage area; the coprocessor reads the sampled original data, performs operation to obtain operation result data, and transmits the operation result data to the second storage area; the coprocessor runs at a period higher than the preset control frequency of the main processor, and immediately triggers the operation of the sampled original data after completing the collection of the sampled original data; the main processor performs control loop calculation, reads the operation result data when the newest operation result data is needed, and loads the newest operation result data for updating operation; the main processor runs the control program at the preset control frequency, and the control program triggering time is set in a minimum allowable time window before the control output quantity loading moment. Through the above arrangement, real-time sampling is effectively realized, CPU load is optimized, and the control performance of the converter is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of current transformer, in particular to a three-phase current transformer control method, system, medium and equipment. BACKGROUND

[0002] With the rapid development of power electronics technology, high-power three-phase current transformer as the core device of power conversion is increasingly widely used in industrial transmission, power storage, new energy power generation, power transformation, power distribution and other fields. Its control performance directly affects the efficiency, stability and dynamic response ability of the system. In recent years, the update iteration of power electronic semiconductor devices has significantly improved the switching frequency, although it has reduced the design cost of magnetic devices and filters, but it has put higher requirements on the operation performance of digital controllers - higher switching frequency requires shorter control period, and the operation ability of traditional single-processor architecture has been difficult to meet the real-time requirements in high-frequency control scenarios.

[0003] To solve this problem, the hardware architecture of the digital controller gradually develops towards the direction of multiple operation cores (such as multi-core chips integrating multiple control law accelerators CLA), which is an important way to improve the control frequency by sharing the calculation tasks of different operation cores. For the double-loop control of high-power three-phase PWM current transformer (usually including voltage outer loop and current inner loop), its control logic involves complex operations such as phase-locked loop calculation and coordinate transformation, which takes a long time to calculate, and needs to be optimized by hardware architecture to reduce the operation load of the controller. The existing technology proposes some solutions, for example, patent CN117175965A discloses a double-loop control timing optimization method for AC / DC microgrid current transformer, which uses CPU+CLA chip with CLA to deploy outer loop control, feedforward and active damping calculation in CLA to reduce the operation load of CPU; patent CN110568781A proposes a double-CPU+double-CLA chip solution, which shares the operation load through SDRAM interaction. However, the existing solutions have the following shortcomings: on the one hand, they are strongly dependent on specific chips (such as processors with CLA), which limits the universality of the technology. On the other hand, the control response speed and accuracy are still limited by the update lag of the sampling data.

[0004] Therefore, how to design a current transformer control scheme that does not depend on specific chips, can effectively solve the update lag of sampling data and optimize the CPU load, has become a technical problem to be solved in the field. SUMMARY

[0005] To solve at least one of the deficiencies of the existing three-phase current transformer control scheme, the embodiments of the present application provide a three-phase current transformer control method, system, medium and equipment to effectively realize instant sampling, thereby improving the performance of the controller and optimizing the CPU load.

[0006] In a first aspect, the three-phase converter control method provided by the embodiments of the present application comprises the following steps: The main processor transmits the sampling raw data of the three-phase converter to the first storage area; The coprocessor reads the sampling raw data in the first storage area and performs coordinate transformation and phase-locked loop operation to obtain operation result data, and transmits the operation result data to the second storage area; wherein the coprocessor runs at a frequency higher than the preset control frequency of the main processor, and triggers the operation of the sampling raw data immediately after the collection of the sampling raw data is completed; The main processor performs control loop calculation, reads the operation result data in the second storage area when the latest operation result data is needed, and loads the latest operation result data for update operation to obtain control output after other operations are completed; wherein the main processor runs the control program at the preset control frequency, and the control program trigger time is set within the minimum allowable time window before the loading time of the control output.

[0007] In some embodiments, the main processor further writes sampling zero offset setting parameters and coefficient correction parameters to the third storage area, and the coprocessor reads the sampling zero offset setting parameters and coefficient correction parameters and applies them to the operation of the sampling raw data.

[0008] In some embodiments, the first storage area is configured to be readable and writable by the main processor and readable only by the coprocessor; the second storage area is configured to be readable and writable by the coprocessor and readable only by the main processor; the third storage area is configured to be readable and writable by the main processor and readable only by the coprocessor, and the first storage area, the second storage area and the third storage area are independent partitions in a shared memory.

[0009] In some embodiments, the running frequency of the coprocessor is more than 4 times the preset control frequency of the main processor, and the control period of the main processor is consistent with the switching period of the main power device of the three-phase converter.

[0010] In some embodiments, the control loop calculation comprises current loop control and voltage loop control; the current loop control calculates voltage reference values based on d-axis and q-axis current components in the operation result data through a PI regulator; and the voltage loop control optimizes the current loop output through feedforward compensation or decoupling control based on DC bus voltage or grid voltage components in the operation result data.

[0011] In some embodiments, the PI regulator in the current loop control and the voltage loop control adopts a difference equation form of a discrete transfer function, and is further modified into a difference equation form, and the difference equation satisfies:

[0012] Where, is the difference between the current cycle output and the previous cycle output of the PI controller, , , is the proportional coefficient of the PI controller, is the integral coefficient of the PI controller, For the control cycle of the main processor, is the input deviation of the PI controller in the current cycle, is the input deviation of the PI controller in the previous cycle.

[0013] In some embodiments, the voltage reference value includes a d-axis reference voltage and q-axis reference voltage ; No. The d-axis reference voltage at time The calculation formula is as follows:

[0014]

[0015]

[0016]

[0017]

[0018] Where, is the d-axis grid voltage, 、 、 Respectively Time, Time, The bus voltage error at the moment; 、 Respectively Time, The d-axis current component error of the inductor current at time t; is the inductance of the filter inductor; is the grid voltage angular frequency; is the q-axis component of the three-phase inductor current at the nth moment; 、 、 、 Respectively Moment The first voltage value, the second voltage value, the third voltage value, and the fourth voltage value of the item; 、 、 、 Based on the DC voltage loop PI parameters 、 and d-axis current loop PI parameters 、 The coefficient of , , , ; No. The q-axis reference voltage at time The calculation formula is as follows:

[0019]

[0020]

[0021]

[0022] Where, is the d-axis grid voltage, 、 Respectively Time, The q-axis current component error of the inductor current at time ; is the inductance of the filter inductor; is the grid voltage angular frequency; The three-phase inductor current The d-axis component of the moment; 、 、 、 Respectively time The first voltage value, the second voltage value, the third voltage value, and the fourth voltage value of the item; 、 Based on the q-axis current loop PI parameters 、 The coefficient of , .

[0023] In a second aspect, an embodiment of the present invention further provides a three-phase converter control system, comprising: a main processor, a coprocessor, a first storage area, and a second storage area that are communicatively connected; The main processor is configured to transmit the sampling raw data of the three-phase converter to a first storage area, run a control program at a preset control frequency, and perform control loop calculation, read the operation result data in the second storage area when the latest operation result data is needed, and load the latest operation result data for update operation to obtain a control output after other operations are completed; and a trigger time of the control program of the main processor is set within a minimum allowable time window before a loading time of the control output. The coprocessor is configured to read the sampling raw data in the first storage area, perform coordinate transformation and phase-locked loop operation to obtain operation result data, and transmit the operation result data to the second storage area; the coprocessor is configured to run at a period higher than the preset control frequency of the main processor, and is configured to trigger the operation of the sampling raw data immediately after the collection of the sampling raw data is completed.

[0024] In a third aspect, a computer readable storage medium is provided, and the computer readable storage medium stores computer instructions. When the computer instructions are executed by a processor, the three-phase converter control method according to any one of the embodiments of the first aspect is implemented.

[0025] In a fourth aspect, an electronic device is provided, and the electronic device includes at least one processor and a memory connected to the processor in communication. The memory stores instructions executable by the at least one processor. The instructions are executed by the at least one processor to cause the processor to perform the three-phase converter control method according to any one of the embodiments of the first aspect.

[0026] Compared with the prior art, the three-phase converter control method provided by the embodiments of the present application has the following advantages: 1. By sharing the processing of the main processor and the coprocessor, the data processing link can be separated from the main processor, the operation burden and the occupation time of the main processor can be significantly reduced, the demand of the control performance of the controller for the switching frequency of the power electronic device is met, and the application of new energy power generation, power transformation and power distribution with higher control frequency is adapted. 2. The coprocessor triggers the operation immediately after the sampling is completed, which avoids the lag of the sampling data waiting for processing in the traditional single-processor architecture. Meanwhile, the trigger time of the control program of the main processor is set within a minimum allowable time window before the loading time of the control output, and the operation result of the coprocessor is read only when the latest operation result data is needed, so that the sampling delay and the control delay are maximally shortened. 3. By using the design of the first storage area and the second storage area, the main processor and the coprocessor realize efficient data interaction, the data flow is clear, the memory access conflict is avoided, the mutual interference is reduced, and the reliability is further improved. 4. The general cooperative architecture of the main processor and the coprocessor is adopted, and the hardware characteristics of specific chips (such as special chips with CLA) are not relied on; performance optimization is realized through task allocation and timing design at the software level, and the technical solution is suitable for various digital controllers with multi-core operation capability, thereby widening the application scenarios of the technical solution and reducing the dependence cost of specific hardware.

[0027] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor; in the following description, the positional relationship described in the drawings is the direction of the components drawn in the drawings as the reference, unless otherwise specified.

[0029] Figure 1 、 Figure 2 The structural block diagram of the three-phase converter control method provided by an embodiment of the present application is shown in the figure. Figure 3 The running flowchart of the three-phase converter, the main processor, the coprocessor and the shared memory is shown in the figure. Figures 4~6 The running flowchart of the main processor, the coprocessor and the shared memory in different variants is shown in the figure. Figure 7 The schematic diagram of the switching cycle, the acquisition cycle and the processing timing of the main processor and the coprocessor of the three-phase converter control method provided by an embodiment of the present application is shown in the figure. Figure 8 The three-phase converter control loop schematic diagram using the PI controller is shown in the figure. Figure 9 The loop control schematic diagram after reorganization is shown in the figure. Figure 10 The structural block diagram of the electronic device provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0030] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application; as long as there is no conflict, the technical features designed in the different implementation manners described below can be combined with each other; based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0031] In the description of the present application, it should be noted that all the terms (including technical terms and scientific terms) used in the present application have the same meanings as those generally understood by a person of ordinary skill in the art to which the present application belongs, and should not be understood as a limitation on the present application; it should be further understood that the terms used in the present application should be understood as having meanings consistent with the meanings of these terms in the context of the present specification and the related art, and should not be understood in an idealized or overly formal sense, unless defined explicitly in the present application.

[0032] At present, the operation ability of the traditional single-processor architecture has been difficult to meet the real-time requirements of the three-phase converter in the high-frequency control scene; and the multi-operation core architecture adopted in the prior art has strong dependence on a specific chip (such as a processor with CLA), which limits the universality of the technology; on the other hand, the control response speed and accuracy are still limited by the update lag of the sampling data due to the sampling delay, which greatly restricts the control performance of the three-phase converter.

[0033] Based on the above problems, the embodiments of the present application provide a three-phase converter control method, system, medium and equipment, which aims to optimize the control timing and operation process through the cooperative work of the main processor and the coprocessor, reduce the load of the main processor and shorten the control delay, and adapt to higher control frequency requirements.

[0034] The three-phase converter control method, system, medium and equipment will be described and introduced in detail below with reference to the specific embodiments and the drawings.

[0035] Embodiment one Please refer to Figure 1 The three-phase converter control method provided by an embodiment of the present application at least includes the following steps: The main processor transmits the sampling original data of the three-phase converter to the first storage area; The coprocessor reads the sampling raw data of the first storage area and performs coordinate transformation and phase-locked loop operation to obtain operation result data, and transmits the operation result data to the second storage area; wherein, the coprocessor runs at a period higher than the preset control frequency of the main processor, and triggers the operation of the sampling raw data immediately after the collection of the sampling raw data is completed; The main processor performs control loop calculation, reads the operation result data of the second storage area when the latest operation result data is needed, and loads the latest operation result data for update operation to obtain control output after other operations are completed; wherein, the main processor runs the control program at the preset control frequency, and the control program trigger time is set within the minimum allowed time window before the loading time of the control output.

[0036] The main processor can adopt a microprocessor (such as DSP or MCU) with high performance operation capability, mainly responsible for control loop calculation (such as current loop and voltage loop regulation), event diagnosis, and complex logic function processing, and runs the control program at a preset control frequency. The main processor is integrated in the main control chip. In this embodiment, the control period of the main processor is consistent with the switching period of the main power device of the three-phase converter.

[0037] Preferably, referring to Figure 3 , the main control chip further includes a TIMER module, an ADC module, and a DMA module. The TIMER module is used to generate and drive pulse control signals, and generate control program trigger signals and sampling trigger signals. The switching frequency is , the frequency of the sampling trigger signal is In order to fully utilize the operation capability of the coprocessor, in this embodiment, the , is preferably 4, 8, or 16. The control output obtained by the main processor through the control loop will be used to update the TIMER module and generate control pulses. The ADC module includes an analog-to-digital converter. The sampling trigger signal generated by the TIMER module is output to the ADC module to trigger the ADC module to sample. At the same time, the ADC module triggers a sampling completion signal and transmits it to the main processor when the sampling is completed. The DMA module is used to respond to the sampling completion signal output by the ADC module, and to move the sampling raw data to the first storage area.

[0038] The coprocessor adopts an auxiliary operation core compatible with the main processor. The coprocessor can be integrated on an independent coprocessor chip or on the same main control chip as the main processor. It focuses on sampling data processing and does not participate in control decision or external event response, and independently runs at a period at least 4 times higher than the preset control frequency of the main processor.

[0039] The first storage area and the second storage area can be integrated in the same memory or different memories, and can be integrated in independent chips or integrated in a master chip. The first storage area is used for storing the sampling raw data transmitted by the main processor, and the second storage area is used for storing the operation result data of the coprocessor.

[0040] Preferably, referring to Figure 2 , the three-phase converter control method further comprises the following steps: the main processor writes the sampling zero offset setting parameters and the coefficient correction parameters into the third storage area, and the coprocessor reads the sampling zero offset setting parameters and the coefficient correction parameters and applies them to the operation of the sampling raw data.

[0041] Preferably, the first storage area is configured to be readable and writable by the main processor and readable only by the coprocessor, the second storage area is configured to be readable and writable by the coprocessor and readable only by the main processor, the third storage area is configured to be readable and writable by the main processor and readable only by the coprocessor, and the first storage area, the second storage area and the third storage area are independent partitions in a shared memory.

[0042] The integration mode of the main processor, the shared memory and the coprocessor can be various, which is not limited in the embodiment. As an example, as shown in Figure 3 , the main processor is integrated on a master chip, the coprocessor is integrated on a coprocessor chip, and the shared memory is independently integrated; as shown in Figure 4 , the main processor and the shared memory are integrated on a master chip, and the coprocessor is integrated on a coprocessor chip; as shown in Figure 5 , the main processor, the shared memory and the coprocessor are integrated on the same master chip; as shown in Figure 6 , the main processor is integrated on a master chip, and the coprocessor and the shared memory are integrated on a coprocessor chip.

[0043] In the embodiment, the main processor can collect the original signals (such as three-phase grid voltage, inductor current and DC bus voltage) of the three-phase converter through the ADC module, and transmit the unprocessed sampling raw data (such as three-phase voltage instantaneous value and three-phase current instantaneous value) to the first storage area in real time. The transmission process is completed through the memory access instruction of the main processor, so as to ensure the timeliness of data update.

[0044] Preferably, the running frequency of the coprocessor is more than 4 times of the preset control frequency of the main processor. That is, the coprocessor runs at a period of more than 4 times of the preset control frequency of the main processor (for example, when the control frequency of the main processor is 10 kHz, the running frequency of the coprocessor is not less than 40 kHz), and triggers operation immediately after the ADC module completes each sampling (achieved by hardware interruption or timer synchronization). The specific process includes: reading the latest sampling raw data from the first storage area; pre-processing the sampling raw data, applying the sampling zero offset setting parameters and coefficient correction parameters (such as eliminating current sensor zero drift, calibrating voltage sampling gain) of the third storage area; then performing coordinate transformation to convert the voltage and current signals in the three-phase static coordinate system (abc) into components in the two-phase rotating coordinate system (d-axis, q-axis) (specifically, obtained by Clarke transformation and Park transformation); then, performing phase-locked loop operation to calculate the grid synchronous phase θ and frequency f based on the grid voltage signal, providing a synchronous reference for coordinate transformation; finally, writing the operation result data into the second storage area to overwrite the old data to ensure the beat consistency when the main processor reads the operation result data.

[0045] The main processor runs the control program at a preset control frequency, and the trigger time of the control program is accurately set in the minimum allowed time window before the control output quantity loading time (for example, 5-10 μs in advance, which is determined according to the operation speed of the main processor) by a timer, so as to shorten the control delay. The control period of the main processor is consistent with the switching period of the main power device of the converter in this embodiment. The specific process of the control loop calculation of the main processor includes: Control loop calculation preparation: the main processor first performs operation without the latest operation result data (such as temporary storage of the control quantity of the previous period, packaging of communication data, etc.); Reading the latest operation result: when entering the key control loop calculation (such as current loop PI regulation), the operation result data output by the coprocessor is read from the second storage area; Update operation and control quantity generation: the main processor substitutes the read latest operation result data into the control loop to perform voltage loop calculation and current loop calculation; and introduces inductance L and grid angular frequency ω for cross-coupling compensation to eliminate the coupling interference of d-axis and q-axis components; Output control quantity: the main processor loads the finally calculated control output quantity (such as PWM duty cycle signal) to the driving circuit through the timer to control the switching state of the three-phase converter main power device.

[0046] The present application realizes instant sampling and efficient control of the three-phase converter through the timing coordination design of the main processor and the coprocessor. In the above control process, the sampling delay and control delay are effectively optimized by designing the trigger time of the control program of the main processor and the running calculation trigger time of the coprocessor. The followingFigure 7 The timing setting is described in detail. Assuming that the switching period of the main power device of the three-phase inverter is , and the control period of the main processor is consistent with the switching period, the preset control frequency of the main processor is (such as s At this time, ). Assuming that the operation period of the coprocessor is , the operation frequency of the coprocessor is 4 times (such as ) of the preset control frequency of the main processor At this time, , that is , thereby ensuring that the coprocessor can complete the processing of multiple sampling data in one control period of the main processor. At the same time, the operation trigger time of the coprocessor is closely related to the sampling of the ADC module, and the instant trigger timing of the coprocessor is: when the ADC module collects three-phase voltage, current and other sampling raw data with as the period, the coprocessor is triggered to start operation immediately after the collection is completed (wherein represents the trigger time of the coprocessor for operating the sampling raw data), avoiding the retention of sampling data. Further, the embodiment preferably controls the operation time of the coprocessor to be within 1 / 2 of (such as ≤12.5μs) when the operation of the sampling raw data is triggered, and saves the operation result data in the second storage area, ensuring that the data read by the main processor is the latest value.

[0047] The main processor runs the control program with as the period, and sets the trigger time of the control program as . The trigger time is accurately set in the minimum allowed time window before the load duty moment (LoadDuty). For example, if the main processor needs 50μs to complete the control loop calculation, then is set at 50~60μs before LoadDuty (for example, no more than 1.2 times of the calculation time), ensuring that the calculation result is ready before loading. At the same time, the main processor only reads the operation result of the second storage area in the control loop calculation when the latest operation result data is needed (such as the current loop and voltage loop adjustment stage), and preferentially executes tasks that do not require real-time data (such as other data processing or calculation processing, etc.) before, reducing the data waiting time. Moreover, the control output (such as the PWM duty ratio) is loaded into the drive circuit at the LoadDuty moment, at which time the main processor has completed the update operation of the latest operation result data, ensuring that the output matches the current state of the system. Through the above timing setting, on the one hand, the sampling delay ) optimization, i.e. the time interval from the sampling completion of the ADC module to the reading of the operation result data by the main processor in the embodiment is ≤ / 4, as , . On the other hand, the optimization of the control delay (T ) is also effectively realized, i.e. the time interval from the completion of the control loop calculation by the main processor to the loading of the duty is ≤ / 4, avoiding the lag of the control decision and the actual working condition.

[0048] As shown in Figure 7 , in the embodiment, the loading time of the control output quantity is located at the carrier peak value of , the trigger time of the control program is triggered at somewhere of the rising edge of the carrier of , and the trigger time of the control degree in the embodiment is preferably , i.e. the trigger time of the control program is relatively close to the loading time, so that the loading can be performed as soon as possible after the completion of the loop calculation, which helps to reduce the control delay. The operation trigger time of the coprocessor is triggered at the zero value after the completion of .

[0049] That is, the high-frequency and instant operation of the coprocessor and the accurate trigger control of the main processor form a timing closed loop: in one control cycle of the main processor, the coprocessor can complete more than 4 times of sampling data processing, the main processor reads the latest result as needed, realizes the seamless connection of "sampling-processing-control", improves the control frequency, and ensures the timeliness of the sampling data, which is suitable for new energy power scenarios such as high-power three-phase PWM converters which have high requirements on dynamic response.

[0050] In an embodiment, the control loop calculation includes current loop control and voltage loop control; the current loop control is based on the d-axis and q-axis current components in the operation result data, and the voltage reference value is calculated through a PI regulator; and the voltage loop control is based on the DC bus voltage or grid voltage component in the operation result data, and the current loop output is optimized through feedforward compensation or decoupling control.

[0051] Based on the above, the main purpose of the operation flow optimization of the converter in the embodiment is to concentrate the update position of the operation result data in the loop control, and to update and operate after the completion of other calculation operations, so as to optimize the operation processing speed under the cooperation of the dual processors and realize instant sampling. Therefore, the operation formula of the control loop is also optimized in the embodiment, and the PI controller is expressed by a discrete transfer function and is further transformed into a difference equation form to facilitate the loading and update operation of the latest operation result data.

[0052] Please refer to Figure 8Fig. 1 is a schematic diagram of a three-phase inverter control loop using PI controller, where the input of the loop is bus reference voltage , bus voltage , , , , , , , and finally the reference port voltage , and the modulation duty cycle are obtained by coordinate transformation and modulation.

[0053] Specifically, the PI regulator in the current loop control and the voltage loop control adopts the difference equation form of the discrete transfer function, and the PI controller in the discrete case (using backward difference method) is as follows:

[0054] In the formula, is the discrete transfer function; is the PI controller output; is the PI controller input, generally the difference between the command and the feedback; is the proportional coefficient, is the integral coefficient, is the control period, is the discrete transformation operator.

[0055] The formula is further modified into the difference equation form to facilitate calculation:

[0056] Introducing , , , the difference equation is obtained as follows:

[0057] In the formula, is the difference between the current period output and the last period output of the PI controller, is the proportional coefficient of the PI controller, is the integral coefficient of the PI controller, is the control period of the main processor, is the input deviation of the PI controller in the current period, is the input deviation of the PI controller in the last period.

[0058] Then, the original PI link in the loop is changed to the transfer function representation, and after reorganization, the following is obtained: Figure 9The rearranged loop control diagram is shown in Figure 1, where the discrete transfer function is expressed as:

[0059]

[0060]

[0061] Where, 、 、 They represent the discrete transfer functions of the bus voltage loop, d-axis current loop, and q-axis current loop respectively; 、 、 Respectively represent the proportional coefficients of the bus voltage loop, d-axis current loop, and q-axis current loop; 、 、 They represent the integral coefficients of the bus voltage loop, d-axis current loop, and q-axis current loop respectively.

[0062] Another, and The voltage reference values ​​are summed up for Item, and use 、 、 replace Figure 9 The corresponding position in the block diagram can be obtained as follows:

[0063]

[0064]

[0065]

[0066] =

[0067]

[0068]

[0069]

[0070]

[0071] Finally, the voltage reference value is expressed in the form of a differential equation, and the voltage reference value includes the d-axis reference voltage and q-axis reference voltage ; Based on the real-time acquisition sequence, The d-axis reference voltage at time The calculation formula is as follows:

[0072]

[0073]

[0074]

[0075]

[0076] Where, is the d-axis grid voltage, 、 、 Respectively Time, Time, The bus voltage error at the moment; 、 Respectively Time, The d-axis current component error of the inductor current at time t; is the inductance of the filter inductor; is the grid voltage angular frequency; is the q-axis component of the three-phase inductor current at the nth moment; 、 、 、 Respectively Moment The first voltage value, the second voltage value, the third voltage value, and the fourth voltage value of the item; 、 、 、 Based on the DC voltage loop PI parameters 、 and d-axis current loop PI parameters 、 The coefficient of , , ， ; No. The q-axis reference voltage at time The calculation formula is as follows:

[0077]

[0078]

[0079]

[0080] In the formula, is a d-axis grid voltage, , is a first time, a second time inductive current q-axis current component error; is a filter inductance; is a grid voltage angular frequency; is a three-phase inductive current d-axis component at a first time; , , , are a first voltage value, a second voltage value, a third voltage value, and a fourth voltage value of the first term at a first time, a second time; , are coefficients based on q-axis current loop PI parameters , , and , .

[0081] The embodiment can shorten the use time of each sampling value in the program as much as possible by modifying the loop in the above form, cooperate with the key timing design of the main processor, coprocessor, first storage area, and second storage area, and can immediately obtain the operation result data from the second storage area when the main processor needs the operation result data calculated by the coprocessor at last, realize immediate sampling, further shorten the control delay time, and be applicable to various power electronic control systems in different working conditions and different complexity.

[0082] Embodiment Two Please continue to refer to Figure 1 , the embodiment of the application further provides a three-phase converter control system, comprising: a main processor, a coprocessor, a first storage area, and a second storage area connected in communication; The main processor is configured to transmit the sampling original data of the three-phase converter to the first storage area, run a control program at a preset control frequency, and perform control loop calculation, read the operation result data of the second storage area when the latest operation result data is needed, and load the latest operation result data to perform update operation to obtain a control output after other operations are completed; the trigger time of the control program of the main processor is set in a minimum allowable time window before the loading time of the control output; The coprocessor is configured to read the sampling raw data of the first storage area, and perform coordinate transformation and phase-locked loop operation to obtain operation result data, and transmit the operation result data to the second storage area; the coprocessor is configured to run at a period higher than the preset control frequency of the main processor, and is configured to trigger the operation of the sampling raw data immediately after the collection of the sampling raw data is completed.

[0083] Similarly, the main processor, the coprocessor, and the first storage area and the second storage area can be integrated in one or more chips to realize the functions, and the specific settings are made according to actual needs, which are not limited here.

[0084] It should be noted that the specific processing method and function of each module can be referred to the embodiment one, and will not be repeated here.

[0085] Embodiment three The embodiment of the application further provides a computer readable storage medium, which stores computer instructions, and the computer is executed by the processor to realize the three-phase converter control method of the embodiment one.

[0086] In specific implementation, the computer readable storage medium is a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), etc.; the computer readable storage medium can also include a combination of the above-mentioned types of memories.

[0087] Embodiment four Please refer to Figure 10 The embodiment of the application further provides an electronic device, which includes at least one processor and a memory connected with the processor in communication, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to make the processor execute the three-phase converter control method of the embodiment one.

[0088] In practice, the number of processors can be one or more, and the processor can be a central processing unit (CPU). The processor can also be other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or a combination thereof. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0089] The memory and the processor can be connected by a bus or other means, and the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the processor to perform the three-phase converter control method as described in the above embodiment one.

[0090] In summary, the three-phase converter control method, system, medium and device provided by the embodiment of the application have the following advantages: 1. By sharing the processing of the main processor and the coprocessor, the data processing link can be separated from the main processor, significantly reducing the computational burden and occupation time of the main processor; meeting the demand of the controller operation performance for the switching frequency improvement of power electronic devices, thereby adapting to higher control frequency of new energy power generation, power transformation and power distribution applications; 2. The coprocessor triggers operation immediately after sampling, avoiding the lag of waiting for processing of sampling data in the traditional single-processor architecture; at the same time, the main processor control program trigger time is set in the minimum allowable time window before the control output quantity loading time, and the operation result data of the coprocessor is read only when the latest operation result data is needed, which maximally shortens the sampling delay and control delay; this optimization enables the control loop to respond more quickly to system state changes, improving the dynamic control accuracy and stability of the three-phase converter; 3. By using the design of the first storage area and the second storage area, the main processor and the coprocessor realize efficient data interaction, and the data flow is clear, avoiding memory access conflicts; at the same time, the coprocessor is only responsible for data processing and does not participate in control loop decision and external event response, and the main processor focuses on core control logic, the function boundary of the two is clear, reducing mutual interference and improving the reliability of system operation.

[0091] 4. The general cooperative architecture of the main processor and the coprocessor is adopted, and the hardware characteristics of specific chips (such as special chips with CLA) are not relied on; performance optimization is realized through task allocation and timing design at the software level, and the technical solution is suitable for various digital controllers with multi-core operation capability, thereby widening the application scenarios of the technical solution and reducing the dependence cost of specific hardware; 5. The PI controller based on the difference equation is adopted in the control loop calculation of the main processor, the sampling value update position is centrally arranged, the latest operation result data is loaded after other operations are completed, and it is ensured that the latest operation result data is used in the calculation of the control output. In combination with the accurate coordinate transformation result and the phase-locked loop parameter provided by the coprocessor, the adjustment precision of the control loop is improved, which is helpful for the three-phase converter to realize more stable double-loop control (current loop and voltage loop), reduce harmonic distortion, and improve energy conversion efficiency.

[0092] In addition, those skilled in the art should understand that although there are many problems in the prior art, each embodiment or technical solution of the present application can only be improved in one or several aspects, and it is not necessary to solve all the technical problems listed in the prior art or background art at the same time. Those skilled in the art should understand that the content not mentioned in a claim should not be regarded as a limitation of the claim.

[0093] Finally, it should be pointed out that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of controlling a three-phase inverter, characterized by, The method comprises the following steps: The main processor transmits the sampling raw data of the three-phase converter to the first storage area; The coprocessor reads the sampling raw data of the first storage area and performs coordinate transformation and phase-locked loop operation to obtain operation result data, and transmits the operation result data to the second storage area; wherein, the coprocessor runs at a period higher than the preset control frequency of the main processor, and triggers the operation of the sampling raw data immediately after the collection of the sampling raw data is completed; The main processor performs control loop calculation, reads the operation result data of the second storage area when the latest operation result data is needed, and loads the latest operation result data for update operation to obtain control output after other operations are completed; wherein, the main processor runs the control program at the preset control frequency, and the trigger time of the control program is set within the minimum allowable time window before the loading time of the control output.

2. The three-phase inverter control method of claim 1, wherein: The method further comprises the following steps: The main processor writes the sampling zero offset setting parameters and coefficient correction parameters into the third storage area, and the coprocessor reads the sampling zero offset setting parameters and coefficient correction parameters and applies them to the operation of the sampling raw data.

3. The three-phase inverter control method of claim 2, wherein: The first storage area is configured to be readable and writable by the main processor and readable only by the coprocessor; the second storage area is configured to be readable and writable by the coprocessor and readable only by the main processor; the third storage area is configured to be readable and writable by the main processor and readable only by the coprocessor, and the first storage area, the second storage area and the third storage area are independent partitions in a shared memory.

4. The method of claim 1, 2 or 3, wherein: The running frequency of the coprocessor is more than 4 times of the preset control frequency of the main processor, and the control period of the main processor is consistent with the switching period of the main power device of the three-phase converter.

5. The three-phase inverter control method of claim 4, wherein: The control loop calculation comprises current loop control and voltage loop control; the current loop control is based on the d-axis and q-axis current components in the operation result data, and the voltage reference value is calculated through a PI regulator; The voltage loop control is based on the DC bus voltage or grid voltage component in the operation result data, and the current loop output is optimized through feedforward compensation or decoupling control.

6. The three-phase inverter control method of claim 5, wherein: The PI regulator in the current loop control and the voltage loop control adopts a difference equation form of a discrete transfer function, and is further modified into a difference equation form, and the difference equation satisfies: wherein, is the difference between the current period output and the previous period output of the PI controller, , , is the proportional coefficient of the PI controller, is the integral coefficient of the PI controller, is the control period of the main processor, is the input deviation of the current period of the PI controller, is the input deviation of the previous period of the PI controller.

7. The three-phase inverter control method of claim 6, wherein: The voltage reference value includes a d-axis reference voltage and a q-axis reference voltage ; The first d-axis reference voltage at the moment The calculation formula is as follows: In the formula, is the d-axis grid voltage, , , are the bus voltage errors at the first moment, the first moment, and the first moment, respectively; , are the inductance current d-axis current component errors at the first moment and the first moment, respectively; is the filtered inductance inductance; is the grid voltage angular frequency; is the q-axis component of the n-th moment of the three-phase inductance current; , , , are the first, second, third, and fourth voltage values of the first of the first moment, respectively; , , , are the coefficients based on the DC voltage loop PI parameters , and the d-axis current loop PI parameters , , and , , , ; The first q-axis reference voltage at the moment The calculation formula is as follows: Where, is the d-axis grid voltage, 、 Respectively Time, The q-axis current component error of the inductor current at time ; is the inductance of the filter inductor; is the grid voltage angular frequency; The three-phase inductor current The d-axis component of the moment; 、 、 、 Respectively time The first voltage value, the second voltage value, the third voltage value, and the fourth voltage value of the item; 、 Based on the q-axis current loop PI parameters 、 The coefficient of , .

8. A three-phase inverter control system, characterized by, It comprises: The main processor, the coprocessor, the first storage area and the second storage area are communicatively connected; The main processor is configured to transmit the sampling raw data of the three-phase converter to the first storage area, run the control program at a preset control frequency, and perform control loop calculation, read the operation result data of the second storage area when the latest operation result data is needed, and load the latest operation result data for update operation to obtain control output after other operations are completed; the trigger time of the control program of the main processor is set within the minimum allowable time window before the loading time of the control output. The coprocessor is configured to read the sampling raw data of the first storage area, and perform coordinate transformation and phase-locked loop operation to obtain operation result data, and transmit the operation result data to the second storage area; the coprocessor is configured to run at a frequency higher than a preset control frequency of the host processor, and is configured to trigger the operation on the sampling raw data immediately after the collection of the sampling raw data is completed.

9. A computer-readable storage medium, characterized in that: The computer readable storage medium stores computer instructions, and the computer is configured to implement the three-phase converter control method according to any one of claims 1-7 when the computer instructions are executed by the processor.

10. An electronic device, comprising: The computer readable storage medium stores computer instructions, and the computer is configured to implement the three-phase converter control method according to any one of claims 1-7 when the computer instructions are executed by the processor.

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