Driving circuit of switching circuit and motor driving circuit

Abstract

The invention discloses a driving circuit. The driving circuit comprises a PWM end for receiving a PWM signal, first to fourth gate control ends for respectively providing first to fourth control signals, and first and second output ends. The first period has first and second periods, and the PWM signal has a high logic level during the first period and a low logic level during the second period. In the normal operating mode, the first control signal and the fourth control signal have a first voltage level during a first period of the first period, and the second control signal and the fourth control signal have the first voltage level during a second period of the first period. In the power-off mode, during a first period of the first period, the second control signal and the third control signal have a first voltage level, and during a second period of the first period, the second control signal and the fourth control signal have the first voltage level.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to an electronic circuit, and more particularly, to a driving circuit of a switching circuit and a motor driving circuit. BACKGROUND

[0002] In a computer system such as a desktop or a notebook, a main power supply is usually used to supply power to a main processing unit and other peripheral devices. When the main power supply is unplugged during the operation of the computer system, a backup battery will be activated to supply power to the computer system to backup data. Meanwhile, the fan of the system keeps running to dissipate the heat generated by the main processing unit to backup data. Therefore, when the main power supply stops supplying power or is unplugged, the running time of the fan needs to be prolonged to prolong the time of backing up data. SUMMARY

[0003] To solve the above technical problems, embodiments of the present application disclose a driving circuit of a switching circuit and a motor driving circuit.

[0004] According to an embodiment of the present application, a driving circuit of a switching circuit is provided, wherein the switching circuit is configured to drive a motor, the driving circuit comprising: a pulse width modulation end configured to receive a PWM signal; a first gate control end configured to provide a first control signal; a second gate control end configured to provide a second control signal; a third gate control end configured to provide a third control signal; a fourth gate control end configured to provide a fourth control signal; a first output end coupled to a first end of the motor; and a second output end coupled to a second end of the motor. Wherein a first period has a first time period and a second time period, the PWM signal has a high logic level during the first time period and a low logic level during the second time period. Wherein in a normal working mode, during the first time period of the first period, the first control signal and the fourth control signal have a first voltage level, and the second control signal and the third control signal have a second voltage level, during the second time period of the first period, the second control signal and the fourth control signal have the first voltage level, and the first control signal and the third control signal have the second voltage level. Wherein in a power-off mode, during the first time period of the first period, the second control signal and the third control signal have the first voltage level, and the first control signal and the fourth control signal have the second voltage level, during the second time period of the first period, the second control signal and the fourth control signal have the first voltage level, and the first control signal and the third control signal have the second voltage level.

[0005] According to another embodiment of the present application, a driving circuit for an electric machine is provided, comprising: a first switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is configured to receive an input voltage; a second switch having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second switch is coupled to the second terminal of the first switch, and the second terminal of the second switch is configured to be coupled to a reference ground; a third switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is configured to receive the input voltage; a fourth switch having a first terminal, a second terminal and a control terminal, wherein the first terminal of the fourth switch is coupled to the second terminal of the third switch, and the second terminal of the fourth switch is configured to be coupled to the reference ground; a driving control circuit configured to provide a first control signal to the control terminal of the first switch, a second control signal to the control terminal of the second switch, a third control signal to the control terminal of the third switch, and a fourth control signal to the control terminal of the fourth switch in response to a PWM signal; a first output terminal coupled to the second terminal of the first switch, the first terminal of the second switch and a first terminal of the electric machine; and a second output terminal coupled to the second terminal of the third switch, the first terminal of the fourth switch and a second terminal of the electric machine. Wherein the first period has a first time interval and a second time interval, the PWM signal has a high logic level during the first time interval and a low logic level during the second time interval. Wherein in a normal working mode, the first switch and the fourth switch are turned on during the first time interval of the first period, and the second switch and the fourth switch are turned on during the second time interval of the first period. Wherein in a power-off mode, the second switch and the third switch are turned on during the first time interval of the first period, and the second switch and the fourth switch are turned on during the second time interval of the first period.

[0006] According to another embodiment of the present application, a driving circuit for an electric machine is provided, comprising: a first switch and a second switch coupled in series; a third switch and a fourth switch coupled in series; a driving control circuit configured to control the first switch, the second switch, the third switch and the fourth switch in response to a PWM signal; a first output configured to couple a common connection point of the first switch and the second switch to a first end of the electric machine; and a second output configured to couple a common connection point of the third switch and the fourth switch to a second end of the electric machine. Wherein a first period has a first time period and a second time period, the PWM signal has a high logic level during the first time period and a low logic level during the second time period. Wherein in a normal working mode, during the first time period of the first period, a voltage at the first output has a first voltage level and a voltage at the second output has a second voltage level, and during the second time period of the first period, the voltage at the first output and the voltage at the second output both have the second voltage level. Wherein in a power-off mode, during the first time period of the first period, the voltage at the first output has the second voltage level and the voltage at the second output has the first voltage level, and during the second time period of the first period, the voltage at the first output and the voltage at the second output both have the second voltage level.

[0007] According to the embodiment of the present application, by changing the driving timing of the switches, the mechanical energy of the fan is recycled and the capacitor is charged, thereby prolonging the power supply time of the backup power supply. BRIEF DESCRIPTION OF DRAWINGS

[0008] For a better understanding of the present application, the present application will be described in detail with the following drawings. Identical or similar elements include identical reference numerals. The following drawings are merely illustrative and are not necessarily drawn to scale.

[0009] Figure 1 A circuit schematic diagram 100 of a power supply architecture for a computing device application is shown;

[0010] Figure 2 A circuit schematic diagram of a driving circuit 210 for a switching circuit 220 for driving an electric machine M according to an embodiment of the present application is shown;

[0011] Figure 3 A circuit schematic diagram of a driving circuit 300 for an electric machine M according to an embodiment of the present application is shown;

[0012] Figure 4 A circuit schematic diagram of a driving circuit 300 for an electric machine M according to an embodiment of the present application is shown; Figure 2 A working waveform diagram of the driving circuit 210 shown during a positive half cycle;

[0013] Figure 5AFig. 4 shows a schematic diagram of the working principle of the H-bridge circuit driving the motor M in the Ton period of the positive half cycle in the normal working mode according to an embodiment of the present application;

[0014] Figure 5B Fig. 5 shows a schematic diagram of the working principle of the H-bridge circuit driving the motor M in the Toff period of the positive half cycle in the normal working mode according to an embodiment of the present application;

[0015] Figure 6A Fig. 6 shows a schematic diagram of the working principle of the H-bridge circuit driving the motor M in the Ton period of the positive half cycle in the power-off mode according to an embodiment of the present application;

[0016] Figure 6B Fig. 7 shows a schematic diagram of the working principle of the H-bridge circuit driving the motor M in the Toff period of the positive half cycle in the power-off mode according to an embodiment of the present application;

[0017] Figure 7 Fig. 8 shows a schematic diagram of the working principle of the H-bridge circuit driving the motor M in the Ton period of the negative half cycle in the normal working mode according to an embodiment of the present application; Figure 2 Fig. 9 shows a working waveform diagram of the driving circuit 210 in the negative half cycle;

[0018] Figure 8A Fig. 10 shows a schematic diagram of the working principle of the H-bridge circuit driving the motor M in the Toff period of the negative half cycle in the normal working mode according to an embodiment of the present application;

[0019] Figure 8B Fig. 11 shows a schematic diagram of the working principle of the H-bridge circuit driving the motor M in the Ton period of the negative half cycle in the power-off mode according to an embodiment of the present application;

[0020] Figure 9A Fig. 12 shows a schematic diagram of the working principle of the H-bridge circuit driving the motor M in the Toff period of the negative half cycle in the power-off mode according to an embodiment of the present application;

[0021] Figure 9B Fig. 13 shows a schematic diagram of the working principle of the H-bridge circuit driving the motor M in the Toff period of the negative half cycle in the power-off mode according to an embodiment of the present application;

[0022] Figure 10 Fig. 14 shows a circuit schematic diagram of the driving circuit 1010 for the switching circuit 1020 according to another embodiment of the present application;

[0023] Figure 11 Fig. 15 shows a circuit schematic diagram of the driving circuit 1100 for the motor M according to another embodiment of the present application;

[0024] Figure 12 Fig. 16 shows a schematic diagram of the working principle of the H-bridge circuit driving the motor M in the Ton period of the positive half cycle in the normal working mode according to an embodiment of the present application; Figure 10The working waveform diagram of the driving circuit 1010 in the first cycle is shown;

[0025] Figure 13A Schematic diagram showing the working principle of the bridge circuit of the driving motor M in the normal working mode during the Ton period of the first cycle according to one embodiment of the present invention;

[0026] Figure 13B Schematic diagram showing the working principle of the bridge circuit of the driving motor M in the normal working mode during the Toff period of the first cycle according to one embodiment of the present invention;

[0027] Figure 14A 1. A schematic diagram showing the working principle of a bridge circuit for driving a motor M in a power-off mode during a Ton period of a first cycle according to an embodiment of the present invention is shown;

[0028] Figure 14B Schematic diagram showing the working principle of the bridge circuit of the driving motor M in the power-off mode during the Toff period of the first cycle according to one embodiment of the present invention;

[0029] Figure 15 Another embodiment of the present invention is shown Figure 10 The working waveform diagram of the driving circuit 1010 in the second cycle is shown;

[0030] Figure 16A Schematic diagram showing the working principle of the bridge circuit of the driving motor M in the normal working mode during the Ton period of the second cycle according to one embodiment of the present invention;

[0031] Figure 16B FIG. 1 is a schematic diagram showing the working principle of a bridge circuit for driving a motor M in a normal working mode during a Toff period of a second cycle according to an embodiment of the present invention;

[0032] Figure 17A Schematic diagram showing the working principle of the bridge circuit of the driving motor M in the power-off mode during the Ton period of the second cycle according to one embodiment of the present invention;

[0033] Figure 17B FIG. 1 is a schematic diagram showing the working principle of a bridge circuit driving a motor M in a power-off mode during a Toff period of a second cycle according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] Specific embodiments of the present application will now be described in detail with reference to the drawings, which are by way of illustration only and are not intended to be limiting. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application can be practiced without the specific details. In other instances, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring the present application. As used in this application, the term "couple" and its derivatives mean an indirect connection or coupling through an intermediate wired or wireless connection.

[0035] Reference throughout this specification to "an embodiment", "embodiments", "one example", or "examples" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" or "one example" or "an example" in various places throughout this specification are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable

[0036] Figure 1 A circuit schematic 100 for a power supply architecture for a computing device application is shown. The power supply architecture includes a primary power source 110, a backup power source 120, and capacitors C1-C2. The computing device includes a primary processing unit 130 and a motor unit 140. In some embodiments, the computing device includes, but is not limited to, a personal computer, a notebook computer, a smartphone, or other similar devices. In some embodiments, the primary processing unit 130 includes a central processing unit (CPU), a graphics processing unit (GPU), or other processing units. In some embodiments, the motor unit 140 includes a motor and a motor drive circuit. In some embodiments, the motor is a motor of a fan, and the motor drive circuit is used to drive the fan to dissipate heat generated by the primary processing unit 130.

[0037] During normal operation of the power supply architecture, the primary power source 110 coupled to the capacitor C1 is configured to supply power to the primary processing unit 130 and the motor unit 140. For example, the primary power source 110 is configured to provide an input voltage or an input current to the primary processing unit 130 and the motor unit 140. When the primary power source 110 stops supplying power or when the input voltage or the input current of the computing device drops, the backup power source 120 coupled to the capacitor C2 is configured to supply power to the primary processing unit 130 and the motor unit 140.

[0038] In some embodiments, the computing device needs to backup data in the main processing unit 130 immediately when the main power supply 110 stops supplying power, or when the main power supply 110 is unplugged, or when the input voltage or input current supplied by the main power supply 110 drops. This requires the backup power supply 120 to supply power to the main processing unit 130 and the motor unit 140. However, the backup power supply 120 can run out of power before the data backup is completed. Embodiments of the present invention provide a motor drive circuit that is capable of recovering motor energy and storing the energy back to the capacitor C2, which can extend the running time of the main processing unit 130 and the motor unit 140 when backing up data.

[0039] For example, when the main power supply 110 is unplugged, the fan enters a power-off mode. In particular, when the input current of the fan is below a value or equal to zero, it represents that the main power-off is detected. The fan driver controls the fan to rotate at a lower speed in inertia to reduce the power consumption in the power-off mode. In one embodiment, in the power-off mode, the fan driver drives the fan at a lower target speed using the duty cycle of the PWM signal. In another embodiment, in the power-off mode, the frequency of the PWM signal is used to control the target speed of the fan or to reduce the power consumption. In embodiments of the present invention, by changing the driving of the switching circuit (changing the switching timing of the switches), the mechanical energy of the fan is transferred back to charge the capacitor (e.g., C2) to extend the power supply time of the backup power supply 120.

[0040] Figure 2 A circuit schematic of a drive circuit 210 for driving a switching circuit 220 of a motor M is shown, according to an embodiment of the present invention. In some embodiments, the motor M includes a single-phase motor (e.g., a fan motor), and the switching circuit 220 includes an H-bridge circuit to supply power to the motor M. In particular, the switching circuit 220 includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The first switch S1 and the second switch S2 are coupled in series, and the third switch S3 and the fourth switch S4 are coupled in series. For example, a first end of the first switch S1 is configured to receive an input voltage VIN, a second end of the first switch S1 and a first end of the second switch S2 are both coupled to a node OUT1, and a second end of the second switch S2 is configured to be coupled to a reference ground. A first end of the third switch S3 is configured to receive the input voltage VIN, a second end of the third switch S3 and a first end of the fourth switch S4 are both coupled to a node OUT2, and a second end of the fourth switch S4 is configured to be coupled to the reference ground. In one embodiment, the switching circuit 220 further includes an input capacitor CIN to filter the input voltage VIN.

[0041] In some embodiments, the node OUT1 of the switching circuit 220 is coupled to a first end of the motor M, and the node OUT2 is coupled to a second end of the motor M to drive the motor M. The switching circuit 220 is configured to provide a current signal to the motor M from the node OUT1 or from the node OUT2. In some embodiments, the motor includes a rotor and a stator. The rotor has permanent magnets forming magnetic poles. The stator has windings wound along stator arms. The current flows through the windings of the stator, which in turn induces an electromagnetic field. The magnetic force generated by the rotor magnetic field and the stator electromagnetic field causes the rotor to rotate.

[0042] The driving circuit 210 is configured to control the turn-on or turn-off of the switches in the switching circuit 220. The driving circuit 210 includes an input voltage terminal VCC, a pulse width modulation (PWM) terminal PWM, a first gate control terminal GH1, a second gate control terminal GL1, a third gate control terminal GH2, a fourth gate control terminal GL2, a first output terminal SW1, and a second output terminal SW2. The input voltage terminal VCC is configured to receive an input voltage VIN. The PWM terminal is configured to receive a PWM signal. The driving circuit 210 is configured to provide control signals to the switching circuit 220 according to the PWM signal. In particular, the first gate control terminal GH1 is configured to provide a first control signal Q1 to the control terminal of the first switch S1, the second gate control terminal GL1 is configured to provide a second control signal Q2 to the control terminal of the second switch S2, the third gate control terminal GH2 is configured to provide a third control signal Q3 to the control terminal of the third switch S3, and the fourth gate control terminal GL2 is configured to provide a fourth control signal Q4 to the control terminal of the fourth switch S4. The first output terminal SW1 is coupled to the node OUT1, and the second output terminal SW2 is coupled to the node OUT2.

[0043] In one embodiment, the driving circuit 210 further includes a terminal to receive a signal M1. The signal M1 represents a power-off instruction. For example, when the signal M1 transitions from a low logic level to a high logic level, the driving circuit 210 detects a power-off instruction representing that the main power supply stops supplying power. In response to the power-off instruction, the driving circuit 210 enters a power-off mode. In one embodiment, the power-off instruction can be detected based on the PWM signal. For example, when the duty cycle of the PWM signal decreases to less than a threshold value (e.g., <0.05) within a period of time (e.g., 2 ms), it represents that the power-off instruction is detected, and the driving circuit controls the motor to enter the power-off mode. In another embodiment, when the PWM signal remains at a low logic level for a period of time (e.g., 2 ms), it represents that the power-off instruction is detected, and the driving circuit controls the motor to enter the power-off mode. In some embodiments, the power-off instruction can be detected according to the frequency of the PWM signal. In other embodiments, when the input current is less than a value (e.g., <0.5 A) for a period of time (e.g., >0.5 ms), it represents that the power-off instruction is detected.

[0044] In some embodiments, the driving circuit 210 is integrated in an integrated circuit, and the switching circuit 220 is an external circuit of the driving circuit 210. The input voltage terminal VCC, the PWM terminal, the first gate control terminal GH1, the second gate control terminal GL1, the third gate control terminal GH2, the fourth gate control terminal GL2, the first output terminal SW1 and the second output terminal SW2 are pins of the integrated circuit.

[0045] Figure 3 A circuit schematic of a driving circuit 300 for a motor M according to an embodiment of the present application is shown. The driving circuit 300 comprises a driving control circuit 310, a switching circuit 320, a first output terminal SW1 and a second output terminal SW2. The switching circuit 320 comprises a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4. The first switch S1 and the second switch S2 are coupled in series, and the third switch S3 and the fourth switch S4 are coupled in series. A first terminal of the first switch S1 is configured to receive an input voltage VIN, a second terminal of the first switch S1 and a first terminal of the second switch S2 are both coupled to a node OUT1, and a second terminal of the second switch S2 is configured to be coupled to a reference ground. A first terminal of the third switch S3 is configured to receive the input voltage VIN, a second terminal of the third switch S3 and a first terminal of the fourth switch S4 are both coupled to a node OUT2, and a second terminal of the fourth switch S4 is configured to be coupled to the reference ground.

[0046] In some embodiments, the first output terminal SW1 is coupled to the node OUT1 and a first terminal of the motor M, and the second output terminal SW2 is coupled to the node OUT2 and a second terminal of the motor M. The switching circuit 320 is configured to provide a current signal to the motor M from the node OUT1 or from the node OUT2.

[0047] The driving control circuit 310 is configured to provide a first control signal Q1 to a control terminal of the first switch S1, a second control signal Q2 to a control terminal of the second switch S2, a third control signal Q3 to a control terminal of the third switch S3, and a fourth control signal Q4 to a control terminal of the fourth switch S4 in response to a PWM signal.

[0048] In some embodiments, the driving circuit 300 further comprises an input voltage terminal VCC to receive the input voltage VIN. In one embodiment, the input voltage terminal VCC is coupled to an input capacitor CIN to filter the input voltage VIN. In some embodiments, the driving circuit 300 further comprises a PWM terminal to receive the PWM signal. In some embodiments, the driving circuit 300 further comprises a terminal to receive a signal M1 representing a power-off instruction.

[0049] In some embodiments, the driving control circuit 310 and the switching circuit 320 are integrated in the same integrated circuit. The input voltage terminal VCC, the PWM terminal, the first output terminal SW1 and the second output terminal SW2 are pins of the integrated circuit.

[0050] Figure 4 Fig. 6 shows a working waveform diagram of the H-bridge circuit driving the motor M in the normal working mode according to an embodiment of the present application. Figure 2 Fig. 7 shows a working waveform diagram of the driving circuit 210 in the positive half cycle. Figure 4 Fig. 7 shows a working waveform diagram of the driving circuit 210 in the positive half cycle.

[0051] In some embodiments, when the signal Ml is at the low logic level, the driving circuit 210 works in the normal working mode. When the signal Ml changes from the low logic level to the high logic level, the driving circuit 210 receives a power-off instruction and enters the power-off mode.

[0052] As shown in Fig. 8, in the normal working mode, in the Ton period of the positive half cycle, the first control signal Ql and the fourth control signal Q4 are both at the high logic level, and the second control signal Q2 and the third control signal Q3 are both at the low logic level. In some embodiments, the switches S1-S4 are N-type metal oxide semiconductor field effect transistors (NMOS). Accordingly, the high logic level corresponds to the high voltage level for turning on the NMOS, and the low logic level corresponds to the low voltage level for turning off the NMOS. In other embodiments, the switches S1-S4 are PMOS. Accordingly, the high logic level corresponds to the low voltage level for turning on the PMOS, and the low logic level corresponds to the high voltage level for turning off the PMOS. Figure 4

[0053] Figure 5A Fig. 6 shows a working waveform diagram of the H-bridge circuit driving the motor M in the normal working mode according to an embodiment of the present application. Figure 4 ​The first control signal Q1 and the fourth control signal Q4 are shown to be high logic level, and the first switch S1 and the fourth switch S4 are turned on. The current I1 flows through the first switch S1, from the node OUT1 through the motor M to the node OUT2, and then to the fourth switch S4. Since the first switch S1 is turned on, the voltage at the node OUT1 is at a high voltage level (i.e. VIN). Since the fourth switch S4 is turned on, the voltage at the node OUT2 is at a low voltage level (i.e. reference ground voltage).

[0054] With continued reference to Figure 4 In the normal operation mode, during the Toff period of the positive half cycle, the second control signal Q2 and the fourth control signal Q4 are both at high logic level, and the first control signal Q1 and the third control signal Q3 are both at low logic level.

[0055] Figure 5B A schematic diagram showing the operation of the H-bridge circuit driving the motor M in the normal operation mode during the Toff period of the positive half cycle is shown. During the Toff period of the positive half cycle, in response to the second control signal Q2 and the fourth control signal Q4 being shown to be high logic level, the second switch S2 and the fourth switch S4 are turned on. The current I1 flows through the fourth switch S4, the second switch S2, from the node OUT1 through the motor M to the node OUT2. Since both the second switch S2 and the fourth switch S4 are turned on, the voltages at the nodes OUT1 and OUT2 are both at a low voltage level (i.e. reference ground voltage). Figure 4

[0056] With continued reference to Figure 4 In the power-off mode, during the Ton period of the positive half cycle, the second control signal Q2 and the third control signal Q3 are both at high logic level, and the first control signal Q1 and the fourth control signal Q4 are both at low logic level.

[0057] Figure 6A A schematic diagram showing the operation of the H-bridge circuit driving the motor M in the power-off mode during the Ton period of the positive half cycle is shown. During the Ton period of the positive half cycle, in response to the second control signal Q2 and the third control signal Q3 being shown to be high logic level, the second switch S2 and the third switch S3 are turned on. The current I2 flows through the second switch S2, from the node OUT1 through the motor M to the node OUT2, and then through the third switch S3. Since the third switch S3 is turned on, the voltage at the node OUT2 is at a high voltage level (i.e. VIN). Since the second switch S2 is turned on, the voltage at the node OUT1 is at a low voltage level (i.e. reference ground voltage). Figure 4

[0058] ​​Therefore, in the power-off mode, during the Ton period of the positive half cycle, the current I2 flows into the capacitor CIN to charge it. In some embodiments, before the main power is restored, the energy stored in the capacitor CIN can be used to power the driving circuit 210.

[0059] Continue to refer Figure 4 In the power-off mode, during the Toff period of the positive half cycle, the second control signal Q2 and the fourth control signal Q4 are both at a high logic level, and the first control signal Q1 and the third control signal Q3 are both at a low logic level.

[0060] Figure 6B FIG. 1 is a schematic diagram showing the working principle of the H-bridge circuit of the driving motor M in the power-off mode during the Toff period of the positive half cycle according to an embodiment of the present invention. Figure 4 As shown, the second control signal Q2 and the fourth control signal Q4 turn on the second switch S2 and the fourth switch S4. Current I2 flows through the fourth switch S4, the second switch S2, and then from node OUT1 through the motor M to node OUT2. Because both the second switch S2 and the fourth switch S4 are turned on, the voltages at nodes OUT1 and OUT2 are both at a low voltage level (i.e., reference ground).

[0061] Figure 7 shows an embodiment of the present invention Figure 2 The driving circuit 210 is shown as a working waveform diagram during a negative half cycle. In some embodiments, when the signal M1 changes from a low logic level to a high logic level, the driving circuit 210 switches to a power-off mode.

[0062] like Figure 7 As shown, in the normal operating mode, during the Ton period of the negative half cycle, the second control signal Q2 and the third control signal Q3 are both at a high logic level, and the first control signal Q1 and the fourth control signal Q4 are both at a low logic level.

[0063] Figure 8A The schematic diagram shows the working principle of the H-bridge circuit driving the motor M in the normal working mode in the negative half cycle Ton period according to one embodiment of the present invention. In the negative half cycle, the current flows from the node OUT2 through the motor M to the node OUT1. In the negative half cycle Ton period, in response to Figure 7 As shown, the second and third control signals Q2 and Q3 are both turned on. Current I3 flows through the third switch S3, from node OUT2 through the motor M to node OUT1, and then to the second switch S2. Since the third switch S3 is turned on, the voltage at node OUT2 is at a high voltage level (i.e., VIN). Since the second switch S2 is turned on, the voltage at node OUT1 is at a low voltage level (i.e., the reference ground voltage).

[0064] With continued reference Figure 7 In the normal operating mode, during the Toff period of the negative half cycle, both the second control signal Q2 and the fourth control signal Q4 are at a high logic level, and both the first control signal Q1 and the third control signal Q3 are at a low logic level.

[0065] Figure 8B A schematic diagram illustrating the operation of the H-bridge circuit driving the motor M in the normal operating mode during the Toff period of the negative half cycle is shown. During the Toff period of the negative half cycle, in response to the second control signal Q2 and the fourth control signal Q4 being as shown, Figure 4 the second switch S2 and the fourth switch S4 are turned on. The current I3 flows through the second switch S2, the fourth switch S4, and then from the node OUT2 through the motor M to the node OUT1. Since both the second switch S2 and the fourth switch S4 are turned on, the voltage at the nodes OUT1 and OUT2 are both at a low voltage level (i.e., the reference ground voltage).

[0066] With continued reference Figure 7 In the power-off mode, during the Ton period of the negative half cycle, both the first control signal Q1 and the fourth control signal Q4 are at a high logic level, and both the second control signal Q2 and the third control signal Q3 are at a low logic level.

[0067] Figure 9A A schematic diagram illustrating the operation of the H-bridge circuit driving the motor M in the power-off mode during the Ton period of the negative half cycle is shown. During the Ton period of the negative half cycle, in response to the first control signal Q1 and the fourth control signal Q4 being as shown, Figure 7 the first switch S1 and the fourth switch S4 are both turned on. The current I4 flows through the fourth switch S4, from the node OUT2 through the motor M to the node OUT1, and then through the first switch S1. Since the first switch S1 is turned on, the voltage at the node OUT1 is at a high voltage level (i.e., VIN). Since the fourth switch S4 is turned on, the voltage at the node OUT1 is at a low voltage level (i.e., the reference ground voltage).

[0068] Thus, in the power-off mode, during the Ton period of the negative half cycle, the current I4 flows into the capacitor CIN to charge it. In some embodiments, the energy stored in the capacitor CIN can be used to power the drive circuit 210 before the main power supply is restored.

[0069] With continued reference Figure 7 In the power-off mode, during the Toff period of the negative half cycle, both the second control signal Q2 and the fourth control signal Q4 are at a high logic level, and both the first control signal Q1 and the third control signal Q3 are at a low logic level.

[0070] Figure 9BFig. 6 shows a schematic diagram illustrating the operation of the H-bridge circuit of the drive motor M in the off-mode during the Toff period of the positive half cycle according to an embodiment of the present application. During the Toff period of the positive half cycle, the second switch S2 and the fourth switch S4 are turned on in response to the second control signal Q2 and the fourth control signal Q4 as shown in Fig. 6. The current I4 flows through the second switch S2, the fourth switch S4, and then from the node OUT2 to the node OUT1 through the motor M. Since both the second switch S2 and the fourth switch S4 are turned on, the voltage at the nodes OUT1 and OUT2 are both at a low voltage level (i.e., the reference ground voltage). Figure 7

[0071] Figure 4 As described in the embodiments, the drive circuit 210 enters the off-mode during the positive half cycle. In some embodiments, after the end of the positive half cycle, the drive circuit 210 continues to operate in the off-mode during the next negative half cycle, the signals of the drive circuit 210 during the negative half cycle are as shown in Fig. 5. Figure 7 Figure 7 As described in the embodiments, the drive circuit 210 enters the off-mode during the negative half cycle. In some embodiments, after the end of the negative half cycle, the drive circuit 210 continues to operate in the off-mode during the next positive half cycle, the signals of the drive circuit 210 during the positive half cycle are as shown in Fig. 6. Figure 4

[0072] Figure 10 Fig. 4 shows a schematic diagram illustrating the circuit of the drive circuit 210 for the switching circuit 102 according to another embodiment of the present application. In some embodiments, the motor M is a three-phase motor, and the switching circuit 102 is a three-phase bridge configuration. In one embodiment, the switching circuit 102 further includes a fifth switch S5 and a sixth switch S6 coupled in series. The first end of the fifth switch S5 is configured to receive the input voltage VIN, the second end of the fifth switch S5 and the first end of the sixth switch S6 are both coupled to the node OUT3, and the second end of the sixth switch S6 is configured to be coupled to the reference ground. The node OUT3 of the switching circuit 102 is coupled to the third terminal of the motor M.

[0073] In one embodiment, the drive circuit 1010 further includes a fifth gate control end GH3, a sixth gate control end GL3, and a third output end SW3. The fifth gate control end GH3 is configured to provide a fifth control signal G5 to the control end of the fifth switch S5. The sixth gate control end GL3 is configured to provide a sixth control signal G6 to the control end of the sixth switch S6. The third output end SW3 is coupled to the node OUT3.

[0074] Figure 11 ​​​​A circuit schematic of a drive circuit 1100 for a motor M according to another embodiment of the present application is shown. In some embodiments, the motor M is a three-phase motor, and the switching circuit 1120 is a three-phase bridge configuration. In one embodiment, the switching circuit 1120 further comprises a fifth switch S5 and a sixth switch S6, and the drive control circuit 1110 is further configured to provide a fifth control signal G5 and a sixth control signal G6 to control terminals of the fifth switch S5 and the sixth switch S6, respectively, in response to the PWM signal. The drive control circuit 1100 further comprises a third output terminal SW3 coupled to the node OUT3 and a third terminal of the motor M.

[0075] Figure 12 A circuit schematic of a drive circuit 1010 for a motor M according to one embodiment of the present application is shown. Figure 10 The drive circuit 1010 is shown in a first period of operation. During the first period, a current flows from a first output terminal SW1 of the drive circuit 1010 through the motor M to a second output terminal SW2. In some embodiments, the drive circuit 1010 is further configured to operate in other periods in addition to the first period, such as Figure 15 a second period shown. The operation of the drive circuit 1010 in the other periods is understood by those skilled in the art according to embodiments of the present application.

[0076] Figure 13A A schematic diagram of the operation of a bridge circuit for driving a motor M according to one embodiment of the present application in a Ton period of a first period in a normal operation mode is shown. In the Ton period of the first period, in response to Figure 12 the first control signal Q1 and the fourth control signal Q4 shown, the first switch S1 and the fourth switch S4 are both turned on. A current I5 flows through the first switch S1 from a node OUT1 through the motor M to a node OUT2, and then to the fourth switch S4. As a result of the first switch S1 being turned on, the voltage at the node OUT1 is at a high voltage level (i.e., VIN). As a result of the fourth switch S4 being turned on, the voltage at the node OUT2 is at a low voltage level (i.e., a reference ground voltage).

[0077] Figure 13B A schematic diagram of the operation of a bridge circuit for driving a motor M according to one embodiment of the present application in a Toff period of a first period in a normal operation mode is shown. In the Toff period of the first period, in response to Figure 12 the second control signal Q2 and the fourth control signal Q4 shown, the second switch S2 and the fourth switch S4 are turned on. The current I5 flows through the fourth switch S4 and the second switch S2, and then from the node OUT1 through the motor M to the node OUT2. As a result of the second switch S2 and the fourth switch S4 being turned on, the voltages at the nodes OUT1 and OUT2 are both at a low voltage level (i.e., a reference ground voltage).

[0078] Figure 14AFIG. 1 is a schematic diagram showing the working principle of the bridge circuit of the driving motor M in the power-off mode in the first cycle of the Ton period according to an embodiment of the present invention. Figure 12 As shown, the second and third control signals Q2 and Q3 are both turned on. Current I6 flows through the second switch S2, from node OUT1 through the motor M to node OUT2, and then through the third switch S3. Since the third switch S3 is turned on, the voltage at node OUT2 is at a high voltage level (i.e., VIN). Since the second switch S2 is turned on, the voltage at node OUT1 is at a low voltage level (i.e., the reference ground voltage).

[0079] Figure 14B FIG. 1 is a schematic diagram showing the working principle of the bridge circuit of the driving motor M in the power-off mode during the first cycle Toff period according to an embodiment of the present invention. Figure 12 As shown, the second control signal Q2 and the fourth control signal Q4 turn on the second switch S2 and the fourth switch S4. Current I6 flows through the fourth switch S4 and the second switch S2, and then flows from the node OUT1 through the motor M to the node OUT2. Because the second switch S2 and the fourth switch S4 are both turned on, the voltages at the nodes OUT1 and OUT2 are both at a low voltage level (i.e., the reference ground voltage).

[0080] Figure 15 Another embodiment of the present invention is shown Figure 10 The working waveform of the driving circuit 1010 in the second cycle is shown. In the second cycle, the current flows from the first output terminal SW1 of the driving circuit 1010 through the motor M to the third output terminal SW3.

[0081] Figure 16A FIG. 1 shows a schematic diagram of the working principle of the bridge circuit of the driving motor M according to an embodiment of the present invention in the normal working mode during the Ton period of the second cycle. Figure 15 As shown, the first control signal Q1 and the sixth control signal Q6 are both turned on, and the first switch S1 and the sixth switch S6 are both turned on. Current I7 flows through the first switch S1, from node OUT1 through the motor M to node OUT3, and then to the sixth switch S6. Since the first switch S1 is turned on, the voltage at node OUT1 is at a high voltage level (i.e., VIN). Since the sixth switch S6 is turned on, the voltage at node OUT3 is at a low voltage level (i.e., the reference ground voltage).

[0082] Figure 16B FIG. 1 is a schematic diagram showing the working principle of the bridge circuit of the driving motor M according to an embodiment of the present invention in the normal working mode during the Toff period of the second cycle. Figure 15The second control signal Q2 and the sixth control signal Q6 are shown to be asserted. The current I7 flows through the sixth switch S6 and the second switch S2, and then from the node OUT1 through the motor M to the node OUT3. Since both the second switch S2 and the sixth switch S6 are asserted, the voltage at the nodes OUT1 and OUT3 are both at the low voltage level (i.e., the reference ground voltage).

[0083] Figure 17A The operation of the bridge circuit driving the motor M in the power-off mode during the Ton period of the second cycle is shown. During the Ton period of the second cycle, the second control signal Q2 and the fifth control signal Q5 are asserted in response to the assertion of the first control signal Q1 and the de-assertion of the third control signal Q3 and the fourth control signal Q4. Figure 15 The second control signal Q2 and the fifth control signal Q5 are shown to be asserted. The current I8 flows through the second switch S2 from the node OUT1 through the motor M to the node OUT3, and then through the fifth switch S5. Since the fifth switch S5 is asserted, the voltage at the node OUT3 is at the high voltage level (i.e., VIN). Since the second switch S2 is asserted, the voltage at the node OUT1 is at the low voltage level (i.e., the reference ground voltage).

[0084] Figure 17B The operation of the bridge circuit driving the motor M in the power-off mode during the Toff period of the second cycle is shown. During the Toff period of the second cycle, the second control signal Q2 and the sixth control signal Q6 are de-asserted in response to the de-assertion of the first control signal Q1 and the assertion of the third control signal Q3 and the fourth control signal Q4. Figure 15 The second control signal Q2 and the sixth control signal Q6 are shown to be asserted. The current I8 flows through the sixth switch S6 and the second switch S2, and then from the node OUT1 through the motor M to the node OUT3. Since both the second switch S2 and the sixth switch S6 are asserted, the voltage at the nodes OUT1 and OUT3 are both at the low voltage level (i.e., the reference ground voltage).

[0085] Embodiments of the present application provide a drive circuit that recycles energy from the motor in the power-off mode to extend the run time of the motor. In addition, for notebook computer applications where battery life is important, the recycled energy can be used to backup data before the system is powered off when the main power supply is stopped.

[0086] While the application has been described with reference to several exemplary embodiments, it is to be understood that the use of other words or terms such as "preferably," "according to an embodiment," and "in one embodiment" is intended to convey that the particular naming and placement of an embodiment are not to be taken as a limitation or in a manner limiting of other embodiments. Furthermore, the present application has been described with reference to several exemplary embodiments thereof. It will be understood by those skilled in the art that various changes can be made and equivalents can be substituted for elements thereof without departing from the scope of the present application. In addition, many modifications can be made to adapt a particular situation or material to the teachings of the present application without departing from the central inventive concept described herein. Accordingly, the present application is not limited to the embodiments described above, but extends to all embodiments that would be understood by those skilled in the art to fall within the scope and spirit of the present application as defined by the appended claims, and their equivalents.

Claims

1. A driving circuit for a switching circuit configured to drive a motor, the driving circuit comprising: a pulse width modulation (PWM) terminal configured to receive a PWM signal; a first gate control terminal configured to provide a first control signal; a second gate control terminal configured to provide a second control signal; a third gate control terminal configured to provide a third control signal; a fourth gate control terminal configured to provide a fourth control signal; a first output terminal coupled to a first end of the motor; and a second output terminal coupled to a second end of the motor; wherein a first period has a first time interval and a second time interval, the PWM signal has a high logic level during the first time interval and a low logic level during the second time interval; wherein in a normal operation mode, during the first time interval of the first period, the first control signal and the fourth control signal have a first voltage level, the second control signal and the third control signal have a second voltage level, and during the second time interval of the first period, the second control signal and the fourth control signal have the first voltage level, the first control signal and the third control signal have the second voltage level; and wherein in a power-off mode, during the first time interval of the first period, the second control signal and the third control signal have the first voltage level, the first control signal and the fourth control signal have the second voltage level, and during the second time interval of the first period, the second control signal and the fourth control signal have the first voltage level, the first control signal and the third control signal have the second voltage level. 2.The driving circuit of claim 1, wherein: in the normal operation mode, during the first time interval of the first period, a voltage at the first output terminal has a third voltage level, a voltage at the second output terminal has a fourth voltage level, and during the second time interval of the first period, the voltage at the first output terminal and the voltage at the second output terminal both have the fourth voltage level; and wherein in the power-off mode, during the first time interval of the first period, the voltage at the first output terminal has the fourth voltage level, the voltage at the second output terminal has the third voltage level, and during the second time interval of the first period, the voltage at the first output terminal and the voltage at the second output terminal both have the fourth voltage level. 3.The driving circuit of claim 1, wherein a second period has a first time interval and a second time interval, wherein in the normal operation mode, during the first time interval of the second period, the second control signal and the third control signal have the first voltage level, and during the second time interval of the second period, the second control signal and the fourth control signal have the first voltage level; and wherein in the power-off mode, during the first time interval of the second period, the first control signal and the fourth control signal have the first voltage level, and during the second time interval of the second period, the second control signal and the fourth control signal have the first voltage level. 4.The driving circuit of claim 3, wherein: ​ ​ ​ in the normal operation mode, the voltage at the first output has the fourth voltage level during the first period of the second cycle, and the voltage at the second output has the third voltage level, and the voltage at the first output and the voltage at the second output both have the fourth voltage level during the second period of the second cycle; and wherein in the power-off mode, the voltage at the first output has the third voltage level during the first period of the second cycle, and the voltage at the second output has the fourth voltage level, and the voltage at the first output and the voltage at the second output both have the fourth voltage level during the second period of the second cycle.

5. The driving circuit of claim 1, further comprising: a fifth gate control terminal configured to provide a fifth control signal; a sixth gate control terminal configured to provide a sixth control signal; and a third output terminal coupled to a third terminal of the motor; wherein the second cycle has a first period and a second period; wherein in the normal operation mode, the first control signal and the sixth control signal have the first voltage level during the first period of the second cycle, and the second control signal and the sixth control signal have the first voltage level during the second period of the second cycle; and wherein in the power-off mode, the second control signal and the fifth control signal have the first voltage level during the first period of the second cycle, and the second control signal and the sixth control signal have the first voltage level during the second period of the second cycle.

6. The driving circuit of claim 5, wherein: in the normal operation mode, the voltage at the first output has the third voltage level during the first period of the second cycle, and the voltage at the second output and the voltage at the third output have the fourth voltage level, and the voltage at the first output, the voltage at the second output, and the voltage at the third output all have the fourth voltage level during the second period of the second cycle; and wherein in the power-off mode, the voltage at the first output and the voltage at the second output have the fourth voltage level during the first period of the second cycle, and the voltage at the third output has the third voltage level, and the voltage at the first output, the voltage at the second output, and the voltage at the third output all have the fourth voltage level during the second period of the second cycle.

7. A driving circuit for a motor, comprising: a first switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal is configured to receive an input voltage; a second switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the second terminal of the first switch, and the second terminal of the second switch is configured to be coupled to a reference ground; a third switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal is configured to receive the input voltage; a fourth switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth switch is coupled to the second terminal of the third switch, and the second terminal of the fourth switch is configured to be coupled to the reference ground; ​ a driving control circuit configured to provide a first control signal to a control terminal of the first switch, a second control signal to a control terminal of the second switch, a third control signal to a control terminal of the third switch, and a fourth control signal to a control terminal of the fourth switch in response to the PWM signal; a first output terminal coupled to a second terminal of the first switch, a first terminal of the second switch, and a first terminal of the motor; and a second output terminal coupled to a second terminal of the third switch, a first terminal of the fourth switch, and a second terminal of the motor; wherein the first period has a first time interval and a second time interval, the PWM signal has a high logic level during the first time interval and a low logic level during the second time interval; wherein in the normal operation mode, the first switch and the fourth switch are turned on during the first time interval of the first period, and the second switch and the fourth switch are turned on during the second time interval of the first period; and wherein in the power-off mode, the second switch and the third switch are turned on during the first time interval of the first period, and the second switch and the fourth switch are turned on during the second time interval of the first period.

8. The driving circuit of claim 7, wherein: in the power-off mode, during the first time interval of the first period, the current flows through the second switch, from the first output terminal through the motor to the second output terminal, and through the third switch.

9. The driving circuit of claim 7, wherein: in the power-off mode, during the second time interval of the first period, the current flows through the fourth switch and the second switch, and from the first output terminal through the motor to the second output terminal.

10. The driving circuit of claim 7, wherein the second period has a first time interval and a second time interval, wherein in the normal operation mode, the second switch and the third switch are turned on during the first time interval of the second period, and the second switch and the fourth switch are turned on during the second time interval of the second period; and wherein in the power-off mode, the first switch and the fourth switch are turned on during the first time interval of the second period, and the second switch and the fourth switch are turned on during the second time interval of the second period.

11. The driving circuit of claim 10, wherein: in the power-off mode, during the first time interval of the second period, the current flows through the fourth switch, from the second output terminal through the motor to the first output terminal, and through the first switch.

12. The driving circuit of claim 10, wherein: in the power-off mode, during the second time interval of the second period, the current flows through the second switch and the fourth switch, and from the second output terminal through the motor to the first output terminal.

13. The driving circuit of claim 7, wherein the switching circuit further comprises: a fifth switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal is configured to receive an input voltage; a sixth switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the sixth switch is coupled to the second terminal of the fifth switch, and the second terminal of the sixth switch is configured to be coupled to a reference ground; and a third output terminal coupled to the second terminal of the fifth switch, the first terminal of the sixth switch, and a third terminal of the motor.

14. The driving circuit of claim 13, wherein: in the normal operation mode, the fifth switch and the sixth switch are turned on during the first time interval of the first period, and the fifth switch and the sixth switch are turned on during the second time interval of the first period.

15. The driving circuit of claim 13, wherein: in the power-off mode, the fifth switch and the sixth switch are turned on during the first time interval of the first period, and the fifth switch and the sixth switch are turned on during the second time interval of the first period. wherein the drive control circuit is further configured to provide a fifth control signal to a control terminal of the fifth switch and a sixth control signal to a control terminal of the sixth switch in response to the PWM signal; wherein the second period has a first time segment and a second time segment; and wherein in the normal operation mode, the first switch and the sixth switch are turned on during the first time segment of the second period, and the second switch and the sixth switch are turned on during the second time segment of the second period.

14. The drive circuit of claim 13, wherein: in the power-off mode, the second switch and the fifth switch are turned on during the first time segment of the second period, and the second switch and the sixth switch are turned on during the second time segment of the second period.

15. A drive circuit for an electric machine, comprising: a first switch and a second switch coupled in series; a third switch and a fourth switch coupled in series; a drive control circuit configured to control the first switch, the second switch, the third switch, and the fourth switch in response to a PWM signal; a first output configured to couple a common connection point of the first switch and the second switch to a first terminal of the electric machine; and a second output configured to couple a common connection point of the third switch and the fourth switch to a second terminal of the electric machine; wherein the first period has a first time segment and a second time segment, the PWM signal has a high logic level during the first time segment and a low logic level during the second time segment; wherein in the normal operation mode, a voltage at the first output has a first voltage level and a voltage at the second output has a second voltage level during the first time segment of the first period, and the voltage at the first output and the voltage at the second output both have the second voltage level during the second time segment of the first period; and wherein in the power-off mode, the voltage at the first output has the second voltage level and the voltage at the second output has the first voltage level during the first time segment of the first period, and the voltage at the first output and the voltage at the second output both have the second voltage level during the second time segment of the first period.

16. The drive circuit of claim 15, wherein: in the normal operation mode, the first switch and the fourth switch are turned on during the first time segment of the first period, and the second switch and the fourth switch are turned on during the second time segment of the first period; and wherein in the power-off mode, the second switch and the third switch are turned on during the first time segment of the first period, and the second switch and the fourth switch are turned on during the second time segment of the first period.

17. The drive circuit of claim 15, wherein the second period has a first time segment and a second time segment, wherein in the normal operation mode, the voltage at the first output has the second voltage level and the voltage at the second output has the first voltage level during the first time segment of the second period, and the voltage at the first output and the voltage at the second output both have the second voltage level during the second time segment of the second period; and ​ wherein in the power-off mode, during the first period of the second cycle, the voltage at the first output has the first voltage level, the voltage at the second output has the second voltage level, and during the second period of the second cycle, the voltage at the first output and the voltage at the second output both have the second voltage level.

18. The drive circuit of claim 17, wherein in the normal operation mode, during the first period of the second cycle, the second switch and the third switch are turned on, and during the second period of the second cycle, the second switch and the fourth switch are turned on; and wherein in the power-off mode, during the first period of the second cycle, the first switch and the fourth switch are turned on, and during the second period of the second cycle, the second switch and the fourth switch are turned on.

19. The drive circuit of claim 15, wherein the switching circuit further comprises: a fifth switch and a sixth switch coupled in series; and a third output coupled to the fifth switch, the sixth switch, and a third terminal of the motor; wherein the drive control circuit is further configured to control the fifth switch and the sixth switch in response to the PWM signal; wherein the second cycle has a first period and a second period; wherein in the normal operation mode, during the first period of the second cycle, the voltage at the first output has the first voltage level, the voltage at the second output and the voltage at the third output have the second voltage level, and during the second period of the second cycle, the voltage at the first output, the voltage at the second output, and the voltage at the third output all have the second voltage level; and wherein in the power-off mode, during the first period of the second cycle, the voltage at the first output and the voltage at the second output have the second voltage level, the voltage at the third output has the first voltage level, and during the second period of the second cycle, the voltage at the first output, the voltage at the second output, and the voltage at the third output all have the second voltage level.

20. The drive circuit of claim 19, wherein: in the normal operation mode, during the first period of the second cycle, the first switch and the sixth switch are turned on, and during the second period of the second cycle, the second switch and the sixth switch are turned on; and wherein in the power-off mode, during the first period of the second cycle, the second switch and the fifth switch are turned on, and during the second period of the second cycle, the second switch and the sixth switch are turned on. ​

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