Signal delay control with inverse feedback

Abstract

The invention relates to signal delay control with inverse feedback. A system may include a delay circuit configured with a chain of delay elements along a forward path of the delay circuit; and one or more feedback elements providing electrical feedback to the forward path. The feedback element may be or include a feedback inverter, such as a tri-state inverter, having one or more inputs operable to control signal strength at an output of the feedback inverter. A feedback signal may oppose a signal along the forward path, which may reduce a voltage level associated with the forward signal. By controlling the strength of the feedback signal, the delay circuit can dynamically adjust the delay of the forward signal.

Description

[0001] Cross reference

[0002] The present patent application claims priority to U.S. Patent Application No. 19 / 040,661, entitled “SIGNAL DELAY CONTROL WITH INVERTED FEEDBACK,” filed January 29, 2025, in the name of Hollis et al., and claims priority to U.S. Patent Application No. 63 / 636,520, entitled “SIGNAL DELAY CONTROL WITH INVERTED FEEDBACK,” filed April 19, 2024, in the name of Hollis et al., each of which is assigned to the assignee hereof and each of which is hereby expressly incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The following relates to one or more systems for memory, including signal delay control with inverted feedback. BACKGROUND

[0004] Memory devices are used in electronic systems to store information, such as in computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells can be programmed to one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, an individual memory cell can support more than two states, any of which can be stored by the memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. SUMMARY

[0005] An electronic device is described. The electronic device can include an input terminal; an output terminal; and a delay circuit comprising: a plurality of delay elements coupled in series between the input terminal and the output terminal along a sequence of alternating odd nodes and even nodes; one or more first feedback elements each configured to send an inverted first signal of a corresponding one of the even nodes to a corresponding preceding one of the even nodes along the sequence; and one or more second feedback elements each configured to send an inverted second signal of a corresponding one of the odd nodes to a corresponding preceding one of the odd nodes along the sequence.

[0006] A method at an electronic device is described. The method can include receiving a first signal at an input of a delay circuit, the delay circuit including a plurality of delay elements coupled in series between the input and an output of the delay circuit along a sequence of alternating odd nodes and even nodes, and generating a second signal at the output of the delay circuit based at least in part on receiving the first signal, the second signal having a delay relative to the first signal, where generating the second signal is based at least in part on sending a respective first inverted signal of at least one of the even nodes to a corresponding preceding one of the even nodes along the sequence, sending a respective second inverted signal of at least one of the odd nodes to a corresponding preceding one of the odd nodes along the sequence, or a combination thereof.

[0007] A memory device is described. The memory device can include one or more memory arrays, a signal source associated with a first signal, and a delay circuit configured to generate a second signal associated with accessing the one or more memory arrays and having a delay relative to the first signal based at least in part on receiving the first signal from the signal source, the delay circuit comprising: a plurality of delay elements coupled in series between an input of the delay circuit and an output of the delay circuit along a sequence of alternating odd nodes and even nodes, one or more first feedback elements each configured to send an inverted first signal of a corresponding one of the even nodes to a corresponding preceding one of the even nodes along the sequence, and one or more second feedback elements each configured to send an inverted second signal of a corresponding one of the odd nodes to a corresponding preceding one of the odd nodes along the sequence. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 An example of a system supporting signal delay control with inverted feedback is shown in accordance with examples disclosed herein.

[0009] Figure 2 An example of a circuit supporting signal delay control with inverted feedback is shown in accordance with examples disclosed herein.

[0010] Figure 3 An example of a timing diagram supporting signal delay control with inverted feedback is shown in accordance with examples disclosed herein.

[0011] Figure 4 A flow diagram illustrating one or more methods supporting signal delay control with inverted feedback is shown in accordance with examples disclosed herein. DETAILED DESCRIPTION

[0012] Some systems (e.g., semiconductor systems, memory systems, host systems, processor systems) can include circuitry (e.g., delay circuitry, delay chains) associated with timing of a delayed signal (e.g., a timing signal, a data signal, a control signal, a command signal, a memory access signal, or other types of signals) (e.g., delaying rising edges, delaying falling edges, adjusting signal timing relative to a latching event). In some cases, circuit elements (e.g., capacitive circuit elements) used to generate a delayed output signal can be associated with reduced bandwidth capabilities (e.g., due to reduced slew rates of input signals, due to reduced edge rates) or can be susceptible to signal fluctuations (e.g., jitter). Such effects can degrade signal integrity and can constrain bandwidth (e.g., processing speed, memory access speed, throughput) of the system. Additionally, some systems (e.g., some delay circuits) can not support configurable control of delays along a signal path. For example, delays (e.g., time values of delays) can be preconfigured based on physical characteristics (e.g., physical components) of the system, and the system can not support dynamically adapting delay circuitry to support various applications, manufacturing characteristics, or operating characteristics (e.g., operating speed, operating frequency, operating temperature, operating voltage), among other constraints.

[0013] According to one or more techniques described herein, a system can include a delay circuit configured with a chain of delay elements (e.g., a sequence of delay elements, delay elements connected in series) along a forward path of the delay circuit and one or more feedback elements providing electrical feedback (e.g., inverting feedback, negative feedback) to the forward path. In some examples, the one or more feedback elements can be or include a feedback inverter, such as a tri-state inverter, having one or more inputs (e.g., analog inputs, digital inputs) operable to control a strength of a signal at an output of the feedback inverter. In some examples, the delay elements along the forward path can be implemented as inverters (e.g., forward path inverters), and the one or more feedback elements can provide a feedback signal across an even number (e.g., two) of the forward path inverters. For example, a feedback inverter can couple an output of a first inverter along the forward path to an input of a second inverter along the forward path before (e.g., immediately before) the first inverter. The feedback signal can oppose (e.g., cancel, counteract, suppress) a signal (e.g., a voltage of a forward signal) on the forward path, which can reduce (e.g., compress, cancel) a voltage level (e.g., a voltage range, a voltage amplitude) associated with the forward signal. Based on reducing the voltage level, the forward signal can transition from one state to another state (e.g., from a high voltage state to a low voltage state, from a low voltage state to a high voltage state, for a falling edge, for a rising edge) more quickly, for example for a given slew rate between signal states, which can reduce a delay duration associated with the delay elements. In some examples, a feedback element, such as the feedback inverter, can be operable to control a strength of the feedback signal based on biasing a first input (e.g., a head gate) of the feedback element with a first voltage (e.g., a head input voltage) and biasing a second input (e.g., a foot gate) of the feedback element with a second voltage (e.g., a foot input voltage). Thus, by controlling the strength of the feedback signal, the delay circuit can be able to dynamically adjust (e.g., tune, modulate) a delay of the forward signal over a relatively large range. Thus, the delay circuitry described herein can be associated with improved signal integrity, relatively high bandwidth and relatively flexible timing, among other benefits.

[0014] In addition to being applied in the memory systems described herein, techniques for signal delay control with inverted feedback can also generally be implemented to improve the performance of various electronic devices and systems, including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and gaming. Some electronic device applications, including high-performance applications such as AI, AR, VR, and gaming, can be associated with relatively high processing requirements to meet user expectations. As such, improving the processing capabilities of electronic devices by reducing response times, improving power consumption, reducing complexity, increasing data throughput or access speed, reducing communication times, or increasing memory capacity or density, among other performance metrics, can improve user experience or appeal. Implementing the techniques described herein can improve the performance of electronic devices by improving the flexibility of adjusting signal delays with relatively less impact on processing bandwidth, which can reduce processing or latency times, improve response times or otherwise improve user experience, among other benefits.

[0015] Features of the present disclosure are illustrated and described in the context of systems. Features of the present disclosure are further illustrated and described in the context of circuitry, timing diagrams, block diagrams, and flowcharts.

[0016] Figure 1 An example of a system 100 that supports signal delay control with inverted feedback in accordance with examples disclosed herein is illustrated. The system 100 can include portions of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, a smartphone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or other fixed or portable electronic system, among other examples. The system 100 includes a host device 105, a memory system 110, and one or more channels 115 coupling (e.g., for supporting communicatively coupling) the host device 105 with the memory system 110. The system 100 can include any number of memory systems 110 coupled with the host system 105.

[0017] The host system 105 can include one or more components (e.g., circuitry, processing circuitry, one or more processing components) that use memory to perform processes, any or more of which can be referred to as or included in a processor 125. The processor 125 can include at least one of one or more processing elements that can be collocated or distributed, including a general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a controller, discrete gate or transistor logic, one or more discrete hardware components, or a combination thereof. The processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC or component thereof, among other examples.

[0018] The host system 105 can also include at least one of one or more components (e.g., circuitry, logic, instructions) that implement functionality of an external memory controller, such as a host system memory controller, which can be referred to or included in the host system controller 120. For example, the host system controller 120 can issue commands or other signaling for operating the memory system 110, such as write commands, read commands, configuration signaling, or other operational signaling. In some examples, the host system controller 120 or associated functionality described herein can be implemented by or be part of the processor 125. For example, the host system controller 120 can be hardware, instructions (e.g., software, firmware), or some combination thereof implemented by the processor 125 or other component of the host system 105. In various examples, the host system 105 or host system controller 120 can be referred to as a host.

[0019] The memory system 110 provides physical memory locations (e.g., addresses) that can be used or referenced by the system 100. The memory system 110 can include a memory system controller 140 and one or more memory devices 145 (e.g., memory packages, memory dies, memory chips) that are operable to store data. The memory system 110 can be configured to operate with different types of host systems 105 and can respond to commands from the host system 105 (e.g., from the host system controller 120). For example, the memory system 110 (e.g., the memory system controller 140) can receive a write command indicating that the memory system 110 store data received from the host system 105, or receive a read command indicating that the memory system 110 provide data stored in the memory devices 145 to the host system 105, or receive a refresh command indicating that the memory system 110 refresh data stored in the memory devices 145, among other types of commands and operations.

[0020] The memory system controller 140 can include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control operations of the memory system 110. The memory system controller 140 can include hardware or instructions that support the memory system 110 to perform various operations, and can be operable to receive, transmit, or respond to commands, data, or control information related to operations of the memory system 110. The memory system controller 140 can be operable to communicate with one or more of the host system controller 120, one or more memory devices 145, or the processor 125. In some examples, the memory system controller 140 can cooperate with the host system controller 120, local controllers 150 of the memory devices 145, or any combination thereof to control operations of the memory system 110. Although an example of the memory system controller 140 is illustrated as a separate component of the memory system 110, in some examples, aspects of the functionality of the memory system 110 can be implemented by at least one of the processor 125, the host system controller 120, one or more local controllers 150, or any combination thereof.

[0021] Each memory device 145 can include a local controller 150 and one or more memory arrays 155. The memory arrays 155 can be a set of memory cells (e.g., two-dimensional array, three-dimensional array), where each memory cell is operable to store data (e.g., as one or more bits of storage). Each memory array 155 can include memory cells of various architectures, such as random access memory (RAM) cells, dynamic RAM (DRAM) cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, ferroelectric RAM (FeRAM) cells, magnetic RAM (MRAM) cells, resistive RAM (RRAM) cells, phase change memory (PCM) cells, chalcogenide memory cells, or nonvolatile (NOR) memory cells and non-volatile NAND memory cells, or any combination thereof.

[0022] The local controller 150 can include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control operation of the memory device 145. In some examples, the local controller 150 can be operable to communicate (e.g., receive or transmit data or commands, or both) with the memory system controller 140. In some examples, the memory system 110 can not include the memory system controller 140, and the local controller 150 or the host system controller 120 can perform the functions of the memory system controller 140 described herein. In some examples, the local controller 150 or the memory system controller 140, or both, can include a decode component operable to access addresses of the memory array 155, a sense component to sense states of memory cells of the memory array 155, a write component to write states to memory cells of the memory array 155, or various other components operable to support the described operations of the memory system 110.

[0023] The host system 105 (e.g., the host system controller 120) and the memory system 110 (e.g., the memory system controller 140) can communicate information (e.g., data, commands, control information, configuration information, timing information) using one or more channels 115. Each channel 115 can be an example of a transmission medium that carries information, and each channel 115 can include one or more signal paths (e.g., transmission media, electrical conductors, conductive paths) between terminals (e.g., nodes, pins, contacts) associated with components of the system 100. A terminal can be an example of a conductive input or output point of a device of the system 100, and a terminal can be operable as part of a channel 115. To support communication via a channel 115, the host system 105 (e.g., the host system controller 120) and the memory system 110 (e.g., the memory system controller 140) can include receivers (e.g., latches) to receive signals, transmitters (e.g., drivers) to transmit signals, decoders to decode or demodulate received signals, or encoders to encode or modulate signals to be transmitted, among other components to support signaling via a channel 115, which can be included in respective interface portions of the respective systems.

[0024] Channels 115 can be dedicated to communicating one or more types of information, and channels 115 can include unidirectional channels, bidirectional channels, or both. For example, channels 115 can include one or more command / address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some examples, channels 115 can be configured to provide power from one system to another (e.g., from host system 105 to memory system 110, according to a regulated voltage). In some examples, at least a subset of channels 115 can be configured according to a protocol (e.g., a logical protocol, a communication protocol, an operational protocol, an industry standard) that can support configuration operations of host system 105 and memory system 110 and interactions between host system 105 and memory system 110.

[0025] Command / address channels (e.g., CA channels) can be operable to communicate commands between host system 105 and memory system 110, including control information (e.g., address information, configuration information) associated with the commands. Commands carried by command / address channels can include write commands having an address of data written to memory system 110 or read commands having an address of data read from memory system 110.

[0026] Clock signal channels can be operable to communicate one or more clock signals between host system 105 and memory system 110. Clock signals can oscillate between a high state and a low state and can support coordination (e.g., in time) between operations of host system 105 and memory system 110. In some examples, clock signals can provide a timing reference for operations of memory system 110. Clock signals can be referred to as control clock signals, command clock signals, or system clock signals. System clock signals can be generated by a system clock, which can include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors).

[0027] Data channels (e.g., DQ channels) can be operable to communicate information (e.g., data, control information) between host system 105 and memory system 110 (e.g., bidirectionally). For example, data communications can communicate information written from host system 105 to memory system 110 or information read from memory system 110 to host system 105. In some examples, channels 115 can include one or more error detection code (EDC) channels. EDC channels can be operable to communicate error detection signals (e.g., checksums or parity bits), which can accompany information passed through data channels.

[0028] Signaling can be communicated over the lanes 115 using single data rate (SDR) signaling or double data rate (DDR) signaling, among other rates (e.g., relative to a clock signal). In SDR signaling, one modulation symbol (e.g., signal level) of a signal can be registered for each clock cycle (e.g., on a rising edge or a falling edge of a clock signal). In DDR signaling, two modulation symbols of a signal can be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0029] One or more components of the system 100, as well as other electronic systems, can include circuitry (e.g., delay circuitry, delay chains) associated with delaying a timing of a signal (e.g., a timing signal, a data signal, a control signal, a command signal, a memory access signal, or other type of signal) (e.g., delaying a rising edge, delaying a falling edge, adjusting a signal timing relative to a latching event). For example, the memory system 110 (e.g., the memory system controller 140, the memory devices 145, the local controllers) can include delay circuitry to delay clock signaling (e.g., clock signaling generated at an oscillator of the memory system 110, clock signaling received from the host system 105 over one or more of the lanes 115), which can be used to initiate various operations of the memory system 110 (e.g., access operations, data transfer operations, communication operations, multiplexing operations). Additionally or alternatively, the host system 105 (e.g., the processor 125, the host system controller 120) or the memory system 110 (e.g., the memory system controller 140, the memory devices 145, the local controllers 150) can include delay circuitry to adjust a signal timing (e.g., of a clock signal, a data signal, a control signal, a command signal) relative to a latching event, such as a latch for initiating a data processing operation (e.g., for performing a processing operation), a latch for initiating a data communication operation (e.g., for latching a received signal), a latch for initiating an access operation (e.g., for accessing a memory array 155), or other. For example, the host system 105, the memory system, or both, can implement delay circuitry for training the lanes 115 (e.g., for data lane and data lane gating training (e.g., DQ-DQS training), for decision feedback equalization (DFE) tap training, for phase timing training). Although these represent some examples for implementing delay circuitry at one or more components of a system, the described techniques can be implemented in other applications for delaying an output signal relative to an input signal.

[0030] In some cases, circuit elements (e.g., capacitive circuit elements) used to generate a delayed output signal can be associated with reduced bandwidth capabilities (e.g., due to reduced conversion rates of input signals, due to reduced edge rates) or can be susceptible to signal fluctuations (e.g., jitter). Such effects can degrade signal integrity and can constrain bandwidth (e.g., processing speed, memory access speed, throughput). Additionally, some systems (e.g., some delay circuits) can not support configurable control of delays along a signal path. For example, delays (e.g., time values of delays) can be preconfigured based on physical characteristics (e.g., physical components) of a system, and the system can not support dynamically adapting delay circuitry to support various applications, manufacturing characteristics, or operating characteristics (e.g., operating speed, operating frequency, operating temperature, operating voltage), among other constraints.

[0031] According to one or more techniques described herein, one or more components of system 100 (e.g., host system 105, processor 125, host system controller 120, memory system 110, memory system controller 140, memory device 145, local controller 150), and other electrical components can include a delay circuit configured with a chain of delay elements (e.g., a sequence of delay elements, delay elements connected in series) along a forward path of the delay circuit and one or more feedback elements providing electrical feedback (e.g., inverting feedback, negative feedback) to the forward path. In some examples, the one or more feedback elements can be or include a feedback inverter, such as a tri-state inverter, having one or more inputs (e.g., analog inputs, digital inputs) operable to control a strength of a signal at an output of the feedback inverter. In some examples, the delay elements along the forward path can be implemented as inverters (e.g., forward path inverters), and the one or more feedback elements can provide a feedback signal across an even number (e.g., two) of the forward path inverters. For example, a feedback inverter can couple an output of a first inverter along the forward path to an input of a second inverter along the forward path before (e.g., immediately before) the first inverter. The feedback signal can counteract (e.g., cancel, oppose, suppress) a signal (e.g., a voltage of a forward signal) on the forward path, which can reduce (e.g., compress, cancel) a voltage level (e.g., a voltage range, a voltage amplitude) associated with the forward signal. Based on reducing the voltage level, the forward signal can transition faster from one state to another state (e.g., from a high voltage state to a low voltage state, from a low voltage state to a high voltage state, for falling edges, for rising edges), such as for a given slew rate between signal states, which can reduce a delay duration associated with the delay elements. In some examples, a feedback element, such as the feedback inverter, can be operable to control a strength of the feedback signal based on biasing a first input (e.g., a head gate) of the feedback element with a first voltage (e.g., a head input voltage) and biasing a second input (e.g., a foot gate) of the feedback element with a second voltage (e.g., a foot input voltage). Thus, by controlling the strength of the feedback signal, the delay circuit can be capable of dynamically adjusting (e.g., tuning, modulating) a delay of the forward signal over a relatively large range. Thus, the delay circuitry described herein can support improved signal integrity, relatively higher bandwidth, and relatively flexible timing, among other benefits, for one or more components of system 100 and other implementations.

[0032] Figure 2An example of a circuit 200 (e.g., delay circuit, delay chain) that supports signal delay control with inverted feedback is shown in accordance with the examples disclosed herein. The circuit 200 can include an input 240 (e.g., input node, input terminal) and an output 245 (e.g., output node, output terminal), and can be configured to output (e.g., generate) a second signal (e.g., output signal, delayed signal, second timing signal) at the output 245 that has a delay with respect to a first signal (e.g., input signal) received at the input 240.

[0033] Any number of one or more instances of the circuit 200 can be included in an electronic device (e.g., host system 105, processor 125, host system controller 120, memory system 110, memory system controller 140, memory device 145, local controller 150, and other electronic devices), where each instance of the circuit 200 is configured to generate an output signal at the output 245 that has a respective delay with respect to an input signal at the input 240. For example, the circuit 200 can be implemented to delay timing signals, data signals, control signals, command signals, memory access signals, or other types of signals (e.g., delay rising edges, delay falling edges, adjust signal timing with respect to a latching event). For example, the memory system 110 (e.g., memory system controller 140, memory device 145, local controller) can include one or more instances of the circuit 200 to delay clock signaling (e.g., generated at an oscillator of the memory system 110, clock signaling received from the host system 105 over one or more channels 115) that can be used to initiate various operations of the memory system 110 (e.g., access operations, data transfer operations, communication operations, multiplexing operations). Additionally or alternatively, the host system 105 (e.g., processor 125, host system controller 120) or the memory system 110 (e.g., memory system controller 140, memory device 145, local controller 150) can include one or more instances of the circuit 200 to adjust signal timing (e.g., of clock signals, data signals, control signals, command signals) with respect to a latching event, such as a latch for initiating a data processing operation (e.g., for performing a processing operation), a latch for initiating a data communication operation (e.g., for latching a received signal), a latch for initiating an access operation (e.g., for accessing a memory array 155), or other. For example, the host system 105, the memory system, or both can implement the delay circuit 200 for training a channel 115 (e.g., for data channel and data channel strobe training (e.g., DQ-DQS training), for decision feedback equalization (DFE) tap training, for phase timing training). Although these represent some examples for implementing the delay circuit 200 at one or more components of a system, the described techniques can be implemented in other applications for delaying an output signal with respect to an input signal.

[0034] Circuit 200 can be configured to receive a signal at respective input 240. For example, circuit 200 (e.g., input 240) can include or be coupled with a terminal of an electronic device configured to output (e.g., generate, provide) a first signal. The first signal can be a timing signal (e.g., a clock signal), a data signal (e.g., a data transfer signal, random data movement signaling), a command signal, a communication signal, a control signal, or some other signal. In some examples, the first signal can be received from an external system (e.g., an external oscillator, an external source), such as a signal source included in a different device than a device including an instance of circuit 200. In some other examples, the first signal can be generated by a signal source integrated with circuit 200 (e.g., via an on-board oscillator, via an on-board signal source, not shown). In some examples, circuit 200 can be implemented in or as part of a memory device, and can include one or more memory arrays, a signal source (e.g., a timing signal source, an oscillator) associated with the first signal, or both (e.g., coupled with the memory arrays, the signal source, or both).

[0035] In some cases, a system (e.g., system 100, memory system 110, host system 105, or other electronic system) can implement circuitry associated with delaying an input signal at an output of the circuitry. However, at least some circuit elements (e.g., capacitive circuit elements) used to generate a delayed output signal can be associated with reduced bandwidth capabilities (e.g., due to reduced slew rates of the input signal, due to reduced edge rates) or can be susceptible to signal fluctuations (e.g., jitter). Such effects can reduce signal integrity and can constrain bandwidth (e.g., processing speed, memory access speed, throughput) of the system. Additionally, some systems (e.g., some delay circuits) can not support configurable control of delay along a signal path. For example, a delay (e.g., a time value of the delay) can be pre-configured based on physical characteristics (e.g., physical components) of the system, and the system can not support dynamically adapting the delay circuitry to support various applications, manufacturing characteristics, or operating characteristics (e.g., operating speed, operating frequency, operating temperature, operating voltage), among other constraints.

[0036] According to one or more techniques described herein, circuit 200 can be configured to support delay control with respect to an input signal to an output signal while maintaining relatively high bandwidth capabilities (e.g., processing bandwidth, communication bandwidth, memory access bandwidth, timing signal frequency) and signal integrity (e.g., by avoiding adding capacitance for delay control to enable more abrupt transitions between states). For example, circuit 200 can include one or more feedback paths (e.g., feedback paths having staggered coupling points along a forward signal path), and elements of circuit 200 can control delay based on strength of one or more feedback signals (e.g., inverted feedback signals) introduced into the forward path.

[0037] Circuit 200 can include a plurality of delay elements coupled in series (e.g., along a forward path, along a central path) between input 240 and output 245. In the illustrated example, such delay elements are implemented as a chain of inverters 205 (e.g., inverters 205-a-l through 205-a-10, inverter chain) coupled in series between input 240 and output 245. For example, an output of inverter 205-a-l can be coupled with an input of inverter 205-a-2, and an output of inverter 205-a-2 can be coupled with an input of inverter 205-a-3, and so on (e.g., along a forward path). Such delay elements can be coupled between input 240 and output 245 along a sequence of alternating odd nodes 210 and even nodes 210. For example, a delay element illustrated by inverter 205-a-2 can precede node 210-a-l (e.g., an odd node) along a forward path, a delay element illustrated by inverter 205-a-3 can be between node 210-a-l and node 210-a-2 (e.g., an even node following an odd node) along a forward path, and so on, as well as other implementations of alternating odd and even nodes 210. Although some delay elements according to the described techniques can be associated with signal inversion (e.g., by way of inverters 205-a), some other delay elements coupled between input 240 and output 245 according to the described techniques can not be associated with signal inversion or can implement other arrangements of circuitry (e.g., logic circuitry, logic gates, NAND gates, transistor types and arrangements).

[0038] Circuit 200 can also include one or more feedback paths (e.g., interleaved feedback paths) coupled with the forward path at one or more nodes along the forward path. For example, a feedback path can include a feedback element configured to send a signal (e.g., an inverted signal, an opposite signal, a suppressed signal) from one node 210 to a preceding node 210 along the forward path. In the illustrated example, such feedback elements include inverters 205-b along one or more feedback paths (e.g., feedback loops) of circuit 200 (e.g., between one or more pairs of even nodes 210, between one or more pairs of odd nodes 210). For example, circuit 200 can include one or more feedback elements (e.g., as inverters 205-b) configured to send an inverted signal of a corresponding one of even nodes 210-a to a corresponding preceding one of even nodes 210-a (e.g., inverter 205-b-5 sends an inverted signal of even node 210-a-4 to preceding even node 210-a-2, which can be the immediately preceding even node, and so on). Additionally or alternatively, circuit 200 can include one or more feedback elements (e.g., as inverters 205-b) configured to send an inverted signal of a corresponding one of odd nodes 210-a to a corresponding preceding one of odd nodes 210-a (e.g., inverter 205-b-1 sends an inverted signal of odd node 210-a-3 to preceding odd node 210-a-1, which can be the immediately preceding odd node, and so on). Accordingly, inverters 205-b can each have a respective input (e.g., respective input 235-a-2) coupled with an output of a first inverter 205-a of inverter chain 205-a and a respective output (e.g., respective output 260) coupled with an input of a second inverter 205-a of inverter chain 205-a preceding (e.g., immediately preceding) the first inverter 205-a along inverter chain 205.

[0039] Although the inverting feedback elements are illustrated and described with reference to pairs of even nodes and pairs of alternating odd nodes (e.g., across a pair of inverting delay elements as inverters 205-a, across an even number of delay elements as inverters 205-a), the inverting feedback elements can be implemented as feedback of any number of one or more delay elements (e.g., from a node 210 to any preceding node 210) when such delay elements are not associated with signal inversion. Moreover, although some feedback elements according to the described techniques can be associated with signal inversion (e.g., by way of inverters 205-a), some other feedback components implemented along the forward path according to the described techniques can not be associated with signal inversion (e.g., when implemented across an odd number of inverters 205-a) or can implement other arranged circuitry (e.g., logic circuitry, logic gates, NAND gates, transistor types and arrangements).

[0040] Although the illustrated example of circuit 200 includes a particular number of inverters 205 (e.g., a particular number of delay elements, a particular number and configuration of feedback elements), various examples of circuit 200 can include different numbers and configurations of components, including inverters and other components, which can be implemented in a given electronic device to support generation of output signals having different relative timing in accordance with the described techniques for implementing different relative delays. For example, although Figure 2 Circuit 200 is illustrated with a non-limiting example of a 10-stage forward path (e.g., with 10 inverters 205-a), but circuit 200 can include any number of inverters (e.g., any number of stages) along the forward path including more or fewer inverters 205-a and other implementations of delay elements, which can support different amounts of delay at output 245 relative to input 240. Moreover, although Figure 2 Circuit 200 is illustrated with a non-limiting example of a number of feedback paths and inverters 205-b, but circuit 200 can include any number of feedback paths with any number of feedback inverters 205-b in each feedback path and other implementations of feedback elements. In some examples, delay control can be proportional to the number of feedback paths and the number of inverters 205-b.

[0041] In some examples, at least some (if not each) inverter 205-a (e.g., along the forward path) can include a circuit 215 (e.g., illustrated as an extension of inverter 205-a-1 as an example of an inverting delay element), which can include 2 transistors (a p-type transistor and an n-type transistor, a p / n inverter) coupled as shown. For example, inverter 205-a can include an input 250 and an output 255. At output 255, circuit 215 can output (e.g., generate) an inverted version of a signal provided at input 250 (e.g., as a voltage inversion). In some examples, inverter 205-a can generate an inverted signal based on a voltage source 225 (e.g., Vdd, a high logic state voltage) and a voltage source 230 (e.g., a ground voltage, a low logic state voltage). For example, if a relatively low voltage signal is provided at input 250, then circuit 215 (e.g., a p-type transistor) can couple voltage source 225 with output 255 to generate a relatively high voltage signal at the output. If a relatively high voltage signal is provided at input 250, then circuit 215 (e.g., an n-type transistor) can couple voltage source 230 with output 255 to generate a relatively low voltage signal at output 255.

[0042] In some examples, at least some (if not each) inverter 205-b (e.g., along respective feedback paths) can include a circuit 220 (e.g., illustrated as an extension of inverter 205-b-l as an example of implementing an inverting feedback element), which can include 4 transistors (e.g., 2 p-type transistors and 2 n-type transistors as a tri-stable inverter). Circuit 220 of inverter 205-b can include multiple (e.g., 3) inputs 235 and one output 260. At output 260, circuit 220 can output (e.g., generate) an inverted version (e.g., as a voltage inversion) of a signal provided at input 235-a-2. In some examples, inverter 205-b can generate an inverted signal based on voltage source 225 and voltage source 230 (e.g., which can be the same or different voltage sources as inverter 205-a). For example, inverter 205-b can adjust a strength of the inverted signal at output 260 based on respective voltages applied to input 235-a-l (e.g., a head gate bias input) and input 235-a-3 (e.g., a foot gate bias input). Respective input 235-a-l of inverter 205-b can be coupled with respective voltage source 265 (e.g., a respective head voltage source V H1 , V H2 , V H3 , V H4 , etc.), and respective input 235-a-3 of inverter 205-b can be coupled with respective voltage source 270 (e.g., a respective foot voltage source V F1 , V F2 , V F3 , V F4 , etc.). Although circuit 220 is illustrated as an example for implementing inverter 205-b, in some examples, circuit 220 can be implemented for inverter 205-a (e.g., along a forward path), which can support turning off the forward path, reducing leakage current, and other functionality.

[0043] In some examples, each inverter 205-b can correspond to (e.g., be coupled between) an even number of inverters 205-a (e.g., 2) along the forward path. However, in some examples, the output of a last inverter 205-a along the chain of inverters 205-a can be coupled with its own input via an even number of inverters 205-b (e.g., to maintain an overall odd number of feedback inverters relative to the even number of forward path inverters). As an example, the output of inverter 205-a-10 (e.g., at node 210-a-9) can be coupled with its own input at node 210-a-8 via a pair of inverters 205-b (e.g., inverters 205-b-8 and 205-b-9). In some examples, multiple feedback elements (e.g., multiple inverters 205-b) can be coupled along a feedback path (e.g., a feedback loop). For example, the output of at least one of the inverters 205-b can be directly coupled with the input of another of the inverters 205-b. As an example, the output of inverter 205-b-2 can be directly coupled with the input of inverter 205-b-l, and so on.

[0044] Each inverter 205-b can include a first input coupled with a respective voltage source 265, a second input coupled with a respective voltage source 270, and a third input coupled with the output of a respective inverter 205-a. In some examples, the delay (e.g., duration of the delay) of the output signal of the delay circuit 200 (e.g., at output 245) relative to the input signal can be based on the respective first voltage of voltage source 265 and the respective second voltage of voltage source 270. In some examples, one or more of the voltage sources 265 (e.g., each head gate bias) can collectively produce (e.g., provide) the same voltage level for each of the inverters 205-b, or one or more of the voltage sources 265 can each independently produce a respective voltage level (e.g., a different voltage level). Similarly, one or more of the respective voltage sources 270 (e.g., each foot gate bias) can collectively produce the same voltage level for each of the inverters 205-b, or one or more of the voltage sources 270 can each independently produce a respective voltage level (e.g., a different voltage level).

[0045] In some implementations, respective voltage source 265 and voltage source 270 can be associated with controlling the strength of an inversion signal at a given output 260 (e.g., to a given input 250, to a given output 255, to respective node 210) and other signal characteristics. For example, circuit 200 (e.g., or other circuitry of a control electronic device) can increase or decrease the voltage level of voltage source 265 (e.g., head gate bias voltage) or voltage source 270 (e.g., foot gate bias voltage). Accordingly, circuit 200 can adjust the bias of at least a first transistor (e.g., p-type transistor) coupled between output 260 and voltage source 225 or at least a second transistor (e.g., n-type transistor) coupled between output 260 and voltage source 230, or both. Such bias voltage can at least partially enable or disable the first transistor and / or the second transistor (e.g., at least partially activate respective channel portions of the transistors), allowing a variable (e.g., configurable, controllable) charge (e.g., voltage) level to be provided to output 260 via voltage source 225 or drained from output 260 via voltage source 230.

[0046] At one or more of nodes 210-a, a feedback signal from a feedback element (e.g., inverter 205-b) can oppose a forward signal along the main forward path. This signal opposition can reduce (e.g., compress, oppose, suppress) a voltage amplitude associated with the forward signal. Based on the reduced voltage level, the forward signal can transition faster from one voltage state (e.g., high voltage state, low voltage state) to a second voltage state (e.g., low voltage state, high voltage state) (e.g., based on a reduced voltage range traversed by the signal, which can be related to a given slew rate). Reducing the transition duration can cause the signal to be advanced (e.g., ahead of) in time domain, which can appear as an overall delay reduction at output 245. Moreover, the delay of the forward signal can accumulate at each node 210-a along the forward path (e.g., based on the accumulation of feedback signals along the forward path).

[0047] Based on possible implementations of the feedback elements (e.g., as inverters 205-b or other implementations), various options for delay control are possible in circuit 200. For example, the head and foot voltages of inverters 205-b can be controlled via feedback width control (e.g., via finger enablement and / or disablement) to enable and / or disable subsets of the feedback loops (e.g., enable every other feedback loop, enable every feedback loop in the first feedback path), or based on variable head and foot lengths (e.g., via source and drain tapping), among other implementations. Moreover, because the delay of delay circuit 200 can be based on the strength of the feedback signals from the feedback elements (e.g., as a function of strength), the delay can be controlled (e.g., modified) by adjusting the analog voltages on the head and foot gates of inverters 205-b (which can be performed asymmetrically across different inverters 205-b), among other feedback element implementations. For example, applying various analog voltages to the inverters 205-b and head and foot gates, delay circuit 200 can support adjusting the rise transition rate, fall transition rate, or transition point (e.g., crossing point, time of midpoint crossing between voltage states) of signals along delay circuit 200, or any combination thereof, which can support symmetric adjustment (e.g., using symmetric shifting of head and foot voltages) or asymmetric adjustment (e.g., using asymmetric shifting of head and foot voltages) of rise and fall transition rates, among other examples. Additionally or alternatively, the delay of delay circuit 200 can be modified via digital control of the head and foot gates of inverters 205-b. For example, digital control can include incrementally enabling and / or disabling additional legs of the head and foot gates (e.g., by increasing the number of head and foot transistors) or multiple legs of inverters 205-b. Moreover, head and / or foot transistors can be shared among one or more inverters 205-b (e.g., where the p-type transistor coupled with input 235-a-1 is shared among multiple inverters 205-b, where the n-type transistor coupled with input 235-a-3 is shared among multiple inverters 205-b).

[0048] In some examples, it can be advantageous to utilize voltages provided by a supply other than the supply for the delay chain used to control the delay. For example, adjusting the head or foot voltage used to control the delay can benefit from analog voltages applied to the gates that are higher than the nominal circuit voltage. In some examples, VPP (e.g., > 1.5 V) can be applied to enable / disable the strength of the feedback, while other circuits (e.g., the forward path and feedback circuits) can be powered by VDD (e.g., about 1.0 V).

[0049] As non-limiting examples, inverter 205-a is shown to include circuitry 215 and inverter 205-b is shown to include circuitry 220. However, inverter 205-a and inverter 205-b, as well as other delay elements and feedback elements, can include different circuitry than shown (e.g., other transistor circuitry or other circuitry that implements an electrical inversion operation). For example, inverter 205-a, inverter 205-b, or both, can be implemented with one or more logic elements (e.g., NAND gates), which can support other logic functions, improve delay control, improve energy savings, or other logic operations contemplated. In some examples, inverter 205-a can instead be implemented with circuitry 220 (e.g., as a tri-stable inverter). For example, inverter 205-a can also be associated with a head voltage source and a foot voltage source, which can allow for deactivation of the forward path and reduce leakage current. In some examples, inverter 205-a, inverter 205-b, or both, can have different sizes (e.g., channel widths, at different locations along the forward path between input 240 and output 245) and can have inputs and outputs associated with different physical lengths (e.g., different signal path lengths). For example, the size of each inverter 205-a along the forward path can increase relative to the previous inverter 205-a. Additionally or alternatively, the length (e.g., trace length, conductive wire length) can increase after each inverter 205-a. Such variations in inverter size and path length can improve signal integrity at output 245.

[0050] Figure 3 Examples of timing diagram 300-a and timing diagram 300-b that support signal delay control with inverted feedback according to examples disclosed herein are shown. Timing diagram 300 illustrates examples of circuit 200 operating according to different configurations, including different signals of different nodes of different configurations. For example, graph 310-a-l and graph 310-b-l can show signals at a first node (e.g., input 240) of circuit 200 during a window of time (e.g., time to t3), graph 310-a-3 and graph 310-b-3 can show signals at a third node (e.g., output 245, node 210-a-9) of circuit 200, and graph 310-a-2 and graph 310-b-2 can show signals at a second node (e.g., an internal node, one of nodes 210-a-l to 210-a-8) between the first node and the third node of circuit 200. Timing diagram 300-a can be associated with a first configuration of circuit 200, in which one or more feedback elements (e.g., inverter 205-b) are deactivated (e.g., no feedback signal is introduced into the forward signal path). Timing diagram 300-b can be associated with a second configuration, in which the one or more feedback elements are at least partially activated (e.g., a counteracting feedback signal is provided into the forward signal path).

[0051] Circuit 200 can receive a first signal (e.g., a timing signal, a data signal, a control signal, a command signal) at an input 240 (e.g., of a chain of delay elements, of an inverter chain 205-a). The input signal can be shown in FIG. 310-a-l and FIG. 310-b-l. The delay can be accumulated by each stage of circuit 200 along the forward path (e.g., by successive delay elements, at successive nodes 210-a). For example, FIG. 310-a-2 and FIG. 310-b-2 can show the forward signal at an intermediate node (e.g., node 210-a-5) of circuit 200 between input 240 and output 245. That is, the signal can have been processed by one or more delay elements (e.g., other nodes, such as node 210-a-3 and node 210-a-4) before the signal of FIG. 310-a-2 and 310-b-2, and can be further processed by one or more additional delay elements (e.g., other nodes, such as node 210-a-6 and node 210-a-7) after the signal of FIG. 310-a-2 and 310-b-2. Circuit 200 can generate a second signal at output 245 based on receiving the first signal, and the second signal can have a delay relative to the first signal. FIG. 310-a-3 and FIG. 310-b-3 can show the delayed signal at output 245.

[0052] Generating the second signal can be based on the at least one first delay element (e.g., first inverter 205-a, such as inverter 205-a-7) having an output coupled with an input of a respective previous second delay element (e.g., second inverter 205-a, such as inverter 205-a-6, at node 210-a-5) via a feedback element (e.g., a feedback inverter, such as inverter 205-b-3, that is not along the forward path), the feedback element configured to send an inhibitory signal to the input of the previous delay element (e.g., sending the inverted signal of node 210-a-7 to node 210-a-5). In some examples, generating the second signal can be based on the output of the previous second delay element being directly coupled with the input of the at least one first delay element (e.g., as a pair of inverters 205-a associated with a respective feedback inverter 205-b, such as paired inverters 205-a-6 and 205-a-7). In some examples, generating the second signal can be based on the output of a respective feedback element (e.g., inverter 205-b, such as inverter 205-b-3) being directly coupled with the input of another feedback element (e.g., another inverter 205-b, such as inverter 205-b-2).

[0053] The delay of the signal at output 245 relative to input 240 can be based on the reduction of the voltage level provided to the input of a delay element (e.g., inverter 205-a, e.g., inverter 205-a-6) along the forward path based on the output of a feedback element (e.g., inverter 205-b, e.g., inverter 205-b-3). For example, as illustrated in FIG. 310-b-2, the voltage range associated with at least a portion of the input signal is reduced (e.g., compressed relative to the signal of FIG. 310-a-2) from an initial range V0 to VI to a compressed range of V2 to V3. In some examples, the signal can include an overshoot 320, which can be associated with the opposing feedback signal (e.g., a delay of the signal from node 210-a-7 relative to the signal from node 210-a-5 of one or more of inverters 205-a-7, 205-a-8, and 205-b-3). However, in some other examples, the overshoot 320 can not be present, which can be related to the degree of capacitance at node 205-a-5, the amount of delay along the forward path or along the feedback path, and other electrical characteristics.

[0054] The voltage reduction (e.g., associated with the suppression of the inverting feedback signal, following the overshoot 320, where applicable) can result in the rising and falling edges of the signal transitioning from one voltage state to another voltage state at a given node 210-a or inverter 205-a in a relatively short duration (e.g., which can be the same or similar for a given slew rate for different configurations of circuit 200). For example, for the signal illustrated by FIG. 310-a-2, where the suppression feedback signal can be disabled, the transition between signal states can involve a duration Ati, while for the signal illustrated by FIG. 310-b-2, where the suppression signal can be enabled (e.g., by inverter 205-b-3), the transition between signal states can involve a duration At2 that is shorter than Ati associated with a shorter delay (e.g., at the output of inverter 205-a-6, at the output of inverter 205-a-7). Thus, the amount of time involved for a given signal transition can be configured based on the amount of suppression feedback provided along the forward path. Such delays (e.g., shortened delays, compressed delays) can accumulate at each stage of circuit 200 (e.g., through multiple nodes 210-a), which can reduce the overall delay at output 245 relative to input 240. For example, FIGS. 310-a-3 and 310-b-3 can show a difference between the crossing point of the signal at time t8 in FIG. 310-b-3 (e.g., in the case where one or more of the feedback inverters 205-b are at least partially activated) and the crossing point of the signal at time t9 in FIG. 310-a-3 (e.g., in the case where the feedback inverters 205-b are deactivated). Thus, activating one or more feedback elements according to timing diagram 300-b can be associated with an overall delay that is shortened by a duration At3.

[0055] Circuit 200 can be configured to control a delay of the input signal by adjusting one or more voltage values of respective voltage source 265 and respective voltage source 270. For example, inverter 205-b can be a respective tri-state inverter, and a first voltage can be applied (e.g., by voltage source 265) at a first input (e.g., input 235-a-l) of the respective tri-state inverter. Further, a second voltage can be applied (e.g., by voltage source 270) at a second input (e.g., input 235-a-3) of inverter 205-b. Accordingly, a delayed second signal can be generated based on the application of the first voltage and the application of the second voltage, while a third input (e.g., input 235-a-2) of the respective tri-state inverter can be coupled with the output of inverter 205-a along the forward path.

[0056] In some examples, generating the second signal can include controlling a value of a delay relative to the first signal based on a first value of respective voltage source 265 and a second value of respective voltage source 270. In some examples, voltage source 265 (e.g., a head voltage source) and voltage source 270 (e.g., a foot voltage source) can have complementary gate bias values (e.g., a sum of the values of voltage source 265 and voltage source 270 can equal a threshold voltage, such as 1 volt). In some examples, voltage source 265 and voltage source 270 can be adjusted in relatively small increments (e.g., in an analog manner), which can support fine tuning of a delay value at output 245. That is, by adjusting analog voltages of head and foot inputs (e.g., inputs 235-a-l and 235-a-3, respectively) at inverter 205-b, an electronic device can increase or decrease a delay (e.g., a time difference between t8 and t9) according to the analog voltage values to achieve a target delay (e.g., a target rise transition rate of a signal, a target fall transition rate of a signal, a target transition crossing point of a signal, or a combination thereof) at output 245. In additional or alternative examples, an electronic device can control head and foot inputs of inverter 205-b in a digital manner. For example, an electronic device can enable or disable a subset of inverters 205-b in circuit 200 to achieve a target delay value (e.g., a target rise transition rate of a signal, a target fall transition rate of a signal, a target transition crossing point of a signal, or a combination thereof). Further, regardless of the case, an electronic device can control all voltage sources 265 (e.g., with a same first voltage value) and voltage sources 270 (e.g., with a same second voltage value) of inverters 205-b uniformly, or can control each of voltage sources 265 and voltage sources 270 (e.g., with different respective voltage values) of inverters 205-b independently.

[0057] In some examples, the circuits and timing diagrams described herein can be implemented in the context of calibrating and minimizing transitions between different phases of a clock. For example, the circuits and timing diagrams can be implemented in a two-phase clocking, where complementary clock signals are transmitted or otherwise sent together, but only the rising (or falling) portion of each of the two complements is employed. Depending on the routing context and / or gate delays on the IC, there can be some systematic misalignment of the timing of the complementary signals, which can otherwise result in a loss of timing margin. The present disclosure allows for one or both of the complementary clock signals to be adjusted in time relative to the complement, thereby maximizing the margin. Such adjustments can be made during probe testing or another testing phase of manufacture (e.g., of an associated device) or in the field through closed-loop control of the delay.

[0058] In other examples, the circuits and timing diagrams described herein can be implemented in the context of optimizing the timing of a clock at a data sampler or flip-flop. Such timing adjustments can maximize the timing margin of the clock signal.

[0059] Accordingly, an electronic device can include one or more instances of circuit 200 to support increasing the range of delay adjustments (e.g., to fine-tune delays over a relatively large range), which can enable more efficient operation in electronic systems that utilize delay circuits (e.g., memory system 110, host system 105, memory device 145). Additionally, the techniques described herein can increase the speed of the last edge (e.g., at a nearly constant slew rate) rather than decreasing the speed of the last edge (e.g., instead of adding capacitance to slow down the edge), and can reduce the accumulation of signal fluctuations (e.g., reduce jitter accumulation). Moreover, one or more feedback paths can also counteract signal attenuation (e.g., associated with high frequency signals), which can simultaneously control signal-to-signal interference and enable relatively high processing bandwidths (e.g., high speed data movement).

[0060] Figure 4 A flow diagram illustrating a method 400 that supports signal delay control with inverted feedback in accordance with examples as disclosed herein is shown. The operations of method 400 can be implemented by an electronic device or its components as described herein. For example, the operations of method 400 can be performed by an electronic device as described with reference to FIGS. 1-2 and 5-7. Figures 1 to 3 The electronic device described can execute a set of instructions that are stored in one or more storage elements to perform the functions described. Additionally or alternatively, the electronic device can perform one or more steps of the functions described using special-purpose hardware.

[0061] At 405, the method can include receiving a first signal at an input (e.g., input 240) of a delay circuit (e.g., delay circuit 200), the delay circuit including a plurality of delay elements (e.g., inverters 205-a or other delay elements) coupled in series along a sequence of alternating odd and even nodes (e.g., nodes 210) between an input and an output of the delay circuit.

[0062] At 410, the method can include generating a second signal at an output of the delay circuit based at least in part on receiving the first signal, the second signal having a delay relative to the first signal, where generating the second signal is based at least in part on sending a respective first inverted signal of at least one of the even nodes (e.g., via a feedback element, via inverter 205-b) to a corresponding previous one of the even nodes along the sequence, sending a respective second inverted signal of at least one of the odd nodes to a corresponding previous one of the odd nodes along the sequence, or a combination thereof.

[0063] In some examples, an apparatus described herein can perform one or more methods, such as method 400. An apparatus can include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing aspects of the disclosure, or any combination thereof:

[0064] Aspect 1 : A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions for, or any combination thereof: receiving a first signal at an input (e.g., input 240) of a delay circuit (e.g., delay circuit 200), the delay circuit including a plurality of delay elements (e.g., inverters 205-a or other delay elements) coupled in series between the input and an output of the delay circuit along a sequence of alternating odd nodes and even nodes (e.g., nodes 210); and generating a second signal at the output of the delay circuit based at least in part on receiving the first signal, the second signal having a delay relative to the first signal, where generating the second signal is based at least in part on sending a respective first inverted signal of at least one of the even nodes (e.g., via a feedback element, via inverter 205-b) to a corresponding previous one of the even nodes along the sequence, sending a respective second inverted signal of at least one of the odd nodes to a corresponding previous one of the odd nodes along the sequence, or a combination thereof.

[0065] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, where generating the second signal is based at least in part on the corresponding previous one of the even nodes being an even node immediately preceding the corresponding one of the even nodes or the corresponding previous one of the odd nodes being an odd node immediately preceding the corresponding one of the odd nodes, or both.

[0066] Aspect 3: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-2, wherein the delay of the second signal relative to the first signal is based at least in part on the inverted signal corresponding to the one of the even nodes decreasing a voltage at the corresponding one of the even nodes or the inverted signal corresponding to the one of the odd nodes decreasing a voltage at the corresponding one of the odd nodes, or a combination thereof.

[0067] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-3, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination thereof: generating the respective first inverted signal, generating the respective second inverted signal, or both, via a respective tri-stable inverter (e.g., according to circuit 220).

[0068] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of aspect 4, wherein generating the respective first inverted signal, generating the respective second inverted signal, or both, is based at least in part on applying a first voltage at a first input (e.g., input 235-a-l) of the respective tri-stable inverter and applying a second voltage at a second input (e.g., input 235-a-3) of the respective tri-stable inverter.

[0069] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of aspect 5, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination thereof: controlling a value of the delay relative to the first signal based at least in part on controlling a first value of the first voltage and controlling a second value of the second voltage.

[0070] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-6, wherein generating the second signal is based at least in part on an output of a last delay element along the sequence being coupled with an input of the last delay element via an even number of inverters (e.g., a pair of inverters 205-b, inverters 205-b-8 and 205-b-9).

[0071] It should be noted that the aspects described herein describe possible implementations, and that the operations and steps can be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods can be combined.

[0072] An apparatus is described. An overview of aspects of the apparatus described herein is provided below:

[0073] Aspect 8: An electronic device, comprising: an input terminal (e.g., input 240); an output terminal (e.g., output 245); and a delay circuit (e.g., delay circuit 200), comprising: a plurality of delay elements (e.g., inverters 205-a) coupled in series between the input terminal and the output terminal along a sequence of alternating odd nodes and even nodes (e.g., nodes 210); one or more first feedback elements (e.g., inverters 205-b) each configured to send an inverted first signal of a corresponding one of the even nodes to a corresponding preceding one of the even nodes along the sequence; and one or more second feedback elements (e.g., inverters 205-b) each configured to send an inverted second signal of a corresponding one of the odd nodes to a corresponding preceding one of the odd nodes along the sequence.

[0074] Aspect 9: The electronic device of Aspect 8, wherein for at least one of the one or more first feedback elements, the corresponding preceding one of the even nodes is an even node immediately preceding the corresponding one of the even nodes, or for at least one of the one or more second feedback elements, the corresponding preceding one of the odd nodes is an odd node immediately preceding the corresponding one of the odd nodes, or both.

[0075] Aspect 10: The electronic device of any of Aspects 8-9, wherein an output of at least one of the one or more first feedback elements is directly coupled with an input of another of the one or more first feedback elements, or an output of at least one of the one or more second feedback elements is directly coupled with an input of another of the one or more second feedback elements, or both.

[0076] Aspect 11: The electronic device of any of Aspects 8-10, wherein a delay of the delay circuit between the output terminal and the input terminal is based at least in part on a reduction in voltage at the corresponding preceding one of the even nodes corresponding to the inverted first signal of the one of the even nodes or a reduction in voltage at the corresponding preceding one of the odd nodes corresponding to the inverted second signal of the one of the odd nodes, or a combination thereof.

[0077] Aspect 12: The electronic device of any of Aspects 8-11, wherein at least one of the one or more first feedback elements or at least one of the one or more second feedback elements or both include: a first input (e.g., input 235-a-1) coupled with a first voltage source (e.g., voltage source 265); and a second input (e.g., input 235-a-3) coupled with a second voltage source (e.g., voltage source 270), wherein a delay of the delay circuit between the output terminal and the input terminal is based at least in part on a first voltage of the first voltage source and a second voltage of the second voltage source.

[0078] Aspect 13: The electronic device of any of Aspects 8-12, wherein an output of a last delay element along the sequence is coupled with an input of the last delay element via an even number of inverters.

[0079] Aspect 14: The electronic device of any of Aspects 8-13, wherein at least one of the plurality of delay elements includes a p / n inverter (e.g., according to circuit 215).

[0080] Aspect 15: The electronic device of any of Aspects 8-14, wherein at least one of the plurality of delay elements includes a tri-stable inverter (e.g., according to circuit 220).

[0081] Aspect 16: The electronic device of any of Aspects 8-15, wherein at least one of the one or more first feedback elements, at least one of the one or more second feedback elements, or both include a tri-stable inverter (e.g., according to circuit 220).

[0082] Aspect 17: The electronic device of any of Aspects 8-16, wherein at least one of the one or more first feedback elements, at least one of the one or more second feedback elements, or both include a NAND gate.

[0083] An apparatus is described. A summary of aspects of the apparatus described herein is provided below:

[0084] Aspect 18: A memory device (such as the memory device 145) including: one or more memory arrays (such as the memory array 155); a signal source associated with a first signal; and a delay circuit (such as the delay circuit 200) configured to generate, based at least in part on receiving the first signal from the signal source, a second signal associated with accessing the one or more memory arrays having a delay relative to the first signal, the delay circuit including: a plurality of delay elements (such as the inverters 205-a) coupled in series along a sequence of alternating odd and even nodes (such as the nodes 210) between an input of the delay circuit and an output of the delay circuit; one or more first feedback elements (such as the inverters 205-b) each configured to send, along the sequence, an inverted first signal of a corresponding one of the even nodes to a corresponding previous one of the even nodes; and one or more second feedback elements (such as the inverters 205-b) each configured to send, along the sequence, an inverted second signal of a corresponding one of the odd nodes to a corresponding previous one of the odd nodes.

[0085] Aspect 19: The memory device of Aspect 18, wherein the delay is based at least in part on the inverted first signal corresponding to the one of the even nodes reducing a voltage at the corresponding previous one of the even nodes or the inverted second signal corresponding to the one of the odd nodes reducing a voltage at the corresponding previous one of the odd nodes, or a combination thereof.

[0086] Aspect 20: The memory device of any of Aspects 18-19, wherein: at least one of the plurality of delay elements includes a p / n inverter (such as according to the circuit 215); and at least one of the one or more first feedback elements, at least one of the one or more second feedback elements, or both, include a tri-stable inverter (such as according to the circuit 220).

[0087] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or symbols, which can be referenced throughout the above description, can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, such signals can represent a bus of signals, where buses can have a variety of bit widths.

[0088] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components in which the components support the flow of signals between the components. Components can be considered in electronic communication (e.g., in conductive contact, connected, coupled) with each other if there exists any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. The conductive path between components in electronic communication (e.g., in conductive contact, connected, coupled) with each other can be open or closed based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components or can be an indirect conductive path that includes intermediate components (e.g., switches, transistors, or other components). In some examples, the flow of signals between connected components can be interrupted, for example, using one or more intermediate components (e.g., switches or transistors) for a period of time.

[0089] The term "isolated" can refer to a relationship between components in which signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, when a switch positioned between two components is open, the components separated by the switch are isolated from each other. When a component isolates two components, the component can cause a change that prevents signals from flowing between the other components using a conductive path that previously permitted the flow of signals.

[0090] The term "coupled" (e.g., "electrically coupled") can refer to a condition that transforms an open circuit relationship between components (in which signals cannot currently be communicated (e.g., via a conductive path) between the components) to a closed circuit relationship between the components (in which signals can be communicated (e.g., via a conductive path) between the components). When a component, such as a controller, couples other components together, the component can cause a change that permits signals to flow between the other components via a conductive path that previously did not permit the flow of signals.

[0091] The switching components (e.g., transistors) discussed herein can be field effect transistors (FETs) and can include a source (e.g., source terminal), a drain (e.g., drain terminal), a channel between the source and the drain, and a gate (e.g., gate terminal). The conductivity of the channel can be controlled (e.g., modulated) by applying a voltage to the gate, which in some examples can cause the channel to become conductive. The switching components can be examples of n-type FETs or p-type FETs.

[0092] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0093] In the drawings, like reference numerals can be used to denote like components throughout the several views. Like components can be further denoted by the use of a prefix with a hyphen and a following number to indicate like components grouped together. If only the first reference numeral is used in the specification, the description is applicable to any one of the likewise components having the same first reference numeral irrespective of the extra reference numerals.

[0094] The functions described herein can be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions can be stored on or transmitted over as one or more instructions (e.g., code) on a computer-readable medium. The functions described herein can be implemented using software, hardware, firmware, hardwiring, or a combination of any of these methods and approaches. Features described herein can be physically located in various places, including being distributed such that portions of functions are implemented at different physical locations.

[0095] The illustrative blocks and modules described herein can be implemented or performed with one or more processors (e.g., DSPs, ASICs, FPGAs, discrete logic circuitry, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof) designed to perform the functions described herein. A processor can be an example of a microprocessor, controller, microcontroller, state machine, or other types of processor. A processor can also be implemented as at least one of a plurality of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0096] As used herein, including in the claims, “or” as used in a list of items (for example, the phrase “at least one of A, B, or C”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0097] As used herein (including in the claims), the article "a" or "an" preceding a noun is open-ended and should be understood to refer to "at least one" of these nouns or "one or more" of these nouns. Thus, the terms "a," "at least one," "one or more," and "at least one of one or more" are interchangeable. For example, if a claim recites "a component" that performs one or more functions, each of the individual functions may be performed by a single component or any combination of multiple components. Thus, the term "a component" having a characteristic or performing a function may refer to "at least one of one or more components" having a specific characteristic or performing a specific function. Subsequent use of the term "the / said" to refer to a component introduced with the article "a" may refer to any or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components," and subsequent reference to "the component" in a claim may be understood to be equivalent to referring to "at least one of the one or more components." Similarly, subsequent use of the term "the" or "said" to refer to a component introduced as "one or more components" may refer to any or all of the one or more components. For example, subsequent reference to "one or more components" in a claim may be understood as equivalent to referring to "at least one of the one or more components."

[0098] Computer-readable media includes both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media or combination of media that can be accessed by a computer. By way of example, but not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a computer or one or more processors.

[0099] The description and drawings are provided to enable one of ordinary skill in the art to make or use the present disclosure. Various modifications of the present disclosure will be apparent to one of ordinary skill in the art, and the techniques disclosed herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An electronic device comprising: an input terminal; an output terminal; and a delay circuit comprising: a plurality of delay elements coupled in series between the input terminal and the output terminal along a sequence of alternating odd nodes and even nodes; one or more first feedback elements each configured to send an inverted first signal of a corresponding one of the even nodes to a corresponding preceding one of the even nodes along the sequence; and one or more second feedback elements each configured to send an inverted second signal of a corresponding one of the odd nodes to a corresponding preceding one of the odd nodes along the sequence.

2. The electronic device of claim 1, wherein for at least one of the one or more first feedback elements, the corresponding preceding one of the even nodes is an even node immediately preceding the corresponding one of the even nodes, or for at least one of the one or more second feedback elements, the corresponding preceding one of the odd nodes is an odd node immediately preceding the corresponding one of the odd nodes, or both.

3. The electronic device of claim 1, wherein an output of at least one of the one or more first feedback elements is directly coupled with an input of another of the one or more first feedback elements, or an output of at least one of the one or more second feedback elements is directly coupled with an input of another of the one or more second feedback elements, or both.

4. The electronic device of claim 1, wherein a delay of the delay circuit between the output terminal and the input terminal is based at least in part on the inverted first signal corresponding to the one of the even nodes reducing a voltage at the corresponding preceding one of the even nodes or the inverted second signal corresponding to the one of the odd nodes reducing a voltage at the corresponding preceding one of the odd nodes, or a combination thereof.

5. The electronic device of claim 1, wherein at least one of the one or more first feedback elements or at least one of the one or more second feedback elements, or both, comprises: a first input coupled with a first voltage source; and a second input coupled with a second voltage source, wherein a delay of the delay circuit between the output terminal and the input terminal is based at least in part on a first voltage of the first voltage source and a second voltage of the second voltage source.

6. The electronic device of claim 1, wherein an output of a last delay element along the sequence is coupled with an input of the last delay element via an even number of inverters.

7. The electronic device of claim 1, wherein at least one of the plurality of delay elements comprises a p / n inverter.

8. The electronic device of claim 1, wherein at least one of the plurality of delay elements comprises a tri-stable inverter.

9. The electronic device of claim 1, wherein at least one of the one or more first feedback elements, at least one of the one or more second feedback elements, or both, comprises a tri-stable inverter. ​ 10. The electronic device of claim 1, wherein at least one of the one or more first feedback elements, at least one of the one or more second feedback elements, or both comprise a NAND gate.

11. A method at an electronic device, comprising: receiving a first signal at an input of a delay circuit, the delay circuit including a plurality of delay elements coupled in series along a sequence of alternating odd nodes and even nodes between the input and an output of the delay circuit; and generating a second signal at the output of the delay circuit based at least in part on receiving the first signal, the second signal having a delay relative to the first signal, wherein generating the second signal is based at least in part on sending a respective first feedback signal of at least one of the even nodes to a corresponding preceding one of the even nodes along the sequence, sending a respective second feedback signal of at least one of the odd nodes to a corresponding preceding one of the odd nodes along the sequence, or a combination thereof.

12. The method of claim 11, wherein generating the second signal is based at least in part on the corresponding preceding one of the even nodes being an even node immediately preceding the corresponding one of the even nodes or the corresponding preceding one of the odd nodes being an odd node immediately preceding the corresponding one of the odd nodes or both.

13. The method of claim 11, wherein the delay of the second signal relative to the first signal is based at least in part on the feedback signal corresponding to the one of the even nodes reducing a voltage at the corresponding preceding one of the even nodes or the feedback signal corresponding to the one of the odd nodes reducing a voltage at the corresponding preceding one of the odd nodes or a combination thereof.

14. The method of claim 11, further comprising: generating the respective first feedback signal, generating the respective second feedback signal, or both via a respective tri-stable inverter.

15. The method of claim 14, wherein generating the respective first feedback signal, generating the respective second feedback signal, or both is based at least in part on applying a first voltage at a first input of the respective tri-state inverter and applying a second voltage at a second input of the respective tri-state inverter.

16. The method of claim 15, further comprising: controlling a value of the delay relative to the first signal based at least in part on controlling a first value of the first voltage and controlling a second value of the second voltage.

17. The method of claim 11, wherein generating the second signal is based at least in part on an output of a last delay element along the sequence being coupled with an input of the last delay element via an even number of inverters.

18. A memory device, comprising: one or more memory arrays; a signal source associated with a first signal; and a delay circuit including a plurality of delay elements coupled in series along a sequence of alternating odd nodes and even nodes between the input and an output of the delay circuit, wherein the delay circuit is configured to generate a second signal at the output of the delay circuit based at least in part on receiving the first signal, the second signal having a delay relative to the first signal, wherein the delay circuit is configured to generate the second signal based at least in part on sending a respective first feedback signal of at least one of the even nodes to a corresponding preceding one of the even nodes along the sequence, sending a respective second feedback signal of at least one of the odd nodes to a corresponding preceding one of the odd nodes along the sequence, or a combination thereof. a delay circuit configured to generate, based at least in part on receiving the first signal from the signal source, a second signal associated with accessing the one or more memory arrays and having a delay relative to the first signal, the delay circuit comprising: a plurality of delay elements coupled in series along a sequence of alternating odd nodes and even nodes between an input of the delay circuit and an output of the delay circuit; one or more first feedback elements each configured to send, along the sequence, an inverted first signal of a corresponding one of the even nodes to a corresponding preceding one of the even nodes; and one or more second feedback elements each configured to send, along the sequence, an inverted second signal of a corresponding one of the odd nodes to a corresponding preceding one of the odd nodes.

19. The memory device of claim 18, wherein the delay is based at least in part on the inverted first signal corresponding to the one of the even nodes reducing a voltage at the corresponding preceding one of the even nodes or the inverted second signal corresponding to the one of the odd nodes reducing a voltage at the corresponding preceding one of the odd nodes, or a combination thereof.

20. The memory device of claim 18, wherein: at least one of the plurality of delay elements comprises a p / n inverter; and at least one of the one or more first feedback elements, at least one of the one or more second feedback elements, or both, comprises a tri-stable inverter.

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