Method and system for synchronizing analog-to-digital converters

Abstract

The invention relates to a method and system for synchronizing analog-to-digital converters. A method for synchronizing an analog-to-digital converter (ADC), the method comprising: a processor stopping sending a master clock signal to the ADC to suspend sampling of the ADC, the master clock signal being provided to the ADC by an external master clock; the ADC detects that a synchronization event has occurred when the master clock is stopped; rebooting, by the processor, a master clock signal to the ADC; the ADC resets an internal filter at a time synchronized with the master clock; and the ADC restores sampling in response to resetting an internal filter of the ADC.

Description

[0001] Priority

[0002] This application claims priority to US non-provisional application no. 18 / 641803. TECHNICAL FIELD

[0003] The present disclosure relates generally to methods and systems for synchronizing an analog-to-digital converter (ADC) and synchronizing two or more ADCs. More specifically, but not exclusively, the present disclosure relates to methods and systems for synchronizing an ADC or synchronizing two or more ADCs by stopping and starting a single master clock signal. BACKGROUND

[0004] Multi-channel instruments often require simultaneous sampling, and use an oversampling ADC to sample an input multiple times to produce one data output, which results in an output frequency lower than the sampling frequency. If the outputs are not synchronized due to decimation, individual channels of a multi-channel instrument can produce outputs at very different phases. In order to achieve accurate and reliable data acquisition in multi-channel, high-speed sampling applications, ADC synchronization at the output is used, and precise timing relationships between the output signals are desired. Furthermore, in certain devices and instruments, there are specific IEEE requirements and standards for the synchronization scheme.

[0005] However, the ADC synchronization process is not simple when multiple ADCs are involved, and can require complex hardware circuitry. The hardware circuitry can typically include multiple input / output devices and multiple system clocks.

[0006] Therefore, there is a need for an improved method and system for operating an ADC or two or more ADCs to ensure adequate synchronization. SUMMARY

[0007] In an ADC system, the ADC continuously performs sampling, i.e., samples an input and produces an output. In particular, in an oversampling ADC system, the ADC samples an input multiple times to produce one data output. In many cases, multiple ADCs share the same master clock signal, and thus sample an input at the same time. However, they can not produce outputs at the same time. This creates synchronization issues between the multiple ADCs in the system, and can result in phase errors in the measurements.

[0008] For example, in the context of a multi-channel instrument, the instrument utilizes an oversampled ADC to sample an input value multiple times to produce a single data output. This means that there is a risk of an increase in phase error between the various instrument channel outputs of a multi-channel instrument. This is a particular problem in systems and devices where components that require synchronized sampling are located geographically far apart from each other. Therefore, there is a need to synchronize the sampling of individual ADCs within a system with respect to a time reference to ensure a reduction in phase error. This in turn enables the operation or synchronization of the ADC system with precise timing relationships between the outputs.

[0009] The present disclosure relates to methods for operating and synchronizing an ADC system. The ADC system can comprise a single ADC or multiple ADCs. The present disclosure provides a method comprising stopping a master clock of the ADC system such that the ADC stops normal operation, e.g. sampling of an input signal. The ADC system then receives or detects information that suggests that the ADC should perform a synchronization with a time reference. Upon restarting the master clock, internal circuitry of the ADC triggers a resumption of ADC sampling. The resumption of ADC sampling can therefore be predictably restarted at a determined time after the master clock is restarted. This method can be used to ensure a predictable restart of ADC sampling with respect to a time reference for a single ADC or multiple ADCs. The present disclosure therefore seeks to provide methods and systems for enabling an ADC system to operate or synchronize with precise timing relationships between the outputs.

[0010] Furthermore, the present disclosure provides methods and systems for synchronizing an ADC or two or more ADCs such that they are time reference synchronized in a robust, reliable and efficient manner. In other words, these methods and systems seek to provide ADC time reference synchronization while significantly reducing phase error in the outputs, reducing complexity of hardware and software, minimizing hardware footprint and improving predictability of synchronization.

[0011] The present disclosure provides an ADC system and a multi-ADC system comprising two or more ADCs. In both systems, the system can comprise at least one ADC, a processor and a master clock. The master clock is a device external to the one or more ADCs. In the system with multiple ADCs, the ADCs are arranged such that all ADCs share the master clock. In conjunction with the ADC system, the present disclosure provides a method of operating the ADC system. The method comprises stopping the master clock of the ADC by the processor and pausing sampling, then triggering or detecting a synchronization event on the ADC while the master clock is stopped. Next, the method restarts the master clock of the ADC. Upon the master clock being restarted, an internal filter of the ADC is reset at a time that is synchronized with the master clock being restarted, thereby restarting sampling of the ADC in response to the reset of the internal filter. The sampling of the one or more ADCs can be synchronized with respect to a time reference.

[0012] In a first aspect, there is provided a method for synchronizing an analog-to-digital converter, ADC. The method comprises: a processor stopping sending a master clock signal to the ADC to pause sampling of the ADC, the master clock being provided to the ADC by an external master clock; the ADC detecting that a synchronization event has occurred at the time the master clock was stopped; the master clock signal being restarted to the ADC by the processor; the ADC resetting an internal filter at a time synchronized with the master clock; and the ADC resuming sampling in response to resetting the internal filter of the ADC.

[0013] The method for synchronizing an ADC provides the advantage of enabling the ADC to be used in a robust and reliable manner, as the ADC can be used in conjunction with other ADCs without creating phase errors between the outputs of the ADCs, e.g. the ADCs are time reference synchronized. This is because it enables synchronization of multiple ADCs without the need for a separate synchronization signal, nor the need for isolated components. This allows for reduced system complexity, reduced hardware cost, and limits possible points of failure, among others.

[0014] In a second aspect, there is provided a method for synchronizing two or more analog-to-digital converters, ADCs, the method comprising: a processor stopping sending a shared master clock signal to the two or more ADCs to pause sampling of the two or more ADCs, the shared master clock being provided to the two or more ADCs by an external master clock; detecting, by each of the two or more ADCs, that a synchronization event has occurred at the time the shared master clock was stopped; restarting the shared master clock signal to each of the two or more ADCs by the processor; resetting, by each of the two or more ADCs, an internal filter at a time synchronized with the master clock; and resuming sampling, by the two or more ADCs, in response to resetting their respective internal filters.

[0015] The method for synchronizing two or more ADCs provides the advantage of enabling the ADCs to be used without phase errors between the outputs. In some examples, the two or more ADCs can be oversampled ADCs, so the method ensures that the two or more ADCs sample the input signal synchronously with respect to a time reference. By ensuring that all ADCs within a system are used in a robust and reliable manner, eliminating phase errors can improve system performance.

[0016] In a third aspect, there is provided an analog-to-digital converter, ADC, system, the system comprising: an ADC comprising an internal filter; a master clock, the master clock being external to the ADC and coupled with the ADC; and a processor, the processor being external to and coupled with the ADC and the master clock; and a memory and computer program code stored thereon, wherein the computer program code, when executed by the processor, causes: the processor to stop sending a master clock signal to the ADC to pause sampling of the ADC, the master clock being provided to the ADC by an external master clock; the ADC to detect that a synchronisation event has occurred at the time the master clock was stopped; the master clock signal to the ADC to be restarted by the processor; the ADC to reset the internal filter at a time synchronised with the master clock; and the ADC to resume sampling in response to resetting the internal filter of the ADC.

[0017] The method for synchronising ADCs provides the advantage of enabling the ADCs to be used in a robust and reliable manner, as the ADCs can be used in conjunction with other ADCs without creating phase errors between the outputs of the ADCs, e.g. the ADCs are time reference synchronised. This is because it enables the synchronisation of multiple ADCs without the need for a separate synchronisation signal, nor the need for isolating components. This allows for reduced system complexity, reduced hardware cost, and limits the possible points of failure, amongst others.

[0018] Further features and advantages will be apparent from the claims that follow.

[0019] Definitions

[0020] In this context, “synchronisation” relates to ensuring that the sampling of each ADC starts at a particular known time. Thus, it can be said that synchronisation relates to time reference synchronisation, where the multiple ADCs do not necessarily need to sample at the same speed, as long as the multiple ADCs can all be initiated at the required particular time.

[0021] “Master clock” refers to a clock signal provided to the ADC from an external clock device or source. The master clock is distinct from the internal clock of the ADC. In a system where multiple ADCs are present, the master clock is a shared master clock, as the same external clock device or source is coupled to all of the multiple ADCs within the system.

[0022] “Internal clock” relates to a clock signal present within any ADC. This clock signal is the clock signal required for the commands to perform the general operation of the ADC.

[0023] “Synchronisation event” relates to some stimulus received by the ADC or detected by the ADC that indicates that the ADC needs or is being instructed to attempt to synchronise the sampling of the ADC with respect to a time reference. The form of this stimulus can be the receipt of a command from a processor, or the detection of any environmental change within the ADC, such as the stopping of the master clock, amongst others.

[0024] The term "internal filter" refers to a component within the ADC's internal circuitry. The internal filter is a device within the ADC that is reset when a synchronization event is detected or indicated. The indication of a synchronization event and the subsequent resetting of the internal filter enable the ADC to resume continuous sampling. During normal operation of the ADC or an oversampled ADC, the internal filter (or internal digital filter) processes the ADC's samples and averages them to digitally filter them. In oversampled ADCs, this process reduces the sampling rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features and advantages of the present disclosure will become apparent from the following description, which is given by way of example only, with reference to the accompanying drawings, in which like reference numerals represent like parts, and in which:

[0026] Figure 1 shows an example schematic diagram of a multi-synchronous ADC system according to one method;

[0027] Figure 2 Shown according to a method Figure 1 Example timing diagram of a multi-synchronous ADC system;

[0028] Figure 3 shows an example schematic diagram of a channel-isolated DAQ system according to one approach;

[0029] Figure 4a shows an example schematic diagram of an ADC according to the present disclosure;

[0030] Figure 4b shows an example schematic diagram of an ADC according to the present disclosure;

[0031] Figure 5 shows an example schematic diagram of an FPGA system according to the present disclosure;

[0032] Figure 6 An example schematic diagram of an MCU system according to the present disclosure is shown.

[0033] Figure 7 Shows the Figure 4a Example timing diagram for use with an ADC system;

[0034] Figure 8 Shows the Figure 4b Example timing diagram for use with an ADC system;

[0035] Figure 9 Shows the Figure 4a Example timing diagram for use with an ADC system;

[0036] Figure 10 An example timing diagram showing operation of an ADC system (e.g., ADC system 4a) in accordance with the present disclosure; Figure 4b An example timing diagram showing operation of an ADC system (e.g., ADC system 4a) in accordance with the present disclosure;

[0037] Figure 11 An example flowchart showing a method of operating an ADC system (e.g., ADC system 4a) in accordance with the present disclosure;

[0038] Figure 12 An example flowchart showing a method of operating an ADC system (e.g., ADC system 4b) in accordance with the present disclosure;

[0039] Figure 13 An example flowchart showing a method of operating an ADC system (e.g., ADC system 4a) in accordance with the present disclosure; and

[0040] Figure 14 An example flowchart showing a method of operating an ADC system (e.g., ADC system 4b) in accordance with the present disclosure. DETAILED DESCRIPTION

[0041] The present disclosure provides methods and systems for synchronizing ADCs or two or more ADCs such that the ADCs are time reference synchronized in a robust, reliable, and efficient manner. Moreover, these methods and systems seek to provide ADC time reference synchronization with no phase error in the output, minimal hardware and software complexity, minimal hardware footprint, high predictability of synchronization, low cost, and the like.

[0042] More specifically, the present disclosure utilizes ADC systems having one or more ADCs and methods of operating the systems in order to provide time reference synchronization of the samples of the one or more ADCs in a simple, yet robust and reliable manner. The ADCs in the system use a master clock, which can be referred to as a shared master clock. In some examples, the ADC system includes two or more ADCs, and all of the ADCs within the system use the same physical master clock. In further examples, the ADC system can include two or more ADCs that are geographically separated. In this example, the two or more ADCs do not physically share a master clock, but rather share a synchronized version of the master clock. In both of the above examples, whether the master clock is a physically identical master clock or a synchronized version of the master clock, the master clock is shared among each of the ADCs of the ADC system.

[0043] The present inventors have recognized that by stopping and starting the master clock, while pausing sampling of one or more ADCs, sampling of the one or more ADCs can be resumed synchronously with respect to a time base. Because the ADC internal filter reset is synchronized with the restarted master clock, the one or more ADCs are synchronized with the time base. Therefore, resuming sampling of the one or more ADCs is synchronized with the time base. Notably, when sampling of the one or more ADCs is resumed in response to resetting the internal filter of each of the one or more ADCs, each ADC is synchronized not only with the master clock but also with each other.

[0044] In some cases, an ADC uses both a synchronization output signal and a synchronization input signal. The synchronization output signal can be synchronized with a shared master clock. The system can then be operated by stopping the master clock. When the master clock stops, the ADC detects a synchronization event. This synchronization event can be detected by receiving a command from the processor requesting synchronization, or by the ADC's internal clock detecting that the master clock has stopped. When the master clock stops, this does not result in a response from the ADC. The master clock is then restarted after a synchronization event is detected. This causes an internal filter (internal to the ADC) to reset. After the ADC detects a synchronization event, the ADC can reset the internal filter. It is worth noting that the ADC's internal filter can refer to the ADC's internal digital filter. Thus, the internal filter or internal digital filter can process the ADC's sampling or output. Alternatively, the state of the internal filter can be reset, for example, the current count of the internal filter is reset. In response to the filter reset, sampling by the ADC resumes. This allows the ADC's time reference synchronization to use only a single master clock signal, without isolation components, and reducing additional signal connections. This means that the system disclosed herein has reduced hardware requirements, reduced floor space, and reduced component and construction costs. The disclosed system also provides the capability of time reference synchronization by being robust to sampling / edge timing ambiguity, thereby reducing the risk of phase errors on the ADC output, thereby improving the reliability of ADC sampling.

[0045] Furthermore, it can be said that resetting the internal filter includes a first state change of the internal filter within a time synchronized with the master clock and a second state change of the filter within a time synchronized with the master clock, wherein the first state change may be opposite to the second state change, and wherein the second state change may occur a fixed number of master clock cycles after the first state change. In this case, resuming ADC sampling may include resuming sampling in response to the second state change of the ADC internal filter.

[0046] In other cases, the present disclosure provides a multi-ADC system arranged such that all of the ADCs of the system share a master clock. Again, time reference synchronization of the ADCs is achieved using only a single master clock signal by restarting the sampling of the ADCs in response to the resetting of the internal filter of each ADC.

[0047] The ADC internal filter can be a digital filter integrated on the ADC. The ADC internal filter is used to remove / reject unwanted signals from a particular spectrum. The decimation process, which is similar to averaging a number of input samples to produce one output data, is also implemented by the internal filter. The internal filter is an inherent part of the ADC, which can be an oversampling ADC. For example, an ADC with an internal filter that performs decimation by 8, takes an average every 8 input samples, and produces one output. If an ADC system includes two ADCs to monitor the same input signal without synchronization, the first ADC can average samples 1, 2, 3, 4, 5, 6, 7, 8 and produce one sample, while the other ADC can average samples 5, 6, 7, 8, 9, 10, 11, 12 and produce one sample. Both ADCs produce outputs at the same rate, but the outputs are different due to the mismatch in the phase of the input signal. The synchronization process of the present disclosure essentially resets the ADC internal filters of both ADCs. As a result, the ADC internal filters on both ADCs will resynchronize the sampling of each ADC.

[0048] In conjunction with the ADC system and the multi-ADC system, the present disclosure provides a method of operating the ADC system. The method includes stopping, by a processor, sending a master clock (MCLK) to the ADC to stop sampling of the ADC, and then detecting a synchronization event. Next, the method restarts the master clock of the ADC. After the master clock is restarted, the ADC responds to the synchronization event by resetting an internal filter of the ADC and, in response, restarts sampling of the ADC. As a result, the sampling of the ADC or the plurality of ADCs is synchronized according to a time reference.

[0049] In some examples, the ADC system is connected to and controlled by a field programmable gate array (FPGA) device. In the present disclosure, the method of operating the ADC system can use the FPGA to issue the instruction to stop the master clock. The FPGA then initiates the synchronization of the ADC by providing a stimulus to the ADC, which the ADC detects as a synchronization event. The FPGA subsequently issues a command to restart the master clock. In some cases, the FPGA can monitor the output of the ADC to determine whether new output data is ready, and thus whether the sampling of the ADC is synchronized to a time reference.

[0050] In other examples, the ADC system is connected to and controlled by a microcontroller unit (MCU) device. In this disclosure, the method of operating the ADC system can use the MCU to issue an instruction to stop the master clock. The MCU then initiates a synchronization of the ADC by providing a stimulus to the ADC, which the ADC detects as a synchronization event. The MCU then issues a command to restart the master clock. In some cases, the MCU can then monitor the output of the synchronized ADC to determine if new output data is ready, and thus whether the sampling of the ADC is synchronized with the time reference.

[0051] The present disclosure will now be discussed in further detail in relation to the relevant drawings.

[0052] Figure 1 An example schematic of a multi-ADC system 1 is shown. This system provides an example of a system for synchronizing multiple ADCs. The multi-ADC system 1 comprises a first ADC 10, a second ADC 12, a master clock (MCLK) 14. The synchronization input signals of the first ADC 10 and the second ADC 12 are coupled together to ensure that the first ADC 10 and the second ADC 12 have a shared synchronization signal (SYNC) 16. From Figure 1 It can also be seen that the multi-ADC system 1 further comprises that each ADC comprises one input pin and one data ready output (DRDY).

[0053] In more detail, it can be seen that the master clock 14 is coupled to the input of the first ADC 10 and the second ADC 12. It is therefore clear that the first ADC 10 and the second ADC 12 share a common master clock 14 signal. Furthermore, as mentioned above, the synchronization input signals of the first ADC 10 and the second ADC 12 are coupled together such that they also share a common SYNC 16.

[0054] In this example, the first ADC 10 and the second ADC 12 sample the input pin multiple times to produce one data output at the DRDY output. In this example, due to the shared master clock 14, the first ADC 10 and the second ADC 12 sample their respective input pins at the same time, however, they can not produce an output of the DRDY output at the same time. This can therefore create synchronization issues with both ADCs and cause phase errors in the measurement.

[0055] This can be described in more detail in relation to Figure 2 the relevant example timing Figure 2 of Figure 2.

[0056] In Figure 2 , the shared master clock 14 (as Figure 1running at a constant frequency. The plot also shows the DRDY output of device 1 and device 2 over time, i.e. the DRDY output of the first ADC 10 and the second ADC 12. Finally, the plot shows the shared SYNC 16 (as indicated) over time. As can be seen, the SYNC 16 can be used to synchronize the sampling between multiple ADCs. This is indicated by the SYNC 16 being initiated at the start point 22, which in turn results in a synchronized DRDY output 24 on the first ADC 10 and the second ADC 12, in other words, device 1 and device 2. Figure 1

[0057] To achieve this, the SYNC 16 needs to be synchronized with the master clock 14, i.e. the falling edge of the SYNC 16 can be aligned with the falling edge of the master clock 14. In this regard, the master clock 14 is driven on the falling edge and sampled on the rising edge. Since the first ADC 10 and the second ADC 12 use the master clock 14 to sample the SYNC 16 signal, when the SYNC 16 is synchronized with the master clock 14 signal, the sampling of the SYNC 16 will always result in the same outcome from a timing perspective.

[0058] However, the synchronization system encounters problems when the SYNC 16 is not synchronized with the master clock 14, i.e. when the SYNC 16 is asynchronous with the master clock 14. The edge timing of the SYNC 16 can be ambiguous. This is because the SYNC 16 cannot instantaneously transition from high to low. As a result, this creates a situation where there is ambiguity between the sampling timing of the SYNC 16 and the master clock 14 signal. As a result, it is possible that one ADC detects the SYNC 16, but the other ADC does not. Therefore, the ADC that detects the SYNC 16 will output on the DRDY output first than the other ADC that does not detect the SYNC 16. A phase offset of one master clock 14 cycle between the ADCs is expected. This can also be seen as a phase error.

[0059] In other words, when the SYNC 16 is asynchronous with the master clock 14, the sampling of the SYNC 16 can cause timing ambiguity between the two ADCs. This happens when the SYNC pulse edge is close to the master clock sampling edge, for example, one ADC registers the SYNC 16, while the other ADC does not. This can result in a phase offset of one master clock 14 cycle between the two ADCs.

[0060] ​Accordingly, there is a need to provide a system and method for synchronizing one or more ADCs with a time reference to develop a more robust and reliable ADC system. More specifically, there is a need to provide a system and method for synchronizing one or more ADCs to a time reference point that is more robust and reliable by reducing or preventing phase errors on the ADC output when providing a synchronized output after ADC sampling.

[0061] Figure 3 An example schematic of a channel-isolated DAQ system 3 is shown in accordance with one approach. The channel-isolated DAQ system 3 includes a plurality of ADCs 30a-30d, each ADC 30a-330d having a corresponding isolator (ISO) 32 and FPGA 34. The channel-isolated DAQ system 3 is arranged such that the ADCs 30a-30d are isolated from the FPGAs 34 by their associated isolators 32.

[0062] In a channel-isolated DAQ system, as shown in Figure 3 synchronization of the ADCs on each channel requires that both the master clock and the SYNC pass through the isolation on the high-speed isolation channel of each ADC channel. This adds a significant amount of power consumption, system complexity, increases the likelihood of system failure points, and increases the cost required for synchronization.

[0063] In a similar example, a network-distributed DAQ system is also used. In a network-distributed DAQ system, synchronized ADCs require the system to generate a master clock with precise timing and a SYNC (this can be achieved through a precise timing protocol such as IEC 1588). However, this increases the resource requirements on the network controller as not all network controllers have two timers, for example, the ADIN1110 MACPHY of 10baseT1L has only one TS_TIMER.

[0064] Accordingly, there is also a need for a system and method for time reference synchronization of an ADC or multiple ADCs that has low system complexity, low system cost, low power consumption, etc., while ensuring robust and reliable synchronization of the ADC output.

[0065] The present disclosure seeks to provide a solution to the above problems. The solution in accordance with the present disclosure will now be discussed in conjunction with FIGS. 4-14.

[0066] Figure 4aAn example schematic of an ADC system 4a is shown. The ADC system 4a includes an ADC, a clock source 40, and a processor 47. The processor 47 is communicatively coupled to the clock source 40. The clock source 40 is coupled to a master clock (MCLK) 41 of the ADC. The processor 47 is coupled to a host interface 43 of the ADC. The ADC also includes a sync out signal (SYNC OUT) 42 and a sync in signal (SYNC IN) 44, which in this non-limiting example are coupled together such that the sync out signal provides a signal to the sync in signal 44. However, in other examples, the sync out signal 42 can be coupled to the sync in signal 44 within the ADC circuitry, as will be discussed in more detail below. Figure 4b

[0067] In this example, the sync out signal 42 is a mechanism or pin that is present in many ADC systems 4a. In this regard, the ADC system 4a can generate a signal from the sync out signal 42 that is synchronized with the master clock 40. Due to the internal arrangement of the ADC 4a, the sync out signal 42 can be triggered in a number of ways, for example, by an asynchronous digital input or an SPI command, etc. Thus, the sync out signal 42 can be coupled to the sync in signal 44 via a coupler 46 in order to synchronize the ADC 4a. This functionality is commonly used to synchronize multiple ADCs, i.e., multiple ADCs will have a shared master clock, and one ADC will produce a sync out signal that is coupled to the sync in signal of all other ADCs. This system ensures that the sync in signal and the master clock are synchronized, but it generally cannot achieve precise timing synchronization due to the lack of timing control over the trigger signal / command, particularly if it is controlled by an MCU-based host device, etc.

[0068] Accordingly, the present disclosure provides a method of operating an ADC system, which can include a single ADC or multiple ADCs, to achieve precise time synchronization. This method of operation will be discussed in more detail below.

[0069] Figure 4b Another example schematic of an ADC system 4b is shown. The ADC system 4b includes an ADC, a clock source 40, and a processor 47. The processor 47 is communicatively coupled to the clock source 40. The clock source 40 is coupled to a master clock (MCLK) 41 of the ADC. The processor 47 is coupled to a host interface 43 of the ADC. Figure 4b The main difference between the ADC system 4b and the ADC system 4a in Figure 4a The main difference between the ADC system 4b and the ADC system 4a in Figure 4b ​The ADC system 4b in the FPGA 50 has a corresponding sync output signal coupled with the sync input signal inside the ADC circuit. Thus, the ADC system 4b has the same functionality in terms of sync signals as the ADC system 4a, despite the lack of external sync input / output signal pins.

[0070] Figure 5 Another example schematic of an ADC system 5 that uses an FPGA 50 to synchronize an ADC or multiple ADCs is shown. As can be seen, the system 5 includes the FPGA 50, an isolator 52, and an ADC 54. The ADC 54 can be an oversampling (OS) ADC. The FPGA 50 includes a first IO pin 502, a second IO pin 504, and an SPI pin 506. The isolator 52 includes a first channel (CH0) 522, a second channel (CH1) 524, and a third channel (CH_SPI) 526. The ADC 54 includes a master clock 541, a sync input signal (SYNC IN) 542, a sync output signal (SYNC OUT) 543, a DRDY pin 544, and an SPI pin 545.

[0071] The first IO pin 502 of the FPGA 50 is connected to the first channel (CH0) 522 of the isolator 52. The first channel (CH0) 522 of the isolator 52, in turn, is connected to the master clock 541 of the ADC 54. Thus, the first IO pin 502 of the FPGA 50 can send instructions to the master clock 541 of the ADC 54 through the first channel (CH0) 522 of the isolator 52. The instructions from the FPGA 50 can be to stop or restart the master clock 541 of the ADC 54. The FPGA 50 restarts the master clock 541 at precisely controlled timing.

[0072] The second IO pin 504 of the FPGA 50 is connected to the second channel (CH1) 524 of the isolator 52. The second channel (CH1) 524 of the isolator 52, in turn, is connected to the DRDY pin 544 of the ADC 54. In this regard, the output signal of the DRDY pin 544 of the ADC 54 is fed to the second channel (CH1) 524 of the isolator 52, and then to the second IO 504 of the FPGA 50. The FPGA 50 uses the connection to the DRDY pin 544 of the ADC 54 to monitor the DRMY signal from the ADC 54 to determine when new output data is ready.

[0073] The SPI pin 506 of the FPGA 50 is connected to the third channel (CH_SPI) 526 of the isolator 52. The third channel (CH_SPI) 526 of the isolator 52 is connected to the SPI pin 545 of the ADC 54. The SPI pin 506 of the FPGA 50, the third channel (CH_SPI) 526 of the isolator 52, and the SPI pin 545 of the ADC all have bidirectional communication. Therefore, the FPGA 50 can send SPI instructions or commands to the ADC 54. This allows the FPGA 50 to control the initiation of the ADC 54 synchronization process. Similarly, the ADC 54 can send SPI data to the FPGA 50 in return.

[0074] Therefore, use one or more of the following steps (numbered steps 1-4 and Figure 5 1-4 related to points 1-4 of FIG. 5 ) to synchronize two or more ADCs 54 using the FPGA 50:

[0075] 1. The first IO pin 502 of the FPGA 50 is used to send a signal to the master clock pin 541 of the ADC 54 (via the first channel (CHO) 522 of the isolator 52) to stop the output of the master clock 541;

[0076] 2. The SPI pin 506 of the FPGA 50 will be used to send an SPI instruction to the SPI pin 545 of the ADC 54 (via the third channel (CH_SPI) 526 of the isolator 52) to trigger the synchronization of the ADC 54;

[0077] 3. The first IO pin 502 of the FPGA 50 will be used to send a signal to the master clock pin 541 of the ADC 54 (through the first channel (CHO) 522 of the isolator 52) to restart the output of the master clock 541;

[0078] 4. The second IO pin 504 of the FPGA 50 will be used to monitor the DRDY 544 signal from the ADC 54 (via the second channel (CH1) 524 of the isolator 52) to determine when new output data is ready and the ADC is sampling synchronously.

[0079] Figure 6An example schematic of a system 6 using MCU 60 to synchronize multiple ADCs is shown. As can be seen, the system 6 comprises MCU 60, MAC+PHY device 62 and ADC 64. The ADC 64 can be an oversampling (OS) ADC. The MCU 60 comprises software and hardware elements. The software elements comprise ADC driver 601, PTP stack 602, network stack 603 and PHY driver 604. The hardware elements comprise IO pin 605. The MAC+PHY device 62 contains hardware elements such as timer (TS_TIMER) 622. The ADC 62 comprises hardware elements such as master clock 642, sync in signal (SYNC_IN) 644, sync out signal (SYNC_OUT) 646 and DRDY pin 648.

[0080] In Figure 6 the example, the PHY driver 604 of the MCU 60 is connected to the MAC+PHY device 62 so that SPI commands (or similar) can be transmitted. The timer (TS_TIMER) 622 of the MAC+PHY device 62 is connected to the master clock 642 of the ADC 64. As previously mentioned, the sync in signal 644 of the ADC 64 is coupled to the sync out signal 646 of the ADC 64. The DRDY pin 648 of the ADC 64 is connected to the IO pin 605 of the MCU 60. The ADC driver 601 of the MCU 60 is also connected to the ADC 64 so that SPI commands (or similar) can be transmitted.

[0081] Hence, using one or more of the following steps (numbered steps 1-4 relate to points 1-4 of Figure 6 of the use of the MCU 60 to synchronize two or more ADCs 64:

[0082] 1. The PHY driver 604 of the MCU 60 is used (via SPI commands etc.) to instruct the MAC+PHY device 62 to stop the master clock 642 of the ADC 64 using the timer 622;

[0083] 2. The ADC driver 601 of the MCU 60 is used to send an SPI command (or similar) to the ADC 64 to initiate synchronization of the ADC 64;

[0084] 3. The PHY driver 604 of the MCU 60 is used (via SPI commands etc.) to instruct the MAC+PHY device 62 to restart the master clock 642 of the ADC 64 using the timer 622 with precisely controlled timing. The precisely controlled timing can be achieved by using a standard or protocol such as IEEE 1588 Precision Time Protocol;

[0085] 4. The IO pin 605 of the MCU 60 is used to monitor changes in the DRDY pin 648 of the ADC 64,

[0086] to determine when new output data is ready and the ADC is sampling synchronously.

[0087] Although Figure 6 The present invention is described with respect to the MAC+PHY device 62, but it is worth noting that the same operation can be achieved using alternative device arrangements. By way of another example, the operation can be achieved by including a MAC with appropriate timestamp and clock synchronization support in the MCU. In another example, the operation can be achieved by having a multi-port Ethernet switch (instead of the MAC+PHY device 62) that includes the same timestamp and clock synchronization support. In either example, the PHY can be incorporated into the MCU+MAC arrangement or incorporated into the multi-port Ethernet switch.

[0088] Figure 7 Timing Figure 7 Corresponding to Figure 4a ADC system 4a. Timing Figure 7 Contains a master clock 70 signal, a sync output signal and a sync input signal 71 (which corresponds to Figure 4a The interface between the synchronous output signal 42 and the synchronous output signal 44) signal, the processor and the ADC 72 (corresponding to Figure 4a / 4b in the host interface 43), ADC internal synchronization latch or ADC internal latch 76 and ADC internal filter reset 77.

[0089] Timing Figure 7The master clock 70 is shown being turned off at point 73. Thus, the master clock 70 of the ADC or all related ADCs is turned off. Turning off the master clock 70 does not cause any problems to the standard ADC operation. During the master clock 70 is turned off, a synchronization event is received at the interface 72, in this example a trigger command (e.g. SPI instruction command) to trigger the synchronization output signal 71 (and the synchronization input signal, as the synchronization output signal and the synchronization input signal are coupled together). The signal triggering the synchronization output signal 71 at the interface 72 can be asynchronous to the master clock 70 and can be recorded by the ADC without the master clock 70 running. On the ADC, both the synchronization output signal and the synchronization input signal 71 are controlled by the internal logic of the ADC, which in turn is controlled by the master clock 70. Thus, when the master clock 70 is turned off, the synchronization output signal 71 does not trigger when the interface 72 receives the synchronization event. Thus, at point 74, the master clock 70 is turned back on. During the turn off of the master clock 70, the ADC internal latch 76 switches in response to the received synchronization event. When the master clock 70 resumes, the ADC internal latch 76 switches back and the synchronization output signal 710 subsequently triggers. The triggering of the synchronization output signal 71 occurs at point 75. Since the ADC within the system utilizes the master clock 70 signal, the ADC internal filter reset is triggered at a time that is synchronized to the master clock 70, after the master clock is restarted 74 and after the synchronization output signal triggers 75. The time synchronization of the ADC restarts in response to the reset of the ADC internal filter 77 occurs at a determined time after the master clock 70 restarts and the ADC internal filter 77 resets. If the master clock 70 is stopped and restarted with precise start-up timing in conjunction with the synchronization output signal / synchronization input signal mechanism, then precise sampling synchronization with respect to a reference time is achieved with only one master clock 70 signal.

[0090] In this example, the accuracy of synchronizing one or more ADCs depends on restarting the master clock at a precisely controlled time.

[0091] To ensure that the master clock 70 is restarted with precise start-up timing, a precise time protocol (PTP) can be used. PTP can be used to synchronize clocks throughout electronic systems, computer networks, and the like; in particular, in networks and systems, PTP can be used to achieve very reliable clock precision. In many cases, such clock precision can be within a range of less than a microsecond, which makes it suitable for a variety of applications. Many PTP standards have been published and will continue to be developed. In addition, there are many ways to achieve precise control of the start-up timing of the master clock, for example, IEEE 1588 can be used.

[0092] In other words, one way to precisely time the method can be for the network system to agree to align on the repetition boundary. For example, the ADC samples can start on the second boundary, or from a multiple of the 32 microsecond period since midnight on December 31, 1970, etc. In this way, the ADCs are all running within a small fraction of the stated time period (32 microseconds, or as the case can be), and they are effectively synchronized. Thus, the device can recover from a fault and then restart the synchronization operation without having to shut down the entire system.

[0093] The sync out signal and the sync in signal can be related to the pins of the ADC, or they can be related to the sync out signal / sync in signal from the ADC. Since the ADC can be arranged such that the sync out signal is coupled to the sync in signal pin, the sync signal out can use the generated logic within the ADC such that the shared master clock ensures that the output signal is synchronized with the shared master clock to create a synchronous ADC. The generated logic of the ADC behaves like a D flip-flop in that the input change is asynchronous to the master clock, but the output is synchronized to the master clock. As previously mentioned, the sync out signal and the sync in signal can be coupled together on an external pin of the ADC or in the internal circuitry of the ADC.

[0094] While the above description discusses that the synchronization event can be an SPI instruction command at the processor / ADC interface 72, other command types can also be used. For example, the synchronization event can be a command issued to the processor / ADC interface 72 through a pin toggle. In this case, the command can be synchronized or asynchronous to the shared master clock and can not be required at a predetermined time.

[0095] It is noted that the master clock (MCLK) 70 can be restarted at a predetermined time, and the predetermined time can correspond to a rising edge.

[0096] Further, as Figure 7 shown, the method can also require the system to monitor the synchronization restart of the ADC samples. This can require monitoring the sync out signal 71 or the DRDY pin (as Figures 5-6 shown) to ensure that all of the ADCs within the system are sampling in synchronization with respect to the time reference.

[0097] The above-described method for synchronizing an ADC or multiple ADCs is performed by a computer-implemented system. The system can include at least one processor and at least one computer-readable storage medium storing computer-readable instructions that, when executed by the processor, cause the processor to perform the method discussed in the examples explained in this disclosure.

[0098] As Figure 7As shown, the above method provides a method of synchronizing one or more ADCs with only one master clock signal and optionally only one other processor signal, which can be referred to as a synchronization signal. This is different from existing synchronization systems, which typically require multiple clock signals and multiple other synchronization signals and components. Thus, the system and method in this disclosure provides a system for time reference synchronization of ADCs with reduced complexity, reduced hardware components, reduced footprint, reduced hardware cost, etc.

[0099] Figure 8 Another example timing related to operating an ADC system Figure 8 Example timing Figure 8 related to an ADC system 4b as shown in Figure 4b because the synchronization output / input signals are coupled together in the internal circuitry of the ADC.

[0100] Timing Figure 8 containing a master clock 80 signal, an interface between the processor and the ADC 82 (corresponding to the host interface 43 in Figure 4b ), an ADC internal synchronization latch or ADC internal latch 86, and an ADC internal filter reset 87.

[0101] Timing Figure 8 shows that the master clock 80 is turned off at point 83. Thus, the master clock 80 of the ADC or all related ADCs is turned off. Turning off the master clock 80 does not cause any problems to the standard ADC operation. During the master clock 80 is turned off, a synchronization event is received at the interface 82, which in this example is a trigger command (e.g., SPI instruction command). In the timing Figure 7 , this step triggers the output of the synchronization output signal (coupled to the synchronization input signal), however, in this example, the synchronization output / input signals are internally coupled. Nonetheless, with the master clock 80 turned off, the ADC does not act on the synchronization event, e.g., the ADC does not act on the trigger command, except for the toggling of the ADC internal latch 86. During the master clock 80 is turned off, the ADC internal latch 86 toggles in response to the received synchronization event. Upon the master clock 80 is turned back on, the ADC internal latch 86 will toggle back, and the ADC internal filter 87 is reset at a determined time after the master clock is restarted. In response to the reset of the ADC internal filter reset 87, the ADC resumes sampling at a determined time after the master clock 80 is restarted and the ADC internal filter 87 is reset. If the master clock 80 is stopped and restarted with precise start timing in combination with the internal synchronization output signal / synchronization input signal mechanism, then precise sampling synchronization with respect to a reference time is achieved with only one master clock 80 signal.

[0102] As previously mentioned, the precision of synchronizing one or more ADCs depends on restarting the master clock at a precisely controlled time. In practice, a MAC+PHY device (or equivalent device) can have an internal frequency and value adjustment clock that matches the timing of the master clock (IEEE 1588). It can then have logic that generates one or more external signals based on this clock (in this case, the master clock that is fed to the ADCs). A "start time register" can then be installed in which the processor installs a value that corresponds to some agreed-upon time in the future. When the synchronized clock in the MAC+PHY matches this start time register value, it can begin operating the master clock output signal to the ADCs. Thus, all synchronized ADCs use the same start time to begin master clock operation, resulting in synchronized ADC outputs.

[0103] Figure 9 Another example timing for operating an ADC system Figure 9 . Example timing Figure 9 for an ADC system 4a as shown in Figure 4a because the ADC system 4a includes coupled external synchronization input / output signal pins.

[0104] Timing Figure 9 includes a master clock 90 signal, a synchronization output signal, and a synchronization input signal 91 (which corresponds to the synchronization output signal 42 and the synchronization output signal 44 of Figure 4a ), an ADC internal synchronization latch or ADC internal latch 96, and an ADC internal filter reset 97. Thus, it can be seen that the example timing Figure 9 and the example timing Figure 7 / 8 differ primarily in that there is no processor / host interface for receiving synchronization events or commands. The ADC and the processor are still coupled at the ADC interface, however, in this example, the interface is not used to receive synchronization events or commands related to synchronization events.

[0105] Instead, the ADC automatically detects the synchronization event by detecting that the master clock has stopped. Thus, it can be said that the example performs automatic synchronization whenever the ADC (or ADCs) detect that the master clock has stopped, as shown in Figure 9

[0106] Thus, in this example, the ADC system 4a operates according to the timing Figure 9 as follows.

[0107] Timing Figure 9 ​The master clock 90 is turned off at point 93. Thus, the master clock 90 for the ADC or all related ADCs is turned off. Turning off the master clock 90 does not cause any problems to the standard ADC operation. The ADC constantly checks the operation of the ADC to make sure that the master clock 90 is still operating in association with the ADC. This can be achieved by polling the master clock pin on the ADC. When the ADC detects that the master clock 90 has stopped, for example at point 93, then the ADC takes this as an indication that a synchronization event has occurred. The ADC now triggers the synchronization output signal 91 (and the synchronization input signal, as the synchronization output signal and the synchronization input signal are coupled together). On the ADC, both the synchronization output signal and the synchronization input signal 91 are controlled by the internal logic of the ADC, which in turn is controlled by the master clock 90. Thus, when a synchronization event is detected (by turning off the master clock 90), the synchronization output signal 91 does not trigger as the master clock 90 has been turned off. During the master clock 90 being turned off, the ADC internal latch 96 toggles in response to the detected synchronization event. Thus, at point 94, the master clock 90 is turned back on. When the master clock 90 resumes, the ADC internal latch 96 toggles back and the synchronization output signal 91 is subsequently triggered. The triggering of the synchronization output signal 91 occurs at point 95. As the ADCs within the system utilize the master clock 90 signal, the ADC internal filter 97 is reset at a determined time after the master clock 90 is turned back on and the synchronization output signal 95 is triggered. The synchronization restart of the ADC sampling occurs at a determined time after the master clock 90 is turned back on, the synchronization output signal 95 is triggered and the ADC internal filter 97 is reset. If the master clock 90 is stopped and restarted with the precise start timing in conjunction with the synchronization output signal / synchronization input signal mechanism, then the precise sampling synchronization with respect to the reference time is achieved with only one master clock 90 signal.

[0108] Figure 10 Another example timing relating to operating an ADC system Figure 10 As shown in Figure 4b, an example timing Figure 4b associated with the ADC system 4b Figure 10 as the ADC system 4b includes a synchronization input / output signal coupled internally to the ADC.

[0109] Timing Figure 10 includes the master clock 100 signal, the ADC internal synchronization latch or ADC internal latch 106 and the ADC internal filter reset 107. Thus, as can be seen, the main difference between the example timing Figure 10 and the example timing Figure 7 / 8 is that the timing Figure 9Similarly, there is no processor / host interface for receiving synchronization events or commands. The ADC and processor are still coupled at the ADC interface, however, in this example, the interface is not used to receive synchronization events or commands related to synchronization events. Instead, the ADC automatically detects the synchronization event by detecting that the master clock has stopped. Thus, it can be said that, as shown in Figure 10 , this example performs automatic synchronization whenever the ADC (or ADCs) detect that the master clock has stopped.

[0110] Example timing Figure 10 is different from the example timing Figure 9 in that there is no externally coupled synchronization input / output signal pin.

[0111] Thus, in this example, the ADC system 4b operates according to the timing Figure 10 as follows.

[0112] Timing Figure 10 shows that the master clock 100 is turned off at point 103. Thus, the master clock 100 of the ADC or all relevant ADCs is turned off. Turning off the master clock 100 does not cause any problems to the standard ADC operation. The ADC constantly checks the operation of the ADC to make sure that the master clock 100 is still operating in association with the ADC. This can be achieved by polling the master clock pin on the ADC. When the ADC detects that the master clock 100 has stopped, for example at point 103, then the ADC treats this as an indication that a synchronization event has occurred. Thus, when a synchronization event is detected (by turning off the master clock 100), the ADC does not restart sampling because the master clock 100 has been turned off. During the master clock 100 being turned off, the ADC internal latch 106 toggles in response to the detected synchronization event. Thus, at point 104, the master clock 100 is turned back on. When the master clock 100 resumes, the ADC internal latch 106 toggles back, and after a certain time thereafter, the ADC internal filter 97 is reset. Since the ADCs within the system utilize the master clock 90 signal, the synchronization restart of the ADC sampling occurs at a certain time after the master clock 100 restarts and the ADC internal filter 107 is reset. If the master clock 100 is stopped and restarted with precise start timing in combination with the internal synchronization output signal / synchronization input signal mechanism, then precise sampling synchronization with respect to a reference time is achieved with only one master clock 100 signal.

[0113] Figure 11 shows an example flow Figure 11 for operating an ADC system. In particular, the flow Figure 11 is for operating an ADC system in combination with the timing Figure 7 as shown in Figure 7 , such as the ADC system 4a as shown in Figure 4aAn example flow for operating an ADC system is shown Figure 11 One or more of the following steps can be included.

[0114] In s110, the ADC is continuously sampling, e.g. the ADC is running normally and performing its normal operation. The master clock connected to the ADC is then turned off by the processor. Next, in s111, the ADC stops its normal operation, e.g. the ADC stops sampling due to the master clock being turned off. During the master clock being turned off, s112 occurs where the ADC records or detects a synchronization event or synchronization command. The synchronization event or command can be related to an SPI command from an external processor or a trigger triggered by toggling a pin of the ADC, such as an ADC / processor interface pin, for example. After this, the processor resumes sending the master clock signal to the ADC. As previously mentioned, the restart of the master clock is done at a precisely controlled start timing. Next, in s113, the ADC generates a synchronization output signal that is synchronized with the master clock. The synchronization output signal is generated a fixed number of master clock cycles after the master clock has been restarted. In s114, the ADC registers the synchronization output signal at the synchronization input signal in the next master clock cycle (as the synchronization output signal and the synchronization input signal are coupled). In s115, the ADC resets its internal filter a fixed number of master clock cycles after receiving the synchronization input signal. In s116, the ADC resumes continuous sampling, e.g. normal operation. The restart of the ADC sampling occurs at a time equal to the master clock restart time plus the fixed number of master clock cycles in response to the reset of the internal filter in s115.

[0115] Figure 12 An example flow for operating an ADC system is shown Figure 12 . In particular, the flow Figure 12 for operating an ADC system in conjunction with timing Figure 8 (as Figure 8 An example flow for operating an ADC system is shown Figure 4b . In particular, the flow Figure 12 for operating an ADC system in conjunction with timing . In particular, the flow

[0116] In s120, the ADC continues to sample, e.g. the ADC is running normally and performing its normal operation. The main clock connected to the ADC is then turned off by the processor. Next, in s122, the ADC stops its normal operation, e.g. the ADC stops sampling due to the main clock being turned off. During the main clock being turned off, s124 occurs where the ADC records or detects a synchronization event or a synchronization command. The synchronization event or command can be related to an SPI command from an external processor or a trigger triggered by toggling a pin of the ADC, such as an ADC / processor interface pin, for example. Following this, the processor restores the main clock to the ADC. As previously mentioned, the restart of the main clock is done at a precisely controlled start timing. In s126, the ADC, after receiving the synchronization event or synchronization, resets its internal filter block after a fixed number of main clock cycles. This is because the internally coupled synchronization output and input signals perform the operation of s113-s114 internally. In s128, the ADC resumes continuous sampling, e.g. normal operation. The restart of the ADC sampling occurs at a time equal to the main clock restart time plus the fixed number of main clock cycles in response to the reset of the internal filter in s126. Figure 11

[0117] Figure 13 An example flow of operating an ADC system is shown Figure 13 . In particular, the flow Figure 13 operates an ADC system in conjunction with a timing Figure 9 (as shown in Figure 9 ). The flow operates an ADC system such as ADC system 4a (as shown in Figure 4a ). The flow Figure 13 operates an ADC system comprising an ADC or a plurality of ADCs and can include one or more of the following steps.

[0118] ​In s130, the ADC continues to sample, e.g. the ADC is running normally and performing its normal operation. The master clock connected to the ADC is then turned off by the processor. Next, in s131, the ADC stops its normal operation, e.g. the ADC stops sampling due to the master clock being turned off. During the master clock being turned off, s132 occurs in which the ADC detects a synchronization event or a synchronization command. For example, the synchronization event can be related to the ADC detecting that the master clock has stopped and automatically treating this as a synchronization event. The ADC can achieve this by continuously polling the master clock pin to ensure that the external master clock signal is still being received. Once the ADC detects the stopped master clock, it acknowledges that a synchronization event has been detected by latching the ADC’s internal latch. Following this, the processor restores the master clock to the ADC. As previously mentioned, the restart of the master clock is done at a precisely controlled start timing. Next, in s133, the ADC generates a synchronization output signal that is synchronized with the master clock. The synchronization output signal is generated a fixed number of master clock cycles after the master clock has restarted. In s134, the ADC registers the synchronization output signal at the synchronization input signal in the next master clock cycle (as the synchronization output signal and the synchronization input signal are coupled). In s135, the ADC resets its internal filter block a fixed number of master clock cycles after receiving the synchronization input signal. In s136, the ADC resumes continuous sampling, e.g. normal operation. The restart of the ADC sampling occurs in response to the reset of the internal filter in s135 at a time equal to the master clock restart time plus the fixed number of master clock cycles.

[0119] Figure 14 An example flow for operating an ADC system is shown Figure 14 . In particular, the flow Figure 14 operates an ADC system in conjunction with a timing Figure 10 (as shown in Figure 10 ). The flow Figure 4b operates an ADC system comprising an ADC or a plurality of ADCs, and can include one or more of the following steps. Figure 14

[0120] ​In s140, the ADC continues to sample, e.g., the ADC is running normally and performing its normal operation. The master clock connected to the ADC is then turned off by the processor. Next, in s142, the ADC stops its normal operation, e.g., the ADC stops sampling due to the master clock being turned off. During the master clock being turned off, s144 occurs where the ADC detects a synchronization event or a synchronization command. For example, the synchronization event can be related to the ADC detecting that the master clock has stopped and automatically treating it as a synchronization event. The ADC can achieve this by continuously polling the master clock pin to ensure that the external master clock signal is still being received. Once the ADC detects the stopped master clock, it acknowledges that a synchronization event has been detected by latching the ADC’s internal latch. Following this, the processor restores the master clock to the ADC. As previously described, the restart of the master clock will be with a precisely controlled start-up time. In s146, the ADC, after receiving the synchronization event or synchronization, resets its internal filter block after a fixed number of master clock cycles. This is because the internally coupled synchronization output and input signals perform the operations of s133-s134 internally. In s148, the ADC resumes continuous sampling, e.g., normal operation. The restart of the ADC sampling occurs at a time equal to the master clock restart time plus the fixed number of master clock cycles in response to the reset of the internal filter in s146. Figure 13

[0121] As previously described with respect to the present disclosure, i.e., the above-described method for performing synchronization of two or more ADCs is performed by a computer- implemented system. The system can include at least one processor and at least one computer- readable storage medium storing computer-readable instructions that, when executed by the processor, cause the processor to at least: stop a shared master clock, the shared master clock being a master clock used to synchronize two or more ADCs; receive a command to trigger a synchronization output signal of a first ADC of the two or more ADCs while the shared master clock is stopped, wherein the synchronization output signal is synchronized with the shared master clock; and restart the shared master clock to synchronize sampling of the two or more ADCs.

[0122] The above-described system for synchronizing two or more ADCs includes one or more processors, two or more ADCs, wherein the ADCs are configured such that a synchronization output signal of a first ADC is coupled to a related synchronization input signal of all other ADCs, and wherein the two or more ADCs have a shared master clock and a storage device and computer program code configured to perform a method according to the present disclosure with the processor.

[0123] ​This has the advantage of providing a system and method that can ensure robust and reliable sampling synchronization in a multi-ADC system. It also has the further advantage of reducing the likelihood of phase errors between ADCs within the system. Furthermore, this method has the advantage of providing reduced complexity, reduced hardware requirements, reduced points of failure, reduced cost, reduced hardware footprint, etc. compared to existing systems and methods for synchronizing multiple ADCs.

[0124] Furthermore, it can be said that the system and method enable synchronization of multiple ADCs without the need for a separate synchronization signal, nor the need for an isolating component. This contributes to the aforementioned advantages as it can reduce system complexity, reduce hardware cost, limit possible points of failure, etc.

[0125] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," "include," "including," and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to." The words "coupled" or "connected" are used broadly and encompass both direct and indirect coupling or connection, as well as over one or more intervening elements.

[0126] As used herein, "coupled" or "connected," which are generally used herein, refer to two or more elements or nodes that can either be connected directly or through one or more intervening elements. Furthermore, the use of "herein," "above," "below," and words of similar effect in this application are intended to refer to this application as a whole and not to any particular portion thereof. Where the context permits, words in the detailed description using the singular or plural number can also include the plural or singular number respectively. The word "or" in reference to a list of two or more items is intended to cover all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0127] It will be appreciated that the above list is not exhaustive and that the methods and systems described herein are applicable to many technical problem areas in which machine learning models can be applied.

[0128] Various modifications, either by addition, substitution or deletion, will be apparent to the intended reader in providing further examples of the present disclosure, where any and all examples are intended to be encompassed by the appended claims.

[0129] Numbered aspects

[0130] As non-limiting examples, some aspects of the present disclosure are set out in the following numbered clauses.

[0131] Numbered Clause 1 : A method for synchronizing analog-to-digital converters, ADCs, the method comprising:

[0132] The processor stops sending a master clock signal to the ADCs to pause sampling of the ADCs, the master clock being provided to the ADCs by an external master clock;

[0133] the ADC detects that a synchronization event has occurred while the master clock is stopped;

[0134] restarting, by the processor, the master clock signal to the ADC;

[0135] resetting, by the ADC, an internal filter at a time synchronized with the master clock; and

[0136] resuming, by the ADC, sampling in response to resetting the internal filter of the ADC.

[0137] Clause 2a: The method of clause 1, wherein resetting the internal filter comprises holding the internal filter in a reset state until sampling resumption has occurred. Preferably, the internal filter is held for a fixed number of master clock cycles after the master clock is restarted. Preferably, the ADC performs the resetting of the internal filter after the ADC detects that a synchronization event has occurred.

[0138] Clause 2b: The method of clause 1, wherein resetting the internal filter comprises making a first change to a state of the internal filter at a time synchronized with the master clock, and making a second change to the state of the internal filter at a time synchronized with the master clock, wherein the first change to the state is opposite the second change to the state, and wherein the second change to the state occurs after a fixed number of master clock cycles after the first change to the state. Preferably, the ADC performs the resetting of the internal filter after the ADC detects that a synchronization event has occurred.

[0139] Clause 3: The method of clause 2b, wherein resuming sampling of the ADC comprises resuming sampling in response to the second change to the state of the internal filter of the ADC.

[0140] Clause 4: The method of any preceding clause, wherein resuming sampling of the ADC comprises resuming sampling after a fixed number of master clock cycles after the master clock is restarted. The fixed number of master clock cycles for resuming sampling of the ADC after the master clock is restarted can be the same as or different from the fixed number of master clock cycles for holding the internal filter in the reset state after the master clock is restarted. Preferably, the number of clock cycles that the internal filter can be held in the reset state is less than the number of master clock cycles after the master clock is restarted for resuming sampling of the ADC.

[0141] Clause 5: The method of any of clauses 1-4, wherein the ADC detecting a synchronization event comprises receiving a command from the processor indicating a request for synchronization, and latching a synchronization event flip-flop of the ADC.

[0142] Numbered clause 6: The method of any one of numbered clauses 1 to 4, wherein the ADC detecting the synchronization event comprises detecting, via an internal clock of the ADC, that the master clock has stopped, and latching a synchronization event trigger of the ADC.

[0143] Numbered clause 7: The method of any preceding numbered clause, wherein restarting, by the processor, the master clock signal to the ADC comprises restarting the master clock signal at a precisely controlled time.

[0144] Numbered clause 8: The method of any preceding numbered clause, wherein the method further comprises:

[0145] A synchronized output signal is generated by the ADC at a synchronized output of the ADC, the synchronized output signal being synchronized with the master clock.

[0146] Numbered clause 9: The method of numbered clause 8, wherein the method further comprises:

[0147] After a fixed number of master clock cycles, the sync output signal is registered by the ADC at the sync input of the ADC.

[0148] Item 10: The method of Item 9, wherein the synchronization output and the synchronization input of the ADC are coupled via external pins of the ADC, and wherein the method further comprises: resetting an internal filter of the ADC after a fixed number of master clock cycles of the synchronization output signal are registered at the synchronization input of the ADC.

[0149] Numbered clause 11: The method of numbered clause 9, wherein the synchronization output and the synchronization input of the ADC are coupled via the ADC internal logic circuit.

[0150] Numbered clause 12: The method of any preceding numbered clause, wherein resetting the internal filter of the ADC at a time synchronized with the master clock comprises resetting relative to a time reference from the master clock. Preferably, the ADC performs the resetting of the internal filter after the ADC detects that a synchronization event has occurred.

[0151] Numbered clause 13: The method of numbered clause 12, wherein the ADC resuming sampling in response to resetting an internal filter of the ADC comprises resuming relative to a time reference.

[0152] Numbered clause 14: The method of any preceding numbered clause, wherein the method further comprises monitoring, by the processor, sampling of the ADC, master clock restarting, and master clock synchronization.

[0153] Clause 15: The method of any preceding numbered clause, wherein the method of stopping the master clock, restarting the master clock, and / or restarting the sampling of the ADC is performed by a processor such as a field programmable gate array (FPGA) or a microcontroller unit (MCU).

[0154] Clause 16: A method for synchronizing two or more analog-to-digital converters (ADCs), the method comprising:

[0155] stopping, by a processor, sending a shared master clock signal to the two or more ADCs to suspend sampling of the two or more ADCs, the shared master clock being provided to the two or more ADCs by an external master clock;

[0156] detecting, by each of the two or more ADCs, that a synchronization event has occurred at the time the shared master clock was stopped;

[0157] restarting, by the processor, the shared master clock signal to each of the two or more ADCs;

[0158] resetting, by each of the two or more ADCs, an internal filter at a time synchronized to the master clock; and

[0159] resuming, by the two or more ADCs, sampling in response to resetting their respective internal filters.

[0160] Clause 17a: The method of Clause 16, wherein resetting the internal filter comprises holding the internal filter in a reset state until the resuming of sampling has occurred. Preferably, the resetting of the internal filter is performed by the ADC after the ADC detects that the synchronization event has occurred.

[0161] Clause 17b: The method of Clause 16, wherein resetting the internal filter comprises making a first change to a state of the internal filter at a time synchronized to the master clock, and making a second change to the state of the internal filter at a time synchronized to the master clock, wherein the first change to the state is opposite to the second change to the state, and wherein the second change to the state occurs a fixed number of master clock cycles after the first change to the state. Preferably, the resetting of the internal filter is performed by the ADC after the ADC detects that the synchronization event has occurred.

[0162] Clause 18: The method of Clause 17b, wherein resuming sampling of the two or more ADCs comprises resuming sampling in response to the second change to the state of the internal filter of the two or more ADCs.

[0163] Clause 19: The method of any one of Clauses 16 to 18, wherein resuming sampling of the two or more ADCs comprises resuming sampling a fixed number of master clock cycles after the master clock is restarted.

[0164] Numbered Clause 20: The method of any one of Numbered Clauses 16-19, wherein detecting, by each of the two or more ADCs, a synchronization event comprises receiving a command from the processor indicating a request to synchronize.

[0165] Numbered Clause 21 : The method of any one of Numbered Clauses 16 or 19, wherein detecting, by each of the two or more ADCs, a synchronization event comprises detecting, by an internal clock of the two or more ADCs, that the master clock has stopped, and latching a synchronization event flip-flop of the two or more ADCs.

[0166] Numbered Clause 22: The method of any one of Numbered Clauses 16-21, wherein restarting, by the processor, the master clock signal to each of the two or more ADCs comprises restarting the master clock signal at a precisely controlled time.

[0167] Numbered Clause 23: The method of any one of Numbered Clauses 16-22, wherein the method further comprises:

[0168] generating, by each of the two or more ADCs, a synchronization output signal at a synchronization output of each of the two or more ADCs, the synchronization output signal being synchronized with the master clock.

[0169] Numbered Clause 24: The method of Numbered Clause 23, wherein the method further comprises:

[0170] registering, by each of the two or more ADCs, the synchronization output signal at a synchronization input of each of the two or more ADCs after a fixed number of master clock cycles.

[0171] Numbered Clause 25: The method of Numbered Clause 24, wherein the synchronization output and the synchronization input of each of the two or more ADCs are coupled via an external pin of each of the two or more ADCs, and wherein the method further comprises:

[0172] resetting an internal filter of each of the two or more ADCs after registering the synchronization output signal at the synchronization input of the two or more ADCs for the fixed number of master clock cycles.

[0173] Numbered Clause 26: The method of Numbered Clause 24, wherein the synchronization output and the synchronization input of each of the two or more ADCs are coupled via internal logic circuitry of the ADC.

[0174] Clause 27: The method of any of clauses 16-27, wherein resetting the internal filter by each of the two or more ADCs at a time synchronized with the master clock comprises resetting with respect to a time reference from the master clock. Preferably, the resetting of the internal filter is performed by the ADC after the ADC detects that a synchronization event has occurred.

[0175] Clause 28: The method of clause 27, wherein resuming sampling by each of the two or more ADCs in response to resetting the internal filter of each of the two or more ADCs comprises resuming with respect to the time reference.

[0176] Clause 29: The method of any of clauses 16-28, wherein the method further comprises monitoring, by the processor, that the sampling of the two or more ADCs is synchronized with the master clock following the restart of the master clock.

[0177] Clause 30: The method of any of clauses 16-29, wherein the method of stopping the master clock, restarting the master clock, and / or resuming sampling of the two or more ADCs is performed by a field programmable gate array (FPGA) or a processor such as a microcontroller unit (MCU).

[0178] Clause 31 : An analog-to-digital converter (ADC) system, the system comprising:

[0179] an ADC comprising an internal filter;

[0180] a master clock external to and coupled with the ADC; and

[0181] a processor external to and coupled with the ADC and the master clock; and

[0182] a memory and computer program code stored thereon, wherein the computer program code, when executed by the processor, causes:

[0183] the processor to stop sending a master clock signal to the ADC to pause sampling of the ADC, the master clock signal being provided to the ADC by the external master clock;

[0184] the ADC to detect that a synchronization event has occurred while the master clock is stopped;

[0185] the processor to restart the master clock signal to the ADC;

[0186] the ADC to reset the internal filter at a time synchronized with the master clock; and

[0187] the ADC to resume sampling in response to resetting the internal filter of the ADC.

[0188] Clause 32: The system of clause 31, wherein the ADC comprises a command trigger interface to receive a command from the processor indicating that the master clock has stopped and to latch the synchronization event trigger of the two or more ADCs.

[0189] Clause 33: The system of clause 31, wherein the ADC comprises an internal clock to detect the synchronization event and to latch the synchronization event trigger of the ADC.

[0190] Clause 34: The system of any one of clauses 31-33, wherein the ADC comprises an external synchronization output signal pin and an external synchronization input signal pin, and the synchronization output signal pin is coupled to the synchronization input signal pin.

[0191] Clause 35: The system of any one of clauses 31-34, wherein the ADC comprises internal logic circuitry to couple the synchronization output and synchronization input of the ADC.

[0192] Clause 36: The system of any one of clauses 31-35, wherein the processor is a field programmable gate array (FPGA) or a microcontroller unit (MCU).

[0193] Clause 37: The system of any one of clauses 31-36, wherein the system comprises two or more ADCs arranged such that each of the two or more ADCs is coupled to the processor and the shared master clock, respectively.

Claims

1. A method for synchronizing an analog-to-digital converter (ADC), the method comprising: a processor stopping a primary clock signal to an ADC to pause sampling by the ADC, the primary clock signal being provided to the ADC from an external primary clock; the ADC detecting that a synchronization event has occurred while the primary clock is stopped; the primary clock signal to the ADC being restarted by the processor; an internal filter of the ADC being reset at a time synchronized to the primary clock; and sampling by the ADC being resumed in response to the internal filter of the ADC being reset.

2. The method of claim 1, wherein resetting the internal filter comprises holding the internal filter in a reset state until sampling resumption has occurred.

3. The method of claim 1, wherein resuming sampling by the ADC comprises resuming sampling a fixed number of primary clock cycles after the primary clock is restarted.

4. The method of claim 1, wherein the ADC detecting a synchronization event comprises one or more of: receiving a command from the processor indicating a request for synchronization and latching a synchronization event flip-flop of the ADC; and detecting that the primary clock has stopped by an internal clock of the ADC and latching a synchronization event flip-flop of the ADC.

5. The method of claim 1, wherein the primary clock signal to the ADC being restarted by the processor comprises restarting the primary clock signal at a precisely controlled time.

6. The method of claim 4, further comprising: generating, by the ADC, a synchronization output signal at a synchronization output of the ADC, the synchronization output signal being synchronized to the primary clock; and registering, by the ADC, the synchronization output signal at a synchronization input of the ADC after a fixed number of primary clock cycles.

7. The method of claim 6, wherein the synchronization output and the synchronization input of the ADC are coupled through an external pin of the ADC, and wherein the method further comprises: resetting an internal filter of the ADC after the fixed number of primary clock cycles of the synchronization output signal being registered at the synchronization input of the ADC.

8. The method of claim 6, wherein the synchronization output and the synchronization input of the ADC are coupled via internal logic circuitry of the ADC.

9. The method of claim 1, wherein the internal filter of the ADC being reset at a time synchronized to the primary clock comprises resetting relative to a time reference from the primary clock.

10. A method for synchronizing two or more analog-to-digital converters (ADCs), the method comprising: a processor stopping a shared primary clock signal to two or more ADCs to pause sampling by the two or more ADCs, the shared primary clock signal being provided to the two or more ADCs from an external primary clock; a synchronization event having occurred while the shared primary clock is stopped being detected by each of the two or more ADCs; the shared primary clock signal being restarted to each of the two or more ADCs by the processor; an internal filter of each of the two or more ADCs being reset at a time synchronized to the primary clock; and sampling by each of the two or more ADCs being resumed. ​ resuming sampling by the two or more ADCs in response to resetting their respective internal filters.

11. The method of claim 10, wherein resetting the internal filter comprises holding the internal filter in a reset state until sampling resumption has occurred.

12. The method of claim 10, wherein resuming sampling of the two or more ADCs comprises resuming sampling after a fixed number of master clock cycles after the master clock has restarted.

13. The method of claim 10, wherein detecting the synchronization event by each of the two or more ADCs comprises one or more of: receiving a command from the processor indicating a request for synchronization and latching a synchronization event flip-flop of the two or more ADCs; and detecting by an internal clock of the two or more ADCs that the master clock has stopped and latching a synchronization event flip-flop of the two or more ADCs.

14. The method of claim 10, wherein restarting the master clock signal to each of the two or more ADCs by the processor comprises restarting the master clock signal at a precisely controlled time.

15. The method of claim 13, wherein the method further comprises: generating, by each of the two or more ADCs, a synchronization output signal at a synchronization output of each of the two or more ADCs, the synchronization output signal being synchronized with the master clock; and registering, by each of the two or more ADCs, the synchronization output signal at a synchronization input of each of the two or more ADCs after a fixed number of master clock cycles.

16. The method of claim 15, wherein the synchronization output and synchronization input of each of the two or more ADCs are coupled via external pins of each of the two or more ADCs, and wherein the method further comprises: resetting the internal filter of each of the two or more ADCs after the fixed number of master clock cycles of registering the synchronization output signal at the synchronization input of the two or more ADCs.

17. The method of claim 15, wherein the synchronization output and synchronization input of each of the two or more ADCs are coupled via internal logic circuitry.

18. The method of claim 10, wherein resetting the internal filter by each of the two or more ADCs at a time synchronized with the master clock comprises resetting with respect to a time reference from the master clock.

19. An analog-to-digital converter (ADC) system, the system comprising: an ADC comprising an internal filter; a master clock, the master clock being external to and coupled with the ADC; and a processor, the processor being external to and coupled with the ADC and the master clock; and a memory and computer program code stored thereon, wherein the computer program code, when executed by the processor, causes: the processor to stop sending a master clock signal to the ADC, the master clock signal being provided to the ADC by the external master clock, to pause sampling of the ADC; the processor to restart the master clock signal to the ADC to resume sampling of the ADC; and the processor to reset the internal filter of the ADC. the ADC detects that a synchronization event has occurred while the master clock is stopped; the processor restarts a master clock signal to the ADC; the ADC resets the internal filter at a time synchronized with the master clock; and the ADC resumes sampling in response to resetting the internal filter of the ADC.

20. The system of claim 19, wherein the system comprises two or more ADCs arranged such that each of the two or more ADCs is coupled to the processor and to a shared master clock, respectively.

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