Semiconductor device

Abstract

A semiconductor device can improve ranging accuracy while satisfying a communication standard. A baseband circuit (BBC) divides an original pulse signal into a plurality of divided pulse signals during transmission such that each frequency bandwidth falls within a frequency bandwidth range specified by a UWB communication standard and overlaps a common frequency range, and sequentially transmits the plurality of divided pulse signals to a reception terminal via an analog front end circuit (AFE) at a predetermined transmission interval. On the other hand, the baseband circuit BBC inputs a plurality of divided pulse signals sequentially received at a predetermined time difference during reception, corrects the time difference as if the plurality of divided pulse signals were simultaneously received, and further corrects the phases of the plurality of divided pulse signals so as to be continuous within a common frequency range. The baseband circuit BBC then recovers the original pulse signal by combining the corrected plurality of split pulse signals.

Description

[0001] Cross Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2024-069299 filed on April 22, 2024, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to semiconductor devices, such as semiconductor devices for wireless communication. BACKGROUND

[0004] The disclosed technology is listed below.

[0005] [Patent Literature 1] Japanese Unexamined Patent Application Publication No. 2021-131307

[0006] Patent Literature 1 discloses a signal processing apparatus for ultrasonic inspection, which can appropriately measure an inspection target. The apparatus first generates ultrasonic waves by driving an ultrasonic probe using a plurality of burst wave signals of different frequencies, and directs it to the inspection target. Subsequently, the apparatus receives a plurality of reflected waves corresponding to each of the burst wave signals incident on the inspection target, and performs detection processing on the received signals to acquire a plurality of detection signals. SUMMARY

[0007] For example, as a distance measurement technology, a technology using Bluetooth (registered trademark) or the like is known. On the other hand, in recent years, UWB (Ultra-Wide Band) technology utilizing an ultra-wide frequency bandwidth has attracted attention to achieve higher distance measurement accuracy. However, the radio frequency and the frequency bandwidth are limited by the UWB communication standard. Therefore, it is difficult to achieve higher distance measurement accuracy using a conventional UWB system. Therefore, a technology is needed to achieve higher distance measurement accuracy in a UWB system without violating the communication standard.

[0008] Embodiments described later are made in view of such a situation, and other problems and novel features will become apparent from the description and the drawings of the present specification.

[0009] A semiconductor device according to one embodiment is a device for UWB wireless communication, which is implemented in a transmission terminal or a reception terminal different from the transmission terminal. The semiconductor device includes a baseband circuit, a reference oscillation circuit, a local oscillation circuit, and an analog front-end circuit. The baseband circuit includes a memory for storing a transmission program or a reception program and a processor for executing the transmission program or the reception program, and the baseband circuit processes a baseband signal. The reference oscillation circuit generates a reference oscillation signal. The local oscillation circuit generates a local signal using the reference oscillation signal. The analog front-end circuit performs frequency conversion from the baseband signal to a high-frequency signal or from the high-frequency signal to the baseband signal using the local signal.

[0010] Here, when the semiconductor device is implemented in a transmission terminal, the baseband circuit performs the process (a) and the process (b) based on a transmission program, and when the semiconductor device is implemented in a reception terminal, the semiconductor device performs the process (c), the process (d), and the process (e) based on a reception program. In the process (a), the baseband circuit divides an original pulse signal that is to be a baseband signal into a plurality of divided pulse signals including a first divided pulse signal and a second divided pulse signal so that each frequency bandwidth is within a frequency bandwidth range specified by a UWB communication standard and overlaps a common frequency range that is a part of the frequency bandwidth. In the process (b), the baseband circuit sequentially transmits the plurality of divided pulse signals to the reception terminal via an analog front-end circuit at a first transmission interval.

[0011] On the other hand, in the process (c), the baseband circuit inputs the plurality of divided pulse signals that are sequentially received based on a time difference of the first transmission interval via the analog front-end circuit, and corrects the time difference of the plurality of divided pulse signals so that the plurality of divided pulse signals are as if received simultaneously. In the process (d), the baseband circuit corrects phases of the plurality of divided pulse signals so as to be continuous within the common frequency range. In the process (e), the baseband circuit restores the original pulse signal by adding the plurality of divided pulse signals after the time difference correction in the process (c) and the phase correction in the process (d) are performed.

[0012] According to the present embodiment, it is possible to improve the distance measurement accuracy while satisfying the communication standard. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a block diagram illustrating a schematic configuration example of a semiconductor device according to one embodiment;

[0014] Figure 2 is a schematic diagram illustrating a processing content of the transmission circuit when dividing the pulse signal; Figure 1

[0015] Figure 3 is a schematic diagram illustrating a processing content of the time difference correction performed by the reception circuit; Figure 1

[0016] Figure 4 Figure 1

[0017] Figure 5 Figure 1

[0018] ​​​​​​Figure 6 is a flowchart illustrating an example of detailed processing contents of the transmission circuit shown in Figure 1

[0019] Figure 7 is a schematic diagram illustrating a part of the processing contents shown in Figure 6

[0020] Figure 8 is a schematic diagram illustrating a part of the processing contents shown in Figure 6

[0021] Figure 9 is a schematic diagram illustrating a part of the processing contents shown in Figure 6

[0022] Figure 10 is a flowchart illustrating an example of detailed processing contents of the reception circuit shown in Figure 1

[0023] Figure 11 is a schematic diagram illustrating a part of the processing contents shown in Figure 10

[0024] Figure 12 is a schematic diagram illustrating a part of the processing contents shown in Figure 10

[0025] Figure 13 is a schematic diagram illustrating a part of the processing contents shown in Figure 10

[0026] Figure 14 is a schematic diagram illustrating an example of modified processing contents of Figure 2

[0027] Figure 15 is a schematic diagram illustrating an example of a distance measurement method using a UWB system;

[0028] Figure 16A is a waveform diagram illustrating an example of a pulse signal used in a UWB system;

[0029] Figure 16B is a graph illustrating an example of frequency characteristics of the pulse signal shown in Figure 16A

[0030] Figure 17A is a schematic diagram illustrating an example of a method for dividing the frequency bandwidth of an original pulse signal during transmission in a UWB system;

[0031] Figure 17B ​​​​​​​​​​is a schematic diagram illustrating an example of a method for splitting a frequency bandwidth of an original pulse signal during transmission in a UWB system;

[0032] Figure 18A is a schematic diagram illustrating an example of a method for recovering an original pulse signal from a plurality of split pulse signals during reception in a UWB system;

[0033] Figure 18B is a schematic diagram illustrating an example of a method for recovering an original pulse signal from a plurality of split pulse signals during reception in a UWB system;

[0034] Figure 19 is a schematic diagram illustrating an example of a problem when using a frequency bandwidth splitting method in a UWB system; and

[0035] Figure 20 is a schematic diagram illustrating another example of a problem when using a frequency bandwidth splitting method in a UWB system. DETAILED DESCRIPTION

[0036] In the following embodiments, for the sake of convenience, the description can be divided into a plurality of sections or embodiments, if necessary, but unless otherwise specifically stated, they are not independent of each other, and one section or embodiment is related to another section or embodiment as a partial or entire modification, a detail, a supplementary explanation, etc. In addition, in the following embodiments, when referring to the number of elements, etc. (including quantity, value, amount, range, etc.), unless otherwise explicitly stated, and unless it is explicitly limited to a specific number, it can be more or less than the specific number.

[0037] In addition, in the following embodiments, it goes without saying that, unless otherwise specifically stated, constituent elements (including element steps, etc.) are not necessarily essential, unless they are considered to be explicitly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of an assembly, etc., unless otherwise specifically stated, and unless it is explicitly considered not to be the case in principle, it is assumed to include those shapes, etc. substantially approximate or similar to the shapes. The same applies to the above-mentioned values and ranges.

[0038] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings. In all the drawings used to explain the embodiments, the same components are given the same reference numerals in principle, and repetitive explanation thereof is omitted.

[0039] (Configuration of Semiconductor Device)

[0040] Figure 1is a block diagram illustrating a schematic configuration example of a semiconductor device 10 according to an embodiment. The semiconductor device 10 is a semiconductor device for UWB wireless communication implemented in a transmission terminal or a reception terminal different from the transmission terminal. The semiconductor device 10 is, for example, an SoC (System on Chip) composed of a single semiconductor chip.

[0041] Figure 1 The illustrated semiconductor device 10 includes an oscillation circuit OSC, a local oscillation circuit LOSC, a baseband circuit BBC, and an analog front-end circuit AFE. The oscillation circuit OSC is connected to a crystal oscillator XTAL provided outside the semiconductor device 10. Thus, the oscillation circuit OSC and the crystal oscillator XTAL constitute a reference oscillation circuit ROSC, in other words, a crystal oscillation circuit that generates a reference oscillation signal RO. Although not illustrated, the semiconductor device 10 operates based on a clock signal generated using the reference oscillation signal RO.

[0042] The local oscillation circuit LOSC generates local signals LOL and LO2 synchronized with the reference oscillation signal RO using the reference oscillation signal RO. The local signals LOL and LO2 have a frequency on the order of GHz, such as 10 GHz, based on a UWB communication standard, and are signals that differ from each other by 90 degrees. The local oscillation circuit LOSC can be specifically configured using, for example, a PLL (Phase-Locked Loop) circuit.

[0043] The baseband circuit BBC includes a processor PRC, a memory MEM, a data transmission circuit DTC, and a divided pulse signal extraction circuit PDE, and processes a baseband signal. The processor PRC is, for example, a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). The memory MEM includes a non-volatile memory NVM and a volatile memory RAM. The non-volatile memory NVM is, for example, an MRAM (Magnetoresistive Random Access Memory) or a flash memory. The volatile memory RAM is, for example, an SRAM (Static RAM).

[0044] The non-volatile memory NVM stores a transmission program PRGtx and a reception program PRGrx. The processor PRC executes the transmission program PRGtx and the reception program PRGrx stored in the MRAM or copied from the flash memory to the volatile memory RAM. By executing the transmission program PRGtx, the processor PRC functions as a pulse signal generation circuit PLSG and a pulse signal division circuit PLSD. In other words, the transmission program PRGtx enables the processor PRC to function as the pulse signal generation circuit PLSG and the pulse signal division circuit PLSD.

[0045] Further, by executing the reception program PRGrx, the processor PRC functions as a time difference correction circuit TDCC, a phase difference estimation circuit PHDE, a phase correction circuit PHCC, and a signal restoration circuit RESC. In other words, the reception program PRGrx enables the processor PRC to function as the time difference correction circuit TDCC, the phase difference estimation circuit PHDE, the phase correction circuit PHCC, and the signal restoration circuit RESC.

[0046] The volatile memory RAM has a transmission data storage area AR-TXD and a reception data storage area AR-RXD. Details thereof will be described later, but the processor PRC generates a transmission digital signal based on the transmission program PRGtx. Then, the processor PRC stores the generated transmission digital signal in the transmission data storage area AR-TXD. The data transmission circuit DTC sequentially transmits the transmission digital signal stored in the transmission data storage area AR-TXD to the analog front-end circuit AFE. The data transmission circuit DTC can be implemented using a circuit similar to a DMA (Direct Memory Access) controller.

[0047] Further, as will be described in detail later, the split pulse signal extraction circuit PDE stores a digital signal received from the analog front-end circuit AFE in the reception data storage area AR-RXD. The split pulse signal extraction circuit PDE can also be implemented using a circuit similar to a DMA controller. The processor PRC processes a reception digital signal stored in the reception data storage area AR-RXD based on the reception program PRGrx.

[0048] The analog front-end circuit AFE includes digital-to-analog converters DAC1 and DAC2, analog-to-digital converters ADC1 and ADC2, a frequency conversion circuit FCV, a transmission amplifier AMP, and a reception amplifier LNA. The digital-to-analog converters DAC1 and DAC2 convert a transmission digital signal stored in the transmission data storage area AR-TXD and input via the data transmission circuit DTC into a transmission analog signal. The transmission analog signal as well as the transmission digital signal is also a baseband signal, and in UWB, it becomes a transmission pulse signal Ptx.

[0049] The analog-to-digital converters ADC1 and ADC2 convert a reception analog signal from the frequency conversion circuit FCV into a reception digital signal. The reception analog signal and the reception digital signal are also baseband signals, and in UWB, it becomes a reception pulse signal Prx. Then, the analog-to-digital converters ADC1 and ADC2 store the converted reception digital signal in the reception data storage area AR-RXD via the split pulse signal extraction circuit PDE.

[0050] In this example, in order to perform quadrature modulation / demodulation (IQ modulation / IQ demodulation), a pair of digital-to-analog converters DAC1 and DAC2 and a pair of analog-to-digital converters ADC1 and ADC2 are provided. However, various circuit configurations of an analog front-end circuit AFE used in UWB are known, and are not necessarily limited to Figure 1 The circuit configuration shown.

[0051] The frequency conversion circuit FCV includes a transmission conversion circuit CVtx and a reception conversion circuit CVrx. The transmission conversion circuit CVtx has filters FLTt1 and FLTt2, mixers MIXt1 and MIXt2, and an adder ADD. The reception conversion circuit CVrx has filters FLTr1 and FLTr2 and mixers MIXr1 and MIXr2.

[0052] In the transmission conversion circuit CVtx, the filters FLTt1 and FLTt2 filter transmission analog signals (i.e., transmission pulse signals Ptx) from the digital-to-analog converters DAC1 and DAC2. The mixers MIXt1 and MIXt2 multiply the filtered signals with local signals LO1 and LO2 from the local oscillation circuit LOSC. The adder ADD adds the signals from the mixers MIXt1 and MIXt2.

[0053] With this configuration, the transmission conversion circuit CVtx performs frequency conversion from a baseband signal to a high-frequency signal, i.e., up-conversion, using the local signals LO1 and LO2 from the local oscillation circuit LOSC. Further, in this example, the transmission conversion circuit CVtx inputs I and Q signals that constitute the transmission pulse signals Ptx from the digital-to-analog converters DAC1 and DAC2, and performs quadrature modulation using the local signals LO1 and LO2 having a 90-degree phase difference.

[0054] On the other hand, in the reception conversion circuit CVrx, the mixers MIXr1 and MIXr2 multiply high-frequency signals from the reception amplifier LNA with the local signals LO1 and LO2 from the local oscillation circuit LOSC. The filters FLTr1 and FLTr2 filter the signals from the mixers MIXr1 and MIXr2, and output them to the analog-to-digital converters ADC1 and ADC2.

[0055] With this configuration, the reception conversion circuit CVrx performs frequency conversion from a high-frequency signal to a baseband signal, i.e., down-conversion, using the local signals LO1 and LO2 from the local oscillation circuit LOSC. Further, in this example, the reception conversion circuit CVrx inputs high-frequency signals from the reception amplifier LNA, and quadrature-demodulates them into I and Q signals using the local signals LO1 and LO2.

[0056] The transmission amplifier AMP amplifies the high-frequency signal from the transmission conversion circuit CVtx, specifically from the adder ADD. Then, the transmission amplifier AMP radiates the amplified high-frequency signal RFtx into the air via an antenna ANT provided outside the semiconductor device 10. On the other hand, the reception amplifier LNA (e.g., a low-noise amplifier) amplifies the high-frequency signal RFrx received by the external antenna ANT, and outputs the amplified high-frequency signal to the reception conversion circuit CVrx, specifically to the mixers MIXrl and MIXr2.

[0057] The pulse signal generation circuit PLSG, the pulse signal division circuit PLSD, the transmission data storage region AR-TXD, the data transmission circuit DTC, the digital-analog converters DACl and DAC2, the transmission conversion circuit CVtx, and the transmission amplifier AMP constitute the transmission circuit TXC. On the other hand, the time difference correction circuit TDCC, the phase difference estimation circuit PHDE, the phase correction circuit PHCC, the signal recovery circuit RESC, the reception data storage region AR-RXD, the analog-digital converters ADCl and ADC2, the reception conversion circuit CVrx, and the reception amplifier LNA constitute the reception circuit RXC.

[0058] Further, in this example, the baseband circuit BBC is implemented by program processing by the processor PRC. However, the baseband circuit BBC is not limited to the processor PRC, and can be implemented using, for example, an FPGA (Field Programmable Gate Array) or a dedicated digital circuit. That is, the baseband circuit BBC can be implemented by using a combination of the processor PRC and the FPGA or the dedicated digital circuit. Figure 1 The semiconductor device 10 illustrated can include an FPGA or a dedicated digital circuit. Before explaining details of the semiconductor device 10 illustrated, Figure 1 Before explaining details of the semiconductor device 10 illustrated,

[0059] (Regarding the distance measurement method)

[0060] Figure 15 is a schematic diagram illustrating an example of a distance measurement method using a UWB system. Figure 15 The UWB system illustrated includes two transceiver terminals TRXl and TRX2. As Figure 1 As illustrated, both of the transceiver terminals TRXl and TRX2 implement semiconductor devices 10a and 10b.

[0061] In this UWB system, first, the transceiver terminal TRX1 functions as a transmission terminal, and transmits a pulse signal to the transceiver terminal TRX2 at timing t0. The transmitted pulse signal arrives at the transceiver terminal TRX2 after a time of flight ToF. The transceiver terminal TRX2 functions as a reception terminal, and estimates the arrival timing tOA1 of the pulse signal from the transceiver terminal TRX1. Then, the transceiver terminal TRX2 functions as a transmission terminal, and transmits a pulse signal to the transceiver terminal TRX1 after waiting for a predetermined waiting time Tw from the estimated arrival timing tOA1.

[0062] The transmitted pulse signal arrives at the transceiver terminal TRX1 after a time of flight ToF. The transceiver terminal TRX1 functions as a reception terminal, and estimates the arrival timing tOA2 of the pulse signal from the transceiver terminal TRX2. Then, the transceiver terminal TRX1 calculates the time of flight ToF as "2 ToF + Tw". That is, the transceiver terminal TRX1 can calculate the time of flight ToF by subtracting the waiting time Tw from the time from the timing t0 to the arrival timing tOA2 and dividing the result by 2. Furthermore, the transceiver terminal TRX1 can also calculate the distance between the two transceiver terminals TRX1 and TRX2 based on the time of flight ToF.

[0063] (Regarding pulse signals based on the UWB standard)

[0064] Figure 16A is a waveform chart illustrating examples of pulse signals Pa and Pb used in a UWB system. Figure 16B is a chart illustrating Figure 16A an example of the frequency characteristics of the pulse signals Pa and Pb shown. In a UWB system, as shown in Figure 16A , pulse signals Pa and Pb having a high peak value and a narrow time width are used. By transmitting and receiving such pulse signals Pa and Pb between two terminals, distance measurement as shown in Figure 15 can be performed.

[0065] Here, in distance measurement, the measurement error increases as the time width of the pulse signals Pa and Pb increases. That is, as shown in Figure 15 , the estimation error of the arrival timings tOA1 and tOA2 can become large. Therefore, in order to improve the accuracy of distance measurement, it is desirable to use pulse signals with a clearer waveform.

[0066] On the other hand, in such pulse signals, the more acute the waveform shape, that is, the higher the peak value and the narrower the time width, the greater the frequency bandwidth. In Figure 16B the example shown, the frequency bandwidth of the pulse signal Pa is 250 MHz. In contrast, the frequency bandwidth of the pulse signal Pb having a more acute waveform shape is 500 MHz.

[0067] However, the allowable frequency bandwidth is often limited to a predetermined value based on the communication standard, to avoid interference with other communication devices. For example, if the allowable frequency bandwidth is limited to 250 MHz, it can be difficult to perform distance measurement using a pulse signal Pb with a sharper waveform shape. Therefore, it can also be difficult to improve the accuracy of distance measurement.

[0068] (Division of frequency bandwidth)

[0069] Therefore, a method for dividing the frequency bandwidth of a pulse signal is considered. Figure 17A and Figure 17B are schematic diagrams showing an example of a method for dividing the frequency bandwidth of an original pulse signal during transmission in a UWB system. Figure 17A The amplitude (Mag) spectrum and the phase (Phase) spectrum of an original pulse signal POtx for transmission are shown. The original pulse signal POtx has a frequency bandwidth from a frequency fl to a frequency f2.

[0070] Furthermore, Figure 17A Two or two-channel spectrum masks SMcl and SMc2 are shown. Each spectrum mask SMcl and SMc2 defines an allowable range of the frequency bandwidth and the amplitude contained in a pulse signal based on the communication standard. In this example, the spectrum mask SMcl limits the pulse signal to a bandwidth from the frequency fl to a frequency f3 (< f2). On the other hand, the spectrum mask SMc2 limits the pulse signal to a bandwidth from the frequency f3 to the frequency f2.

[0071] The semiconductor device 10 divides the original pulse signal POtx into two divided pulse signals PD1 and PD2 each having a different frequency bandwidth, using the two spectrum masks SMcl and SMc2, so as to be within the frequency bandwidth range specified by the communication standard. Then, as Figure 17B shown, the semiconductor device 10 sequentially transmits the two divided pulse signals PD1 and PD2 with a certain time offset. Therefore, the frequency bandwidth of the signal transmitted at one time can satisfy the communication standard.

[0072] Figure 18A and Figure 18B are schematic diagrams showing an example of a method for recovering an original pulse signal from a plurality of divided pulse signals PD1 and PD2 during reception in a UWB system. As Figure 18A shown, the semiconductor device 10 sequentially receives a plurality of divided pulse signals PD1 and PD2 transmitted with a certain time offset, and corrects the time difference to eliminate the offset time. That is, the semiconductor device 10 corrects the time difference of the plurality of divided pulse signals PD1 and PD2 so that they are received simultaneously at timing tl.

[0073] Then, asFigure 18A As shown, the semiconductor device 10 synthesizes (specifically, adds) the signals having the corrected time difference to recover the original pulse signal POrx. Ideally, the recovered pulse signal POrx has the same waveform shape as the original pulse signal POtx at the transmission time. That is, as shown, the amplitude spectrum and the phase spectrum of the recovered original pulse signal POrx are the same as Figure 18B the amplitude spectrum and the phase spectrum of the original pulse signal POtx at the transmission time. Figure 17A

[0074] (Problems regarding the frequency bandwidth division method)

[0075] However, Figure 17A , Figure 17B , Figure 18A and Figure 18B The frequency bandwidth division method described in PTL 1 and PTL 2 can cause the following problems. Figure 19 is a schematic diagram showing an example of a problem when the frequency bandwidth division method is used in a UWB system. As a first problem, as shown, phase shifts 21 and 22 can occur in the divided pulse signals PD1 and PD2 received by the reception terminal based on the phase PHo of the original pulse signal POtx at the transmission time. Figure 19

[0076] The main reason for such phase shifts 21 and 22 is, for example, Figure 15 as shown, the two transceiver terminals TRX1 and TRX2 do not share the reference oscillation circuit ROSC shown in Figure 1 . That is, the transceiver terminal TRX1 is connected to the crystal oscillator XTAL implemented in the transceiver terminal TRX1 and operates based on the vibration of the crystal oscillator XTAL. On the other hand, the transceiver terminal TRX2 is connected to another crystal oscillator XTAL implemented in the transceiver terminal TRX2 and operates based on the vibration of the crystal oscillator XTAL. As a result, the frequency and the phase recognized by each of the two transceiver terminals TRX1 and TRX2 can strictly differ from each other.

[0077] When the phase shifts 21 and 22 occur, in the recovered original pulse signal POrx, a discontinuous point 24 occurs at the boundary between the phase PHr1 of the divided pulse signal PD1 and the phase PHr2 of the divided pulse signal PD2. As a result, a pulse signal POrx having a waveform shape different from the original pulse signal POtx at the transmission terminal can be recovered at the reception terminal. When the pulse signal POrx differs from the pulse signal at the time of transmission recovered in this way, as shown, Figure 15 the accuracy of distance measurement can be reduced based on the pulse signal POrx.

[0078] ​​Figure 20 is a diagram illustrating another example of a problem when a frequency bandwidth division method is used in a UWB system. As Figure 20 indicated, for example, with reference to the antenna ANT, the transmission interval Ttx of the two divided pulse signals PD1 and PD2 in the transceiver terminal TRX1 and the reception interval Trx of the two divided pulse signals PF1 and PD2 in the transceiver terminal TRX2 have the same length.

[0079] Therefore, for example, the two transceiver terminals TRX1 and TRX2 can hold in advance the number of common clock periods "N" indicating the transmission interval Ttx and the reception interval Trx. As a result, as Figure 18A indicated, the transceiver terminal TRX2 can align the two divided pulse signals PD1 and PD2 at the same timing tl by internal processing based on the number of common clock periods "N".

[0080] However, in practice, the two transceiver terminals TRX1 and TRX2 do not share the reference oscillation circuit ROSC as Figure 1 indicated. Therefore, as a second problem, as Figure 20 indicated, the number of clock periods "N" in the transceiver terminal TRX1 indicating the transmission interval Ttx and the number of clock periods "M" in the transceiver terminal TRX2 indicating the reception interval Trx can be different. As a result, in the method of defining the number of common clock periods "N" as described above, it can be difficult to perform a high-precision recovery process. Therefore, it is beneficial to use the semiconductor device 10, and in particular the baseband circuit BBC, as Figure 1 indicated.

[0081] (Outline of main components of transmission circuit)

[0082] Figure 2 is a diagram illustrating an example of the processing content when the transmission circuit TXC divides a pulse signal, as Figure 1 indicated. In Figure 2 , similarly to the case of Figure 17A , the transmission circuit TXC divides the original pulse signal POtx having a frequency bandwidth from the frequency fl to the frequency f2 into a plurality of divided pulse signals, in this example, two divided pulse signals PD1 and PD2, so that each frequency bandwidth falls within the range specified by the UWB communication standard.

[0083] However, in this case, unlike the case in Figure 17A , the transmission circuit TXC divides the original pulse signal POtx into two divided pulse signals PD1 and PD2 to overlap with the common frequency range 30 that is a part of the frequency bandwidth. Then, similarly to Figure 17BSimilar to the case in , the transmission circuit TXC sequentially transmits the two divided pulse signals PD1 and PD2 at predetermined transmission intervals.

[0084] (Overview of the main parts of the receiving circuit)

[0085] On the other hand, Figure 18A Similar to the case of , the receiving circuit RXC first receives a plurality of divided pulse signals, for example, two divided pulse signals PD1 and PD2, sequentially at a predetermined receiving interval (i.e., a time difference based on a predetermined transmission interval). Then, the baseband circuit BBC within the receiving circuit RXC corrects the time difference of the two divided pulse signals PD1 and PD2 sequentially input via the analog front-end circuit AFE, as if the plurality of divided pulse signals were received simultaneously. However, in this case, the baseband circuit BBC uses a method of calculating a correlation function as described below, which is different from Figure 20 The method mentioned in for determining the number "N" of common clock cycles representing the transmission interval Ttx and the reception interval Trx is different.

[0086] (Time difference correction)

[0087] Figure 3 The diagram is provided by Figure 1 FIG. 1 is a schematic diagram showing an example of the processing contents of the time difference correction performed by the receiving circuit RXC shown in FIG. Figure 1 The divided pulse signal extraction circuit PDE shown extracts received digital signals Drd1 and Drd2 corresponding to the divided pulse signals PD1 and PD2 respectively from the received digital signals from the analog-to-digital converters ADC1 and ADC2 based on the time difference of the common clock cycle number "N" mentioned above.

[0088] Then, if Figure 3 As shown, the divided pulse signal extraction circuit PDE stores the extracted reception digital signals Drd1 and Drd2 in the reception data storage area AR-RXD. Figure 20 As shown, the correct time difference between the two divided pulse signals PD1 and PD2 is not necessarily the number of common clock cycles "N", but may also be a number before or after it.

[0089] Therefore, in the case where the reception timing of one divided pulse signal (here, PD2) is offset, the baseband circuit BBC in the receiving circuit RXC uses the received digital signals Drd1 and Drd2 stored in the received data storage area AR-RXD to calculate the correlation function of the two divided pulse signals PD1 and PD2, as shown in FIG. Figure 3The baseband circuit BBC then searches for an offset that maximizes the correlation function (i.e., similarity) of the two split pulse signals PD1 and PD2. Specifically, the baseband circuit BBC calculates the correlation function, i.e., inner product, of the two split pulse signals PD1 and PD2 based on Equation (1).

[0090] (Drd1, Drd2) =∑(Drd1(i)Drd2(j) (Equation 1)

[0091] In Equation 1, Drd1(i) is the digital value of the split pulse signal PD1 sampled at the sampling timing (i). Drd2(j) is the digital value of the split pulse signal PD2 sampled at the offset sampling timing (j). The baseband circuit BBC performs the operation shown in Equation 1 to find the offset that maximizes the inner product, and applies the offset to perform the time difference correction to match the reception timings of the two split pulse signals PD1 and PD2.

[0092] In the example shown, when the reception timing of the split pulse signal PD2 is offset from the common clock period number “N” as a starting point, the inner product is maximized at the offset candidate [1]. The baseband circuit BBC can correct the time difference by applying this offset candidate [1], thereby matching the reception timings of the two split pulse signals PD1 and PD2. Figure 3 (Regarding Phase Correction)

[0093]

[0094] is a schematic diagram illustrating an example of the processing content of the phase correction performed by the reception circuit RXC shown in Figure 4 As shown in Figure 1 , the baseband circuit BBC within the reception circuit RXC corrects the phases of the two split pulse signals PD1 and PD2 after the time difference correction so that they are continuous within the common frequency range 30. Specifically, the baseband circuit BBC corrects the phase PHr2 of the split pulse signal PD2 to the phase PHr2c so that it is continuous with the phase PHr1 of the split pulse signal PD1 within the common frequency range 30, as shown in Figure 4 Figure 4

[0095] The baseband circuit BBC then synthesizes (specifically, adds) the two split pulse signals PD1 and PD2 after the phase correction to restore the original pulse signal POrx. By performing such time difference correction and phase correction, the original pulse signal POrx restored at the reception time will have the same waveform shape as the original pulse signal POtx at the transmission time.

[0096] On the other hand, in order to perform the phase correction as Figure 4 ​​The phase correction shown requires obtaining a phase difference between the phase PHr1 of the divided pulse signal PD1 and the phase PHr2 of the divided pulse signal PD2. For example, one method for obtaining such a phase difference is to use a Fourier transform. However, using a Fourier transform can result in a large amount of calculation.

[0097] Therefore, the baseband circuit BBC multiplies the divided pulse signals PD1 and PD2 to obtain a phase difference, and extracts a DC component from the multiplication result. That is, the baseband circuit BBC applies a low-pass filter to the multiplication result to remove an AC component. As a result, the baseband circuit BBC can estimate the phase difference between the phase PHr1 of the divided pulse signal PD1 and the phase PHr2 of the divided pulse signal PD2 with a small amount of calculation.

[0098] Figure 5 is a diagram illustrating when Figure 1 A diagram illustrating the operation principle when the reception circuit RXC estimates a phase difference between the two divided pulse signals PD1 and PD2 is shown. First, the multiplication result of the divided pulse signals PD1 and PD2 is given by Equation 2. In Equation 2, f1, θ1, and A1 are the frequency, phase, and amplitude of the divided pulse signal PD1, respectively. f2, θ2, and A2 are the frequency, phase, and amplitude of the divided pulse signal PD2, respectively.

[0099] 2A1cos(2πf1t+θ1)A2cos(2πf2t+θ2)=A1A2cos{2π(f1+f2)t+(θ1+θ2)}+A1A2cos{2π(f1-f2)t+(θ1-θ2)}

[0100] (Equation 2)

[0101] Here, in Equation 2, if the frequency f1 and the frequency f2 do not match, a DC component is not generated. On the other hand, if the frequency f1 and the frequency f2 match, a DC component "A1A2cos(θ1-θ2)" is generated. Therefore, by applying a low-pass filter to the multiplication result, the DC component "A1A2cos(θ1-θ2)" can be extracted.

[0102] As Figure 5 shown, the extracted DC component "A1A2cos(θ1-θ2)" represents a phase difference "θ1-θ2" at a matching frequency fX included in the common frequency range 30. Therefore, the baseband circuit BBC can cause the phase PHr1 of the divided pulse signal PD1 and the phase PHr2 of the divided pulse signal PD2 to be continuous within the common frequency range 30 based on the phase difference "θ1-θ2" at the matching frequency fX, as Figure 4 shown.

[0103] (Detailed operation of the transmission circuit TXC)

[0104] Figure 6 is a flowchart illustrating an example of detailed processing contents of the transmission circuit TXC. Figure 1 Figure 7 、 Figure 8 and Figure 9 are schematic diagrams that explain a part of the processing contents illustrated in Figure 6 in more detail. In Figure 6 , first, the pulse signal generation circuit PLSG generates the original pulse signal POtx (step S101). As Figure 7 illustrated, the original pulse signal POtx has a frequency bandwidth from a frequency flL to a frequency f2H.

[0105] Subsequently, in step S102, the pulse signal dividing circuit PLSD divides the original pulse signal POtx into a plurality of divided pulse signals, for example, two divided pulse signals PD1 and PD2, so that each frequency bandwidth falls within a range specified by a UWB communication standard. At this time, the pulse signal dividing circuit PLSD divides the original pulse signal POtx into two divided pulse signals PD1 and PD2 that overlap with the common frequency range 30. Then, the pulse signal dividing circuit PLSD stores transmission digital signals Dtd1 and Dtd2 corresponding to the two divided pulse signals PD1 and PD2 in the transmission data storage area AR-TXD.

[0106] Specifically, in step S102, as Figure 7 illustrated, the pulse signal dividing circuit PLSD divides the original pulse signal POtx into two divided pulse signals PD1 and PD2 using two filters FLTdl and FLTd2. The filter FLTdl has a passband from a frequency lower than the frequency flL to a frequency flH. On the other hand, the filter FLTd2 has a passband from a frequency f2L (< flH) to a frequency f2H or more. The common frequency range 30 is a range from the frequency f2L to the frequency flH.

[0107] The two filters FLTdl and FLTd2 have frequency characteristics such that they have a predetermined gain value, in this example, "1", in a frequency band other than the common frequency range 30. On the other hand, the two filters FLTdl and FLTd2 have frequency characteristics such that the sum of the gain value of the filter FLTdl and the gain value of the filter FLTd2 produces a predetermined gain value "1" within the common frequency range 30. That is, the combined filter FLTd of the two filters FLTdl and FLTd2 has a predetermined gain value "1" within the frequency bandwidth of the original pulse signal POtx.

[0108] Next, in Figure 6 ​In step S103 shown, the data transmission circuit DTC sequentially transmits the two divided pulse signals PD1 and PD2, specifically the transmission digital signals Dtd1 and Dtd2 stored in the transmission data storage area AR-TXD, to the digital-to-analog converters DAC1 and DAC2 at a predetermined transmission interval Ttx. Specifically, Figure 8 As shown, the transmission digital signals Dtd1 and Dtd2 are stored as time-series data in the memory address MADR area which is sequentially allocated starting from predetermined start addresses #A1 and #A2 in the transmission data storage area AR-TXD.

[0109] The data transmission circuit DTC sequentially reads out the transmission digital signal Dtd1 from the transmission data storage area AR-TXD at a transmission speed of, for example, several GHz, and then sequentially reads out the transmission data signal Dtd2 after a predetermined transmission interval Ttx. The digital-to-analog converters DAC1 and DAC2 convert the sequentially read transmission digital signals Dtd1 and Dtd2 into analog signals at a sampling frequency of, for example, several GHz, which is the same as the transmission speed.

[0110] Later, in Figure 6 In step S104 shown, the transmission conversion circuit CVtx uses the local signals LO1 and LO2 to up-convert the two divided pulse signals PD1 and PD2 converted into analog signals by the digital-to-analog converters DAC1 and DAC2 into high-frequency signals. Figure 9 Next, as Figure 9 As shown, the transmission amplifier AMP amplifies the up-converted high frequency signal (step S105 ) and then radiates the amplified high frequency signal RFtx into the air via the external antenna ANT (step S106 ).

[0111] (Detailed Operation of Receiver Circuit RXC)

[0112] Figure 10 It shows Figure 1 Flowchart showing an example of detailed processing contents of the reception circuit RXC. Figure 11 、 Figure 12 and Figure 13 A more specific explanation Figure 10 A schematic diagram of a portion of the processing content shown. Figure 10 In the present invention, first, the receiving circuit RXC receives the high-frequency signal RFrx via the external antenna ANT (step S201).

[0113] Then, in step S202, as Figure 11As shown, a receive amplifier LNA amplifies a received high-frequency signal RFrx. Further, a receive conversion circuit CVrx down-converts the amplified high-frequency signal to a baseband signal. Then, analog-digital converters ADC1 and ADC2 sequentially convert the down-converted signal to a reception digital signal at a sampling frequency of, for example, several GHz.

[0114] Next, in Figure 10 As shown in step S203, a split pulse signal extraction circuit PDE extracts two split pulse signals PD1 and PD2 from the reception digital signals from the analog-digital converters ADC1 and ADC2 based on a predetermined time difference. Then, the split pulse signal extraction circuit PDE stores the extracted two split pulse signals PD1 and PD2, specifically, reception digital signals Drd1 and Drd2 corresponding to the two split pulse signals PD1 and PD2, in a reception data storage area AR-RXD.

[0115] Specifically, in step S203, as Figure 12 shown, the split pulse signal extraction circuit PDE previously holds a value of a time difference determined based on a transmission interval Ttx, that is, a reception interval Trx, and extracts reception digital signals Drd1 and Drd2 corresponding to the two split pulse signals PD1 and PD2 based on the value of the time difference. Then, the split pulse signal extraction circuit PDE stores the extracted reception digital signals Drd1 and Drd2 as time series data in a memory address MADR area allocated sequentially from predetermined start addresses #A1 and #A2 in the reception data storage area AR-RXD.

[0116] However, as Figure 20 shown, the number of clock cycles representing a time difference at a transmission terminal can be different from the number of clock cycles representing the same time difference at a reception terminal. Therefore, as Figure 12 shown, when matching the reception timings of the two reception digital signals Drd1 and Drd2 stored in the reception data storage area AR-RXD, a timing error At can occur, and thereby causing an offset of the memory address MADR.

[0117] Therefore, in Figure 10 step S204 shown, a time difference correction circuit TDCC corrects the time difference of the two split pulse signals PD1 and PD2 by performing the process described in Figure 3 Figure 12 , using the reception digital signals Drd1 and Drd2 stored in the reception data storage area AR-RXD. That is, the time difference correction circuit TDCC makes the timing error At shown closer to zero. To perform Figure 3 ​The split pulse signal extraction circuit PDE extracts the split pulse signal PD2 including a time period before and after the predetermined time difference, by the process described in the section.

[0118] Subsequently, in Figure 10 the step S205, the phase difference estimation circuit PHDE estimates the phase difference "θ1-θ2" of the two split pulse signals PD1 and PD2 within the common frequency range 30, by the process described in the section. Figure 5 That is, the phase difference estimation circuit PHDE estimates the phase correction amount used in the phase correction circuit PHCC. Then, as Figure 4 indicated, the phase correction circuit PHCC corrects the phases of the two split pulse signals PD1 and PD2 to be continuous within the common frequency range 30 based on the estimated phase difference (step S206). In Figure 4 the example indicated, the phase correction circuit PHCC corrects the phase PHr2 of the split pulse signal PD2 to be the phase PHr2c.

[0119] Figure 13 is a block diagram showing a schematic configuration example of the phase correction circuit PHCC in Figure 1 . The phase correction circuit PHCC includes, for example, a digital complex mixer as Figure 13 indicated. In brief, the phase correction circuit PHCC uses such a complex mixer to multiply the received digital signal Drd2 corresponding to the split pulse signal PD2 by the cosθ and sinθ components, thereby shifting the phase of the split pulse signal PD2 by "θ". In Figure 10 the step S205, the value of "θ" is set to the estimated phase difference value, i.e. Figure 5 "θ1-θ2" in

[0120] In detail, the phase correction circuit PHCC inputs an I signal and a Q signal corresponding to the received digital signal Drd2. The I signal and the Q signal are IQ-demodulated by the mixers MIXr1 and MIXr2 as Figure 1 indicated, and are signals digitized by the analog-digital converters ADC1 and ADC2. The phase correction circuit PHCC multiplies the I signal and the Q signal by cosθ and -sinθ, respectively. Then, the phase correction circuit PHCC generates an I signal and a Q signal whose phase difference is corrected, i.e., the received digital signal Drd2, by adding the multiplication results "I x cosθ" and "Q x (-sinθ)".

[0121] Next, in Figure 10 the step S207, as Figure 4As shown, the signal recovery circuit RESC synthesizes, specifically adds, the two divided pulse signals PD1 and PD2 after the time difference correction in step S204 and the phase correction in step S206 to recover the original pulse signal POrx. The recovered original pulse signal POrx has a waveform shape equal to that of the original pulse signal POtx at the time of transmission.

[0122] (Modified example)

[0123] Figure 14 is explained from Figure 2 a schematic diagram of an example of the processing content of the modification. In Figure 2 , a case in which the original pulse signal POtx is divided into two divided pulse signals PD1 and PD2 is exemplified, but the number of divisions can be three or more. In Figure 14 the example shown, the transmission circuit TXC, specifically the pulse signal dividing circuit PLSD, divides the original pulse signal POtx having a frequency bandwidth from a frequency fl to a frequency f2 into three divided pulse signals PD1, PD2, and PD3.

[0124] As in the case in Figure 2 , the divided pulse signals PD1 and PD2 have a common frequency range of 30a. Similarly, the divided pulse signals PD2 and PD3 also have a common frequency range of 30b. As in the case of Figure 8 or the like, the transmission circuit TXC sequentially transmits the three divided pulse signals PD1, PD2, and PD3 at a predetermined transmission interval Ttx. Even when three divided pulse signals PD1, PD2, and PD3 are used, in addition to the divided pulse signals PD1 and PD2, the processing described in Figure 6 and Figure 10 may be performed with respect to the divided pulse signals PDG and PD3.

[0125] (Main effects of the embodiment)

[0126] As described above, the semiconductor device according to one embodiment divides an original pulse signal into a plurality of divided pulse signals so that common frequency ranges overlap during transmission, and then sequentially transmits the divided pulse signals at a predetermined transmission interval. Furthermore, the semiconductor device corrects the plurality of divided pulse signals received at a predetermined time difference during reception as if the plurality of divided pulse signals are received simultaneously, and corrects the phases of the plurality of divided pulse signals so that the phases are continuous in the common frequency ranges. With such a configuration, it is possible to narrow the time width of a pulse signal while satisfying a communication standard. As a result, it is possible to improve the accuracy of distance measurement. Furthermore, by using the time difference correction and the phase correction, it is possible to accurately recover the waveform shape of the original pulse signal at the time of transmission at the time of reception. This allows further improvement of the ranging accuracy.

[0127] The inventor's application has been specifically described based on the embodiments, but the present application is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit thereof. For example, the above-described embodiments have been described in detail to clearly explain the present application, and the above-described embodiments are not necessarily limited to those including all the described configurations. Part of the configuration of one embodiment can also be replaced with that of another embodiment, and the configuration of another embodiment can be added to that of one embodiment. Furthermore, part of the configuration of each embodiment can be added, deleted, or replaced with other configurations.

[0128] Each part is typically implemented by program processing using a CPU (Central Processing Unit). That is, the CPU implements each part by executing a program stored in a memory. However, the implementation of each part is not limited to such software, and can be hardware such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), or a combination of software and hardware.

[0129] The above-described program can be stored in a non-transitory tangible computer-readable recording medium and provided to a computer. For example, such a recording medium includes a magnetic recording medium represented by a hard disk drive, an optical recording medium represented by a DVD (Digital Versatile Disc) and a Blu-ray Disc, and a semiconductor memory represented by a flash memory and an SSD (Solid State Drive).

Claims

1. A semiconductor device for ultra-wideband (UWB) wireless communication, implemented in a transmission terminal or a reception terminal different from the transmission terminal, the semiconductor device comprising: a memory for storing a transmission program or a reception program; a processor for executing the transmission program or the reception program; a baseband circuit for processing a baseband signal; a reference oscillation circuit for generating a reference oscillation signal; a local oscillation circuit for generating a local signal using the reference oscillation signal; and an analog front-end circuit for performing frequency conversion from the baseband signal to a high-frequency signal or from the high-frequency signal to the baseband signal using the local signal, when the semiconductor device is implemented in the transmission terminal, the baseband circuit, based on the transmission program, (a) divides an original pulse signal to be the baseband signal into a plurality of divided pulse signals including a first divided pulse signal and a second divided pulse signal such that each frequency bandwidth is within a frequency bandwidth defined by the UWB communication standard and overlaps a common frequency range that is a part of the frequency bandwidth, (b) sequentially transmits the plurality of divided pulse signals to the reception terminal via the analog front-end circuit at a first transmission interval, and when the semiconductor device is implemented in the reception terminal, the baseband circuit, based on the reception program, (c) inputs the plurality of divided pulse signals received sequentially based on a time difference of the first transmission interval via the analog front-end circuit, corrects the time difference of the plurality of divided pulse signals so that the plurality of divided pulse signals are as if received simultaneously, (d) corrects phases of the plurality of divided pulse signals to be continuous within the common frequency range, and (e) restores the original pulse signal by adding the plurality of divided pulse signals after the time difference correction in (c) and the phase correction in (d) are performed.

2. The semiconductor device according to claim 1, wherein the reference oscillation circuit generates the reference oscillation signal based on a frequency of a crystal oscillator externally connected to the semiconductor device, and when the semiconductor device is implemented in the transmission terminal, the semiconductor device is connected to the crystal oscillator implemented in the transmission terminal, and when the semiconductor device is implemented in the reception terminal, the semiconductor device is connected to the crystal oscillator implemented in the reception terminal.

3. The semiconductor device according to claim 1, the analog front-end circuit includes a frequency conversion circuit for performing the frequency conversion, and a digital-to-analog converter or an analog-to-digital converter, wherein when the semiconductor device is implemented in the transmission terminal, the digital-to-analog converter converts a plurality of transmission digital signals stored in the memory into an analog signal corresponding to the plurality of divided pulse signals, and outputs the analog signal to the frequency conversion circuit, ​ wherein when the semiconductor device is implemented in the reception terminal, the analog-to-digital converter converts the plurality of divided pulse signals from the frequency conversion circuit into digital signals, and stores the digital signals in the memory as a plurality of reception digital signals.

4. The semiconductor device according to claim 3, wherein the memory stores first and second reception digital signals corresponding to the first and second divided pulse signals, respectively, and during the time difference correction in (c), when the reception timing of one of the first and second divided pulse signals is offset, the baseband circuit uses the first and second reception digital signals to calculate a correlation function between the first and second divided pulse signals.

5. The semiconductor device according to claim 3, wherein the memory stores first and second reception digital signals corresponding to the first and second divided pulse signals, respectively, and during the phase correction in (d), the baseband circuit (dl) multiplies the first and second divided pulse signals using the first and second reception digital signals, and extracts a DC component from the multiplication result to estimate the phase difference between the first and second divided pulse signals within the common frequency range.

6. The semiconductor device according to claim 5, wherein during the phase correction in (d), the baseband circuit (d2) further shifts the phase of the second divided pulse signal by θ by multiplying the second divided pulse signal by cos θ and sin θ components using a complex mixer, where the phase difference estimated in (dl) is θ.

7. The semiconductor device according to claim 3, wherein during the dividing into the plurality of divided pulse signals in (a), the baseband circuit generates first and second transmission digital signals corresponding to the first and second divided pulse signals, respectively, using first and second filters, wherein the first and second filters have frequency characteristics that produce predetermined gain values in frequency bands other than the common frequency range, wherein the first and second filters have frequency characteristics such that the sum of the gain values of the first and second filters becomes the predetermined gain value within the common frequency range.

8. The semiconductor device according to claim 3, wherein the memory includes an MRAM for storing the transmission program or the reception program, and a volatile memory for storing the plurality of transmission digital signals or the plurality of reception digital signals.

9. A semiconductor device for ultra wide band (UWB) wireless communication, comprising: a memory; a baseband circuit for processing a baseband signal; a reference oscillation circuit for generating a reference oscillation signal; a local oscillation circuit for generating a local signal using the reference oscillation signal; and an analog front-end circuit for performing frequency conversion from the baseband signal to a high frequency signal or from the high frequency signal to the baseband signal using the local signal, wherein the baseband circuit as a transmission circuit includes a pulse signal dividing circuit that divides an original pulse signal to be the baseband signal into a plurality of divided pulse signals including a first divided pulse signal and a second divided pulse signal so that each frequency bandwidth falls within a frequency bandwidth range specified by the UWB communication standard and overlaps a common frequency range as a part of the frequency bandwidth, and a data transmission circuit that sequentially transmits the plurality of divided pulse signals via the analog front-end circuit as a reception circuit at a first transmission interval, wherein the baseband circuit as a reception circuit includes a time difference correction circuit that inputs the plurality of divided pulse signals received sequentially based on a time difference of the first transmission interval via the analog front-end circuit and corrects the time difference of the plurality of divided pulse signals so that the plurality of divided pulse signals are as if received simultaneously, a phase correction circuit that corrects phases of the plurality of divided pulse signals to be continuous within the common frequency range, and a signal recovery circuit that recovers the original pulse signal by adding the plurality of divided pulse signals after the time difference correction by the time difference correction circuit and the phase correction by the phase correction circuit.

10. The semiconductor device according to claim 9, the analog front-end circuit includes a frequency conversion circuit for performing the frequency conversion, a digital-to-analog converter as the transmission circuit, and an analog-to-digital converter as the reception circuit, wherein the digital-to-analog converter corresponds to a digital signal of each of the plurality of divided pulse signals, converts a plurality of transmission digital signals stored in the memory into an analog signal, and outputs the analog signal to the frequency conversion circuit, wherein the analog-to-digital converter converts the plurality of divided pulse signals from the frequency conversion circuit into a digital signal, and stores the digital signal as a plurality of reception digital signals in the memory.

11. The semiconductor device according to claim 10, wherein the memory stores a first reception digital signal and a second reception digital signal corresponding to the first divided pulse signal and the second divided pulse signal, respectively, wherein when a reception timing of one of the first divided pulse signal and the second divided pulse signal is shifted, the time difference correction circuit uses the first reception digital signal and the second reception digital signal to calculate a correlation function between the first divided pulse signal and the second divided pulse signal.

12. The semiconductor device according to claim 10, further comprising a phase difference estimation circuit for estimating a correction amount of a phase used in the phase correction circuit, wherein the memory stores a first received digital signal and a second received digital signal corresponding to the first divided pulse signal and the second divided pulse signal, respectively, wherein the phase difference estimation circuit multiplies the first divided pulse signal and the second divided pulse signal using the first received digital signal and the second received digital signal, and extracts a DC component from a multiplication result.

Images