Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. The semiconductor structure includes a plurality of bit line structures laterally spaced apart on a substrate, a landing pad between the bit line structures, a metal oxynitride layer overlying a top surface of the landing pad, and a capacitance structure extending vertically over the landing pad. A method of forming a semiconductor structure includes the following operations. A plurality of bit line structures are received on a substrate. A landing pad is formed between the bit line structures. A metal oxynitride layer is formed covering a top surface of the landing pad. And forming a sacrificial stack structure at the top of the metal oxynitride layer and the bit line structure. A trench is formed in the sacrificial stack structure to expose the metal oxynitride layer. A capacitor structure is formed in the trench. The semiconductor structure with the metal nitrogen oxide layer can protect the landing pad from being etched by the alkaline etchant.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor structure and a method of forming a semiconductor structure. BACKGROUND

[0002] Semiconductor devices can be used in a variety of electronic applications, such as computers, cell phones, digital cameras, or other electronic devices. The manufacturing process of semiconductor devices generally includes depositing one or more layers of semiconductor, dielectric, and conductive layers on a substrate, followed by performing a photolithography process to pattern some of the different material layers. In order to pursue lower cost, higher efficiency, and higher device density, the size of semiconductor devices has gradually become smaller. However, as the size of semiconductor devices continues to shrink, more and more problems begin to emerge, such as the degradation of electronic properties, quality, and yield of semiconductor devices. Therefore, how to improve the above problems is still a great challenge. SUMMARY

[0003] The present disclosure provides a semiconductor structure including a substrate, a plurality of bit line structures, a landing pad, a metal oxynitride layer, and a capacitor structure. The plurality of bit line structures are laterally spaced apart on the substrate. The landing pad is between the bit line structures, wherein a top surface of the landing pad is higher than a top surface of the bit line structures. The metal oxynitride layer is on the top surface of the landing pad. The capacitor structure extends vertically above the landing pad, wherein a bottom of the capacitor structure contacts the metal oxynitride layer.

[0004] In some embodiments, the metal oxynitride layer has a nitrogen content above 5 wt%.

[0005] In some embodiments, the metal oxynitride layer has a nitrogen content between 20 wt% and 40 wt%.

[0006] In some embodiments, the metal oxynitride layer has an oxygen content between 10 wt% and 30 wt%.

[0007] In some embodiments, the metal oxynitride layer is a tungsten oxynitride layer.

[0008] In some embodiments, the metal oxynitride layer has a thickness between 5 angstroms and 30 angstroms.

[0009] In some embodiments, the capacitor structure is cylindrical and includes a bottom outer diameter, a top outer diameter, and an intermediate outer diameter. The intermediate outer diameter is greater than the bottom outer diameter and the top outer diameter.

[0010] In some embodiments, the bottom outer diameter is less than the top outer diameter.

[0011] In some embodiments, the top surface of the landing pad is substantially planar.

[0012] A method of forming a semiconductor structure is provided, and the method includes the following. A plurality of bitline structures are received on a substrate. A landing pad is formed between the bitline structures, wherein a top surface of the landing pad is higher than a top surface of the bitline structures. A metal oxynitride layer is formed covering the top surface of the landing pad. A sacrificial stack structure is formed on top of the metal oxynitride layer and the bitline structures. A trench is formed in the sacrificial stack structure to expose the metal oxynitride layer. A capacitor structure is formed in the trench, wherein a bottom of the capacitor structure contacts the metal oxynitride layer.

[0013] In some embodiments, forming the metal oxynitride layer covering the top surface of the landing pad includes treating the top surface of the landing pad with a forming gas containing hydrogen and nitrogen.

[0014] In some embodiments, the nitrogen content of the forming gas is between 4 vol% and 50 vol%.

[0015] In some embodiments, forming the sacrificial stack structure on top of the metal oxynitride layer and the bitline structures includes sequentially forming a silicon nitride layer, a first dielectric layer, a silicon nitride layer, a second dielectric layer, and a silicon nitride layer on top of the metal oxynitride layer and the bitline structures.

[0016] In some embodiments, the first dielectric layer includes borophosphosilicate glass and the second dielectric layer includes tetraethoxysilane.

[0017] In some embodiments, the method of forming a semiconductor structure further includes, prior to forming the capacitor structure in the trench, etching the first dielectric layer at the bottom of the trench with an alkaline etchant to remove portions of the first dielectric layer such that a space surrounded by the first dielectric layer is larger than a space surrounded by the second dielectric layer.

[0018] In some embodiments, the alkaline etchant has a higher selectivity to the first dielectric layer than to the second dielectric layer.

[0019] In some embodiments, forming the capacitor structure in the trench includes sequentially forming an outer capacitor electrode layer, a capacitor dielectric layer, and an inner capacitor electrode layer, wherein the outer capacitor electrode layer contacts the metal oxynitride layer.

[0020] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the present application as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0021] The present application can be more fully understood with reference to the following detailed description when read in conjunction with the accompanying drawings, in which:

[0022] Figure 1 is a cross-sectional view of a semiconductor structure in accordance with some embodiments.

[0023] Figure 2 is a flowchart of a method of forming a semiconductor structure according to some embodiments.

[0024] Figures 3 to 9 are cross-sectional views of a semiconductor structure at various stages of forming a semiconductor structure according to some embodiments.

[0025] Figures 10A to 10B is a scanning electron microscope image of a semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0026] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0027] It should be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, sections, regions, layers and / or parts, these elements, sections, regions, layers and / or parts should not be limited by these terms. The terms are only used to distinguish one element, section, region, layer or part from another element, section, region, layer or part. Thus,“a first element,”“element” being discussed below could be called a second element, element, region, layer or part without departing from the teachings herein.

[0028] In addition, spatially relative terms, such as“beneath,”“below,”“lower,”“above,”“upper,”“top,” and the like, can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0029] The present application relates to structures composed of different layers. When the terms“on,”“above” or“over” are used to refer to two different layers (including a substrate), they simply mean that one layer is on top of the other layer or that one layer is on another layer. These terms do not require that the two layers be in direct contact, and allow for other layers to be between the two layers. For example, all of the layers of a structure can be considered to be“on” a substrate, even if they are not all in direct contact with the substrate. The term“directly” can be used to indicate that two layers are in direct contact with each other, and that there are no layers between the two layers.

[0030] In some embodiments, "about" or "substantially" as used herein can mean that the value of a given quantity varies within 20% of the stated value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the stated value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" can refer to a percentage of the stated value as interpreted by one of ordinary skill in the relevant art in view of the teachings herein.

[0031] The present invention relates to a metal oxynitride layer covering a landing pad to prevent the landing pad from being damaged by an alkaline etchant. In other words, the metal oxynitride layer can be considered as a passivation layer to protect the landing pad from being etched by the alkaline etchant.

[0032] Figure 1 is a cross-sectional view of a semiconductor structure 100 according to some embodiments. Figure 1 As shown, semiconductor structure 100 includes a substrate 102, a plurality of bit line structures 110, a plurality of spacers 120, a polysilicon layer 122, a plurality of landing pads 124, a metal oxynitride layer 126, an etch stop layer 128, a capacitor structure 130, and a sacrificial stack structure 140. In some embodiments, substrate 102 is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator substrate, or other similar substrate. In some embodiments, the semiconductor substrate includes an elemental semiconductor, a compound semiconductor material, or an alloy semiconductor material. Elemental semiconductors include single crystal, polycrystalline, or amorphous forms of silicon (Si) or germanium (Ge). Compound semiconductor materials include silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), other suitable materials, or combinations thereof. The alloy semiconductor material includes silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), other suitable materials, or combinations thereof. In some embodiments, the alloy semiconductor material includes silicon germanium (SiGe) having a gradient Ge characteristic, wherein the composition of Si and Ge changes from a ratio at one location in the gradient SiGe characteristic to another ratio at another location. In some embodiments, SiGe is formed on a Si substrate. In some embodiments, the SiGe is mechanically strained by another material in contact with the SiGe. In some embodiments, substrate 102 may include one or more multilayer structures, or substrate 102 may include one or more multilayer semiconductor substrates. It should be understood that the present invention is not limited to the aforementioned materials.

[0033] like Figure 1As shown, bit line structures 110 are laterally spaced apart on substrate 102. In some embodiments, each bit line structure 110 includes a silicon nitride layer 112, a first conductive layer 114, and a mask layer 116. The first conductive layer 114 is disposed on the silicon nitride layer 112, and the mask layer 116 is disposed on the first conductive layer 114. In some embodiments, the first conductive layer 114 includes a metal or alloy material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), nickel (Ni), molybdenum (Mo), manganese (Mn), ruthenium (Ru), zirconium (Zr), platinum (Pt), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbon nitride (TaCN), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), other suitable materials, or combinations thereof. In some embodiments, the mask layer 116 includes silicon nitride (Si3N4), silicon dioxide, silicon oxynitride, other materials, or combinations thereof. It should be understood that the bit line structure 110 and its components are intended to be non-limiting examples only. The semiconductor structure 100 can be implemented with any number of bit line structures 110, such as one, two, three, four, five, etc.

[0034] like Figure 1 As shown, a spacer 120 is disposed adjacent to the bit line structure 110 and on the substrate 102. In some embodiments, the spacer 120 is a single layer or multiple layers. In some embodiments, the spacer 120 comprises Si3N4, silicon dioxide, or a combination thereof.

[0035] like Figure 1 As shown, a polysilicon layer 122 is disposed adjacent to the spacers 120 and on the substrate 102. In some embodiments, a top surface of the polysilicon layer 122 is lower than a top surface of the bit line structure 110.

[0036] like Figure 1 As shown, landing pads 124 are disposed between bit line structures 110 and on polysilicon layer 122. In some embodiments, the top surface of landing pads 124 is higher than the top surface of bit line structure 110. In some embodiments, landing pads 124 partially cover the top surface of bit line structure 110. In some embodiments, each landing pad 124 has a top surface and two concave surfaces extending downward from the top surface. In some embodiments, landing pads 124 include a metal or alloy material, such as W, Mo, Al, Cu, Zr, TiAl, TiAlN, TaCN, TiN, WN, TiSiN, other suitable materials, or combinations thereof.

[0037] like Figure 1As shown, a metal oxynitride layer 126 is coated on the top surface of the landing pad 124. In some embodiments, the nitrogen content of the metal oxynitride layer 126 is greater than 5 wt%. For example, the nitrogen content is greater than 5 wt% and less than or equal to 40 wt%, such as 10 wt%, 15 wt%, 20 wt%, 25 wt%, 30 wt%, 35 wt%, or 40 wt%. In some embodiments, the nitrogen content of the metal oxynitride layer 126 is between 20 wt% and 40 wt%, such as 20 wt%, 22 wt%, 24 wt%, 26 wt%, 28 wt%, 30 wt%, 32 wt%, 34 wt%, 36 wt%, 38 wt%, or 40 wt%. In some embodiments, the oxygen content of the metal oxynitride layer 126 is between 10 wt% and 30 wt%, such as 10 wt%, 12 wt%, 14 wt%, 16 wt%, 18 wt%, 20 wt%, 22 wt%, 24 wt%, 26 wt%, 28 wt%, or 30 wt%. In some embodiments, the metal content of the metal oxynitride layer 126 is between 30 wt% and 70 wt%, such as 30 wt%, 35 wt%, 40 wt%, 45 wt%, 50 wt%, 55 wt%, 60 wt%, 65 wt%, or 70 wt%. In some embodiments, the metal species in the metal oxynitride layer 126 is tungsten (W), iron (Fe), cobalt (Co), Ni, Mo, Al, or other suitable metal species. In some embodiments, the metal oxynitride layer 126 is a tungsten oxynitride layer. In some embodiments, the thickness of the metal oxynitride layer 126 is about 5 angstroms. to 30 angstroms Between, for example or In some embodiments, metal oxynitride layer 126 is a passivation layer. In some embodiments, metal oxynitride layer 126 covering the top surface of landing pad 124 can protect landing pad 124 from being etched. In some embodiments, metal oxynitride layer 126 conformally covers the top surface and concave surface of landing pad 124. Metal oxynitride layer 126 can protect landing pad 124 from being etched.

[0038] like Figure 1 As shown, an etch stop layer 128 is disposed adjacent to the metal oxynitride layer 126. In some embodiments, a bottom portion of the etch stop layer 128 contacts the bit line structure 110 and the spacer 120. In some embodiments, the etch stop layer 128 comprises silicon nitride, a metal oxide, or a combination thereof. In some embodiments, the etch stop layer 128 contacts the metal oxynitride layer 126. In some embodiments, the etch stop layer 128 has a top surface that is substantially coplanar with the metal oxynitride layer 126.

[0039] like Figure 1As shown, the capacitor structures 130 extend vertically above the landing pads 124. In some embodiments, a bottom of each capacitor structure 130 is in contact with the metal nitride oxide layer 126. In some embodiments, the capacitor structures 130 are cylindrical. In some embodiments, each capacitor structure 130 includes a bottom outer diameter dl, a top outer diameter d2, and an intermediate outer diameter d3, which is greater than the bottom outer diameter dl and the top outer diameter d2. In some embodiments, the bottom outer diameter dl is less than the top outer diameter d2. It should be understood that the capacitor structures 130 are intended only as non-limiting examples of implementation. The sacrificial stack structures 140 are between the capacitor structures 130. In some embodiments, a bottom of the sacrificial stack structures 140 is in contact with the etch stop layer 128.

[0040] Figure 2 is a flowchart of a method 200 of forming the semiconductor structure 100 according to some embodiments. The method 200 includes operation 205, operation 210, operation 215, operation 220, operation 225, operation 230, operation 235, operation 240, operation 245, and operation 250. Figures 3 to 9 is a cross-sectional view of the semiconductor structure 100 at various stages of forming the semiconductor structure 100 according to some embodiments. Although the methods disclosed herein are described using a series of operations or steps, the order of the operations or steps should not be construed as a limitation on the present disclosure. For example, some operations or steps can be performed in different order and / or other steps can be performed concurrently. In addition, not all of the illustrated operations, steps and / or features can be required to implement an embodiment of the present disclosure. Furthermore, each of the operations or steps described herein can include some sub-steps or actions.

[0041] Referring to Figure 2 with Figure 3Method 200 begins with operation 205, receiving a substrate 102. In operation 210, a plurality of bitline structures 110 are received on the substrate 102. The bitline structures 110 can be formed by the following operations. A plurality of layers (not shown) including a silicon nitride layer, a first conductive layer, and a masking layer are sequentially deposited on the substrate 102 after operation 205. In some embodiments, the silicon nitride layer, the first conductive layer, and the masking layer are deposited by, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, low pressure CVD (LPCVD), another deposition process, or any suitable combination thereof. The silicon nitride layer, the first conductive layer, and the masking layer are etched to form the bitline structures 110 including the silicon nitride layer 112, the first conductive layer 114, and the masking layer 116. In some embodiments, the layers are etched by an etching process implemented as, for example, but not limited to, a wet etching process, a dry etching process, a reactive ion etching process, another etching process, or a combination thereof.

[0042] With continued reference to Figure 2 With reference to Figure 3 Prior to etching the layers, a photoresist layer (not shown) is deposited and patterned on the layers. That is, photoresist can be deposited and then selectively exposed to visible light, ultraviolet light, deep ultraviolet light (i.e., DUV lithography), extreme ultraviolet light (i.e., EUV lithography), or the like via a mask, followed by developing the exposed photoresist, resulting in patterned photoresist. The layers not protected by the patterned photoresist are then removed by the aforementioned etching process, followed by removing the photoresist by a plasma ashing process, a solvent such as N-methylpyrrolidone, or other suitable method to form the bitline structures 110. In some embodiments, the patterned photoresist is used to define the location of the bitline structures 110.

[0043] With continued reference to Figure 2 With reference to Figure 3In operation 215, spacers 120 are formed around bitline structures 110. In detail, a conformal spacer layer (not shown) is deposited and then partially etched to form spacers 120 around bitline structures 110. In some embodiments, the conformal spacer layer includes a dielectric material such as silicon dioxide, silicon nitride (Si3N4), silicon oxynitride, silicon carbon nitride, silicon carbon oxide, silicon carbon oxynitride, aluminum oxide, a low-k material, or a combination thereof. In some embodiments, the conformal spacer layer is deposited by, for example and without limitation, CVD, PVD, ALD, sputtering, LPCVD, another deposition process, or any suitable combination thereof. In some embodiments, the conformal spacer layer is etched by an etching process implemented as, for example and without limitation, a wet etching process, a dry etching process, a reactive ion etching process, another etching process, or a combination thereof. In some embodiments, a photoresist layer (not shown) is deposited and patterned on the conformal spacer layer prior to etching the conformal spacer layer. That is, a photoresist can be deposited and then selectively exposed to visible light, ultraviolet light, deep ultraviolet light (i.e., DUV lithography), extreme ultraviolet light (i.e., EUV lithography), or the like via a mask, followed by developing the exposed photoresist to produce a patterned photoresist. The conformal spacer layer not protected by the patterned photoresist is then removed by the aforementioned etching process, followed by removing the photoresist by a plasma ashing process, a solvent such as N-methyl pyrrolidone, or other suitable methods to form spacers 120. As shown in some embodiments, multiple horizontal portions of the conformal spacer layer are etched and removed to form spacers 120 around bitline structures 110. Figure 3

[0044] Referring back to Figure 2 with Figure 3 In operation 220, a polysilicon layer 122 is formed between spacers 120. In detail, the polysilicon layer (not shown) is formed by deposition and then an etching process. The polysilicon layer is formed by deposition such as, for example and without limitation, CVD, PVD, ALD, sputtering, LPCVD, another deposition process, or any suitable combination thereof. The polysilicon layer is patterned by an etching process such as, for example and without limitation, a wet etching process, a dry etching process, a reactive ion etching process, another etching process, or a combination thereof to form polysilicon layer 122. In some embodiments, a photoresist layer (not shown) is deposited and patterned on the polysilicon layer prior to etching the polysilicon layer. That is, a photoresist can be deposited and then selectively exposed to visible light, ultraviolet light, deep ultraviolet light (i.e., DUV lithography), extreme ultraviolet light (i.e., EUV lithography), or the like via a mask, followed by developing the exposed photoresist to produce a patterned photoresist. The polysilicon layer not protected by the patterned photoresist is then removed by the aforementioned etching process, followed by removing the photoresist by a plasma ashing process, a solvent such as N-methyl pyrrolidone, or other suitable methods.

[0045] ​With continued reference Figure 2 With Figure 3 In operation 225, a landing pad 124 is formed between the bit line structures 110. In some embodiments, the landing pad 124 is formed on the polysilicon layer 122. In some embodiments, the landing pad 124 is formed by the following operations. A second conductive layer (not shown) is deposited on the polysilicon layer 122, the bit line structures 110, and the spacers 120. Then, the second conductive layer is etched to form the landing pad 124. In some embodiments, the second conductive layer includes W, Mo, Al, Cu, Zr, TiAl, TiAlN, TaCN, TiN, WN, TiSiN, other suitable materials, or combinations thereof. In some embodiments, the second conductive layer is deposited by, for example, but not limited to, CVD, PVD, ALD, sputtering, LPCVD, another deposition process, or any suitable combination thereof. In some embodiments, the top surface of the second conductive layer is not planar. In some embodiments, the second conductive layer is planarized by chemical mechanical planarization (CMP). In some embodiments, an etching process is used to form the openings 150, where the etching process includes a wet etching process, a dry etching process, a reactive ion etching process, another etching process, or a combination thereof. In some embodiments, portions of the mask layer 116 and portions of the spacers 120 are removed by the etching process. In some embodiments, the mask layer 116 has a concave surface exposed from the openings 150, respectively. In some embodiments, the spacers 120 have a concave surface exposed from the openings 150, respectively.

[0046] With reference Figure 2 With Figure 4 In operation 230, a metal oxynitride layer 126 is formed and covers the top surface of the landing pad 124. In some embodiments, the metal oxynitride layer 126 is formed by treating the top surface of the landing pad 124 with a forming gas. In some embodiments, the forming gas contains hydrogen and nitrogen. In some embodiments, the nitrogen content of the forming gas is between 4 vol% and 50 vol%, such as 4 vol%, 6 vol%, 8 vol%, 10 vol%, 12 vol%, 14 vol%, 16 vol%, 18 vol%, 20 vol%, 22 vol%, 24 vol%, 26 vol%, 28 vol%, 30 vol%, 32 vol%, 34 vol%, 36 vol%, 40 vol%, 42 vol%, 44 vol%, 46 vol%, 48 vol%, or 50 vol%. In some embodiments, the metal oxynitride layer 126 protects the landing pad 124 from being etched in subsequent processes. In some embodiments, the forming gas includes ammonia (NH3) or a mixture of hydrogen (H2) and nitrogen (N2).

[0047] Referring to Figure 2 With Figure 5 In operation 235, an etch stop layer 128 is formed between the landing pads 124. In detail, the etch stop layer 128 is deposited on the metal oxynitride layer 126, the bitline structure 110, and the spacers 120, and then an etch process is performed on the etch stop layer 128. In some embodiments, the etch stop layer 128 is deposited by, for example but not limited to, CVD, PVD, ALD, sputtering, LPCVD, another deposition process, or any suitable combination thereof. In some embodiments, the etch process includes a wet etch process, a dry etch process, a reactive ion etch process, another etch process, or a combination thereof. In some embodiments, a top surface of the etch stop layer 128 is aligned with a top surface of the metal oxynitride layer 126.

[0048] Continuing to refer to Figure 2 With Figure 5 In operation 240, a sacrificial stack structure 140 is formed on top of the metal oxynitride layer 126, the bitline structure 110, and the etch stop layer 128. In some embodiments, the sacrificial stack structure 140 is formed on top of the metal oxynitride layer 126, the bitline structure 110, and the etch stop layer 128 by sequentially forming a silicon nitride layer 142, a first dielectric layer 144, a silicon nitride layer 142, a second dielectric layer 146, and a silicon nitride layer 142. In some embodiments, the first dielectric layer 144, the silicon nitride layer 142, and the second dielectric layer 146 are formed by a deposition process of CVD, PVD, ALD, sputtering, LPCVD, another deposition process, or any suitable combination thereof. In some embodiments, the first dielectric layer 144 includes borophosphosilicate glass. In some embodiments, the second dielectric layer 146 includes tetraethoxysilane.

[0049] Referring to Figure 2 , Figure 5 With Figure 6In operation 245, a plurality of trenches 154 are formed in the sacrificial stack structure 140 to expose the metal oxynitride layer 126. In some embodiments, a photoresist layer (not shown) is deposited and patterned on the sacrificial stack structure 140 prior to forming the trenches 154. That is, the photoresist can be deposited and then selectively exposed to visible light, ultraviolet light, deep ultraviolet light (i.e., DUV lithography), extreme ultraviolet light (i.e., EUV lithography), or the like via a mask 152, followed by developing the exposed photoresist, resulting in a patterned photoresist. The sacrificial stack structure 140 that is not protected by the patterned photoresist is then removed by an etching process, such as a wet etching process, a dry etching process, a reactive ion etching process, other etching processes, or a combination thereof, followed by removing the photoresist by a plasma ashing process, a solvent such as N-methyl pyrrolidone, or other suitable methods, to form the trenches 154. It should be noted that the metal oxynitride layer 126 can protect the landing pad 124 from being etched.

[0050] Referring to Figure 2 With Figure 7 After operation 245, the first dielectric layer 144 at the bottom of the trench 154 is etched with a basic etchant to remove portions of the first dielectric layer 144 such that the space encircled by the first dielectric layer 144 is larger than the space encircled by the second dielectric layer 146. In some embodiments, the basic etchant includes sodium hydroxide (NaOH), potassium hydroxide (KOH), ammonium hydroxide (NH4OH), tetramethyl ammonium hydroxide (TMAH, N(CH3)4OH), other suitable basic etchants, or a combination thereof. In some embodiments, the basic etchant has a higher selectivity to the first dielectric layer 144 than to the second dielectric layer 146. It should be noted that the metal oxynitride layer 126 can protect the landing pad 124 from being etched by the basic etchant.

[0051] Referring to Figure 2 With Figure 8 In operation 250, the capacitor structures 130 are formed in the trenches 154. In some embodiments, the bottom of the capacitor structures 130 is in contact with the top of the metal oxynitride layer 126. In some embodiments, each of the capacitor structures 130 includes an outer capacitor electrode layer 132, a capacitor dielectric layer 134, and an inner capacitor electrode layer 136 formed in sequence. In some embodiments, the outer capacitor electrode layer 132 is in contact with the metal oxynitride layer 126. In some embodiments, the outer capacitor electrode layer 132, the capacitor dielectric layer 134, and the inner capacitor electrode layer 136 are formed by a deposition process, such as but not limited to CVD, PVD, ALD, sputtering, LPCVD, another deposition process, or any suitable combination thereof. As Figure 9As shown, after operation 250, the capacitor structure 130 is planarized until the top surface of the capacitor structure 130 is aligned with the sacrificial stack structure 140. In some embodiments, the capacitor structure 130 is planarized by, for example, CMP.

[0052] Figures 10A to 10B is a scanning electron microscope image of a semiconductor structure according to some embodiments. In Figure 10A , the landing pad 160 is covered and protected by the metal nitride oxide layer 162. In Figure 10B , the landing pad 164 is not covered by the metal nitride oxide layer. Comparing Figure 10A to Figure 10B , in Figure 10A , the landing pad 160 is substantially undamaged and formed in black color. In contrast, in Figure 10B , the landing pad 164 is etched to a depth and formed in white color. As Figure 10B shown, the white area formed in the landing pad 164 indicates that the landing pad 164 is damaged. As Figure 10A shown, it can be seen that the metal nitride oxide layer 162 covering the landing pad 160 can prevent the landing pad 160 from being damaged. However, in Figure 10B , the absence of the metal nitride oxide layer covering the landing pad 164 can cause the landing pad 164 to disappear. Therefore, the metal nitride oxide layer can protect the landing pad from being damaged and etched.

[0053] In summary, the present application provides a semiconductor structure and a method of forming a semiconductor structure. In the semiconductor structure, the metal nitride oxide layer covering the landing pad can be regarded as a passivation layer to protect the landing pad from being damaged or etched by, for example, alkaline etchant. Therefore, by providing the metal nitride oxide layer on the landing pad, the above-mentioned problems can be overcome, and thus a semiconductor structure with better quality and high yield can be formed.

[0054] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present application without departing from the scope or spirit of the application. In light of the foregoing, it is intended that the present application cover modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

[0055]

Symbolic Description

[0056] 100: semiconductor structure

[0057] 102: substrate

[0058] 110: bit line structure

[0059] 112: silicon nitride layer

[0060] 114: first conductive layer

[0061] 116: mask layer

[0062] 120: spacer

[0063] 122: polysilicon layer

[0064] 124: landing pad

[0065] 126: metal oxynitride layer

[0066] 128: etch stop layer

[0067] 130: capacitor structure

[0068] 132: outer capacitor electrode layer

[0069] 134: capacitor dielectric layer

[0070] 136: inner capacitor electrode layer

[0071] 140: sacrificial stack

[0072] 142: silicon nitride layer

[0073] 144: first dielectric layer

[0074] 146: second dielectric layer

[0075] 150: opening

[0076] 152: mask

[0077] 154: trench

[0078] 160: landing pad

[0079] 162: metal oxynitride layer

[0080] 164: landing pad

[0081] 200: method

[0082] 205: operation

[0083] 210: operation

[0084] 215: operation

[0085] 220: operation

[0086] 225: operation

[0087] 230: operation

[0088] 235: operation

[0089] 240: operation

[0090] 245: operation

[0091] 250: operation

[0092] d1 : bottom outside diameter

[0093] d2: top outside diameter

[0094] d3: middle outside diameter

Claims

1. A semiconductor structure, characterized by, comprising: a plurality of bitline structures laterally spaced apart on a substrate; a landing pad between the plurality of bitline structures, wherein a top surface of the landing pad is higher than a top surface of the plurality of bitline structures; a metal oxynitride layer covering the top surface of the landing pad; and a capacitor structure vertically extending above the landing pad, wherein a bottom of the capacitor structure contacts the metal oxynitride layer.

2. The semiconductor structure of claim 1, wherein a nitrogen content of the metal oxynitride layer is above 5 wt%.

3. The semiconductor structure of claim 1, wherein a nitrogen content of the metal oxynitride layer is between 20 wt% and 40 wt%.

4. The semiconductor structure of claim 1, wherein an oxygen content of the metal oxynitride layer is between 10 wt% and 30 wt%.

5. The semiconductor structure of claim 1, wherein the metal oxynitride layer is a tungsten oxynitride layer.

6. The semiconductor structure of claim 1, wherein a thickness of the metal oxynitride layer is between 5 angstroms and 30 angstroms.

7. The semiconductor structure of claim 1, wherein the capacitor structure is cylindrical and comprises: a bottom outer diameter; a top outer diameter; and an intermediate outer diameter that is greater than the bottom outer diameter and the top outer diameter.

8. The semiconductor structure of claim 7, wherein the bottom outer diameter is less than the top outer diameter.

9. The semiconductor structure of claim 1, wherein the top surface of the landing pad is substantially planar. comprising: receiving a plurality of bitline structures on a substrate; 10. A method of forming a semiconductor structure, comprising: forming a landing pad between the plurality of bitline structures, wherein a top surface of the landing pad is higher than a top surface of the plurality of bitline structures; forming a metal oxynitride layer covering the top surface of the landing pad; forming a sacrificial stack structure on top of the metal oxynitride layer and the plurality of bitline structures; forming a trench in the sacrificial stack structure to expose the metal oxynitride layer; and forming a capacitor structure in the trench, wherein a bottom of the capacitor structure contacts the metal oxynitride layer.

11. The method of claim 10, wherein forming the metal oxynitride layer covering the top surface of the landing pad comprises treating the top surface of the landing pad with a forming gas containing hydrogen and nitrogen.

12. The method of claim 11, wherein a nitrogen content of the forming gas is between 4 vol% and 50 vol%.

13. The method of claim 10, wherein forming the sacrificial stack structure on top of the metal oxynitride layer and the plurality of bitline structures comprises sequentially forming a silicon nitride layer, a first dielectric layer, a silicon nitride layer, a second dielectric layer, and a silicon nitride layer on top of the metal oxynitride layer and the plurality of bitline structures.

14. The method of claim 13, wherein the first dielectric layer comprises borophosphosilicate glass and the second dielectric layer comprises tetraethoxysilane. ​ ​ ​ 15. The method of claim 13, wherein, Also included is etching the first dielectric layer at a bottom of the trench with an alkaline etchant to remove portions of the first dielectric layer before forming the capacitive structure in the trench, such that a space surrounded by the first dielectric layer is greater than a space surrounded by the second dielectric layer.

16. The method of claim 15, wherein the alkaline etchant has a higher selectivity to the first dielectric layer than to the second dielectric layer.

17. The method of claim 10, wherein forming the capacitive structure in the trench includes sequentially forming an outer capacitive electrode layer, a capacitive dielectric layer, and an inner capacitive electrode layer, wherein the outer capacitive electrode layer contacts the metal nitride oxide layer.

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