Memory element and manufacturing method thereof
By segmenting the channel pillars, support pillars, and partition walls, the etching process difficulty caused by the increased aspect ratio was solved, achieving more efficient etching control and lower process variation risk.
Patent Information
- Application Number
- CN202410516256.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-04-16
- Filing Date
- 2024-04-26
- Publication Date
- 2025-10-24
AI Technical Summary
As the number of gate layers increases, the aspect ratio of the holes or partition channels extending through the stacked structure becomes larger and larger, which increases the difficulty of the etching process and makes it easy for etching variations to occur.
By using a segmented method to form channel pillars, support pillars, and partition walls, multiple sacrificial pillars and walls are used to reduce the aspect ratio of holes or channels, thereby reducing the difficulty of the etching process and avoiding etching variations.
It effectively reduces the difficulty of the etching process, reduces abnormal connectivity caused by hole or channel tilting, and improves the controllability and yield of the etching process.
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Figure CN120835563A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor device and a method of manufacturing the same, and more particularly to a memory device and a method of manufacturing the same. BACKGROUND
[0002] Non-volatile memory has the advantage that the data stored therein will not disappear after power-off, and thus is widely used in personal computers and other electronic devices. Currently, three-dimensional memory devices commonly used in the industry include NOR (not-OR) memory and NAND (not-AND) memory. In addition, another type of three-dimensional memory device is AND memory, which can be applied in a multi-dimensional memory array to achieve high integration and high area utilization, and has the advantage of fast operation speed. Therefore, the development of three-dimensional memory devices has gradually become a current trend. SUMMARY
[0003] The present application provides a memory device and a method of manufacturing the same, which can reduce the aspect ratio of a hole or a channel during etching to reduce the difficulty of etching.
[0004] An embodiment of the present application provides a memory device, which includes a stack structure, a channel pillar, a charge storage structure, and a separation wall. The stack structure is located above a dielectric base and includes a plurality of conductor layers and a plurality of insulating layers alternately stacked. The channel pillar passes through the stack structure. The charge storage structure is located between the channel pillar and the conductor layers. The separation wall passes through the stack structure and includes a plurality of sub-walls stacked. In adjacent two sub-walls of the plurality of sub-walls of the separation wall, an upper width of a lower sub-wall is greater than a lower width of an upper sub-wall.
[0005] An embodiment of the present application provides a method of manufacturing a memory device, which includes the following steps. A stack structure is formed above a base, and the stack structure includes a plurality of conductor layers and a plurality of insulating layers alternately stacked. A channel pillar is formed in the stack structure. A charge storage structure is formed between the channel pillar and the conductor layers. A separation wall is formed to pass through the stack structure, and the separation wall includes a plurality of sub-walls stacked. In adjacent two sub-walls of the plurality of sub-walls of the separation wall, an upper width of a lower sub-wall is greater than a lower width of an upper sub-wall. A support pillar is formed to pass through a stepped structure of the stack structure and a dielectric layer on the stepped structure. The support pillar includes a plurality of sub-pillars stacked. In adjacent two sub-pillars of the plurality of sub-pillars of the support pillar, an upper width of a lower sub-pillar is greater than a lower width of an upper sub-pillar.
[0006] Based on the above, the method of manufacturing a memory device of an embodiment of the present application can be integrated with existing processes to reduce the aspect ratio of a hole or a channel during etching to reduce the difficulty of etching and reduce abnormal connection caused by the inclination of the hole or the channel. BRIEF DESCRIPTION OF DRAWINGS
[0007] Figures 1A-1L is a cross-sectional schematic view of a manufacturing flow of a memory element according to an embodiment of the present application.
[0008] Figures 2A-2L is a cross-sectional schematic view of another manufacturing flow of a memory element according to an embodiment of the present application.
[0009] Figure 3 is a top view of a memory element according to an embodiment of the present application.
[0010] Figures 4A-4D respectively show Figure 1L and Figure 2L are enlarged schematic views of the passage pillars of
[0011] Figure 5A and Figure 5B respectively show Figure 1L and Figure 2L are enlarged schematic views of the partition walls of
[0012] Figure 6A and Figure 6B respectively show Figure 2L are enlarged schematic views of the support pillars of
[0013] Figures 7A-7C is a cross-sectional schematic view of the profile of the combined structure.
[0014] BRIEF DESCRIPTION OF DRAWINGS
[0015] 96, 97, 98, 99: turn
[0016] 100: substrate
[0017] 103: semiconductor layer
[0018] 104, 204, 304: insulating layer
[0019] 105, 205, 305: dielectric layer
[0020] 106, 206, 306: intermediate layer
[0021] 110: passage layer
[0022] 112: insulating pillar
[0023] 114: conductor plug
[0024] 114B: lower part
[0025] 114U: upper part
[0026] 122: tunneling layer
[0027] 124: charge storage layer
[0028] 126: barrier layer
[0029] 128: charge storage structure
[0030] 134: horizontal opening
[0031] 137: barrier layer
[0032] 138: gate layer
[0033] 142: liner layer
[0034] 144: conductor layer
[0035] 160, 260, 360, 163, 263, 363: sacrificial post
[0036] 162, 262, 362: sacrificial wall
[0037] 315: top cap insulating layer
[0038] 701, 702, 703: profile
[0039] AG: air gap
[0040] AR: array region
[0041] CP: channel post
[0042] CS1, CS2, CS3: combined structure
[0043] GSK1-GSK3: stacked structure
[0044] OP1: opening
[0045] OP2: hole
[0046] OP2': hole
[0047] P1-P3: portion
[0048] PIC: support post
[0049] SC1-SC3, SC: stepped structure
[0050] SF1, SF2, SF3: top surface
[0051] SK1-SK3: stacked structure
[0052] SLT: separation wall
[0053] SR: stepped region
[0054] ST1, ST2: separation trench
[0055] ST2': channel
[0056] SW1, SW11, SW12, SW2, SW21, SW22, SW3, SW31, SW32, SW7a, SW7b: side wall
[0057] T1-T3: sub-wall
[0058] TP, TS: cover portion
[0059] TR1: first level
[0060] TR2: second level
[0061] TR3: third level
[0062] VC: hole
[0063] VC': opening
[0064] W op1 : diameter
[0065] W ST1 , W1-W12: width
[0066] W10: lower width
[0067] S1-S3: sub-pillar
[0068] θ11, θ12, θ13, θ21, θ22, θ23, θ31, θ32, θ33: included angle DETAILED DESCRIPTION
[0069] As the number of gate layers is continuously increased, the aspect ratio of the hole or the separation channel extending through the stacked structure is increasingly large, resulting in increasingly high difficulty of etching. The present application forms the passage pillar, the support pillar, and the separation wall by dividing them into multiple sacrificial pillars and sacrificial walls, respectively, to reduce the aspect ratio of the hole or the separation channel formed in each part, thereby reducing the difficulty of the etching process and reducing problems caused by etching variation.
[0070] Figures 1A-1L is a cross-sectional schematic diagram of a manufacturing process of a memory element according to an embodiment of the present application.
[0071] Referring to Figure 1A, a substrate 100 is provided. The substrate 100 includes an array region AR and a staircase region SR. The substrate 100 includes a semiconductor, such as silicon. The substrate 100 can include metal interconnect structures and dielectric layers, such as silicon oxide layers, over the metal interconnect structures. A semiconductor layer 103 is formed on the substrate 100. The semiconductor layer 103 is, for example, a polysilicon layer that is grounded. The semiconductor layer 103 can also be referred to as a sacrificial gate, which can be used to shut down a leakage path. A stack structure SK1 is formed on the semiconductor layer 103. The stack structure SK1 can also be referred to as an insulating stack structure SK1. In the present embodiment, the stack structure SK1 is composed of insulating layers 104 and intermediate layers 106 that are alternately stacked on the substrate 100. The insulating layers 104 are, for example, silicon oxide layers. The intermediate layers 106 are, for example, silicon nitride layers. The intermediate layers 106 can serve as sacrificial layers that are locally removed in a subsequent process.
[0072] Next, the stack structure SK1 is patterned to form a staircase structure SC1 in the staircase region SR. Thereafter, a dielectric layer 105 is formed on the staircase structure SC1. The material of the dielectric layer 105 is, for example, silicon oxide. The dielectric layer 105 can be planarized by a planarization process, such as a chemical mechanical polishing process.
[0073] Next, referring to Figure 1A , a plurality of openings OP1 and a slit trench ST1 are formed in the array region AR of the stack structure SK1. The openings OP1 and the slit trench ST1 extend from the stack structure SK1 to the semiconductor layer 103. In the present embodiment, the profiles of the openings OP1 and the slit trench ST1 are different, and the sizes of the openings OP1 and the slit trench ST1 are different, as viewed in a top-down direction. The openings OP1 have a circular profile (not shown), but the present application is not limited thereto. The slit trench ST1 has a long strip shape (not shown). The width W ST1 of the slit trench ST1 is greater than the diameter W op1 of the openings OP1. Since the width W ST1 of the slit trench ST1 is greater than the diameter W op1The etching rate of the separation trench ST1 is greater than that of the opening OP1, so the depth of the separation trench ST1 in the semiconductor layer 103 is greater than that of the opening OP1 in the semiconductor layer 103. In some embodiments, the upper width of the opening OP1 is greater than the lower width, and the cross section is, for example, conical. Similarly, the upper width of the separation trench ST1 is greater than the lower width, and the cross section is, for example, conical. In the process, the number of layers of the intermediate layer 106 and the insulating layer 104 of the stack structure SK1, photolithography, and etching process are controlled so that the opening OP1 and the separation trench ST1 have the desired profile and shape, and there is sufficient distance between the opening OP1 and the separation trench ST1. The separation trench does not tilt or shift due to the difficulty in controlling the etching plasma because the depth is too deep, causing the opening OP1 to form a notch, resulting in abnormal communication between the opening OP1 and the separation trench ST1.
[0074] Referring to Figure 1B A sacrificial material is formed in the openings OP1 and the separation trenches ST1 on the stack structure SK1. Then, a back etching or chemical mechanical polishing process is performed to remove the excess sacrificial material on the stack structure SK1 to form a plurality of sacrificial columns 160 and a plurality of sacrificial walls 162 in the plurality of openings OP1 and the plurality of separation trenches ST1, respectively. The material of the sacrificial columns 160 and the sacrificial walls 162 is different from that of the insulating layer 104 and the intermediate layer 106. The sacrificial columns 160 and the sacrificial walls 162 are, for example, amorphous silicon or carbon-containing organic material. The carbon-containing organic material can be a polymer, such as photoresist. The photoresist can be positive photoresist or negative photoresist. The material of the sacrificial columns 160 and the sacrificial walls 162 is not limited to this, and other materials, such as polysilicon or tungsten, can also be used. The sacrificial columns 160 have a circular profile (not shown). The sacrificial walls 162 have a long strip shape (not shown). In some embodiments, the upper width of the sacrificial column 160 is greater than the lower width, and the cross section is, for example, conical. Similarly, the upper width of the sacrificial wall 162 is greater than the lower width, and the cross section is, for example, conical. Thus, the first tier TR1 is formed.
[0075] Referring to Figure 1C The stack structure SK2 is formed on the stack structure SK1. In this embodiment, the stack structure SK2 can be composed of insulating layers 204 and intermediate layers 206 stacked alternately. The materials of the insulating layers 204 and the intermediate layers 206 can be the same as or similar to those of the insulating layers 104 and the intermediate layers 106, respectively. Then, the stack structure SK2 is patterned to form a staircase structure SC2 in the staircase region SR according to the method described above. Then, a dielectric layer 205 is formed on the staircase structure SC2.
[0076] Subsequently, a plurality of sacrificial pillars 260 and sacrificial walls 262 are formed in the stack structure SK2 according to the above method. In the process, the number of layers of the intermediate layers 206 and the insulating layers 204 of the stack structure SK2, the photolithography and etching process are controlled such that the formed sacrificial pillars 260 land on the sacrificial pillars 160; the sacrificial walls 262 land on the sacrificial walls 162. The sacrificial pillars 260 have a circular profile (not shown). The sacrificial walls 262 have a strip shape (not shown). In some embodiments, the upper width of the sacrificial pillars 260 is greater than the lower width, for example, a tapered profile. Similarly, the upper width of the sacrificial walls 262 is greater than the lower width, for example, a tapered profile. Thus, a second tier TR2 is formed.
[0077] Referring to Figure 1D , a stack structure SK3 is formed on the stack structure SK2. In the present embodiment, the stack structure SK3 can be composed of insulating layers 304 and intermediate layers 306 stacked in sequence and staggered. The materials of the insulating layers 304 and the intermediate layers 306 can be the same as or similar to the insulating layers 104 and the intermediate layers 106, respectively. Then, the stack structure SK3 is patterned to form a staircase structure SC3 in the staircase region SR according to the above method. Subsequently, a dielectric layer 305 is formed on the staircase structure SC3. The staircase structures SC1, SC2, SC3 can be collectively referred to as a staircase structure SC.
[0078] Subsequently, a plurality of sacrificial pillars 360 and sacrificial walls 362 are formed in the stack structure SK3 according to the above method. The sacrificial pillars 360 land on the sacrificial pillars 260; the sacrificial walls 362 land on the sacrificial walls 262. Similarly, the sacrificial pillars 360 have a circular profile (not shown). The sacrificial walls 362 have a strip shape (not shown). In some embodiments, the upper width of the sacrificial pillars 360 is greater than the lower width, for example, a tapered profile. Similarly, the upper width of the sacrificial walls 362 is greater than the lower width, for example, a tapered profile.
[0079] The lower width of the sacrificial pillars 360 is less than the upper width of the sacrificial pillars 260, and the lower width of the sacrificial pillars 260 is less than the upper width of the sacrificial pillars 160. The lower width of the sacrificial walls 362 is less than the upper width of the sacrificial walls 262, and the lower width of the sacrificial walls 262 is less than the upper width of the sacrificial walls 162. Thus, a third tier TR3 is formed. The sacrificial pillars 360, 260, 160 will be replaced to form channel pillars CP subsequently. The sacrificial walls 362, 262, 162 will be replaced to form separation walls SLT, as shown in Figure 3 , subsequently. In Figure 3 , the channel pillars CP extend along the direction Z, and the separation walls SLT extend along the direction Y and the direction Z in a strip shape. Therefore, from the top view of Figure 3 , it can be seen that the channel pillars CP and the separation walls SLT can be seen as the top view profiles of the sacrificial pillars 360 and the sacrificial walls 362 are circular and strip-shaped.
[0080] Thereafter, a cap insulating layer 315 is formed on the stack structure SK3. The material of the cap insulating layer 315 is, for example, silicon oxide. The cap insulating layer 315 can be planarized via a planarization process, such as a chemical mechanical polishing process.
[0081] Referring to Figure 1E , a patterning process, such as a photolithography and etching process, is performed to form a plurality of openings VC' in the cap insulating layer 315. The openings VC' expose the sacrificial posts 360. In some embodiments, the diameter of the openings VC' can be smaller than the top width of the sacrificial posts 360. In other embodiments, the diameter of the openings VC' can be substantially equal to the top width of the sacrificial posts 360 (not shown). When the diameter of the openings VC' is smaller than the top width of the sacrificial posts 360, the sidewall SW12 of the subsequently formed conductor plug 114 will have a kink 97, as shown in Figure 4B and Figure 4D . When the diameter of the openings VC' is substantially equal to the top width of the sacrificial posts 360, the subsequently formed conductor plug 114 has a smooth sidewall SW12, as shown in Figure 4A and Figure 4C . Figures 4A-4C enlarged schematic views of the channel posts CP of Figure 1L and Figure 2L , respectively.
[0082] Referring to Figure 1F , the sacrificial posts 360 exposed by the plurality of openings VC' and the sacrificial posts 260 and 160 thereunder are removed to form a plurality of holes VC. The holes VC extend through the stack structures SK3, SK2 and SK1. In embodiments of the present application, the profile of the sidewall of each hole VC is, for example, in a bamboo shape. The method of removing the sacrificial posts 360, 260 and 160 can utilize a dry removal method or a wet removal method. When the sacrificial posts 360, 260 and 160 are carbon-containing organic materials, a dry removal method, such as an oxygen plasma ashing method, can be employed to remove without problems of over-etching or insufficient etching depth of the holes VC. When the sacrificial posts 360, 260 and 160 are polysilicon or tungsten, a wet removal method can be employed to remove.
[0083] Referring to Figure 1G , Figures 4A-4DA charge storage structure 128 and a channel pillar CP are formed in the hole VC. The charge storage structure 128 can include a tunneling layer 122, a charge storage layer 124, and a blocking layer 126. The tunneling layer 122 is, for example, silicon oxide. The charge storage layer 124 is, for example, silicon nitride. The blocking layer 126 is, for example, silicon oxide or a high dielectric constant material having a dielectric constant greater than or equal to 7, such as aluminum oxide (AI2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), a transition metal oxide, a lanthanide oxide, or a combination thereof. In other embodiments, the blocking layer 126 can also be formed in the horizontal opening 134 after the horizontal opening 134 is subsequently formed and before the barrier layer 137 is formed (not shown).
[0084] Referring to Figure 1G , Figures 4A-4D A channel layer 110 is formed on the charge storage structure 128. In one embodiment, the material of the channel layer 110 includes polysilicon. In one embodiment, the channel layer 110 covers the charge storage structure 128 on the sidewalls of the hole VC, and also covers the channel layer 110 on the bottom surface of the hole VC. Next, an insulating pillar 112 is formed at the lower portion of the hole VC. In one embodiment, the material of the insulating pillar 112 includes silicon oxide. Thereafter, a conductor plug 114 is formed at the upper portion of the hole VC, and the conductor plug 114 is in contact with the channel layer 110. In one embodiment, the material of the conductor plug 114 includes polysilicon. The channel layer 110, the insulating pillar 112, and the conductor plug 114 can be collectively referred to as the channel pillar CP. The charge storage structure 128 surrounds the vertical outer surface of the channel pillar CP.
[0085] Referring to Figure 1H A plurality of support pillars PIC is formed on the substrate 100. The plurality of support pillars PIC is located in the staircase region SR from the dielectric layer 305, 205, or 105 through the staircase structure SC to the semiconductor layer 103. The support pillars PIC include an insulating material, such as silicon oxide. The support pillars PIC are formed by, for example, a photolithography and etching process to form a plurality of holes in the dielectric layer 305, 205, or 105, the staircase structure SC. Next, an insulating material is formed on the cap insulating layer 315 and in the plurality of holes. Thereafter, a back etching or chemical mechanical planarization process is performed to remove the excess insulating material on the cap insulating layer 315, and the insulating material remaining in the plurality of holes forms the plurality of support pillars PIC.
[0086] Referring to Figure 1I A patterning process, such as a photolithography and etching process, is performed to form a plurality of trenches ST2’ in the cap insulating layer 315. The trenches ST2’ expose the sacrificial walls 362.
[0087] Referring to Figure 1J, the sacrificial walls 362 are removed to expose the sacrificial walls 262 and 162 thereunder, so as to expose the separation trenches ST2. Please refer to Figure 1J and Figure 3 The separation trenches ST2 extend in the direction Y and extend through the stack structures SK3, SK2 and SK1 in the direction Z. Please refer to Figure 1J In the embodiment of the present application, the profile of the sidewall of each separation trench ST2 is, for example, in a bamboo shape. The method for removing the sacrificial walls 362, 262 and 162 can be a dry etching method or a wet etching method. When the sacrificial walls 362, 262 and 162 are organic materials containing carbon, a dry etching method, such as an oxygen plasma ashing method, can be used to remove the same without over-etching or under-etching of the separation trenches ST2. When the sacrificial walls 362, 262 and 162 are polysilicon or tungsten, a wet etching method can be used to remove the same.
[0088] Since the separation trenches ST2 are formed by forming the sacrificial walls 162, 262 and 362 in a segmented manner and then removing the same, the multiple insulating layers 104, 204 and 304 and the intermediate layers 106, 206 and 306 of the stack structures SK3, SK2 and SK1 do not need to be etched at this stage. In other words, the separation trenches ST2 can be regarded as self-aligned separation trenches, so that the difficulty of the process can be reduced and the adjacent channel pillars CP can be prevented from being damaged by improper etching control.
[0089] Please refer to Figure 1K An etching process, such as a wet etching process, is performed to remove the multiple intermediate layers 306, 206 and 106 around the separation trenches ST2 to form multiple horizontal openings 134.
[0090] Please refer to Figure 1LA plurality of gate layers (or conductor layers) 138 are formed in the plurality of horizontal openings 134. The gate layers 138 are, for example, tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru). In some embodiments, a barrier layer 137 is also formed prior to the formation of the plurality of gate layers 138. The barrier layer 137 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The barrier layer 137 and the gate layers 138 are formed, for example, by sequentially forming a barrier material and a conductor material in the separation trenches ST2 and the horizontal openings 134, and then performing a back-etching process to form the barrier layer 137 and the gate layers 138 in the plurality of horizontal openings 134. In other embodiments, the barrier layer 137 can be formed prior to the formation of the gate layers 138. The barrier layer 137 is, for example, silicon oxide or a high dielectric constant material having a dielectric constant greater than or equal to 7, such as aluminum oxide (AI2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxide, lanthanide oxide, or a combination thereof.
[0091] At this point, the stack structures GSK1, GSK2, GSK3 are formed.
[0092] Figure 5A With Figure 5B respectively. Figure 1L With Figure 2L respectively.
[0093] At this point, the stack structures GSK1, GSK2, GSK3 are formed. Figure 1L respectively. Figure 5A respectively. Figure 5B The separation walls SLT are formed in the separation trenches ST2. The separation walls SLT are formed in the separation trenches ST2, but not in the holes. The separation walls SLT are formed by filling an insulating liner material and a conductor material in the stack structures GSK3 and the separation trenches ST2. The insulating liner material is, for example, silicon oxide. The conductor material is, for example, polysilicon, titanium / titanium nitride, tungsten, or a combination thereof. The excess insulating liner material and the conductor material on the stack structures GSK3 are then removed by a back-etching process or a planarization process to form the liner 142 and the conductor layer 144. The liner 142 and the conductor layer 144 are collectively referred to as the separation walls SLT. In yet other embodiments, the conductor layer 144 of the separation walls SLT can further encapsulate the air gaps AG. In other embodiments, the separation walls SLT can also be filled with an insulating material without any conductor layer. In yet other embodiments, the separation walls SLT can also be the liner 142, and the liner 142 encapsulates the air gaps AG without any conductor layer.
[0094] At this point, the stack structures GSK1, GSK2, GSK3 are formed.
[0095] In the above embodiments, the support pillar PIC is formed after the formation of the channel pillar CP. The sidewall of the support pillar PIC is continuous and without a kink. In other embodiments, the support pillar PIC can also be formed by first forming a sacrificial pillar and then replacing it. Figures 2A-2L is a cross-sectional schematic view of another flow of fabricating a memory element according to an embodiment of the present application.
[0096] Referring to Figure 2A The semiconductor layer 103, the stack structure SK1, the staircase structure SC1 and the dielectric layer 105 are formed on the substrate 100 according to the above method. Then, the sacrificial pillars 163 are also formed when the sacrificial pillars 160 and the sacrificial walls 162 are formed. The sacrificial pillars 163 pass through the stack structure SK1, the staircase structure SC1, the dielectric layer 105 and the semiconductor layer 103 of the staircase region SR. The sacrificial pillars 163 have a circular profile (not shown). In some embodiments, the upper width of the plurality of sacrificial pillars 163 is greater than the lower width, and the cross-section is, for example, conical. The sacrificial pillars 160, the sacrificial walls 162 and the sacrificial pillars 163 are, for example, amorphous silicon or carbon-containing organic material. The carbon-containing organic material can be a polymer, for example, photoresist. The photoresist can be positive photoresist or negative photoresist. Thus far, the first tier TR1 is formed.
[0097] In terms of process, by controlling the number of layers of the intermediate layer 106 of the stack structure SK1 and the insulating layer 104, photolithography and etching process, the opening for forming the sacrificial pillar 163 has the desired profile and shape, and there is also sufficient distance between the opening for forming the sacrificial pillar 163 and the separation trench ST1, so that the separation trench does not tilt or shift due to the difficulty in controlling the deep etching of the plasma, causing the opening for forming the sacrificial pillar 163 to form a notch, resulting in the opening for forming the sacrificial pillar 163 and the separation trench ST1 to be abnormally connected.
[0098] Referring to Figure 2B, the second-tier TR2 and the third-tier TR3 are formed according to the above method. When the sacrificial posts 260, 360 and the sacrificial walls 262, 362 of the second-tier TR2 and the third-tier TR3 are formed, a plurality of sacrificial posts 263 and 363 are also formed at the same time, respectively. The sacrificial posts 263 land on the sacrificial posts 163; the sacrificial posts 363 land on the sacrificial posts 263. In this embodiment, the profiles of the sacrificial posts 163, 263, 363 are, for example, in a bamboo shape. Thereafter, a top- insulating layer 315 is formed on the stack structure SK3. Up to this point, the stack structures SK1, SK2, SK3 composed of the insulating layers 104, 204, 304 and the intermediate layers 106, 206, 306 are formed, the dielectric layers 105, 205, 305 are formed around the stack structures SK1, SK2, SK3, and the top-insulating layer 315 is formed on the stack structure SK3. In other embodiments, the stack structures SK1, SK2, SK3, the dielectric layers 105, 205, 305, and the top-insulating layer 315 can also be formed by any known method.
[0099] Referring to Figure 2C , a patterning process, such as photolithography and etching, is performed to form a plurality of holes OP2' in the top-insulating layer 315. The holes OP2' expose the sacrificial posts 363.
[0100] Referring to Figure 2D , the sacrificial posts 363 exposed by the plurality of holes OP2' and the sacrificial posts 263 and 163 thereunder are removed so that a plurality of holes OP2 are exposed. The holes OP2 extend through the stack structures SK3, SK2 and SK1. The method of removing the sacrificial posts 363, 263 and 163 can utilize a dry-removal method or a wet-removal method. When the sacrificial posts 363, 263 and 163 are organic materials containing carbon, a dry-removal method, such as an oxygen plasma ashing method, can be used to remove them without problems of over-etching or insufficient etching depth of the holes OP2. In embodiments of the present application, the profile of the sidewall of each hole OP2 is, for example, in a bamboo shape.
[0101] Referring to Figure 2E , a plurality of support posts PIC are formed in the holes OP2. The support posts PIC comprise an insulating material, such as silicon oxide. The support posts PIC are formed, for example, by forming an insulating material on the top-insulating layer 315 and in the plurality of holes. Thereafter, an etch-back or chemical mechanical planarization process is performed to remove the excess insulating material on the top-insulating layer 315, leaving the insulating material in the plurality of holes to form the plurality of support posts PIC. It can be seen that the profile of the support posts PIC is circular. Figure 3
[0102] Referring to Figures 2F-2H , the second-tier TR2 and the third-tier TR3 are formed according to the above method. When the sacrificial posts 260, 360 and the sacrificial walls 262, 362 of the second-tier TR2 and the third-tier TR3 are formed, a plurality of sacrificial posts 263 and 363 are also formed at the same time, respectively. The sacrificial posts 263 land on the sacrificial posts 163; the sacrificial posts 363 land on the sacrificial posts 263. In this embodiment, the profiles of the sacrificial posts 163, 263, 363 are, for example, in a bamboo shape. Thereafter, a top- insulating layer 315 is formed on the stack structure SK3. Up to this point, the stack structures SK1, SK2, SK3 composed of the insulating layers 104, 204, 304 and the intermediate layers 106, 206, 306 are formed, the dielectric layers 105, 205, 305 are formed around the stack structures SK1, SK2, SK3, and the top-insulating layer 315 is formed on the stack structure SK3. In other embodiments, the stack structures SK1, SK2, SK3, the dielectric layers 105, 205, 305, and the top-insulating layer 315 can also be formed by any known method. Figures 1E-1G A patterning process is performed to form a plurality of openings VC' in the cap insulating layer 315, such as Figure 2F Next, the sacrificial pillars 360, 260, and 160 are removed to form a plurality of holes VC, as shown in FIG. Figure 2G Then, a charge storage structure 128 and a channel column CP are formed in the hole VC, as shown in FIG. Figure 2H as well as Figures 4A-4D shown.
[0103] Reference Figures 2I-2L , according to the above reference Figures 1I-1L A patterning process is performed to form a plurality of trenches ST2' in the cap insulating layer 315, such as Figure 2I Remove the sacrificial wall 362 exposed by the multiple trenches ST2' and the sacrificial walls 262 and 162 thereunder, so that the multiple separation trenches ST2 are exposed. Figure 2J An etching process, such as a wet etching process, is performed to remove the multi-layer intermediate layers 306, 206, and 106 around the separation trench ST2 to form a horizontal opening 134, as shown. Figure 2K Afterwards, a barrier layer 137 and a gate layer 138 are formed in the horizontal opening 134, as shown in FIG. Figure 2L shown.
[0104] Reference Figure 2L as well as Figure 5A and Figure 5B Then, a separation wall SLT is formed in the separation trench ST2. Then, a contact window (not shown) is formed in the step region SR. The contact window lands at the end of the gate layer 138 in the step region SR and is electrically connected thereto.
[0105] Reference Figures 4A-4D In an embodiment of the present invention, the channel column CP includes a plurality of stacked parts P1, P2, and P3. Two adjacent parts of the channel column CP, such as parts P1 and P2, are connected near the boundary between the gate stack structures GSK1 and GSK2, or parts P2 and P3 are connected near the boundary between the gate stack structures GSK2 and GSK3. In the two adjacent parts of the channel column CP (such as parts P3 and P2), the upper width (i.e., the upper radial dimension) W1 of the lower part (e.g., part P2) is greater than the lower width (i.e., the lower radial dimension) W2 of the upper part (e.g., part P3). The sidewall SW1 of the channel column CP is not smooth, but has a turning point 97 where the parts are connected. Figures 4A-4D In FIG. 1 , the top surface of the upper portion of portion P1 and the sidewall of the lower portion of portion P2 form a transition 97 with an included angle θ11. The top surface of the upper portion of portion P2 and the sidewall of the lower portion of portion P3 form a transition 97 with an included angle θ12. The included angles θ11 and θ12 are less than 90 degrees.
[0106] The channel layer 110 and the conductor layer 114 in the channel pillar CP are formed via a deposition process, thus, from the top surface of the gate stack structure GSK3 continuously to the bottom surface of the gate stack structure GSK1, and there is no planarization interface between the portions P3 and P2 or between the portions P2 and P1.
[0107] Furthermore, in some embodiments, the sidewalls of the channel layer 110 of the channel pillar CP can be electrically connected with the semiconductor layer 103, as shown in Figure 4A Figure 4B Figure 4C Figure 4D
[0108] Referring to Figure 4A Figure 4C The top-to-bottom width of the channel pillar CP is, for example, 130-80 nm. The sidewall SW12 of the conductor plug 114 is connected with the sidewall SW11 of the portion P3. The upper portion 114U and the lower portion 114B of the conductor plug 114 are substantially the same size. The sidewall SW12 of the conductor plug 114 is smooth, and does not have a turn 97 at the connection between the upper portion 114U and the lower portion 114B. Referring to Figure 4B Figure 4D The conductor plug 114 includes an upper portion 114U and a lower portion 114B. The width W3 of the upper portion 114U is less than the width W4 of the lower portion 114B. The sidewall SW12 of the conductor plug 114 is not smooth, but has a turn 97 at the connection between the upper portion 114U and the lower portion 114B. The turn 97 formed by the sidewall of the upper portion 114U and the top surface SF1 of the lower portion 114B has an included angle θ13. The included angle θ13 is less than 90 degrees.
[0109] Referring to Figure 5A Figure 5B Figure 3 In embodiments of the present application, the separation wall SLT includes a plurality of sub-walls T1, T2, T3 stacked along the direction Z, each of which extends along the direction Y and extends from the array region AR to the staircase region SR, thus in Figure 3 The top view of the spacer wall SLT is shown in FIG. 1A. The spacer wall SLT includes three sub-walls T1, T2, T3. The sub-walls T1, T2, T3 are buried in the stack structures GSK1, GSK2, GSK3, respectively. Two adjacent sub-walls of the spacer wall SLT are connected to each other. For example, the sub-walls T1 and T2 are connected near the interface of the stack structures GSK1 and GSK2, or the sub-walls T2 and T3 are connected near the interface of the stack structures GSK2 and GSK3. In the two adjacent sub-walls (e.g., the sub-walls T3 and T2) of the spacer wall SLT, the upper width W5 of the lower sub-wall (e.g., the sub-wall T2) is greater than the lower width W6 of the upper sub-wall (e.g., the sub-wall T3). The maximum width (e.g., the upper width W5 of the sub-wall T2) of the spacer wall SLT is less than 400 nm. The minimum width (e.g., the lower width W6 of the sub-wall T3) of the spacer wall SLT is greater than 80 nm.
[0110] The sidewall SW3 of the spacer wall SLT is not smooth, but has a corner 98 at the connection of the sub-walls.
[0111] In Figure 5A In 5B In the corner 98 formed by the top surface of the upper portion of the sub-wall T1 and the sidewall of the lower portion of the sub-wall T2 has an included angle θ21. In the corner 98 formed by the top surface of the upper portion of the sub-wall T2 and the sidewall of the lower portion of the sub-wall T3 has an included angle θ22. The included angles θ21, θ22 are less than 90 degrees.
[0112] The spacer wall SLT includes a liner 142 and a conductor layer 144. The liner 142 and the conductor layer 144 are formed by a deposition process, thus, the liner 142 and the conductor layer 144 are continuous from the top surface of the stack structure GSK3 to the bottom surface of the stack structure GSK1 (shown in FIG. 1A). There is no planarization interface between the sub-walls T3 and T2 or between the sub-walls T2 and T1. Figure 1L
[0113] Figure 5A The spacer wall SLT of 5B is shown in FIG. 1B. Figure 1L Figure 2L The spacer wall SLT of
[0114] Referring to Figure 5A and Figure 5B , the spacer wall SLT further includes a cap portion TP. The cap portion TP is buried in the top cap insulating layer 315 and is located on the sub-wall T3. Referring to Figure 5A , the width W8 of the cap portion TP is less than the upper width W7 of the sub-wall T3 adjacent to the cap portion TP. The sidewall SW22 of the cap portion TP is connected to the sidewall SW21 of the sub-wall T3 via the top surface SF1 of the sub-wall T3.
[0115] Referring to Figure 5B , the width W8 of the cap portion TP can also be substantially equal to the upper width W7 of the sub-wall T3 adjacent to the cap portion TP. The sidewall SW22 of the cap portion TP is connected to the sidewall SW21 of the sub-wall T3. The cap portion TP can have a vertical sidewall SW4 or an inclined sidewall. InFigure 5A In the embodiment, the turning point 98 formed by the top surface SF2 of the upper portion of the sub-wall T3 and the side wall SW22 of the top cover insulating layer 315 has an included angle θ23. The included angles θ21, θ22, and θ23 are less than 90 degrees.
[0116] Figure 6A and Figure 6B Shown separately Figure 2L An enlarged schematic diagram of the support column PIC.
[0117] PIC reference Figure 6A and 6B In an embodiment of the present invention, a support column PIC includes a plurality of stacked sub-pillars S1, S2, and S3, respectively embedded within the stepped structures SC1, SC2, and SC3 of the stacked structures GSK1, GSK2, and GSK3, as well as dielectric layers 105, 205, and 305. Of two adjacent sub-pillars (e.g., sub-pillars S3 and S2) within a support column PIC, the upper width (i.e., upper radial dimension) W9 of the lower sub-pillar (e.g., sub-pillar S2) is greater than the lower width (i.e., lower radial dimension) W10 of the upper sub-pillar (e.g., sub-pillar S3). The sidewalls SW3 of the support column PIC are not smooth, but rather have inflections 99 at the junctions between the sub-pillars.
[0118] exist Figures 6A-6B In the embodiment, the top surface of the upper portion of the sub-pillar S1 and the side wall of the lower portion of the sub-pillar S2 form a turning point 99 with an included angle θ31. The top surface of the upper portion of the sub-pillar S2 and the side wall of the lower portion of the sub-pillar S3 form a turning point 99 with an included angle θ32. The included angles θ31 and θ32 are less than 90 degrees.
[0119] The material of the support column PIC is formed by a deposition process after the hole OP2 is formed, and thus continuously extends from the top surface of the stack structure GSK3 to the bottom surface of the stack structure GSK1 (shown in FIG. Figure 1L ), and there is no flattened interface between sub-pillars S3 and S2 or between sub-pillars S2 and S1.
[0120] Reference Figure 6A and Figure 6B The support column PIC further includes a cover portion TS. The cover portion TS is buried in the top cover insulating layer 315 and is located on the sub-column S3. Figure 6A The width W12 of the cover portion TS is smaller than the upper width W11 of the adjacent sub-pillar S3. The sidewall SW32 of the cover portion TS is connected to the sidewall SW31 of the sub-pillar S3 via the top surface SF3 of the sub-pillar S3.
[0121] Reference Figure 6B , the width W12 of the cover TS can also be roughly equal to the upper width W11 of the adjacent sub-column S3. The side wall SW32 of the cover TS is connected to the side wall SW31 of the sub-column S3. The cover TS can have a vertical side wall SW6 or an inclined side wall (not shown).Figure 6A In the embodiment, the corner 99 formed by the top surface of the upper portion of the sub-column S3 and the sidewall of the top cap insulating layer 315 has an included angle θ33. The included angle θ33 is less than 90 degrees.
[0122] Referring to Figure 2L , the corners 97, 98, 99 at the junctions of the stack structures GSK1 and GSK2 have substantially the same height. The corners 97, 98, 99 at the junctions of the stack structures GSK2 and GSK3 have substantially the same height. The corners 97, 98, 99 at the junctions of the stack structures GSK3 and the top cap insulating layer 315 have substantially the same height.
[0123] Referring to Figures 4A-6B In the above embodiment, the profiles of the channel columns CP, the spacer walls SLT and the support columns PIC (collectively referred to as the combined structure CS1) in the gate stack structures GSK1, GSK2, GSK3 are as shown in the profile 701 of Figure 7A However, embodiments of the present application are not limited thereto. In some cases, the profiles of the channel columns CP, the spacer walls SLT and the support columns PIC (collectively referred to as the combined structure CS2, CS3) in the gate stack structures GSK1, GSK2, GSK3 are as shown in the profile 702 of Figure 7B and the profile 703 of Figure 7C .
[0124] Referring to Figures 7A-7C , the combined structure CS1 is a symmetric structure, and the combined structures CS2, CS3 are asymmetric structures. The number of corners 96 of the two sidewalls of the combined structure CS1 are equal, and the number of corners 96 of the two sidewalls SW7a, SW7b of the combined structures CS2, CS3 are not equal. The combined structure CS2 has only one sidewall SW7b with distinct corners 96, and the other sidewall SW7a has no corners 96 and is very smooth. The combined structure CS3 has only one sidewall SW7b with distinct corners 96, and the other sidewall SW7a is not very smooth. In other embodiments, the two sidewalls SW7a, SW7b of the combined structure CS2 both have distinct corners 96, but the number of corners 96 of the two sidewalls are not equal (not shown).
[0125] The above embodiments are described with three stack structures, but the present application can be applied to memory elements with more layers of stack structures. Furthermore, the stack structure (with memory array) of the present application can have complementary metal-oxide semiconductor elements underneath. In some embodiments, these complementary metal-oxide semiconductor elements can be formed before the stack structure is formed, thus being underneath the memory array, which is also known as complementary metal-oxide semiconductor elements under array (CuA) structure. In other embodiments, these complementary metal-oxide semiconductor elements can be bonded underneath the memory array, which is also known as complementary metal-oxide semiconductor elements bonding array (CbA) structure.
[0126] The above embodiments are described with charge storage structures of charge trapping structures, but the present application embodiments can also be applied to floating gate memories. Furthermore, the above embodiments are described with 3D NAND flash memories. However, the present application embodiments are not limited to this, and the present application embodiments can also be applied to 3D NOR flash memories or 3D AND flash memories.
[0127] Based on the above, the memory element of the present application embodiments divides the stack structure into multiple portions to form the holes or trenches in the stack structure with a reduced aspect ratio, to reduce the difficulty of the process and to reduce the manufacturing cost. Furthermore, the present application forms the sacrificial pillars or walls in the previously formed holes or trenches, and these sacrificial pillars or walls can be easily removed after the holes or openings above are formed, to form holes or separation trenches extending through the stack structure with a high aspect ratio. Thus, the present application can simplify the process, and can be integrated with existing processes, to increase the integration, to increase the process yield, and to reduce the manufacturing cost.
Claims
1. A memory element, comprising: a stack structure over a substrate, comprising a plurality of conductor layers and a plurality of insulator layers alternating with each other; a channel pillar through the stack structure; a charge storage structure between the channel pillar and the conductor layers; and a separation wall through the stack structure, the separation wall comprising a plurality of sub-walls stacked, wherein among two adjacent sub-walls of the plurality of sub-walls of the separation wall, an upper width of a lower sub-wall is greater than a lower width of an upper sub-wall.
2. The memory element of claim 1, wherein at least one sidewall of a plurality of sidewalls of the separation wall has at least one first jog.
3. The memory element of claim 1, wherein the separation wall further comprises a cap portion, the cap portion having a width less than an upper width of a sub-wall adjacent thereto.
4. The memory element of claim 1, wherein the channel pillar comprises a plurality of portions stacked.
5. The memory element of claim 4, wherein among two adjacent portions of the plurality of portions of the channel pillar, an upper width of a lower portion is greater than a lower width of an upper portion.
6. The memory element of claim 5, wherein at least one sidewall of a plurality of sidewalls of the channel pillar has at least one second jog.
7. The memory element of claim 1, further comprising a support pillar through a staircase structure of the stack structure and a dielectric layer over the staircase structure, wherein the support pillar comprises a plurality of sub-pillars stacked.
8. The memory element of claim 7, wherein among two adjacent sub-pillars of the plurality of sub-pillars of the support pillar, an upper width of a lower sub-pillar is greater than a lower width of an upper sub-pillar.
9. The memory element of claim 8, wherein at least one sidewall of a plurality of sidewalls of the support pillar has at least one third jog.
10. A method of fabricating a memory element, comprising: forming a stack structure over a substrate, the stack structure comprising a plurality of conductor layers and a plurality of insulator layers alternating with each other; forming a channel pillar in the stack structure; forming a charge storage structure between the channel pillar and the conductor layers; forming a separation wall through the stack structure, the separation wall comprising a plurality of sub-walls stacked, wherein among two adjacent sub-walls of the plurality of sub-walls of the separation wall, an upper width of a lower sub-wall is greater than a lower width of an upper sub-wall; and forming a support pillar through a staircase structure of the stack structure and a dielectric layer over the staircase structure, wherein the support pillar comprises a plurality of sub-pillars stacked, wherein among two adjacent sub-pillars of the plurality of sub-pillars of the support pillar, an upper width of a lower sub-pillar is greater than a lower width of an upper sub-pillar.