Miniature light-emitting chip, miniature light-emitting chip structure and display panel

Abstract

The invention provides a miniature light-emitting chip, a miniature light-emitting chip structure and a display panel. The miniature light-emitting chip comprises two sub-chips, an insulating structure, a first electrode, a second electrode and a conductive element. The insulating structure is arranged between the two sub-chips, so that the two sub-chips are electrically insulated from each other at the insulating structure. The first electrode and the second electrode are respectively connected with the two sub-chips and are respectively provided with a first gap and a second gap. The conductive element is disposed between the first gap of the first electrode and the second gap of the second electrode, and is electrically connected to the two sub-chips. The sum of the orthographic projection areas of the first electrode, the second electrode and the conductive element on a reference plane parallel to the two sub-chips is larger than or equal to 0.6 time of the orthographic projection area of the miniature light-emitting chip on the reference plane.

Description

TECHNICAL FIELD

[0001] The present application relates to a light emitting element and a structure and a panel comprising the same, and in particular to a micro light emitting chip, a micro light emitting chip structure and a display panel. BACKGROUND

[0002] The micro light emitting diode panel comprises an active element substrate and a micro light emitting diode (micro-LED) on the active element substrate, and is electrically connected with a driving circuit layer in the active element substrate. The micro light emitting diode panel has become the focus of research and development of major manufacturers due to its advantages such as high brightness, high resolution and high contrast.

[0003] In the existing tandem chip structure, the general electrode has no gap, so the area of the conductive layer used to connect the two chips is limited, and it is difficult to support the strength of the overall chip structure connected in series, so that the overall chip structure is more likely to break at the junction of the two series-connected chips when being massively transferred to the circuit substrate, resulting in a decrease in the yield of the display panel. SUMMARY

[0004] The present application is directed to a micro light emitting chip with better structural strength.

[0005] The present application is directed to a micro light emitting chip structure with better structural strength and manufacturing yield.

[0006] The present application is directed to a display panel with better structural strength and manufacturing yield.

[0007] Embodiments of the present application propose a micro light emitting chip, comprising two sub-chips, an insulating structure, a first electrode, a second electrode and a conductive element. The insulating structure is arranged between the two sub-chips so that the two sub-chips are electrically insulated from each other at the insulating structure. The first electrode and the second electrode are respectively connected to the two sub-chips and respectively have a first gap and a second gap. The conductive element is arranged between the first gap of the first electrode and the second gap of the second electrode and electrically connects the two sub-chips. The sum of the areas of the orthogonal projections of the first electrode, the second electrode and the conductive element on a reference plane parallel to the two sub-chips is greater than or equal to 0.6 times the area of the orthogonal projection of the micro light emitting chip on the reference plane.

[0008] Embodiments of the present application propose a micro light emitting chip structure, comprising a temporary substrate, a fixing element and a plurality of the above-mentioned micro light emitting chips, which are fixed to the temporary substrate via the fixing element, wherein the micro light emitting chips are electrically insulated from the temporary substrate.

[0009] Embodiments of the present application provide a display panel, which includes a circuit substrate and a plurality of micro light emitting chips. The circuit substrate is provided with a plurality of pixel circuits, and the micro light emitting chips are disposed on the circuit substrate. One of the first electrode and the second electrode is electrically connected to one of the pixel circuits.

[0010] Embodiments of the present application provide a micro light emitting chip, which includes two sub-chips, an insulating structure, a first electrode, a second electrode and a conductive element. The insulating structure is disposed between the two sub-chips to electrically insulate the two sub-chips at the insulating structure. The first electrode and the second electrode are respectively connected to the two sub-chips and respectively have a first notch and a second notch. The conductive element is disposed between the first notch of the first electrode and the second notch of the second electrode and electrically connects the two sub-chips. The first notch and the second notch are away from each other, and the first electrode and the second electrode are 180-degree rotationally symmetrical.

[0011] In the micro light emitting chip, the micro light emitting chip structure and the display panel according to embodiments of the present application, the first electrode and the second electrode respectively have a first notch and a second notch, the conductive element is disposed between the first notch of the first electrode and the second notch of the second electrode, and the sum of the areas of the orthographic projections of the first electrode, the second electrode and the conductive element on a reference plane parallel to the two sub-chips is greater than or equal to 0.6 times the area of the orthographic projection of the micro light emitting chip on the reference plane, or the first notch and the second notch are away from each other, and the first electrode and the second electrode are 180-degree rotationally symmetrical. Therefore, the conductive element can have a larger area and can support the structural strength of the two connected sub-chips to effectively reduce the fracture or tilting of the micro light emitting chip from the connection between the two sub-chips due to uneven stress in the mass transfer process. Therefore, the micro light emitting chip according to embodiments of the present application can have better structural strength, and the micro light emitting chip structure and the display panel according to embodiments of the present application can have better structural strength and manufacturing yield. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1A is a cross-sectional view of a micro light emitting chip according to an embodiment of the present application;

[0013] Figure 1B is a bottom view of the micro light emitting chip of Figure 1A

[0014] Figure 2 is a cross-sectional view of a micro light emitting chip according to an embodiment of the present application;

[0015] Figure 3 is a cross-sectional view of a micro light emitting chip structure according to an embodiment of the present application;

[0016] Figure 4 ​is a cross-sectional view of a display panel according to an embodiment of the present application;

[0017] Figure 5 is a bottom view of a micro light emitting chip according to another embodiment of the present application;

[0018] Figure 6 is a bottom view of a micro light emitting chip according to yet another embodiment of the present application. DETAILED DESCRIPTION

[0019] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0020] Figure 1A is a cross-sectional view of a micro light emitting chip according to an embodiment of the present application, and Figure 1B is Figure 1A a bottom view of a micro light emitting chip according to an embodiment of the present application, wherein Figure 1A is Figure 1B a cross-sectional view of a micro light emitting chip according to an embodiment of the present application along line I-I. Please refer to Figure 1A and Figure 1B The micro light emitting chip 1A of the present embodiment includes two sub-chips (e.g. a first sub-chip 100A and a second sub-chip 100B), a first electrode 121, a second electrode 122, an insulating structure 130, a conductive element 180A, and a protection unit 160. The first sub-chip 100A and the second sub-chip 100B are, for example, micro light emitting diodes (micro LEDs), micro laser diodes, or other size light emitting diodes, without being limited thereto. Preferably, the present embodiment employs micro light emitting diodes.

[0021] On the other hand, the light emitted by the first sub-chip 100A and the second sub-chip 100B can have substantially the same wavelength range. For example, the first sub-chip 100A and the second sub-chip 100B can both be red micro light emitting diodes, green micro light emitting diodes, or blue micro light emitting diodes. On the other hand, the micro light emitting chip 1A of the present embodiment is a flip-chip type micro light emitting diode. For example, the first electrode 121 and the second electrode 122 located on the same side of the epitaxial structure of the micro light emitting chip 1A are aligned with corresponding pads on a pixel circuit (described below), and are bonded to each other after mass transfer to achieve electrical connection between the micro light emitting chip 1A and the pixel circuit, without being limited thereto.

[0022] The first sub-chip 100A and the second sub-chip 100B each can include a first semiconductor layer 101, a second semiconductor layer 102, and a light-emitting layer 103 extending sequentially in the direction Y. The first semiconductor layer 101 can be composed of a III-V or II-VI compound semiconductor and can be a P-type or N-type doped semiconductor material layer. The second semiconductor layer 102 is formed on the light-emitting layer 103 and can be composed of a III-V or II-VI compound semiconductor and can be a P-type or N-type doped semiconductor material layer. One of the first semiconductor layer 101 and the second semiconductor layer 102 is an N-type semiconductor layer, and the other of the first semiconductor layer 101 and the second semiconductor layer 102 is a P-type semiconductor layer.

[0023] The first electrode 121 and the second electrode 122 can be aluminum (Al), gold (Au), silver (Ag), copper (Cu), germanium gold (GeAu), or other metals or alloys suitable for generating ohmic contact with P-type and N-type semiconductors, and materials suitable for connecting with metal bonding pads (described later) of a pixel circuit and solder metal, but the present application is not limited thereto.

[0024] The first electrode 121 can be electrically connected to the first semiconductor layer 101 of the first sub-chip 100A via a via TH11, and the second electrode 122 can be electrically connected to the second semiconductor layer 102 of the second sub-chip 100B via a via TH22. In addition, a conductive element 180A can further electrically connect the first sub-chip 100A and the second sub-chip 100B such that the first sub-chip 100A and the second sub-chip 100B are in series with each other. For example, the conductive element 180A can extend in the direction X and be disposed on the same side of the first sub-chip 100A and the second sub-chip 100B. The two ends of the conductive element 180A can be electrically connected to the second semiconductor layer 102 of the first sub-chip 100A and the first semiconductor layer 101 of the second sub-chip 100B, respectively. The conductive element 180A can be a metal material, such as copper, silver, molybdenum, titanium, or an alloy thereof, or a transparent conductive material, such as indium tin oxide (ITO) or indium gallium zinc oxide (ITZO), but the present application is not limited thereto.

[0025] Accordingly, when the micro light emitting chip 1A is enabled, the first electrode 121 can be selectively provided with a high potential, and the second electrode 122 can be selectively provided with a low potential or a ground potential. Due to the potential difference generated between the first electrode 121 and the second electrode 122, current can pass from the first electrode 121, sequentially through the first semiconductor layer 101, the light emitting layer 103, the second semiconductor layer 102 of the first sub-chip 100A, the conductive element 180A, and then to the first semiconductor layer 101, the light emitting layer 103, the second semiconductor layer 102 and the second electrode 122 of the second sub-chip 100B, so that both the first sub-chip 100A and the second sub-chip 100B can emit light.

[0026] According to the above, the structure of the micro light emitting chip 1A in series can easily adjust the number of sub-chips to adjust the voltage division of each sub-chip, so that each sub-chip can adapt to the corresponding operating voltage (for example, the operating voltage of red microLED is 1.6-2.0 volts, and the operating voltage of blue microLED is 3.0-3.4 volts). When the micro light emitting chip 1A is applied to different displays, different color micro light emitting chips 1A can be provided with the same voltage, achieving the function of reducing power consumption and simplifying the circuit. On the other hand, the micro light emitting chip 1A can also have the advantages of high brightness, high power and high extraction efficiency.

[0027] It is worth mentioning that the insulating structure 130 is disposed between the first sub-chip 100A and the second sub-chip 100B, and electrically insulates the first sub-chip 100A and the second sub-chip 100B at the insulating structure 130. For example, the insulating structure 130 can be directly fabricated on the structure of the micro light emitting chip 1A, that is, the insulating structure 130 can be part of the micro light emitting chip 1A, and located in the region (for example, the space S) between the first sub-chip 100A and the second sub-chip 100B. Here, the insulating structure 130 can change the characteristics of the first semiconductor layer 101 by, for example, ion implantation technology, so that the first semiconductor layer 101 loses the conductivity of the semiconductor. In detail, the lattice of the first semiconductor layer 101 can be defective or irregular by ion implantation, so as to capture or hinder the carrier to pass through the insulating structure 130, so as to reduce the conductivity in the region. In addition, mechanical stress can also be applied to change the band structure to reduce the semiconductor characteristics of the insulating structure 130, and the above-mentioned methods can be used alone or in combination. However, the present application is not limited thereto. In some embodiments, the material of the insulating structure 130 can be different from the material of the first semiconductor layer 101. The insulating structure 130 can be connected between the first semiconductor layer 101 of the first sub-chip 100A and the second sub-chip 100B to have a first contact surface TS1 and a second contact surface TS2, respectively. That is, the portions adjacent to the insulating structure 130 of the two sub-chips are single electrical semiconductor (for example, the first contact surface TS1 contacts the first semiconductor layer 101 of the first sub-chip 100A without contacting the second semiconductor layer 102 of the first sub-chip 100A). In the present embodiment, the portions adjacent to the insulating structure 130 of the two sub-chips have the same electrical property (for example, both are N-type semiconductor or both are P-type semiconductor). In addition, the space between the first contact surface TS1 and the second contact surface TS2 can define the space S, and the insulating structure 130 fills part of the space S. The insulating structure 130 can be, for example, an inorganic insulating material or an organic insulating material, and the present application is not limited thereto. In other embodiments not shown, the insulating structure 130 can also completely fill the space S; that is, the insulating structure 130 can completely cover the first contact surface TS1, the second contact surface TS2, and be flush with the upper surface 101S of the first semiconductor layer 101.

[0028] In addition, in some embodiments, the first sub-chip 100A and the second sub-chip 100B can each include a passivation layer (for example, a silicon oxide layer) on the contact surface connected to the insulating structure 130. That is, the first contact surface TS1 and the second contact surface TS2 can refer to the portions of the passivation layer of the first sub-chip 100A and the second sub-chip 100B, respectively, which are in contact with the insulating structure 130.

[0029] The first electrode 121 and the second electrode 122 have a first notch C1 and a second notch C2, respectively, as shown. Figure 1B The conductive element 180A is disposed between the first notch C1 of the first electrode 121 and the second notch C2 of the second electrode 122, and electrically connects the two sub-chips (i.e., the first sub-chip 100A and the second sub-chip 100B).

[0030] The provision of the conductive element 180A between the first sub-chip 100A and the second sub-chip 100B in the linking direction (i.e., the direction X in the figure) via the insulating structure 130 can provide sufficient structural strength for the micro light emitting chip 1A, and further enable the conductive element 180A to stably connect the first sub-chip 100A and the second sub-chip 100B, thereby enhancing the product reliability of the micro light emitting chip 1A. In addition, the structure of the conductive element 180A connecting the sub-chips in series can reduce the precision or uniformity requirements for the micro light emitting chip 1A when being bonded, picked up, and transferred to other substrates, and is less likely to be damaged, broken, or tilted due to uniformity (e.g., flatness) effects, thereby effectively improving the transfer yield of the carrier board on which the micro light emitting chip 1A is mounted, and enhancing the device reliability of the display panel provided with the micro light emitting chip 1A. In the present embodiment, by designing the first notch C1 and the second notch C2 in the first electrode 121 and the second electrode 122, the conductive element 180A can extend into the notches and have a larger area, and thus the conductive element 180A can further support the structural strength of the two connected sub-chips. In the present embodiment, the sum of the areas of the orthogonal projections of the first electrode 121, the second electrode 122, and the conductive element 180A on the reference plane P1 parallel to the two sub-chips (i.e., the first sub-chip 100A and the second sub-chip 100B) is greater than or equal to 0.6 times the area of the orthogonal projection of the micro light emitting chip 1A on the reference plane P1, which can further ensure that the conductive element 180A has a large enough area to provide good structural support for the two connected sub-chips.

[0031] In the present embodiment, the area of the orthogonal projection of the conductive element 180A on the reference plane P1 is greater than or equal to 0.1 times the area of the orthogonal projection of the micro light emitting chip 1A on the reference plane P1, and less than or equal to 0.5 times the area of the orthogonal projection of the micro light emitting chip 1A on the reference plane P1, which can ensure that the conductive element 180A has a large enough area to provide good structural support for the two connected sub-chips, and can also serve as a reflective layer.

[0032] In the present embodiment, the area of the orthogonal projection of the conductive element 180A on the reference plane P1 is greater than or equal to the area of the orthogonal projection of the first electrode 121 on the reference plane P1, or greater than or equal to the area of the orthogonal projection of the second electrode 122 on the reference plane P1.

[0033] In the present embodiment, the height H1 of the conductive element 180A in the direction perpendicular to the reference plane P1 is smaller than the height H2 of the micro light emitting chip 1A in the direction perpendicular to the reference plane P1. In an embodiment, the height H1 can fall within the range of 0.5 to 2 microns. In the present embodiment, the orthogonal projection of the conductive element 180A on the reference plane P1 is away from the orthogonal projection of the first electrode 121 on the reference plane P1, and away from the orthogonal projection of the second electrode 122 on the reference plane P1, which can be seen from the bottom view of the micro light emitting chip 1A, that is, there is a gap G1 between the orthogonal projection of the conductive element 180A on the reference plane P1 and the orthogonal projection of the first electrode 121 on the reference plane P1, and there is a gap G2 between the orthogonal projection of the conductive element 180A on the reference plane P1 and the orthogonal projection of the second electrode 122 on the reference plane P1. In an embodiment, the minimum values of the gaps G1 and G2, for example, fall within the range of 0.5 to 2 microns. Figure 1B

[0034] In the present embodiment, the first gap C1 and the second gap C2 are opposite to each other. In addition, in the present embodiment, the ratio of the width W1 of the first gap C1 to the width W2 of the first electrode 121 is greater than or equal to 0.2 and less than or equal to 0.5, and the ratio of the width W3 of the second gap C2 to the width W4 of the second electrode 122 is greater than or equal to 0.2 and less than or equal to 0.5, that is, the ratio of the maximum width of the first gap C1 and the first electrode 121 in the same direction (for example, the X direction) is greater than or equal to 0.2 and less than or equal to 0.5, and the ratio of the maximum width of the second gap C2 and the second electrode 122 in the same direction (for example, the X direction) is greater than or equal to 0.2 and less than or equal to 0.5. In addition, the first gap C1 and the second gap C2 can be arc-shaped gaps or polygonal gaps (for example, square gaps), and the present application is not limited thereto. Furthermore, the shape of the side of the conductive element 180A close to the first gap C1 can be complementary to the shape of the first gap C1, and the shape of the side of the conductive element 180A close to the second gap C2 can be complementary to the shape of the second gap C2.

[0035] ​It is worth mentioning that the distance between the first contact surface TS1 and the second contact surface TS2 can vary along the thickness direction (e.g., direction Y) of the insulating structure 130. For example, the first contact surface TS1 and the second contact surface TS2 have a distance d1 on the side adjacent to the first electrode 121 or the second electrode 122, and gradually increase to a distance d2 toward the side away from the first electrode 121 or the second electrode 122. In some embodiments, the relationship between the distance d1 and the distance d2 can be 1.5d1≦d2≦3d1. Here, the width of the first sub-chip 100A or the second sub-chip 100B (e.g., the maximum width of the first semiconductor layer 101 in the direction X) is greater than the distance d2 of the insulating structure 130, for example, less than 10 times the distance d2, to ensure that the insulating structure 130 can provide sufficient connection strength. In some implementations, the distance d1 can be 1.5 microns and the distance d2 can be 2.8 microns. In addition, a side of the insulating structure 130 adjacent to the upper surface 101S may have a concave surface facing the negative Y direction, which may further enhance the light extraction effect of the micro light-emitting chip 1A.

[0036] In addition, the protection unit 160 may be an insulating layer composed of an insulating material. For example, the material of the protection unit 160 may include silicon oxide (Si x O y ) or inorganic substances such as titanium dioxide (TiO2), or a coating layer composed of a single material, but not limited to this. In detail, in this embodiment, the protection unit 160 is configured on the outer surfaces of the first sub-chip 100A, the second sub-chip 100B and the insulating structure 130, and has a first surface 161 and a second surface 162 opposite to each other in the direction Y, and the first sub-chip 100A, the second sub-chip 100B and the insulating structure 130 are located between the first surface 161 and the second surface 162. The first surface 161 and the second surface 162 of the protection unit 160 can partially cover or completely cover the outer surface or upper surface 101S of the first sub-chip 100A, the second sub-chip 100B and the insulating structure 130. Furthermore, in addition to the first surface 161 and the second surface 162, the protection unit 160 can also extend to cover the side walls of the micro light-emitting chip 1A (that is, the circumferential side surfaces in the X direction). In other words, the first sub-chip 100A, the second sub-chip 100B, the insulating structure 130, and the conductive element 180A can all be integrated into the protection unit 160. This prevents moisture, oxygen, or other impurities from invading the first sub-chip 100A and the second sub-chip 100B, while also further enhancing the structural strength of the micro light-emitting chip 1A and improving the device reliability of the micro light-emitting chip 1A.

[0037] In some embodiments, the protection unit 160 can be integrally formed with the insulation structure 130 and be made of the same material. That is, the insulation structure 130 can also be further flush with the first surface 161 of the protection unit 160. Additionally, since the protection unit 160 is integrated with the insulation structure 130, particularly for embodiments in which the insulation structure 130 is not part of the micro light emitting chip 1A, the protection unit 160 on the side of the first surface 161 can function as a support similar to a beam structure. Specifically, without affecting the light emission performance of the upper surface 101S, moderately increasing the thickness of the protection unit 160 on the first surface 161 (e.g., 1.5 to 3 microns) can directly provide support for the first sub-chip 100A and the second sub-chip 100B in the Y direction. In this way, during the transfer process of the chip, the protection unit 160 can have an effect similar to a temporary substrate, giving the entire micro light emitting chip 1A sufficient mechanical strength. In some embodiments, the protection unit 160 can be made in the same process as the insulation structure 130. However, the present application is not limited thereto. In some embodiments, the protection unit 160 can be made of a different material than the insulation structure 130.

[0038] In addition, in the present embodiment, the first sub-chip 100A and the second sub-chip 100B can each further include a first contact layer 111 and a second contact layer 112. The first contact layer 111 is disposed between the first semiconductor layer 101 and the first electrode 121, and the second contact layer 112 is disposed on the second semiconductor layer 102. The first contact layer 111 and the second contact layer 112 are, for example, layers of N-type or P-type semiconductor material with high doping concentration, or other suitable materials, to facilitate Ohmic contact between the conductive element 180A, the first electrode 121, the second electrode 122, the first semiconductor layer 101, and the second semiconductor layer 102. However, the present application is not limited thereto, and in some embodiments, the first sub-chip 100A and the second sub-chip 100B can also not be provided with the first contact layer 111 and the second contact layer 112.

[0039] On the other hand, the micro light emitting chip 1A can further include a Bragg reflector layer 140. The Bragg reflector layer 140 can extend in the direction X and cover the same side of the first sub-chip 100A and the second sub-chip 100B, and in the direction Y, the Bragg reflector layer 140 is disposed between the first sub-chip 100A and the first electrode 121, and between the second sub-chip 100B and the second electrode 122. The Bragg reflector layer 140 can have the functions of insulation and reflecting light beams. And the aforementioned conductive element 180A can be electrically connected to the second semiconductor layer 102 of the first sub-chip 100A and the first semiconductor layer 101 of the second sub-chip 100B through the through hole TH12 and the through hole TH21 passing through the Bragg reflector layer 140, respectively. And the conductive element 180A can be disposed between the Bragg reflector layer 140 formed of an inorganic material and the protection unit 160 to avoid breakage.

[0040] On the other hand, the micro light emitting chip 1A can further include a Bragg reflector layer 140. The Bragg reflector layer 140 can extend in the direction X and cover the same side of the first sub-chip 100A and the second sub-chip 100B, and in the direction Y, the Bragg reflector layer 140 is disposed between the first sub-chip 100A and the first electrode 121, and between the second sub-chip 100B and the second electrode 122. The Bragg reflector layer 140 can have the functions of insulation and reflecting light beams. And the aforementioned conductive element 180A can be electrically connected to the second semiconductor layer 102 of the first sub-chip 100A and the first semiconductor layer 101 of the second sub-chip 100B through the through hole TH12 and the through hole TH21 passing through the Bragg reflector layer 140, respectively. And the conductive element 180A can be disposed between the Bragg reflector layer 140 formed of an inorganic material and the protection unit 160 to avoid breakage.

[0041] Figure 2 is a cross-sectional view of a micro light emitting chip according to an embodiment of the present application. Please refer to Figure 2 The micro light emitting chip 1B of the present embodiment is similar to the micro light emitting chip 1A, and the main difference is that the number of sub-chip series is different. In detail, the micro light emitting chip 1B further includes a third sub-chip 100C and a conductive element 180B, and the protection unit 160 further covers the third sub-chip 100C and the conductive element 180B. The second sub-chip 100B and the third sub-chip 100C can also have an insulating structure 130 between them, and have a first contact surface TS1 and a second contact surface TS2 with the second sub-chip 100B and the third sub-chip 100C, respectively. And the conductive element 180B is electrically connected to the second sub-chip 100B and the third sub-chip 100C. That is, the micro light emitting chip 1B is composed of three sub-chips connected in series with each other. And the second electrode 122 is connected to the transparent conductive layer 170, and then connected to the second semiconductor layer 102 of the third sub-chip 100C through the through hole TH32 passing through the protection unit 160 and the Bragg reflector layer 140.

[0042] In other embodiments, the number of sub-chips can be more than 3 (e.g., 4 or 5), and the number of conductive elements and the number of insulating structures 130 between two adjacent sub-chips can be increased accordingly. For example, when the number of sub-chips is n, the number of conductive elements and the number of insulating structures 130 can be n-1, and the present application is not limited thereto.

[0043] In the present embodiment, the first electrode 121 of the micro light emitting chip 1B can also have a first notch C1 as shown in Figure 1B , and the second electrode 122 of the micro light emitting chip 1B can also have a second notch C2 as shown in Figure 1B , and the conductive element 180A can have a portion located in the first notch C1, and the conductive element 180B can have a portion located in the second notch C2.

[0044] Figure 3 is a cross-sectional view of a micro light emitting chip structure according to an embodiment of the present application. In Figure 3 , two micro light emitting chips 1H are loaded in the micro light emitting chip structure 10A as an exemplary illustration. On the other hand, the first electrode 121 (or the second electrode 122) and the insulating structure 130 are located on opposite sides of the micro light emitting chip 1H, or on opposite sides of the first sub-chip 100A (or the second sub-chip 100B), respectively. In addition, the first electrode 121 and the second electrode 122 are located between the micro light emitting chip 1H and the temporary substrate 11. The fixing element 12 (e.g., an electrically insulating adhesive) fixes the plurality of micro light emitting chips 1H to the temporary substrate 11 via the fixing element 12, wherein the plurality of micro light emitting chips 1H are electrically insulated from the temporary substrate 11. The temporary substrate 11, such as a plastic substrate, a glass substrate, or a sapphire substrate, can be fixed and flat. However, the present application is not limited thereto. In the present embodiment, the micro light emitting chip 1H further includes the optical structure 150 disposed on one side of the micro light emitting chip 1H, such as directly covering the upper surface 101S and covering the micro structure MS, but in another embodiment not shown, the optical structure 150 can not be disposed.

[0045] Figure 4 is a cross-sectional view of a display panel according to an embodiment of the present application. Please refer to Figure 4 , the display panel 20A includes the circuit substrate 21. The circuit substrate 21 has a plurality of pixel circuits 22 and a plurality of contact pads 23 electrically connected to the pixel circuits 22. The plurality of micro light emitting chips 1H are disposed on the circuit substrate 21 and are electrically connected to the contact pads 23 via the first electrode 121 and the second electrode 122, respectively, to complete the electrical connection between the plurality of micro light emitting chips 1H and the circuit substrate 21. In the foregoing Figure 3After the micro light emitting chip 1H is manufactured, a mass transfer technique can be used to pick up multiple micro light emitting chips 1H at the same time and transfer them to the circuit substrate 21 to complete the display panel 20A.

[0046] In this embodiment, the circuit substrate 21 includes multiple signal lines (e.g. data lines, scan lines or power lines, not shown) and pixel circuits 22 connected thereto, and can provide two electrical signals to the two contact pads 23 respectively, so that the micro light emitting chip 1H emits display beams. It is worth mentioning that the three micro light emitting chips 1H shown in Figure 4 may emit beams of different wavelength ranges respectively, for example, the three micro light emitting chips 1H may emit a red light wavelength beam L1, a green light wavelength beam L2 and a blue light wavelength beam L3 respectively, but the present application is not limited thereto. In other embodiments, the beams emitted by multiple micro light emitting chips 1H may also have substantially the same wavelength range.

[0047] The circuit substrate 21 is, for example, a driving substrate using silicon wafer material and including complementary metal oxide semiconductor (CMOS), thereby improving the response speed of each switching element in the circuit substrate 21 and reducing power consumption to meet the requirements of fast response and high resolution of the display panel 20A. However, the present application is not limited thereto. In other embodiments, the circuit substrate 21 can also be a printed circuit board (PCB) or a combination of a glass substrate and a pixel circuit layer formed on the glass substrate by semiconductor process, and the pixel circuit layer can include active elements (e.g. thin film transistors) and multiple signal lines (e.g. data lines, scan lines or power lines, not shown), but is not limited thereto.

[0048] As described above, the display panel 20A using the micro light emitting chip 1H as a display pixel can have the advantages of high brightness, low power consumption and good structural strength, can reduce the probability of occurrence of pixel dead points, improve the bonding yield of the transfer process, and further improve the product competitiveness.

[0049] Figure 5 is a bottom view of the micro light emitting chip of another embodiment of the present application. Please refer to Figure 5 , the micro light emitting chip 1J of this embodiment is similar to the micro light emitting chip 1A of Figure 1B , and the main difference between them is described as follows. In the micro light emitting chip 1J of this embodiment, the first notch C1 and the second notch C2 are away from each other. In an embodiment, the outer shape of the first electrode 121 is 180 degree rotationally symmetrical with the outer shape of the second electrode 122. In this way, the micro light emitting chip 1J is different from Figure 1BIn comparison, the center of gravity of the micro-light emitting chip 1J of this embodiment is closer to the geometric center of the micro-light emitting chip 1J, which can effectively prevent the micro-light emitting chip 1J from tipping over during mass transfer. Figure 1A The orthographic projection area on the insulating structure 130 (as shown) is greater than or equal to Figure 1A The conductive element 180J is further enhanced in support of the conductive element 180J, overcoming the problem of weak structural strength caused by the insulating structure 130 supporting the central region of the micro-light-emitting chip 1J where the conductive element 180J is located. The larger area of ​​the conductive element 180J also helps reduce current crowding. In one embodiment, the ratio of the orthographic projection area of ​​the insulating structure 130 on the reference plane P1 to the orthographic projection area of ​​the conductive element 180J on the reference plane P1 is greater than 0.2 and less than 1. Furthermore, in one embodiment, the ratio of the width W1 of the first notch C1 to the width W2 of the first electrode 121 is greater than or equal to 0.2 and less than or equal to 0.5, and the ratio of the width W3 of the second notch C2 to the width W4 of the second electrode 122 is greater than or equal to 0.2 and less than or equal to 0.5.

[0050] Figure 6 This is a bottom view of a micro light emitting chip according to another embodiment of the present invention. Figure 6 The micro-light emitting chip 1K of this embodiment is Figure 5 The micro-light emitting chip 1J of the present embodiment is similar to the micro-light emitting chip 1J of the present embodiment. The main difference between the two is that in the micro-light emitting chip 1K of the present embodiment, the maximum width W5 of the conductive element 180K is greater than or equal to the maximum width W6 of the first electrode 121, or greater than or equal to the maximum width W7 of the second electrode 122. In addition, in the present embodiment, the conductive element 180K is located on the reference plane P1 (e.g., Figure 1A The orthographic projection area on the reference plane P1 is larger than the orthographic projection area of ​​the first electrode 121 or the orthographic projection area of ​​the second electrode 122 on the reference plane P1. This is because the middle area of ​​the micro light-emitting chip 1J where the conductive element 180J is located is close to the insulating structure 130 (as shown). Figure 1A The problem of weak structural strength is caused by the support of the conductive element 180K (shown). Designing the conductive element 180K to have a larger area can provide better support to overcome this problem. In one embodiment, the ratio of the orthogonal projected area of ​​the conductive element 180K on the reference plane P1 to the orthogonal projected area of ​​the first electrode 121 on the reference plane P1 is greater than 1 and less than or equal to 1.5, and the ratio of the orthogonal projected area of ​​the conductive element 180K on the reference plane P1 to the orthogonal projected area of ​​the second electrode 122 on the reference plane P1 is greater than 1 and less than or equal to 1.5.

[0051] In summary, in the micro light emitting chip, the micro light emitting chip structure and the display panel of the embodiments of the present application, the first electrode and the second electrode have the first notch and the second notch respectively, the conductive element is arranged between the first notch of the first electrode and the second notch of the second electrode, and the sum of the projected areas of the first electrode, the second electrode and the conductive element on the reference plane parallel to the two sub-chips is greater than or equal to 0.6 times the projected area of the micro light emitting chip on the reference plane, or the first notch and the second notch are away from each other, and the contour of the first electrode and the contour of the second electrode are 180-degree rotational symmetrical. Therefore, the conductive element can have a larger area, and the structural strength of the two connected sub-chips can be supported, so as to effectively reduce the fracture or tilting of the micro light emitting chip from the connection between the two sub-chips due to uneven stress in the mass transfer process. Therefore, the micro light emitting chip of the embodiments of the present application can have better structural strength, and the micro light emitting chip structure and the display panel of the embodiments of the present application can have better structural strength and manufacturing yield.

[0052] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A micro light emitting chip, characterized by, The micro light emitting chip comprises: two sub-chips; an insulation structure disposed between the two sub-chips so that the two sub-chips are electrically insulated from each other at the insulation structure; a first electrode and a second electrode respectively connected to the two sub-chips and respectively having a first notch and a second notch; and a conductive element disposed between the first notch of the first electrode and the second notch of the second electrode and electrically connecting the two sub-chips, wherein a total of areas of orthographic projections of the first electrode, the second electrode and the conductive element on a reference plane parallel to the two sub-chips is greater than or equal to 0.6 times of an area of an orthographic projection of the micro light emitting chip on the reference plane. An area of an orthographic projection of the conductive element on the reference plane is greater than or equal to 0.1 times of the area of the orthographic projection of the micro light emitting chip on the reference plane and less than or equal to 0.5 times of the area of the orthographic projection of the micro light emitting chip on the reference plane.

2. The micro light emitting chip of claim 1, wherein, An area of an orthographic projection of the conductive element on the reference plane is greater than or equal to an area of an orthographic projection of the first electrode on the reference plane or greater than or equal to an area of an orthographic projection of the second electrode on the reference plane.

3. The micro light emitting chip of claim 1, wherein, A height of the conductive element in a direction perpendicular to the reference plane is less than a height of the micro light emitting chip in the direction perpendicular to the reference plane.

4. The micro light emitting chip of claim 1, wherein, The orthographic projection of the conductive element on the reference plane is away from the orthographic projection of the first electrode on the reference plane and away from the orthographic projection of the second electrode on the reference plane.

5. The micro light emitting chip of claim 1, wherein, A ratio of a maximum width of the first notch to a maximum width of the first electrode in the same direction is greater than or equal to 0.2 and less than or equal to 0.5, and a ratio of a maximum width of the second notch to a maximum width of the second electrode in the same direction is greater than or equal to 0.2 and less than or equal to 0.

5.

6. The micro light emitting chip of claim 1, wherein, The first notch and the second notch are opposite to each other.

7. The micro light emitting chip of claim 1, wherein, The first notch and the second notch are away from each other.

8. The micro light emitting chip of claim 1, wherein, An area of an orthographic projection of the conductive element on the reference plane is greater than or equal to an area of an orthographic projection of the insulation structure on the reference plane.

9. The micro light emitting chip of claim 8, wherein, A maximum width of the conductive element is greater than or equal to a maximum width of the first electrode or greater than or equal to a maximum width of the second electrode.

10. The micro light emitting chip of claim 8, wherein, The micro light emitting chip comprises:

11. A micro light emitting chip structure, characterized by a temporary substrate; a fixing element; and a plurality of micro light emitting chips fixed to the temporary substrate via the fixing element, wherein the plurality of micro light emitting chips are electrically insulated from the temporary substrate, and each of the plurality of micro light emitting chips comprises: two sub-chips; an insulation structure disposed between the two sub-chips so that the two sub-chips are electrically insulated from each other at the insulation structure; a first electrode and a second electrode respectively connected to the two sub-chips and respectively having a first notch and a second notch; and a conductive element disposed between the first notch of the first electrode and the second notch of the second electrode and electrically connecting the two sub-chips, ​ ​ The sum of the areas of the projections of the first electrode, the second electrode and the conductive element onto a reference plane parallel to the two sub-chips is greater than or equal to 0.6 times the area of the projection of the micro light emitting chip onto the reference plane.

12. A display panel, characterized by, The micro light emitting chip comprises: a circuit substrate provided with a plurality of pixel circuits; and a plurality of micro light emitting chips disposed on the circuit substrate, each of the plurality of micro light emitting chips comprising: two sub-chips; an insulating structure disposed between the two sub-chips such that the two sub-chips are electrically insulated from each other at the insulating structure; a first electrode and a second electrode respectively connected to the two sub-chips and each having a first notch and a second notch, wherein one of the first electrode and the second electrode is electrically connected to one of the plurality of pixel circuits; and a conductive element disposed between the first notch of the first electrode and the second notch of the second electrode and electrically connected to the two sub-chips, wherein the sum of the areas of the projections of the first electrode, the second electrode and the conductive element onto a reference plane parallel to the two sub-chips is greater than or equal to 0.6 times the area of the projection of the micro light emitting chip onto the reference plane.

13. The display panel of claim 12, wherein, The projection of the conductive element onto the reference plane is away from the projection of the first electrode onto the reference plane and away from the projection of the second electrode onto the reference plane.

14. A micro light emitting chip, characterized by The micro light emitting chip comprises: two sub-chips; an insulating structure disposed between the two sub-chips such that the two sub-chips are electrically insulated from each other at the insulating structure; a first electrode and a second electrode respectively connected to the two sub-chips and each having a first notch and a second notch; and a conductive element disposed between the first notch of the first electrode and the second notch of the second electrode and electrically connected to the two sub-chips, wherein the first notch and the second notch are away from each other, and the outer contour of the first electrode and the outer contour of the second electrode are 180-degree rotationally symmetrical.

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