Memory device, memory system, memory controller and operating method

Abstract

The embodiment of the invention discloses a memory device, a memory system, a memory controller and operation, and the memory device comprises a memory unit array which comprises a plurality of memory units, and a preset number of memory units form a code word; the peripheral circuit is coupled with the storage unit array and is configured to perform M times of first adjustment on a target reading voltage of at least one code word according to a first step length, and obtain M first results corresponding to M reading voltages after the M times of first adjustment; taking the minimum first result in the M first results as an inflection point value, and taking the reading voltage corresponding to the inflection point value as an inflection point voltage; n times of second adjustment is carried out on the inflection point voltage according to a second step length, N first results corresponding to the N reading voltages after the N times of second adjustment are obtained, and the second step length is smaller than the first step length; determining a target valley voltage according to the obtained N first results; m and N are positive integers greater than 1.

Description

Memory device, memory system, memory controller and operation method Technical Field

[0001] The present application relates to, but is not limited to, a memory device, a memory system, a memory controller, and an operating method. Background Art

[0002] With the advancement of technology, the integrated circuit industry has seen a growing market. Within this industry, the processes and technologies for non-volatile memory devices have seen rapid advancements in recent years, with NAND memory being particularly widely used. NAND memory achieves data storage by capturing and storing charge within the gate dielectric layer of its memory cells. However, over time, the charge stored in the memory cells can change due to factors such as age, repeated read operations, and cross-temperature fluctuations, thus affecting the accuracy of data reads.

[0003] Summary of the Invention

[0004] In a first aspect, embodiments of the present application provide a memory device, comprising: a memory cell array comprising a plurality of memory cells, wherein a predetermined number of the memory cells form a codeword; a peripheral circuit coupled to the memory cell array and configured to: perform a first adjustment M times on a target read voltage of at least one of the codewords with a first step size, and obtain M first results corresponding to the M read voltages after the M first adjustments; the first result including a number of bits flipped in a read result representing at least one of the codewords at a first read voltage and a second read voltage, wherein the difference between the first read voltage and the second read voltage is less than a predetermined voltage; use a minimum first result among the M first results as an inflection point value, and a read voltage corresponding to the inflection point value as the inflection point voltage; perform a second adjustment N times on the inflection point voltage with a second step size, and obtain N first results corresponding to the N read voltages after the N second adjustments, wherein the second step size is less than the first step size; and determine a target valley voltage based on the obtained N first results, wherein the target valley voltage is used as a read voltage when performing a read operation on the at least one codeword; wherein both M and N are positive integers greater than 1.

[0005] In a second aspect, an embodiment of the present application provides a memory system, comprising: one or more memory devices as provided in any one of the first aspects; and a memory controller coupled to and controlling the memory devices.

[0006] In a third aspect, an embodiment of the present application provides a memory controller coupled to at least one memory device, the memory device including a plurality of memory cells, wherein a preset number of the memory cells form a codeword; the memory controller including: a control unit configured to: perform M first adjustments on a target read voltage of at least one of the codewords with a first step size, and obtain M first results corresponding to the M read voltages after the M first adjustments; the first result including a representation of the number of bits flipped in two read results of the at least one codeword at the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage being less than a preset voltage; using the smallest first result among the M first results as an inflection point value, and the read voltage corresponding to the inflection point value being the inflection point voltage; performing N second adjustments on the inflection point voltage with a second step size, and obtaining N first results corresponding to the N read voltages after the N second adjustments; the second step size being less than the first step size; and determining a target valley voltage based on the obtained N first results; the target valley voltage being used as a read voltage when performing a read operation on the at least one codeword; wherein both M and N are positive integers greater than 1.

[0007] In a fourth aspect, an embodiment of the present application provides an operating method for a memory device, comprising: performing M first adjustments on a target read voltage of at least one codeword with a first step length, and respectively obtaining M first results corresponding to the M read voltages after the M first adjustments; the first result includes the number of bits that are flipped in two read results at a first read voltage and a second read voltage representing a codeword formed by a preset number of storage cells in at least one memory device, and the difference between the first read voltage and the second read voltage is less than a preset voltage; taking the smallest first result among the M first results as an inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; performing N second adjustments on the inflection point voltage with a second step length, and respectively obtaining N first results corresponding to the N read voltages after the N second adjustments; the second step length is smaller than the first step length; and determining a target valley voltage based on the N first results obtained, the target valley voltage being used as a read voltage when performing a read operation on at least one of the codewords; wherein both M and N are positive integers greater than 1.

[0008] In a fifth aspect, an embodiment of the present application provides an operating method for a memory system, comprising: a memory controller in the memory system sends a data acquisition instruction, wherein the data acquisition instruction indicates acquisition of a target valley voltage; a memory device in the memory system receives the data acquisition instruction, acquires the target valley voltage according to the operating method of the memory device described in the fourth aspect, and sends information including the target valley voltage to the memory controller; the memory controller performs a read operation on data stored in the memory device according to the target valley voltage in the information.

[0009] In a sixth aspect, an embodiment of the present application provides an operating method of a memory controller, performing M first adjustments on a target read voltage of at least one codeword with a first step length, and respectively obtaining M first results corresponding to the M read voltages after the M first adjustments; the first result includes the number of bits flipped in two read results at a first read voltage and a second read voltage representing a codeword formed by a preset number of storage cells in a memory device of at least one memory system, and the difference between the first read voltage and the second read voltage is less than a preset voltage; taking the smallest first result among the M first results as an inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; performing N second adjustments on the inflection point voltage with a second step length, and respectively obtaining N first results corresponding to the N read voltages after the N second adjustments; the second step length is smaller than the first step length; and determining a target valley voltage based on the N first results, the target valley voltage being used as a read voltage when performing a read operation on at least one of the codewords; wherein both M and N are positive integers greater than 1.

[0010] In the seventh aspect, an embodiment of the present application provides a storage medium having executable instructions stored thereon. When the executable instructions are executed, the steps of any one of the operating methods provided in the fourth aspect, the fifth aspect, and the sixth aspect can be implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0012] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0013] FIG2A is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0014] FIG2B is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application;

[0015] FIG3 is a schematic diagram of an exemplary memory including peripheral circuits according to an embodiment of the present application;

[0016] FIG4 is a cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present application;

[0017] FIG5 is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuits according to an embodiment of the present application;

[0018] FIG6 is a schematic diagram of an exemplary read operation flow of a memory system provided by the present application;

[0019] FIG7 is a schematic diagram illustrating a flowchart of an implementation of an operation method performed by a peripheral circuit of a memory device according to an embodiment of the present application;

[0020] FIG8 is a schematic diagram of a threshold voltage distribution of a memory cell when obtaining a first result according to an embodiment of the present application;

[0021] FIG9A is a schematic diagram of the distribution of near-valley points and near-valley thresholds provided in one embodiment of the present application;

[0022] FIG9B is a schematic diagram of statistics showing an upward trend when a second adjustment is made to the left, provided by an embodiment of the present application;

[0023] FIG9C is a schematic diagram of statistics showing an upward trend when a second adjustment is made to the right, provided by an embodiment of the present application;

[0024] FIG10 is a schematic diagram of a method for filtering out noise according to an embodiment of the present application;

[0025] FIG11 is a schematic diagram of determining a target valley voltage according to an embodiment of the present application;

[0026] FIG12A is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including two memory bits provided in one embodiment of the present application;

[0027] FIG12B is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including three memory bits provided in one embodiment of the present application;

[0028] FIG12C is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including four memory bits provided in one embodiment of the present application;

[0029] FIG13 is a flowchart of a method for operating a memory device according to an embodiment of the present application;

[0030] FIG14 is a second flowchart of a method for operating a memory device according to an embodiment of the present application;

[0031] FIG15 is a schematic diagram of an exemplary structure of a memory system provided in one embodiment of the present application;

[0032] FIG16 is a block diagram of a memory system provided by an embodiment of the present application;

[0033] FIG17 is a timing diagram of an exemplary start-up single-level read mode operation provided by the present application;

[0034] FIG18 is a timing diagram of determining a target valley voltage and performing a read operation according to an embodiment of the present application;

[0035] FIG19 is a schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0037] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0038] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0039] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to actual circumstances.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] The memory device in the embodiments of the present application includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0042] FIG1 shows a block diagram of an exemplary system 100 with a memory device according to some aspects of the present application. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 can include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be a control unit of an electronic device (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)). Host 108 can be configured to send data to or receive data from memory device 104.

[0043] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0044] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0045] The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 may also be configured to process error correction codes for data read from or written to the memory device 104.

[0046] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0047] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). In other words, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0048] 2A , the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG. 1 ).

[0049] 2B , the memory controller 106 and the plurality of memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG. 1 ). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0050] In some embodiments, each memory block may be coupled to a plurality of word lines, and a plurality of memory cells coupled to each word line constitute a physical page.

[0051] FIG3 illustrates a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to some aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1 . Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to memory cell array 301. For illustration, memory cell array 301 is described as a three-dimensional NAND-type memory cell array, wherein memory cells 306 are NAND-type memory cells provided in an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate memory cell including a floating-gate transistor, or a charge-trapping memory cell including a charge-trapping transistor.

[0052] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0053] It should be noted that the storage state mentioned here is the storage state of the storage unit mentioned in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has 2 storage states (that is, two memory states), wherein these 2 storage states include: a programming state and an erased state. For another example, an MLC type storage cell has 4 storage states, wherein these 4 storage states include: an erased state and three programming states. For another example, a TLC type storage cell has 8 storage states, wherein these 8 storage states include: one erased state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, wherein these 16 storage states include: one erased state and fifteen programming states.

[0054] As shown in FIG3 , each memory string 308 may include a lower select transistor (BSG) 310 (also known as a source-side select transistor) at its source terminal and an upper select transistor (TSG) 312 (also known as a drain-side select transistor) at its drain terminal. The BSG 310 and the TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0055] As shown in FIG3 , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and to unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0056] 3 , each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318 , and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding select transistor (eg, top select transistor (TSG) 312 ).

[0057] FIG4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including a NAND memory string 308 according to some aspects of the present disclosure. As shown in FIG4 , the NAND memory cell array 301 may include a stacked structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically extending through the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form the memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412.

[0058] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0059] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0060] In some embodiments, memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0061] Referring back to FIG3 , the peripheral circuit 302 can be coupled to the memory cell array 301 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG5 shows some exemplary peripheral circuits, including a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in FIG. 5 may also be included.

[0062] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0063] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0064] The control logic 512 can be coupled to each of the other parts in the peripheral circuit described above and is configured to control the operation of each of the other parts in the peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0065] The basic principle of 3D NAND memory is that data is written by injecting a certain amount of charge into a memory cell, via carriers (electrons or holes) across a charge barrier. The stored data can then be read based on the threshold voltage at which the memory cell turns on. Therefore, to ensure accurate data is read, a robust and efficient error correction algorithm is typically employed during data reading.

[0066] However, as the charge stored in a memory cell changes over time due to age, repeated read operations, and temperature fluctuations, this can affect the accuracy of data reads. When the threshold voltage shifts significantly upward or downward, the likelihood of read errors is high when reading the data from the memory cell using the original read voltage. Furthermore, when the read error rate exceeds the error correction capability, data read failures can occur.

[0067] FIG6 is a schematic diagram illustrating an exemplary read operation flow for a memory system. As shown in FIG6 , when a memory controller controls a memory device to perform a read operation, it first performs a default read operation (FW default read) on the memory cell at the corresponding physical address. If the default read operation fails, a reread operation (Read retry) is performed. If the reread operation fails, a soft decode operation is performed. If the soft decode operation fails, a Redundant Array of Independent Disks (RAID) operation is performed. If the RAID operation fails, the read operation ceases and the read fails due to uncorrectable errors. The memory controller then sends a Read Fail signal to the host 108. The reread operation and the default read operation can be applied to hard decode.

[0068] In some embodiments, a reread operation can typically be performed by querying a retry table (or trial and error table) provided by the manufacturer. The essence of the reread operation is an error correction mechanism. The reread table can provide a reference voltage for reading data. By querying the reread table, an attempt is made to read each storage cell again using a read voltage that deviates from the normal threshold voltage and perform error correction in conjunction with an error correction algorithm in an attempt to correctly read the data. If the read error data is corrected, the query to the reread table is stopped. If the read error data cannot be corrected, the reread table is continuously queried until the entire reread table is traversed.

[0069] The aforementioned reread operation method requires querying the reread table line by line, which inevitably increases the number of trial and error cycles and is time-consuming. Furthermore, the reread table provided by the manufacturer is only a reference value for specific environments. Real-world usage scenarios vary greatly, so the manufacturer's reread table does not cover many scenarios. Consequently, even after traversing the reread table, data may not be corrected, resulting in a significant waste of command processing time. In short, rereading by repeatedly polling the reread table is time-consuming, affecting the response time of subsequent commands and, consequently, device performance.

[0070] Based on one or more of the above problems, in a first aspect, embodiments of the present application provide a memory device.

[0071] As shown in FIG7 , the memory device includes: a memory cell array including a plurality of memory cells, wherein a predetermined number of the memory cells form a codeword; and a peripheral circuit coupled to the memory cell array and configured to perform the following steps:

[0072] Step S10: performing M first adjustments on the target read voltage of at least one of the codewords with the first step length, and obtaining M first results corresponding to the M read voltages after the M first adjustments; the first results include a number of bits flipped in the read results of the at least one codeword at the first read voltage and the second read voltage, wherein the difference between the first read voltage and the second read voltage is less than a preset voltage;

[0073] Step S20: taking the smallest first result among the M first results as the inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage;

[0074] Step S30: performing N second adjustments on the knee voltage with a second step size, and respectively obtaining N first results corresponding to N read voltages after the N second adjustments, wherein the second step size is smaller than the first step size; and

[0075] Step S40: determining a target valley voltage based on the N first results obtained, wherein the target valley voltage is used as a read voltage when performing a read operation on at least one of the codewords; wherein both M and N are positive integers greater than 1.

[0076] In some embodiments, a memory device includes a memory cell array, the memory cell array including multiple memory blocks, each memory block including multiple word lines and multiple memory cells coupled to each word line. All memory cells coupled to a word line form a physical page. A predetermined number of memory cells form a code word (CW). A physical page includes one or more code words.

[0077] In some embodiments, the number of storage cells included in a codeword is the same as the number of storage cells included in one encoding or decoding when performing error correction encoding or decoding. In some specific embodiments, the number of storage cells included in a codeword may be less than or equal to the number of storage cells coupled to a physical page, such as the number of storage cells included in a codeword is 1 / 4 of the number of storage cells coupled to a physical page. In some specific embodiments, a codeword may include a number ranging from 2 4 to 2 12 For example, a code word may include 2 4 , 2 8 or 2 12 storage units.

[0078] In general, different memory systems may choose codewords of different sizes to meet their performance, reliability, and storage requirements. The number of bits that can be stored by memory cells (e.g., MLC, TLC, or QLC) in different types of memory devices varies. It is understood that a codeword can include multiple memory cells, and the number of memory cells included in a codeword can be adjusted based on actual conditions.

[0079] It should be noted that in practice, codewords will have some additional reserved space for management and error correction, so the number of storage units actually required may slightly exceed the above calculation result.

[0080] Here, the target valley voltage is used as the read voltage when performing a read operation on at least one of the codewords. In determining the target valley voltage, the first adjustment can be understood as a large-step adjustment, or coarse adjustment. The second adjustment can be understood as a small-step adjustment, or fine adjustment. The core concept of this adjustment scheme is to perform coarse adjustment first and then fine adjustment. This reduces the number of loop iterations and allows for faster determination of the target valley voltage.

[0081] Here, the first step length is greater than the second step length. The first step length can be a larger step length. In some embodiments, the first step length can range from 50mV to 150mV. For example, the first step length can be 50mV, 80mV, 100mV, 120mV, or 150mV. The second step length can be a smaller step length. In some embodiments, the second step length can range from 20mV to 40mV. For example, the second step length can be 20mV, 30mV, or 40mV.

[0082] Here, the adjusted read voltage is used as the horizontal axis, and the first result corresponding to the adjusted target read voltage is used as the vertical axis. These two axes form a point. The inflection point can be understood as a point close to the valley bottom. The valley bottom point corresponds to the target valley voltage as the horizontal axis. The inflection point value is the vertical axis of the inflection point, and the inflection point voltage is the horizontal axis of the inflection point.

[0083] The following describes the meaning of the first result and how to obtain it.

[0084] Here, the first result represents the number of bits flipped in two reading results of the codeword of the to-be-read operation at the corresponding read voltage and a voltage close to the corresponding read voltage.

[0085] In some embodiments, during the reading of the memory device, a read operation may read out data of a physical page. When the number of storage cells contained in a codeword may be less than the number of storage cells coupled to a physical page, the codeword is a unit that can be executed to obtain the first result, but multiple codewords are not actually excluded. In other words, the first result corresponding to at least one codeword under the current read voltage can be obtained here. For example, a physical page can correspond to 4 codewords, and the page buffer hardware operation can count the Fail Bit Count (FBC) of each of the 4 codewords at one time, and then add the FBC of the four codewords to obtain the FBC of a physical page. The subsequent calculation uses the added value. It can be understood that the first result here can be based on the data of a physical page, and a physical page can include multiple codewords.

[0086] Here, the first read voltage and the second read voltage are both general terms, and the difference between the first read voltage and the second read voltage is less than a preset voltage. In some specific embodiments, the second read voltage is greater than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of 5mV to 20mV. For example, the difference between the first read voltage and the second read voltage can be 5mV, 10mV, 15mV, or 20mV. In other specific embodiments, the second read voltage is less than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of -5mV to -20mV. For example, the difference between the first read voltage and the second read voltage can be -5mV, -10mV, -15mV, or -20mV.

[0087] In some embodiments, the peripheral circuit is configured to: read the stored data of the codeword at the first read voltage to obtain a second result; perform a third adjustment on the first read voltage with a third step size to obtain the second read voltage, and read the stored data of the codeword at the second read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count the number of bits in the fourth result that represent that the third result is flipped compared to the second result to obtain the first result.

[0088] In some embodiments, the peripheral circuit includes: a first latch, a second latch, and a third latch; the first latch is configured to store the second result; the second latch is configured to store the third result; and the third latch is configured to store the fourth result.

[0089] Here, the first read voltage and the second read voltage are contextually related, meaning that the second read voltage is obtained by performing a third adjustment on the first read voltage. Based on this, the voltage difference between the first read voltage and the second read voltage is the third step size. The second step size is greater than the third step size, meaning that the third step size can be smaller. In some embodiments, the third step size ranges from 5mV to 20mV. Exemplarily, the third step size can be 5mV, 10mV, 15mV, or 20mV. The preset voltage is related to the third step size and can be a voltage slightly larger than the third step size. In some embodiments, the preset voltage ranges from 6mV to 21mV. Exemplarily, the preset voltage can be 6mV, 11mV, 16mV, or 21mV. In other embodiments, the preset voltage ranges from -6mV to -21mV. Exemplarily, the preset voltage can be -6mV, -10mV, -16mV, or -21mV.

[0090] As previously mentioned, the first read voltage and the second read voltage are both general terms. The target read voltage and the read voltage obtained after adjusting the target read voltage can both be referred to as the first read voltage, and the read voltage obtained after performing the third adjustment on the first read voltage can both be referred to as the second read voltage. In each embodiment of the present application, the first result corresponding to a specific voltage can be understood as: when the specific voltage is adjusted to the third voltage, the number of bits flipped in the codeword read at the specific voltage and after the third adjustment to the specific voltage can be used as the first result corresponding to the specific voltage.

[0091] In some embodiments, before obtaining a first result corresponding to at least one codeword at a corresponding target read voltage, the read mode of the memory device is set to a single-level read mode (Single Level Read, SLR); the single-level read mode includes reading at least one bit of stored data stored in a memory cell using a single-level read voltage. The multi-level read voltage will be described in detail later.

[0092] In some embodiments, the memory device is configured to enter a single-level read mode in response to a mode setting command, and obtain a first result corresponding to at least one codeword at a target read voltage of a first target step in the single-level read mode.

[0093] In some specific embodiments, the stored data of the codeword is read at a first read voltage to obtain a second result; the second result is stored in a first latch of the memory device. For example, as shown in FIG8 , the stored data of at least one codeword is read at a first read voltage V0 to obtain a second result. Specifically, memory cells with a threshold voltage less than a target read voltage V0 are marked as bit 1, and memory cells with a threshold voltage greater than the target read voltage V0 are marked as bit 0, to obtain the second result, which is then stored in the first latch of the memory device.

[0094] Next, a third adjustment is made to the first read voltage to obtain a second read voltage. The stored data of the codeword is read at this second read voltage to obtain a third result. The third result is stored in the second latch of the memory device. For example, as shown in FIG8 , a third adjustment is made to the first read voltage V0. The stored data of the codeword is read at the adjusted second read voltage V1 to obtain a third result. Specifically, memory cells with a threshold voltage less than the second read voltage V1 are marked as bit 1, and memory cells with a threshold voltage greater than the second read voltage V1 are marked as bit 0. This results in a third result, which is then stored in the second latch of the memory device.

[0095] Next, a logical operation is performed on the second result and the third result to obtain a fourth result; the fourth result is stored in the third latch of the memory device. For example, as shown in FIG8 , an exclusive-OR operation is performed on the second result and the third result to obtain a fourth result; the fourth result is stored in the third latch of the memory device. It should be noted that the exclusive-OR operation is one of the basic logical operations. In binary, if two binary numbers in the same position are the same, the result is "0", and if two binary numbers in the same position are different, the result is "1" (i.e., if they are the same, the result is 0, and if they are different, the result is 1).

[0096] Next, the number of bits in the fourth result that represent flipped bits in the third result compared to the second result is counted to obtain a first result. For example, as shown in FIG8 , the bits that are 1 in the fourth result represent the number of memory cells whose threshold voltages differ between the first read voltage V0 and the second read voltage V1. In other words, the bits that are 1 in the fourth result represent the number of bits in the codeword that are flipped between the first read voltage V0 and the second read voltage V1. This number is recorded as the first result Y1 corresponding to the first read voltage.

[0097] It should be noted that the first result is also referred to as FBC in the embodiment of the present application.

[0098] In order to reduce the number of loop iterations, a point with a better position (for example, a point closer to the valley bottom) may be determined before performing the coarse adjustment, and the subsequent coarse adjustment and fine adjustment may be performed based on this point.

[0099] In some embodiments, the peripheral circuit is configured to: determine a near-valley threshold value based on a first result corresponding to at least one of the codewords at an initial target read voltage before performing M first adjustments to the target read voltage of at least one of the codewords with a first step length, wherein the near-valley threshold value is used to characterize the maximum value of the first result corresponding to a voltage close to the target valley bottom; before performing M first adjustments to the target read voltage of at least one of the codewords with a first step length, adjust the initial target read voltage multiple times until the first result corresponding to the adjusted target read voltage is less than the near-valley threshold value; use the adjusted target read voltage corresponding to the first result being less than the near-valley threshold value as the target read voltage, and perform M first adjustments to the target read voltage with a first step length.

[0100] Here, the initial target read voltage may be a read voltage when the threshold voltage of the memory cell has not shifted, such as a read voltage corresponding to a memory cell immediately after writing, in which case the corresponding offset value is 0. In the embodiment of the present application, the first result corresponding to at least one codeword at the initial target read voltage may be obtained by the aforementioned method of obtaining the first result, that is, the initial target read voltage is used as the first read voltage to obtain the corresponding first result.

[0101] The near-valley threshold is used to represent the maximum value of the first result corresponding to the near-valley voltage. In some embodiments, the peripheral circuit is configured to: obtain the near-valley threshold based on the first result corresponding to the target read voltage and a first mapping function; wherein the first mapping function is used to represent the relationship between the near-valley threshold and the first result corresponding to the target read voltage.

[0102] Here, the first mapping function is related to the characteristics of the memory device. The first mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device.

[0103] Before performing M first adjustments on the target read voltage of at least one codeword with a first step length, the initial target read voltage is adjusted multiple times. In some specific embodiments, the multiple adjustments may be blind adjustments.

[0104] In other specific embodiments, the peripheral circuit is configured as follows: before performing M first adjustments to the target read voltage of at least one of the codewords with a first step length, in a process of performing multiple adjustments to the initial target read voltage, according to the first result corresponding to the adjusted target read voltage being greater than or equal to the near-valley threshold, obtaining the next adjusted target read voltage based on the first result corresponding to the target read voltage after the last adjustment; taking the adjusted target read voltage corresponding to the near-valley threshold for the first time after multiple first results corresponding to the adjusted target read voltage are less than the adjusted target read voltage as the near-valley point voltage; in the process of performing M first adjustments to the target read voltage with a first step length, starting from the near-valley point voltage, adjusting in two opposite directions with the first step length until the first results corresponding to the adjusted read voltages in the two directions are both greater than the near-valley threshold.

[0105] Here, multiple adjustments refer to obtaining the next adjusted target read voltage based on the last adjustment. In some embodiments, the peripheral circuit is configured to obtain the next adjusted target read voltage based on a first result corresponding to the last adjusted target read voltage and a second mapping function; the second mapping function is used to represent the relationship between the first result corresponding to the last adjusted target read voltage and the next adjusted predicted read voltage.

[0106] Here, the second mapping function is related to the characteristics of the memory device, while the first mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. However, the second mapping function differs from the first mapping function. The first mapping function only supports a single calculation, while the second mapping function can be iterated multiple times.

[0107] In some specific embodiments, the first result corresponding to the initial target read voltage can be substituted into the first mapping function to obtain the near-valley threshold, and then the first result under the initial target read voltage (as the target read voltage after the last adjustment) can be substituted into the second mapping function to obtain an adjusted target read voltage. If the first result corresponding to the adjusted target read voltage obtained at this time is already less than the near-valley threshold, the point corresponding to the adjusted target read voltage can be directly used as the object of the subsequent first adjustment; if the first result corresponding to the adjusted target read voltage obtained at this time is greater than or equal to the near-valley threshold, the first result corresponding to the adjusted target read voltage can be substituted into the second mapping function again to obtain an adjusted target read voltage, and then the first result under the recovered target read voltage is compared with the near-valley threshold. In this way, the second mapping function is used for loop iteration until the first adjusted target read voltage whose first first result is less than the near-valley threshold is obtained. The adjusted target read voltage whose first first result is less than the near-valley threshold is used as the near-valley point voltage. The point corresponding to the near-valley point voltage is the near-valley point.

[0108] In some embodiments, the peripheral circuit is configured as follows: in a process of performing M first adjustments on the near-valley point voltage with a first step length, starting from the near-valley point voltage, adjusting in a first direction with the first step length until a first result corresponding to the target read voltage after adjustment in the first direction is greater than the near-valley threshold; starting from the near-valley point voltage, adjusting in a second direction opposite to the first direction with the first step length until a first result corresponding to the target read voltage after adjustment in the second direction is greater than the near-valley threshold.

[0109] Here, the first adjustment needs to be performed in two directions: the first direction can be the left direction (or negative direction), and the second direction can be the right direction (or positive direction); or the first direction can be the right direction (or positive direction), and the second direction can be the left direction (or negative direction). During the process of performing the M first adjustments, the order of adjusting the first direction and the second direction can be adjusted according to actual needs.

[0110] In other embodiments, the first adjustment may also be performed in one direction. It should be noted that, for an application scenario, if the direction of the threshold voltage shift can be inferred, the first adjustment may be performed in only one direction. For example, for an application scenario determined to be data retention, if it can be inferred that the threshold voltage distribution of the memory cell is shifted to the left, the first adjustment may be performed only in the left direction (or negative direction).

[0111] For example, as shown in Figure 9A , the first result corresponding to the initial target read voltage is the first FBC. The near-valley threshold is obtained based on this first FBC and the first mapping function. The near-valley point fnvp is found based on this first FBC and the second mapping function (one or more iterations). Starting from the near-valley point, adjustments are made in the left and right directions (or forward directions) with a first step length until the first results corresponding to the adjusted read voltages in both directions are greater than the near-valley threshold.

[0112] In some embodiments, the peripheral circuit is configured as follows: in the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, adjusting in two opposite directions with the second step size respectively; in the process of adjusting in each direction, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, performing an upward trend statistics, and determining the first boundary voltage and the second boundary voltage based on the total number of statistics being greater than or equal to a preset number; in the process of adjusting in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than a preset threshold, or the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as a reference value, when the number of the remaining multiple first results whose differences from the reference value are less than the preset difference is greater than a preset number, stopping the adjustment and using the adjusted target read voltage corresponding to the smallest first result among the multiple first results as the target valley voltage.

[0113] Here, the target read voltage after the last adjustment and the target read voltage after the next adjustment are both general concepts, which are the adjustment with an earlier adjustment time and the adjustment with a later adjustment time in any two adjacent second adjustments.

[0114] Here, the preset number represents the degree to which the inflection point is raised. The preset number can be adjusted according to actual conditions. In some embodiments, the preset number is 3-7 times. Exemplarily, the preset number can be 3, 5 or 7 times.

[0115] During the adjustment process in each direction, if the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, it indicates that the first result corresponding to the target read voltage after the next adjustment is on an upward trend compared to the first result corresponding to the target read voltage after the previous adjustment, and a statistical analysis of the upward trend is performed. If the first result corresponding to the target read voltage after the next adjustment is less than or equal to the first result corresponding to the target read voltage after the previous adjustment, it indicates that the first result corresponding to the target read voltage after the next adjustment is on a downward or unchanged trend compared to the first result corresponding to the target read voltage after the previous adjustment, and a statistical analysis of the upward trend is not performed. In other words, the data of the statistical analysis of the upward trend remains unchanged during this statistical analysis.

[0116] Here, the preset threshold value is used to characterize the maximum value in the range of predicted effective valley voltage. The preset threshold value can be determined based on the first result at the initial target read voltage. It is understandable that when performing a read operation, the further the threshold voltage of the memory cell shifts from the threshold voltage during writing, the larger the first result read using the initial target read voltage will generally be. Based on this, the specific value of the first result at the initial target read voltage can be used to confirm the preset threshold value. The preset threshold value is used to characterize the change (increase) in the valley voltage caused by the shift in the threshold voltage of the memory cell.

[0117] It should be noted that although the preset threshold and the aforementioned near-valley threshold are both obtained based on the first result corresponding to the initial target reading voltage, there are differences between the two. When the first result is less than the near-valley threshold, it means that more precise adjustments or searches can be carried out next; when the first result is less than the preset threshold, it means that you can consider stopping the adjustment or search and directly determine the target valley voltage.

[0118] In some embodiments, when the first result is less than a preset threshold, it indicates that the adjusted target read voltage corresponding to the first result can be used as the target valley voltage.

[0119] In some embodiments, the smallest first result among the plurality of first results corresponding to the target read voltage after N times of second adjustment is used as a reference value. If the number of the remaining plurality of first results whose difference from the reference value is less than a preset difference is greater than a preset number, the search is stopped and the adjusted target read voltage corresponding to the smallest first result among the plurality of first results is used as the target valley voltage. Here, the preset difference and the preset number can be set together based on actual conditions. Generally, a slightly larger preset difference is set, and a relatively larger preset number is also set; generally, a slightly smaller preset difference is set, and a relatively smaller preset number is also set.

[0120] In some embodiments, the peripheral circuit is configured as follows: in the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, adjusting in the first direction with the second step size until the total statistical number of times the upward trend is shown during the adjustment process in the first direction is equal to a preset number; starting from the inflection point voltage, adjusting in a second direction opposite to the first direction with the second step size until the total statistical number of times the upward trend is shown during the adjustment process in the second direction is equal to a preset number.

[0121] Here, the second adjustment needs to be performed in two directions: the first direction can be the left direction (or negative direction), and the second direction can be the right direction (or positive direction); or the first direction can be the right direction (or positive direction), and the second direction can be the left direction (or negative direction). During the process of performing the first adjustment M times, the order of adjusting the first direction and the second direction can be adjusted according to actual needs.

[0122] Here, when the total statistical number of times of the upward trend in the adjustment process toward the first direction / the second direction is equal to a preset number, the second adjustment is stopped.

[0123] In some embodiments, the peripheral circuit is configured to: use the adjusted target read voltage corresponding to the total statistical number of times the upward trend is equal to the preset number during the adjustment in the first direction as the first boundary voltage, and use the adjusted target read voltage corresponding to the total statistical number of times the upward trend is equal to the preset number during the adjustment in the second direction as the second boundary voltage; in the process of adjusting in both directions, if the first boundary voltage and the second boundary voltage have been determined, obtain the first result corresponding to the last adjusted read voltage, and the last adjusted read voltage is the average of the first boundary voltage and the second boundary voltage; and use the read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted read voltages as the target valley voltage.

[0124] Here, the boundary corresponding to the first boundary voltage may be the left boundary, and the boundary corresponding to the second boundary voltage may be the right boundary; or, the boundary corresponding to the first boundary voltage may be the right boundary, and the boundary corresponding to the second boundary voltage may be the left boundary.

[0125] For example, as shown in Figure 9B , after M first adjustments, the point corresponding to the smallest first result among the M first results corresponding to the M first adjustments is determined as the inflection point vtp. Starting from the inflection point vtp, adjustments are made in a second step size toward the left. When the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, an upward trend count is performed. In Figure 9B , both leftward second adjustments show an upward trend, and the total upward trend count is 2. Thereafter, according to the preset number of times, if the preset number has been reached, a second adjustment can be started in a second step size toward the right; if the preset number has not been reached, the second adjustment can continue in a leftward second step size until the preset number is reached.

[0126] For example, as shown in FIG9C , starting from the inflection point vtp, adjustments are made in a second step size toward the right. When the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, an upward trend count is performed. In FIG9C , of the three second adjustments toward the right, the first adjustment shows a downward trend, and the total statistical value of the upward trend is 0. The next two adjustments both show an upward trend, and the total statistical value of the upward trend is 2. Thereafter, according to the preset number of times, if the preset number of times has been reached, the second adjustment can be stopped; if the preset number of times has not been reached, the adjustment can continue toward the right until the preset number of times has been reached, and the second adjustment is stopped.

[0127] It should be noted that filtering out points that have a downward trend since the last adjustment can eliminate the influence of noise, thereby more accurately finding the valley bottom. Specifically, as shown in Figure 10, the horizontal axis in Figure 10 is the threshold voltage, and the vertical axis is the FBC. For the hollow dot in the dashed box in Figure 10, if this point is determined as an inflection point during multiple first adjustments, and there is no mechanism to count only upward trends, but both upward and downward trends are counted, then during multiple second adjustments, if the number of counts in both directions reaches a preset number, such as 3, the second adjustment is stopped. At this time, the hollow dot (a) with the smallest FBC among the multiple second adjustments will be mistakenly regarded as the valley bottom point. However, if there is a mechanism that only counts upward trends, then in the multiple second adjustments to the left, the first and second adjustments show an upward trend, and the statistical value of the upward trend is 2. From the third to the fifth adjustments, there is a downward trend, and the statistical value of the upward trend will remain at 2. Until the sixth adjustment begins to show an upward trend again, the total statistical value of the upward trend will reach 3. At this time, the solid point b with the smallest FBC in the multiple second adjustments will be used as the bottom point.

[0128] Considering that the second adjustment has a step size, if the valley point falls between two adjacent second adjustments, the valley point may be skipped. In some embodiments, if the first boundary voltage and the second boundary voltage have been determined, a first result corresponding to the read voltage of the last adjustment is obtained, where the read voltage of the last adjustment is the average of the first boundary voltage and the second boundary voltage; and the read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted read voltages is used as the target valley voltage.

[0129] Here, the average value of the first boundary voltage and the second boundary voltage is intended to compensate for the aforementioned possible skipping situation, further obtaining a more accurate valley point, and thus obtaining a more accurate valley voltage.

[0130] In some specific embodiments, as shown in FIG11 , the horizontal axis in FIG11 is the threshold voltage, and the vertical axis is the first result. The first result Y1 shown in FIG11 is a near-valley point. The near-valley point can be found in the manner shown in FIG9A , by obtaining the near-valley threshold value based on the first result (first FBC) corresponding to the initial target read voltage and the first mapping function, and based on the first FBC and the second mapping function (one or more iterations).

[0131] In some specific embodiments, for an application scenario determined to be data retention, it can be inferred that the threshold voltage distribution of the memory cell is shifted to the left, and the first adjustment can also be made only in the left direction (or negative direction). For example, as shown in FIG11 , starting from the near-valley point (Y1), the near-valley point voltage Vfnvp corresponding to the near-valley point is adjusted only in the left direction (or negative direction) with a first step length, and a plurality of first results Y2, Y3, and Y4 corresponding to the adjusted read voltages are obtained until the first result Y4 is greater than the near-valley threshold, and the adjustment is stopped. The smallest first result among the plurality of first results is taken as the inflection point value. As shown in FIG11 , the first result Y3 is taken as the inflection point value, and the read voltage corresponding to the inflection point value Y3 is the inflection point voltage V2.

[0132] Starting from the inflection point value (Y3), the inflection point voltage V2 is adjusted in a second step toward the left. When the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, an upward trend count is performed. In Figure 11, the three leftward second adjustments all show an upward trend, and the total number of upward trends is 3, i.e., the first result Y3 is less than the first result Y5, the first result Y5 is less than the first result Y6, and the first result Y6 is less than the first result Y7. Thereafter, according to the preset number of times, if the preset number of times has been reached, the second adjustment can be started in a second step toward the right. If the preset number of times has not been reached, the second adjustment can be continued to the left until the preset number of times has been reached.

[0133] For example, as shown in FIG11 , starting from the inflection point value ( Y3 ), adjustments are made in a second step toward the right. When the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, an upward trend count is performed. In FIG11 , both second adjustments toward the right show a downward trend, and the total statistical value of the upward trend is 0, i.e., the first result Y3 is greater than the first result Y8 , and the first result Y8 is greater than the first result Y9 . Furthermore, if the first result Y9 corresponding to the second target read voltage after the second adjustment toward the right is lower than a preset threshold (not shown in FIG11 ), the adjustment is stopped and the adjusted target read voltage V3 corresponding to the smallest first result ( Y9 ) among the multiple first results is used as the target valley voltage.

[0134] For applications determined to require data retention, it can be inferred that the threshold voltage distribution of the memory cells is shifted to the left. Therefore, the first adjustment can be performed only in the leftward (or negative) direction, eliminating the need for the first adjustment in the rightward (or positive) direction. This allows for flexible adjustment of the first adjustment direction based on the actual application scenario, reducing the number of iterations and enabling faster determination of the target valley voltage.

[0135] In some embodiments, the memory cell array includes memory cells with a storage bit number of P bits, the P storage bits correspond to P pages respectively, and the P-bit memory cells read their P-bit storage data through a Q-level read voltage; P and Q are both integers greater than 1, and Q=2 P -1.

[0136] For example, when the number of storage bits of a memory cell includes two, the corresponding storage states include states 0 to 4. Referring to FIG12A , the four states are state 0 (also called the erased state) E, state 1 (also called the first storage state) P1, state 2 (also called the second storage state) P2, and state 3 (also called the third storage state) P3. The binary data corresponding to these four states are 11, 10, 00, and 01, respectively. Accordingly, the memory device includes two pages, namely, a lower page (LP) and an upper page (UP).

[0137] Taking the memory cell shown in FIG. 12A as an example, the two-bit memory cell reads its two-bit four-state storage data through three-level read voltages (a first-level read voltage L1 , a second-level read voltage L2 , and a third-level read voltage L3 ).

[0138] For example, one page corresponds to multiple read voltages, and the other page corresponds to a single read voltage. As shown in FIG12A , the binary data corresponding to the lower page are 1001, and reading the lower page requires the corresponding first read voltage L1 and third read voltage L3. The binary data corresponding to the upper page are 1100, and reading the upper page requires the corresponding second read voltage L2.

[0139] For example, when the number of storage bits of a memory cell includes three bits, the corresponding storage states include states 0 to 7. Referring to FIG12B , the eight states are state 0 (also called the erased state) E, state 1 (also called the first storage state) P1, state 2 (also called the second storage state) P2, ... state 7 (also called the seventh storage state) P7, and the binary data corresponding to the eight states are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. Accordingly, the memory device includes three pages: a lower page, a middle page (MP), and an upper page.

[0140] Taking the memory cell shown in Figure 12B as an example, the three-bit memory cell reads its three-bit eight-state storage data through 7-level read voltages (first-level read voltage L1, second-level read voltage L2, third-level read voltage L3, fourth-level read voltage L4, fifth-level read voltage L5, sixth-level read voltage L6, and seventh-level read voltage L7).

[0141] For example, each page corresponds to multiple read voltage levels. As shown in FIG12B , the binary data corresponding to the lower page are 10000111, and reading the lower page requires corresponding to the first read voltage L1 and the fifth read voltage L5. The binary data corresponding to the middle page are 11001100, and reading the middle page requires corresponding to the second read voltage L2, the fourth read voltage L4, and the sixth read voltage L6. The binary data corresponding to the upper page are 11100001, and reading the upper page requires corresponding to the third read voltage L3 and the seventh read voltage L7.

[0142] Exemplarily, when the number of storage bits of a memory cell includes four bits, the corresponding storage states include the 0th state to the 15th state. Referring to FIG12C , the 16 states are the 0th state (also called the erased state) E, the 1st state (also called the 1st storage state) P1, the 2nd state (also called the 2nd storage state) P2…the 15th state (also called the 15th storage state) P15, and the binary data corresponding to the 16 states are 1111, 0111, 0110….1110. Accordingly, the memory device includes four pages, namely, a lower page, a middle page, an upper page, and an extra page (XP). Here, the four storage bits corresponding to the 16 states are stored in the lower page, the middle page, the upper page, and the extra page, respectively.

[0143] Taking the memory cell shown in Figure 12C as an example, the four-bit memory cell reads its four-bit sixteen-state storage data through 15 levels of read voltages (first level read voltage L1, second level read voltage L2, third level read voltage L3, fourth level read voltage L4, fifth level read voltage L5, sixth level read voltage L6, seventh level read voltage L7, eighth level read voltage L8, ninth level read voltage L9, tenth level read voltage L10, eleventh level read voltage L11, twelfth level read voltage L12, thirteenth level read voltage L13, fourteenth level read voltage L14, and fifteenth level read voltage L15).

[0144] Exemplarily, each page corresponds to multiple read voltage levels. As shown in FIG12C , the binary data corresponding to the lower page are 1100000011111100, and reading the lower page requires corresponding read voltages L2, L8, and L14. The binary data corresponding to the middle page are 1110000110000111, and reading the middle page requires corresponding read voltages L3, L7, L9, and L13. The binary data corresponding to the upper page are 1111100000110001, and reading the upper page requires corresponding read voltages L5, L10, L12, and L15. The binary data corresponding to the extra pages are 1000110000011111. Reading the extra pages requires corresponding first-level read voltage L1, fourth-level read voltage L4, sixth-level read voltage L6 and eleventh-level read voltage L11.

[0145] In the embodiment of the present application, the target valley voltage for each level of the multi-level read voltage corresponding to each page is determined sequentially. Since the lower page is typically closest to the source / drain, prioritizing the determination of each level of the read voltage corresponding to the lower page results in the fastest access speed and the shortest response time, ensuring balanced performance and durability during data access.

[0146] It should be noted that the method of preferentially determining each level of read voltage corresponding to the next page is only an example and is not used to limit the order of determining each level of read voltage in the multi-level read voltage corresponding to at least part of the pages in the embodiment of the present application.

[0147] In some embodiments, at least some pages correspond to multi-level read voltages, the multi-level read voltages including a first-level read voltage and a second-level read voltage, wherein the second-level read voltage is lower than the first-level read voltage. For example, the first-level read voltage can be understood as the highest read voltage among the multi-level read voltages for each page, and the second-level read voltage can be understood as other read voltages lower than the highest read voltage among the multi-level read voltages for each page.

[0148] It should be noted that the first and second levels are used to distinguish between a high-level read voltage and a low-level read voltage among the multiple-level read voltages corresponding to at least a portion of the page, with the low-level read voltage being lower than the high-level read voltage. For a memory cell containing multiple storage bits, a page corresponding to one storage bit may include one or more levels, and one level may include one or more levels.

[0149] For example, referring to FIG. 12A , a memory device includes a lower page and an upper page, wherein the lower page corresponds to multiple levels, and the multiple levels corresponding to the lower page include a first level and a third level, and a first level read voltage L1 is less than a third level read voltage L3. Here, the third level read voltage L3 corresponds to the read voltage of the first level, and the first level read voltage L1 corresponds to the read voltage of the second level.

[0150] For example, referring to FIG. 12B , a memory device includes a lower page, a middle page, and an upper page, wherein each page corresponds to multiple levels. The multiple levels corresponding to the lower page include a first level and a fifth level, where a first level read voltage L1 is less than a fifth level read voltage L5. The multiple levels corresponding to the middle page include a second level, a fourth level, and a sixth level, where a second level read voltage L2 and a fourth level read voltage L4 are both less than a sixth level read voltage L6. The multiple levels corresponding to the upper page include a third level and a seventh level, where a third level read voltage L3 is less than a seventh level read voltage L7. Here, the fifth level read voltage L5, the sixth level read voltage L6, and the seventh level read voltage L7 correspond to the first level read voltages of the lower, middle, and upper pages, respectively, and the first level read voltage L1, the second level read voltage L2, the fourth level read voltage L4, and the third level read voltage L3 correspond to the second level read voltages of the lower, middle, and upper pages, respectively.

[0151] Exemplarily, referring to Figure 12C, the memory device includes a lower page, a middle page, an upper page and an extra page, wherein each page corresponds to multiple levels, the multiple levels corresponding to the lower page include the second level, the eighth level and the fourteenth level, the second level read voltage L2 and the eighth level read voltage L8 are both less than the fourteenth level read voltage L14, the multiple levels corresponding to the middle page include the third level, the seventh level, the ninth level and the thirteenth level, the third level read voltage L3, the seventh level read voltage L7 and the ninth level read voltage L9 are all less than the thirteenth level read voltage L13, the multiple levels corresponding to the upper page include the fifth level, the tenth level, the twelfth level and the fifteenth level, the fifth level read voltage L5, the tenth level read voltage L10 and the twelfth level read voltage L12 are less than the fifteenth level read voltage L15, the multiple levels corresponding to the extra page include the first level, the fourth level, the sixth level and the eleventh level, the first level read voltage L1, the fourth level read voltage L4 and the sixth level read voltage L6 are less than the eleventh level read voltage L11. Here, the fourteenth-level read voltage L14, the thirteenth-level read voltage L13, the fifteenth-level read voltage L15 and the eleventh-level read voltage correspond to the first-level read voltages of the lower page, middle page, upper page and extra page respectively, the second-level read voltage L2 and the eighth-level read voltage L8 correspond to the second-level read voltage of the lower page, the third-level read voltage L3, the seventh-level read voltage L7 and the ninth-level read voltage L9 correspond to the second-level read voltage of the middle page, the fifth-level read voltage L5, the tenth-level read voltage L10 and the twelfth-level read voltage L12 correspond to the second-level read voltage of the upper page, the first-level read voltage L1, the fourth-level read voltage L4 and the sixth-level read voltage L6 correspond to the second-level read voltage of the extra page.

[0152] In some embodiments, the memory cell array includes memory cells having multiple storage bits; the multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple levels; the peripheral circuit is configured to: after determining the target valley voltage of at least one of the codewords in the target level, determine the target valley voltages of the other levels in the multiple levels except the target level.

[0153] Here, the target order is one order among multiple orders (one level among multiple levels). In some embodiments, the target order may first select the aforementioned first order or a higher order.

[0154] An alternative example of determining other orders is provided below.

[0155] In some embodiments, the multiple stages include a first stage and a second stage, and the read voltage of the second stage is lower than the read voltage of the first stage; the peripheral circuit is configured to: when the stage corresponding to the determined target valley voltage belongs to the first stage, obtain the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower read voltages according to the determined target valley voltage.

[0156] It should be noted that the predicted valley voltage can be used directly as a target valley voltage to perform a read operation on the data to be read, or can be obtained after further processing. The specific method of obtaining the predicted valley voltage will be further described below.

[0157] Here, the first and second orders have been introduced above and will not be repeated here. In the embodiment of the present application, the target valley voltage / predicted valley voltage of the high order (first order) can be used to obtain the predicted valley voltage of the low order (second order) and the predicted valley voltage of the remaining high orders. Specifically, the predicted valley voltage of the order to be predicted (the second order and the remaining first orders) can be obtained based on the target valley voltage / predicted valley voltage of the high order, the order number of the order to be predicted (the second order and the remaining first orders) and the third mapping function. Here, the third mapping function is related to the performance of the memory device (especially the offset performance of the memory cell threshold voltage). The third mapping function can be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. The third mapping function here is different from the above-mentioned first mapping function and the second mapping function. The third mapping function does not support loop iteration.

[0158] On the one hand, in each memory device provided by the embodiment of the present application, the first result (the size of the first result can be several bytes) is transmitted without transmitting at least one codeword (for example, the size of the codeword can be 4KB), the amount of data transmitted is reduced, and the transmission time of the output port is reduced; the process of obtaining the first result is converged inside the memory device, does not occupy the space of, for example, the memory controller, and has a low degree of dependence on, for example, the memory controller. At the same time, in the embodiment of the present application, during the adjustment process, a coarse-first-then-fine adjustment is performed, that is, a large-step adjustment (first adjustment) is performed first, and then a small-step adjustment (second adjustment) is performed. In this way, over-adjustment can be avoided during the adjustment process, thereby reducing the number of loop iterations and determining the target valley voltage more quickly. In addition, in the embodiment of the present application, during the small-step adjustment process, statistics of points that are on an upward trend compared to the previous adjustment are introduced. The statistics can filter out points that are on a downward trend compared to the previous adjustment, eliminate the influence of noise points, and thus more accurately find the valley point.

[0159] FIG13 is a flowchart of a method for operating a memory device according to an embodiment of the present application. The detailed process of determining the target valley voltage will be described in detail below with reference to FIG13. It should be noted that, herein and hereinafter, the target valley voltage refers to the voltage used to perform a read operation on the data to be read.

[0160] In step S101, the target valley voltage acquisition procedure is triggered, and the target valley voltage acquisition process is started. Next, step S102 is executed.

[0161] As previously mentioned, since the memory cell has multiple storage bits, the multiple storage bits correspond to multiple pages, and at least one page corresponds to multiple levels. When determining the target valley voltage, the target valley voltage for each level of the at least one level of read voltage corresponding to each of the multiple pages is determined sequentially. In step S103, one level is selected from the multiple levels corresponding to a page as the target level, and the target read voltage corresponding to the target level read voltage is first determined. For example, using TLC as an example, the target valley voltages for the first level read voltage L1 and the fifth level read voltage L5 corresponding to the next page are first determined. Either L1 or L5 can be selected as the target level. After the target level is determined, step S103 is executed.

[0162] In step S103, the main task is to determine the type of the target level. Here, the target level can be divided into two categories, the first level (also called high level) and the second level (also called low level), wherein the read voltage of the first level is greater than the read voltage of the second level. For example, still taking the lower page of TLC as an example, L5 is the first level and L1 is the second level. If L1 is selected as the target level in step S103, the target level is the second level, that is, the low level; if L5 is selected as the target level in step S104, the target level is the first level, that is, the high level. According to the target level being the low level, execute step S104; according to the target level being the high level, execute step S106.

[0163] In step S104, a predicted valley voltage is obtained. Here, the predicted valley voltage is obtained by deriving the predicted valley voltage corresponding to the lower order based on the target valley voltage corresponding to the higher order and a related mapping function. Here and below, the related mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. Next, step S105 is executed.

[0164] In step S105, it is determined whether the two-step prediction is successful. Here, the so-called two-step prediction may include a first prediction and a second prediction. The first prediction is to obtain a high-order predicted valley voltage. Specifically, the high-order predicted valley voltage is obtained based on the first result corresponding to the target read voltage (default read voltage), the order of the high-order, and the fourth mapping function. The second prediction is to obtain a low-order predicted valley voltage. Specifically, the low-order predicted valley voltage is obtained based on the high-order predicted valley voltage, the order of the low-order, and the third mapping function. After the two-step prediction, the predicted valley voltage is not confirmed. Hard decoding is directly performed using the high-order predicted valley voltage and the low-order predicted valley voltage. If the hard decoding is successful, the two-step prediction is successful. At this time, the search for the target valley voltage is stopped and step S121 is executed. If the hard decoding fails, the two-step prediction fails. At this time, the point corresponding to the predicted valley voltage is used as the near-valley point for the subsequent iteration, and step S107 is continued.

[0165] It should be noted that if the hard decoding fails, it means that the two-step prediction is unsuccessful. At this time, it is necessary to determine the target valley voltage through searching or also called looping (or iteration). Therefore, when the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the search process can be directly executed from the beginning of the loop, that is, jump from step S105 to S107.

[0166] If the target level is high, a search or loop is performed to determine the target valley voltage for the high level. In step S106, a default read voltage is used as the target read voltage. Here, the target read voltage can serve as the initial value for subsequent searches or loops. In some implementations, the default read voltage can be the read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage corresponding to a write operation, in which case the corresponding offset value is 0 DAC. Step S107 is executed after step S106.

[0167] It should be noted that here and below, the conversion relationship between DAC and the aforementioned mv is 1DAC=10mv.

[0168] In step S107, the target valley voltage is determined by searching or looping. After step S107, step S108 is executed.

[0169] For the first execution loop, in step S108, a first result at the target read voltage is obtained. It is understood that for subsequent execution loops, in step S108, a first result at an adjusted target read voltage is obtained. After step S108, step S109 is executed.

[0170] In step S109, the first threshold TH1 is determined or adjusted based on the first result at the target read voltage. It is understandable that when performing a read operation, the further the threshold voltage of the memory cell deviates from the threshold voltage during writing, the larger the first result read using the target read voltage will generally be. Based on this, the specific value of the first result at the default read voltage can be used to confirm the first threshold TH1. The first threshold TH1 is used to characterize the change (increase) in the valley voltage caused by the memory cell threshold voltage deviation. Step S110 is executed after step S109. The first threshold here can be further understood with reference to the relevant description of the preset threshold in the aforementioned embodiment.

[0171] It should be noted that step S109 is mainly for the first execution of the loop process, and can be skipped for subsequent execution of the loop process.

[0172] In step S110, a predicted valley voltage is obtained, and a determination is made as to whether the first result corresponding to the predicted valley voltage is less than the aforementioned first threshold TH1. Based on the first result corresponding to the target read voltage after the previous adjustment and a related mapping function (such as the aforementioned second mapping function), the predicted valley voltage after the next adjustment is obtained, and the first result corresponding to the obtained predicted valley voltage is compared with the first threshold TH1. If the determination result of step S110 is negative, it indicates that the first result corresponding to the predicted valley voltage obtained at this time is greater than or equal to the first threshold TH1. The loop continues with step S108, adjusting the target read voltage and re-obtaining the predicted valley voltage. Each re-obtained first result corresponding to the predicted valley voltage is compared with the first threshold TH1 until the first result corresponding to the obtained predicted valley voltage is less than the first threshold TH1. In other words, the prediction is iterated using the aforementioned prediction formula or related mapping function until the first result corresponding to the obtained predicted valley voltage is less than TH1. When the judgment result of step S110 is yes, it means that the first result corresponding to the predicted valley voltage obtained at this time is less than the first threshold TH1, and the process goes to the next step S111.

[0173] In step S111, an inflection point is found. Here, the target read voltage after each adjustment is used as the horizontal coordinate, and the first result corresponding to the corresponding adjusted target read voltage is used as the vertical coordinate, and the horizontal and vertical coordinates will form a point. The inflection point can be understood as a point relatively close to the bottom of the valley. In some embodiments, it is possible to start from the near-valley point with a coarser step size (first step size), and search to the left and right boundaries respectively until the left and right boundaries are reached, and the point corresponding to the minimum first result in the search process is used as the inflection point. Here, the inflection point is a point that is closer to the bottom of the valley than the near-valley point. The point that is less than the first threshold in the aforementioned step can be used as the near-valley point. For example, the near-valley point can be the point that is less than the first threshold that appears for the first time in the aforementioned step. The first step size can be a larger step size. In some embodiments, the first step size can be 5DAC-15DAC. Exemplarily, the first step size can be 5DAC, 10DAC or 15DAC. Step S112 is performed after step S111.

[0174] In step S112, it is determined whether an inflection point has been found. If no inflection point has been found, the search continues, and step S111 is continued until an inflection point is found. After the inflection point is found, step S113 is executed.

[0175] In step S113 and step S114, the search can be performed starting from the near-valley point with a finer step size (second step size) to the left boundary and the right boundary respectively until the left boundary and the right boundary are reached or the statistics of the upward trend exceed the preset number of times. Here, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, a statistics of the upward trend is performed. In some embodiments, the preset number of times is 3-7 times. Exemplarily, the preset number of times can be 3, 5 or 7 times. It should be noted that the positions of step S113 and step S114 can be interchanged. The second step size can be a smaller step size. In some embodiments, the second step size can be 2DAC-4DAC. Exemplarily, the second step size can be 2DAC, 3DAC or 4DAC.

[0176] When the searches in step S113 and step S114 satisfy the aforementioned conditions (reaching the boundary or the statistics showing an upward trend exceed the preset number of times), step S115 is executed.

[0177] In step S115, the adjusted target read voltage corresponding to the minimum first result is used as the target valley voltage. After step S115, step S116 is executed.

[0178] In step S116, it is determined whether the target valley voltage is valid. The method for determining whether the target valley voltage is valid may be to read data using the target valley voltage and decode the read data via the memory controller. Successful decoding indicates whether the target valley voltage is valid. If the result of step S116 is yes, step S121 is executed; if the result of step S116 is no, step S117 is executed.

[0179] In step S117, it is determined whether the loop has ended. If the determination result of step S117 is yes, step S119 is executed; if the determination result of step S117 is no, step S118 is executed.

[0180] In step S118, the process enters the next loop and continues searching. Step S118 jumps to step S107.

[0181] In step S119, it is determined whether the target order is a high order. If the determination result of step S119 is yes, step S120 is executed; if the determination result of step S119 is no, step S121 is executed.

[0182] In step S120, the predicted valley voltage of the lower order is obtained based on the target valley voltage / predicted valley voltage of the higher order. Here, the predicted valley voltage of the lower order can be obtained using the target valley voltage / predicted valley voltage of the higher order, the order of the lower order, and a related mapping function (such as the third mapping function described above). Step S121 is executed after step S120.

[0183] In step S121, it is determined whether the corresponding target valley voltages have been determined for all the read voltage levels included in the page. If the determination result in step S121 is yes, it means that the target valley voltages corresponding to all the read voltage levels included in the page have been determined, and step S123 can be executed. If the determination result in step S121 is no, it means that the target valley voltages corresponding to all the read voltage levels included in the page have not yet been determined, and step S122 can be executed.

[0184] In step S122, for the steps for which the target valley voltage has not been determined, the target valley voltage of each step is determined in sequence. Step S122 jumps to step S102.

[0185] In step S123 , the process of obtaining the target valley voltage is terminated. It should be noted that after step S123 , the target valley voltages corresponding to the read voltages of all steps of the next page can be determined.

[0186] FIG14 is a second flowchart of the operating method of the memory device provided in one embodiment of the present application. The detailed process of determining the target valley voltage will be described in detail below with reference to FIG14.

[0187] In step S201, the target valley voltage acquisition procedure is triggered, and the target valley voltage acquisition process is started. Next, step S202 is executed.

[0188] In step S202, in some embodiments, the memory device is set to a single-level read mode (SLR). Here, the SLR mode includes reading at least one bit of data stored in the memory cell using a single-level read voltage. Next, step S203 is executed.

[0189] As previously mentioned, since the memory cell has multiple storage bits, the multiple storage bits correspond to multiple pages, and at least one page corresponds to multiple levels. When determining the target valley voltage, the target valley voltage for each level of the at least one level of read voltage corresponding to each of the multiple pages is determined sequentially. In step S203, one level is selected from the multiple levels corresponding to a page as the target level, and the target read voltage corresponding to the target level read voltage is first determined. For example, using TLC as an example, the target valley voltages for the first level read voltage L1 and the fifth level read voltage L5 corresponding to the next page are first determined. Either L1 or L5 can be selected as the target level. After the target level is determined, step S204 is executed.

[0190] In step S204, the main task is to determine the type of the target order. Here, the target order can be divided into two categories, the first order (also called high order) and the second order (also called low order), wherein the read voltage of the first order is greater than the read voltage of the second order. For example, still taking the lower page of TLC as an example, L5 is the first order and L1 is the second order. If L1 is selected as the target order in step S203, the target order is the second order, that is, the low order; if L5 is selected as the target order in step S204, the target order is the first order, that is, the high order. According to the target order being the low order, execute step S205; according to the target order being the high order, execute step S207.

[0191] In step S205, a predicted valley voltage is obtained. Here, the predicted valley voltage is obtained by deriving the predicted valley voltage corresponding to the lower order based on the target valley voltage corresponding to the higher order and a related mapping function. Here and below, the related mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. Next, step S206 is executed.

[0192] In step S206, it is determined whether the two-step prediction is successful. Here, the so-called two-step prediction may include a first prediction and a second prediction. The first prediction is to obtain a high-order predicted valley voltage. Specifically, the high-order predicted valley voltage is obtained based on the first result corresponding to the target read voltage (default read voltage), the order of the high-order, and the fourth mapping function. The second prediction is to obtain a low-order predicted valley voltage. Specifically, the low-order predicted valley voltage is obtained based on the high-order predicted valley voltage, the order of the low-order, and the third mapping function. After the two-step prediction, the predicted valley voltage is not confirmed. Hard decoding is directly performed using the high-order predicted valley voltage and the low-order predicted valley voltage. If the hard decoding is successful, the two-step prediction is successful. At this time, the search for the target valley voltage is stopped and step S245 is executed. If the hard decoding fails, the two-step prediction fails. At this time, the point corresponding to the predicted valley voltage is used as the near-valley point for the subsequent iteration, and step S220 is continued. Step S220 will be described in detail in the subsequent description.

[0193] It should be noted that if the hard decoding fails, it means that the two-step prediction is unsuccessful. At this time, it is necessary to determine the target valley voltage through searching or also called looping (or iteration). Therefore, when the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the search process can be directly executed from the beginning of the loop, that is, jumping from step S206 to S208; or the point corresponding to the predicted valley voltage can be directly used as the near-valley point of the subsequent iteration, that is, jumping from step S206 (S219) to S220.

[0194] If the target level is high, a search or loop is performed to determine the target valley voltage for the high level. In step S207, a default read voltage is used as the target read voltage. Here, the target read voltage can serve as the initial value for subsequent searches or loops. In some implementations, the default read voltage can be the read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage corresponding to a write operation, in which case the corresponding offset value is 0 DAC. Step S208 is executed after step S207.

[0195] In step S208, the target valley voltage is determined by searching or looping. After step S208, step S209 is executed.

[0196] During the first execution of the loop, step S209 is to obtain the first result at the target read voltage. It is understood that during subsequent execution of the loop, step S209 is to obtain the first result at the adjusted target read voltage. Step S210 is executed after step S209.

[0197] In step S210, various parameters are determined or adjusted based on the first result under the target read voltage. Here, the various parameters may include at least a first threshold, a first boundary voltage (the position corresponding to the first boundary voltage is also called the left boundary) and a second boundary voltage (the position corresponding to the second boundary voltage is also called the right boundary). It is understandable that when performing a read operation, the further the threshold voltage of the memory cell shifts compared to the threshold voltage during writing, the larger the first result read using the target read voltage will generally be. Based on this, the specific value of the first result under the default read voltage can be used to confirm the first threshold value. The first threshold value is used to characterize the change (lift) in the valley voltage caused by the shift of the threshold voltage of the memory cell. Here, the initial first boundary voltage and the initial second boundary voltage can be set based on empirical values, such as initially setting an initial first boundary voltage and an initial second boundary voltage with a relatively large range. Then, based on the first result under the target read voltage, the initial first boundary voltage and the initial second boundary voltage are adjusted, such as narrowing the range of the first boundary voltage and the second boundary voltage to obtain the first boundary voltage and the second boundary voltage. Step S211 is performed after step S210.

[0198] It should be noted that step S210 is mainly for the first execution cycle process, and can be skipped for subsequent execution cycles.

[0199] During the first execution of the loop, step S211 determines whether the first result at the target read voltage is less than the first threshold. It is understood that during subsequent executions of the loop, step S211 determines whether the first result at the adjusted target read voltage is less than the first threshold. If the determination result in step S211 is yes, it can be assumed that the first result corresponding to the adjusted target read voltage basically meets the requirements for read data decoding. The process then jumps to step S242, terminating the loop and outputting the corresponding target valley voltage. If the determination result in step S211 is no, the loop continues to step S212.

[0200] In step S212, it is determined whether the target memory block is a partially written memory block. Here, the target memory block is the memory block where at least one codeword to be read is located. A partially written memory block includes a memory block that has both a programmed state and an erased state. If the result of step S212 is yes, step S213 is executed; if the result of step S212 is no, step S214 is executed.

[0201] It should be noted that step S212 is mainly for the first execution of the loop process, and for subsequent execution of the loop process, this step can be skipped. After skipping this step, step S214 is continued.

[0202] In step S213, considering that the offset of the threshold voltage of the storage cell in the underfilled storage block is more complex than the offset of the threshold voltage of the storage cell in the filled storage block (the filled storage block can be understood as a storage block with a write time difference less than a preset time length in the same application scenario as the underfilled storage block), the offset of the threshold voltage of the storage cell in the underfilled storage block is also related to the position of the first blank physical page in the underfilled storage block (the first blank physical page can be understood as the physical page in which the first data state appearing in the underfilled storage block is all erased according to the programming order) and the position of the physical page to be read (the physical page where the at least one codeword to be read is located). Based on this, the predicted valley voltage can be obtained based on the first offset corresponding to the filled storage block, the second offset corresponding to the position of the first blank physical page in the underfilled storage block, and the third offset corresponding to the position of the physical page to be read, and then the process proceeds to step S214. It is understandable that the obtained predicted valley voltage is more targeted than blindly adjusting the target read voltage, and can shorten the search time to a certain extent and determine the target valley voltage more quickly.

[0203] In step S214, determine whether a near-valley point is found. Here, the target read voltage after each adjustment is used as the horizontal coordinate, and the first result corresponding to the corresponding adjusted target read voltage is used as the vertical coordinate, and the horizontal and vertical coordinates will form a point. In the process of adjusting the target read voltage multiple times, the point corresponding to the multiple first results corresponding to the multiple adjusted target read voltages that is first less than the near-valley threshold can be used as the near-valley point. The near-valley threshold is used to characterize the maximum value of the first result corresponding to the voltage close to the bottom of the valley. It should be noted that the near-valley threshold is different from the aforementioned first threshold. When the first result is less than the near-valley threshold, it means that a more refined search can be carried out next; when the first result is less than the first threshold, it means that the search can be stopped next. When the judgment result of step S214 is yes, execute step S219; when the judgment result of step S214 is no, execute step S215.

[0204] If no near-valley point is found in step S215, the process proceeds to step S215, where the predicted read voltage after the next adjustment is obtained based on the first result corresponding to the target read voltage after the previous adjustment and the related mapping function (such as the aforementioned second mapping function). That is, the prediction is iterated using the aforementioned prediction formula or mapping function. After step S215, step S216 is executed.

[0205] In step S216, a determination is made as to whether the next adjusted predicted read voltage hits a boundary. The boundary here can be either the left boundary or the right boundary, and hitting the boundary can be understood as being exactly on the boundary or crossing the boundary. If the determination result in step S216 is yes, step S217 is executed; if the determination result in step S216 is no, step S218 is executed.

[0206] In step S217, the adjustment direction is changed. There are two adjustment directions for adjusting the target read voltage: positive (rightward) and negative (leftward). Adjusting the offset direction can be understood as: previously adjusting to the right, then adjusting to the left after hitting the right boundary; or previously adjusting to the left, then adjusting to the right after hitting the left boundary. After step S217, step S218 is executed.

[0207] In step S218, the first result of the adjusted target read voltage is obtained. After step S218, step S214 is executed. That is, after each target voltage adjustment and the corresponding first result is obtained, a determination is made as to whether the latest adjustment point is a near-valley point. One or more adjustments are performed until a near-valley point is found.

[0208] It should be noted that if the next cycle is entered after the step of finding the near valley point because the subsequent conditions are not met, steps S215 to S218 can be skipped.

[0209] In step S219, you can refer to the description in step S206. When the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the point corresponding to the predicted valley bottom voltage can be directly used as the near-valley point of the subsequent iteration, that is, jump from step S219 to S220.

[0210] In step S220, it is determined whether the predicted valley voltage at the current point (the latest adjusted target read voltage) is valid. In some embodiments, the predicted valley voltage can be determined to be valid by the first result corresponding to the latest adjusted target read voltage being less than the first threshold. It should be noted that although in step S211, when the first result under the (adjusted) target read voltage is not less than the first threshold, S212 and subsequent steps are entered, but before the judgment result of step S214 is yes, the target read voltage is adjusted at least once, so the new adjusted target read voltage may be less than the first threshold at this time. When the judgment result of step S220 is yes, step S224 is executed; when the judgment result of step S220 is no, step S221 is executed.

[0211] In step S221, a determination is made as to whether the first result fbc of the current point is greater than the fbc of the previous point. After finding the near-valley point, a rough search for an inflection point begins to the left. Generally, the magnitude of fbc decreases and then increases. When the first result fbc of the current point is greater than the fbc of the previous point, this indicates that fbc will increase further during the subsequent leftward adjustment, and the previous point was a relatively small point. In this case, the previous point is set as the inflection point. In some embodiments, the step size used for the rough search can be a larger step size, for example, 5DAC-15DAC, or more specifically, 5DAC, 10DAC, or 15DAC. Based on this, if the determination result of step S221 is yes, step S223 is executed; if the determination result of step S221 is no, step S222 is executed.

[0212] In step S222, a rough search is performed to the left starting from the point near the valley, and each search is compared with the fbc of the previous search until a point is found where the value stops decreasing and starts increasing. Once this point is found, step S222 is completed and the process goes to step S223.

[0213] In step S223, the previous point (i.e., the point where the decrease stops and the increase begins) is set as the inflection point, and a fine search is performed to the right starting from the inflection point. In some embodiments, the step size used in the fine search can be a smaller step size, for example, 1DAC-4DAC, more specifically, 2DAC or 3DAC. After step S223, step S225 is executed.

[0214] In step S224, the current point is set as the inflection point, and a fine search is started from the inflection point to the right. In some embodiments, the step size used in the fine search can refer to step S223. After step S224, step S225 is executed.

[0215] In step S225 , it is determined whether the target read voltage is adjusted to the left. If the determination result of step S225 is yes, step S229 is executed; if the determination result of step S225 is no, step S226 is executed.

[0216] In step S226, the target read voltage is adjusted rightward. During the adjustment, a determination is made as to whether the right boundary is hit or whether the rise count (also known as an upward trend count, where an upward trend count is performed when the first result corresponding to the next adjusted target read voltage is greater than the first result corresponding to the previous adjusted target read voltage) exceeds a preset number TH2. In some embodiments, the preset number is 3-7 times, and illustratively, the preset number can be 3, 5, or 7 times. If the determination in step S226 is yes, step S228 is executed; if the determination in step S226 is no, step S227 is executed.

[0217] In step S227, if the right boundary is not hit or the lift count does not exceed the preset number TH2, the search continues to the right boundary, and a judgment is made after each search until the right boundary is hit or the lift count exceeds the preset number TH2. In other words, when step S227 is completed, jump to step S228.

[0218] In step S228 , the target read voltage starts to be adjusted leftward.

[0219] In step S229, while adjusting the target read voltage to the left, it is determined whether the left boundary or lift count is hit. The lift count here can be understood with reference to the aforementioned step S226. The thresholds for the left and right lift counts are generally set to the same value. If the judgment result of step S229 is yes, step S231 is executed; if the judgment result of step S229 is no, step S230 is executed.

[0220] In step S230, if the left boundary is not hit or the lift count does not exceed the preset number TH2, the search continues to the left boundary, and a judgment is made after each search until the left boundary is hit or the lift count exceeds the preset number TH2. That is, when step S230 is completed, jump to step S231.

[0221] In step S231, a determination is made as to whether the most recent first result is the minimum. Here, the most recent first result refers to whether the first result at the adjusted target read voltage after the last target read voltage adjustment is the minimum. At this point, it is necessary to traverse all search points in at least this loop to find the adjusted target read voltage corresponding to the point with the minimum first result. If the determination result in step S231 is yes, step S233 is executed; if the determination result in step S231 is no, step S232 is executed.

[0222] In step S232, the latest first result is updated using the found minimum first result. Step S233 is executed after step S232.

[0223] In step S233, a determination is made as to whether the near-valley count exceeds a preset number TH3. Here, the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as a reference value. If the number of remaining first results whose difference from the reference value is less than a second threshold (equivalent to the preset difference) is greater than a preset number, the search is stopped and the target read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage. In some embodiments, the second threshold (equivalent to the preset difference) and the preset number can be set together based on actual conditions. Generally, a slightly larger second threshold (equivalent to the preset difference) results in a relatively larger preset number; and a slightly smaller second threshold (equivalent to the preset difference) results in a relatively smaller preset number. If the determination result in step S233 is yes, the search is stopped and step S237 is executed. If the determination result in step S233 is no, the process proceeds to the next determination step, step S234.

[0224] In step S234, a determination is made as to whether the repeated valley count exceeds a preset count TH4. During multiple adjustments to the target read voltage, different adjustment methods may be employed. If the target read voltages corresponding to the different adjustment methods exceeding the preset count are the same, and the first result corresponding to the same target read voltage is the minimum value among all first results, the same target read voltage is used as the target valley voltage. In some embodiments, the preset count is 2-4, and illustratively, the preset count can be 2, 3, or 4. If the determination in step S234 is yes, the search stops and step S237 is executed. If the determination in step S234 is no, the process proceeds to the next determination step, step S235.

[0225] It should be noted that step S233 and step S234 belong to different judgment methods and their positions can be interchanged. In other words, the repeated valley count can be judged first, and then the approximate estimate can be judged when the repeated valley count does not meet the conditions. It is understandable that other judgments can also be performed here to determine whether the loop has ended.

[0226] In step S235, it is determined whether the loop has ended. If the determination result of step S235 is yes, step S237 is executed; if the determination result of step S235 is no, step S236 is executed.

[0227] In step S236, the process enters the next loop and continues searching. Step S236 jumps to step S209.

[0228] In step S237, the target step search is completed, and the adjusted target read voltage corresponding to the minimum first result is used as the target valley voltage. After step S237, step S238 is executed.

[0229] In step S238, it is determined whether the target order is a high order. If the determination result of step S238 is yes, step S239 is executed; if the determination result of step S238 is no, step S240 is executed.

[0230] In step S239, the predicted valley voltage of the low order is obtained based on the target valley voltage of the high order. Here, the predicted valley voltage of the low order can be obtained by using the target valley voltage of the high order, the order of the low order, and a related mapping function (such as the third mapping function described above). Step S240 is executed after step S239.

[0231] In step S240, it is determined whether the corresponding target valley voltages have been determined for all the read voltage levels included in the page. If the determination result in step S240 is yes, it means that the target valley voltages corresponding to all the read voltage levels included in the page have been determined, and step S242 can be executed. If the determination result in step S240 is no, it means that the target valley voltages corresponding to all the read voltage levels included in the page have not yet been determined, and step S241 can be executed.

[0232] In step S241, for the steps for which the target valley voltage has not been determined, the target valley voltage of each step is determined in sequence. Step S236 jumps to step S202.

[0233] In step S242 , the process of obtaining the target valley voltage is terminated. It should be noted that after step S242 , the target valley voltages corresponding to the read voltages of all steps of the next page can be determined.

[0234] It should be noted that the method disclosed in the embodiments of the present application can solve many problems existing in the reread operation, but it is not used to limit the application scenarios in the embodiments of the present application. The method disclosed in the embodiments of the present application is also applicable to conventional read operations.

[0235] It should be noted that the execution entity of the specific implementation process of each step in Figures 13 and 14 can be a peripheral circuit or a memory controller.

[0236] In a second aspect, an embodiment of the present application provides a memory system, as shown in Figures 15 and 16, the memory system 102 includes: one or more memory devices 104 as provided in the first aspect; and a memory controller 106, which is coupled to the memory device 104 and controls the memory device 104.

[0237] As shown in FIG15 , in some embodiments, a memory system 102 is coupled to a host, responds to host instructions, and performs various feedback operations. Memory system 102 may include a memory controller 106 and a memory device 104. Memory controller 106 is configured to control memory device 104 to perform operations such as read, write, and erase. Memory controller 106 and memory device 104 may also be coupled in any suitable manner.

[0238] The memory controller 106 may include a host interface (I / F) 1061, a memory interface (I / F) 1062, a control unit 1063, a read-only memory (ROM) 1069, a random access memory (RAM) 1070, an error correction module 1064, a garbage collection module 1065, a wear leveling module 1066, a data buffer 1067, and a bus 1060. The host interface 1061 is a connection interface between the host 108 and the memory controller 106. The host interface 1061 allows the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is a connection interface between the memory controller 106 and the memory device 104. The memory interface 1062 is used to implement data transmission between the memory controller 106 and the memory device 104. The control unit 1063 is used to control the memory system 106 as a whole. The specific steps executed by the memory controller described above are mainly executed and completed by the control unit 1063 here. In some specific embodiments, the control unit 1063 is, for example, a central processing unit (CPU), a microprocessor (MCU), etc. The ROM 1069 generally contains the firmware or firmware program code of the memory controller 106, which is used to initialize and operate the various components of the memory controller. The RAM 1070 is generally used to cache data. The error correction module 1064 can further include an encoding unit and a decoding unit; the encoding unit is used to encode the data to be stored to obtain check data, and the decoding unit is used to decode the check data to detect and correct possible erroneous data during data transmission.

[0239] The garbage collection module 1065 is used to read valid data from some storage blocks, rewrite it, and then mark these storage blocks as new backup storage blocks after the storage space of the memory device reaches a certain threshold. Garbage collection is generally implemented in three steps: selecting a source storage block with less valid data; finding valid data from the source storage block; and writing the valid data to the target storage block. At this point, all data in the source storage block becomes invalid data, and the source storage block is marked and can be used as a new backup storage block. The wear leveling module 1066 is used to maintain a balanced wear (number of erases) on each storage block in the memory system through data statistics and algorithms. Wear leveling is generally implemented in two steps: selecting a source storage block containing cold data; reading valid data from the source storage block and writing it to a storage block with a relatively high erase count. At this point, the valid data in the source storage block becomes invalid data and is marked. The buffer 1067 is used to cache data.

[0240] In some specific embodiments, the memory controller 106 is configured to control the memory device 104 to perform a read operation on at least one codeword.

[0241] In some specific embodiments, a memory device 104 includes: a memory cell array including a plurality of memory cells, wherein a predetermined number of memory cells form a codeword; a peripheral circuit of the memory device 104 coupled to the memory cell array and configured to: perform a first adjustment M times on a target read voltage of at least one codeword with a first step size, and obtain M first results corresponding to the M read voltages after the M first adjustments; the first result including a number of bits flipped in a read result of the at least one codeword at a first read voltage and a second read voltage, wherein the difference between the first read voltage and the second read voltage is less than a predetermined voltage; use a minimum first result among the M first results as a knee point value, and a read voltage corresponding to the knee point value as the knee point voltage; perform a second adjustment N times on the knee point voltage with a second step size, and obtain N first results corresponding to the N read voltages after the N second adjustments, wherein the second step size is less than the first step size; and determine a target valley voltage based on the obtained N first results, wherein the target valley voltage is used as a read voltage when performing a read operation on the at least one codeword; wherein M and N are both positive integers greater than 1.

[0242] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: determine a near-valley threshold value based on a first result corresponding to the at least one codeword at an initial target read voltage before performing M first adjustments on the target read voltage of the at least one codeword with a first step length, where the near-valley threshold value is used to represent the maximum value of the first result corresponding to a voltage close to the valley bottom; adjust the initial target read voltage multiple times before performing M first adjustments on the target read voltage of the at least one codeword with a first step length until the first result corresponding to the adjusted target read voltage is less than the near-valley threshold value; and use the adjusted target read voltage corresponding to the first result being less than the near-valley threshold value as the target read voltage, and perform M first adjustments on the target read voltage with the first step length.

[0243] In some specific embodiments, the peripheral circuit of the memory device 104 is configured as follows: before performing M first adjustments to the target read voltage of at least one codeword with a first step length, during a process of adjusting the initial target read voltage multiple times, according to the first result corresponding to the adjusted target read voltage being greater than or equal to the near-valley threshold, obtaining the next adjusted target read voltage based on the first result corresponding to the target read voltage after the previous adjustment; taking the adjusted target read voltage corresponding to the near-valley threshold for the first time that multiple first results corresponding to the adjusted target read voltage are less than the near-valley threshold as the near-valley point voltage; and during the process of performing M first adjustments to the target read voltage with a first step length, starting from the near-valley point voltage, adjusting in two opposite directions with the first step length until the first results corresponding to the adjusted read voltages in both directions are greater than the near-valley threshold.

[0244] In some specific embodiments, the peripheral circuits of the memory device 104 are configured to: in a process of performing M first adjustments on the near-valley voltage with a first step length, start from the near-valley voltage and adjust in a first direction with a first step length until a first result corresponding to the target read voltage after adjustment in the first direction is greater than a near-valley threshold; and start from the near-valley voltage and adjust in a second direction opposite to the first direction with a first step length until a first result corresponding to the target read voltage after adjustment in the second direction is greater than the near-valley threshold.

[0245] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: obtain a near-valley threshold value based on a first result corresponding to a target read voltage and a first mapping function; wherein the first mapping function is used to characterize the relationship between the near-valley threshold value and the first result corresponding to the target read voltage; obtain the target read voltage after the next adjustment based on the first result corresponding to the target read voltage after the last adjustment and the second mapping function; and the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage after the last adjustment and the predicted read voltage after the next adjustment.

[0246] In some specific embodiments, the peripheral circuit of the memory device 104 is configured as follows: in the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, adjustments are performed in two opposite directions with a second step size; in the process of adjusting in each direction, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, a statistical analysis showing an upward trend is performed, and the first boundary voltage and the second boundary voltage are determined based on the total statistical number being greater than or equal to a preset number; in the process of adjusting in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than a preset threshold, or the smallest first result among multiple first results corresponding to the target read voltage after multiple adjustments is used as a reference value, and when the number of the remaining multiple first results whose differences from the reference value are less than the preset difference is greater than a preset number, the adjustment is stopped and the adjusted target read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage.

[0247] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: during the process of performing N second adjustments to the knee point voltage with a second step size, start from the knee point voltage and adjust in the first direction with the second step size until the total statistical number of times the adjustment in the first direction shows an upward trend equals a preset number; start from the knee point voltage and adjust in a second direction opposite to the first direction with the second step size until the total statistical number of times the adjustment in the second direction shows an upward trend equals a preset number.

[0248] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: use the adjusted target read voltage corresponding to the total statistical number of times the upward trend is equal to a preset number during the adjustment in the first direction as the first boundary voltage, and use the adjusted target read voltage corresponding to the total statistical number of times the upward trend is equal to the preset number during the adjustment in the second direction as the second boundary voltage; in the process of adjusting in both directions, if the first boundary voltage and the second boundary voltage have been determined, obtain the first result corresponding to the last adjusted read voltage, and the last adjusted read voltage is the average of the first boundary voltage and the second boundary voltage; and use the read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted read voltages as the target valley voltage.

[0249] In some specific embodiments, the memory cell array includes memory cells having multiple storage bits; the multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple levels; and the peripheral circuit of the memory device 104 is configured to: after determining a target valley voltage of at least one codeword in a target level, determine the target valley voltages of the other levels in the multiple levels except the target level.

[0250] In some specific embodiments, the multiple stages include a first stage and a second stage, and the read voltage of the second stage is lower than the read voltage of the first stage; the peripheral circuit of the memory device 104 is configured to: when the stage corresponding to the determined target valley voltage belongs to the first stage, obtain the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower read voltages based on the determined target valley voltage.

[0251] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: read the stored data of at least one codeword at a first read voltage to obtain a second result; perform a third adjustment on the first read voltage with a third step size to obtain a second read voltage, and read the stored data of at least one codeword at the second read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count the number of bits in the fourth result indicating that the third result is flipped compared to the second result to obtain the first result.

[0252] In some specific embodiments, the peripheral circuit of the memory device 104 includes: a first latch, a second latch, and a third latch; the first latch is configured to store the second result; the second latch is configured to store the third result; and the third latch is configured to store the fourth result.

[0253] In some embodiments, the memory controller 106 is configured to: send a data acquisition instruction, the data acquisition instruction instructing to obtain the valley voltage; the memory device 104 is configured to: receive the data acquisition instruction, obtain the valley voltage, and send information including the valley voltage to the memory controller 106; the memory controller 106 is further configured to: perform a read operation on the data stored in the memory device 104 according to the valley voltage in the information.

[0254] In some embodiments, the memory controller 106 is further configured to perform an error correction code decoding operation on the read result of the read operation. In some implementations, the error correction code decoding operation includes a hard decoding operation using a low density parity check code (LDPC).

[0255] In some embodiments, the memory controller 106 is configured to: send a mode setting command, the mode setting command indicating that the read mode of the memory device is set to a single-level read mode; the single-level read mode includes reading at least one bit of storage data stored in the memory cell through a first-level read voltage; the memory device 104 is configured to: enter the single-level read mode in response to the mode setting command, and, in the single-level read mode, obtain a first result corresponding to at least one codeword at a target read voltage.

[0256] On the second aspect, in each memory system provided by the embodiments of the present application, the first result is transmitted (the size of the first result can be several bytes) without transmitting at least one codeword (for example, the size of the codeword can be 4KB), the amount of data transmitted is reduced, and the transmission time of the output port is reduced; the process of obtaining the first result is converged inside the memory device, does not occupy the space of, for example, the memory controller, and has a low degree of dependence on, for example, the memory controller. At the same time, in the embodiments of the present application, during the adjustment process, a coarse-first-then-fine adjustment is performed, that is, a large-step adjustment (first adjustment) is performed first, and then a small-step adjustment (second adjustment) is performed. In this way, over-adjustment can be avoided during the adjustment process, thereby reducing the number of loop iterations and determining the target valley voltage more quickly. In addition, in the embodiments of the present application, during the small-step adjustment process, statistics of points that are on an upward trend compared to the previous adjustment are introduced. The statistics can filter out points that are on a downward trend compared to the previous adjustment, eliminate the influence of noise points, and thus more accurately find the valley point.

[0257] In a third aspect, an embodiment of the present application provides a memory controller coupled to at least one memory device, the memory device including a plurality of memory cells, a preset number of the memory cells forming a codeword; the memory controller including: a control unit configured to: perform M first adjustments on a target read voltage of at least one of the codewords with a first step length, and respectively obtain M first results corresponding to the M read voltages after the M first adjustments; the first result including a representation of the number of bits flipped in two read results of at least one of the codewords at the first read voltage and the second read voltage; the first result including a representation of the number of bits flipped in two read results of the at least one codeword ... The difference between the first read voltage and the second read voltage is less than a preset voltage; the smallest first result among the M first results is used as the inflection point value, and the read voltage corresponding to the inflection point value is the inflection point voltage; the inflection point voltage is second-adjusted N times with a second step size, and N first results corresponding to the N read voltages after the N second adjustments are respectively obtained; the second step size is smaller than the first step size; and a target valley voltage is determined based on the N first results obtained; the target valley voltage is used as the read voltage when performing a read operation on at least one of the codewords; wherein, M and N are both positive integers greater than 1.

[0258] In some specific embodiments, the control unit is configured to: determine a near-valley threshold value based on a first result corresponding to the at least one codeword at the initial target read voltage before performing M first adjustments to the target read voltage of at least one codeword with the first step length, the near-valley threshold value being used to characterize the maximum value of the first result corresponding to a voltage close to the valley bottom; adjust the initial target read voltage multiple times before performing M first adjustments to the target read voltage of at least one codeword with the first step length until the first result corresponding to the adjusted target read voltage is less than the near-valley threshold value; use the adjusted target read voltage corresponding to the first result being less than the near-valley threshold value as the target read voltage, and perform M first adjustments to the target read voltage with the first step length.

[0259] In some specific embodiments, the control unit is configured to: before performing M first adjustments to the target read voltage of at least one codeword with a first step length, in a process of adjusting the initial target read voltage multiple times, according to the first result corresponding to the adjusted target read voltage being greater than or equal to the near-valley threshold, obtain the next adjusted target read voltage based on the first result corresponding to the target read voltage after the last adjustment; take the adjusted target read voltage corresponding to the near-valley threshold for the first time when multiple first results corresponding to the adjusted target read voltage are less than the adjusted target read voltage as the near-valley point voltage; in the process of performing M first adjustments to the target read voltage with a first step length, starting from the near-valley point voltage, adjust in two opposite directions with the first step length until the first results corresponding to the adjusted read voltages in the two directions are both greater than the near-valley threshold.

[0260] In some specific embodiments, the control unit is configured to: in the process of performing M first adjustments on the near-valley point voltage with a first step length, start from the near-valley point voltage and adjust in a first direction with a first step length until a first result corresponding to the target read voltage after adjustment in the first direction is greater than a near-valley threshold; start from the near-valley point voltage and adjust in a second direction opposite to the first direction with a first step length until a first result corresponding to the target read voltage after adjustment in the second direction is greater than the near-valley threshold.

[0261] In some specific embodiments, the control unit is configured to: obtain a near-valley threshold value based on a first result corresponding to the target read voltage and a first mapping function; wherein the first mapping function is used to characterize the relationship between the near-valley threshold value and the first result corresponding to the target read voltage; obtain the target read voltage after the next adjustment based on the first result corresponding to the target read voltage after the last adjustment and the second mapping function; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage after the last adjustment and the predicted read voltage after the next adjustment.

[0262] In some specific embodiments, the control unit is configured to: in the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, adjust in two opposite directions with a second step size respectively; in the process of adjusting in each direction, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, perform a statistical analysis showing an upward trend, and determine the first boundary voltage and the second boundary voltage based on the total statistical number being greater than or equal to a preset number; in the process of adjusting in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than a preset threshold, or the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as a reference value, when the number of the remaining multiple first results whose differences from the reference value are less than the preset difference is greater than a preset number, stop the adjustment and use the adjusted target read voltage corresponding to the smallest first result among the multiple first results as the target valley voltage.

[0263] In some specific embodiments, the control unit is configured to: in the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, adjust in the first direction with a second step size until the total statistical number of times the upward trend is shown during the adjustment process in the first direction is equal to a preset number; starting from the inflection point voltage, adjust in a second direction opposite to the first direction with a second step size until the total statistical number of times the upward trend is shown during the adjustment process in the second direction is equal to a preset number.

[0264] In some specific embodiments, the control unit is configured to: use the adjusted target read voltage corresponding to the total statistical number of times the upward trend is equal to the preset number during the adjustment process in the first direction as the first boundary voltage, and use the adjusted target read voltage corresponding to the total statistical number of times the upward trend is equal to the preset number during the adjustment process in the second direction as the second boundary voltage; in the process of adjusting in both directions, if the first boundary voltage and the second boundary voltage have been determined, obtain the first result corresponding to the last adjusted read voltage, and the last adjusted read voltage is the average of the first boundary voltage and the second boundary voltage; and use the read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted read voltages as the target valley voltage.

[0265] In some specific embodiments, the memory cell array includes memory cells having multiple storage bits; the multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple levels; and the control unit is configured to: after determining a target valley voltage of at least one codeword in a target level, determine the target valley voltages of other levels in the multiple levels except the target level.

[0266] In some specific embodiments, the multiple stages include a first stage and a second stage, and the read voltage of the second stage is lower than the read voltage of the first stage; the control unit is configured to: when the stage corresponding to the determined target valley voltage belongs to the first stage, obtain the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower read voltages according to the determined target valley voltage.

[0267] Here, the term "control unit" can be understood in conjunction with the control unit shown in FIG15 . It should be noted that in this embodiment of the present application, the execution subject is replaced by the control unit in the memory controller instead of the aforementioned peripheral circuit. That is, in this embodiment of the present application, the memory device obtains at least one first result; the control unit simultaneously analyzes and processes the at least one first result and determines the target valley voltage based on the analysis and processing.

[0268] It should be noted that the execution subject of the specific implementation process of the aforementioned Figures 13 and 14 can be the control unit in the memory control.

[0269] On the third aspect, in the memory controller provided in the embodiment of the present application, the first result is transmitted (the size of the first result can be several bytes) without transmitting at least one codeword (for example, the size of the codeword can be 4KB), the amount of data transmitted is reduced, and the transmission time of the output port is reduced; the process of obtaining the first result is converged inside the memory device, does not occupy the space of, for example, the memory controller, and has a low degree of dependence on, for example, the memory controller. At the same time, in the embodiment of the present application, during the adjustment process, a coarse-first-then-fine adjustment is performed, that is, a large-step adjustment (first adjustment) is performed first, and then a small-step adjustment (second adjustment) is performed. In this way, over-adjustment can be avoided during the adjustment process, thereby reducing the number of loop iterations and determining the target valley voltage more quickly. In addition, in the embodiment of the present application, during the small-step adjustment process, statistics of points that are on an upward trend compared to the previous adjustment are introduced. The statistics can filter out points that are on a downward trend compared to the previous adjustment, eliminate the influence of noise points, and thus more accurately find the valley point.

[0270] In a fourth aspect, an embodiment of the present application provides an operating method for a memory device, comprising: performing M first adjustments on a target read voltage of at least one codeword with a first step length, and respectively obtaining M first results corresponding to the M read voltages after the M first adjustments; the first result includes the number of bits flipped in two read results at a first read voltage and a second read voltage representing a codeword formed by a preset number of storage cells in at least one memory device, and the difference between the first read voltage and the second read voltage is less than a preset voltage; taking the smallest first result among the M first results as an inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; performing N second adjustments on the inflection point voltage with a second step length, and respectively obtaining N first results corresponding to the N read voltages after the N second adjustments; the second step length is smaller than the first step length; and determining a target valley voltage based on the obtained N first results, the target valley voltage being used as the read voltage when performing a read operation on at least one codeword; wherein M and N are both positive integers greater than 1.

[0271] In some specific embodiments, a method for operating a memory device includes: determining a near-valley threshold value based on a first result corresponding to the at least one codeword at an initial target read voltage before performing M first adjustments on the target read voltage of at least one codeword with a first step length, the near-valley threshold value being used to represent a maximum value of the first result corresponding to a voltage close to a valley bottom; adjusting the initial target read voltage multiple times until the first result corresponding to the adjusted target read voltage is less than the near-valley threshold value before performing M first adjustments on the target read voltage of the at least one codeword with the first step length; and using the adjusted target read voltage corresponding to the first result being less than the near-valley threshold value as the target read voltage, and performing M first adjustments on the target read voltage with the first step length.

[0272] In some specific embodiments, a method for operating a memory device includes: before performing M first adjustments on a target read voltage of at least one codeword with a first step length, during a process of adjusting an initial target read voltage multiple times, obtaining a next adjusted target read voltage based on the first result corresponding to the target read voltage after the previous adjustment, according to the first result corresponding to the adjusted target read voltage being greater than or equal to a near-valley threshold; taking the adjusted target read voltage corresponding to the near-valley threshold when multiple first results corresponding to the adjusted target read voltage are first less than the adjusted target read voltage as a near-valley point voltage; and during a process of performing M first adjustments on the target read voltage with a first step length, starting from the near-valley point voltage, adjusting in two opposite directions with the first step length until the first results corresponding to the adjusted read voltages in both directions are greater than the near-valley threshold.

[0273] In some specific embodiments, a method for operating a memory device includes: in a process of performing M first adjustments on a near-valley voltage with a first step length, starting from the near-valley voltage, adjusting in a first direction with the first step length until a first result corresponding to a target read voltage adjusted in the first direction is greater than a near-valley threshold; and starting from the near-valley voltage, adjusting in a second direction opposite to the first direction with the first step length until a first result corresponding to the target read voltage adjusted in the second direction is greater than the near-valley threshold.

[0274] In some specific embodiments, a method for operating a memory device includes: obtaining a near-valley threshold value based on a first result corresponding to a target read voltage and a first mapping function; wherein the first mapping function is used to characterize the relationship between the near-valley threshold value and the first result corresponding to the target read voltage; obtaining a target read voltage after the next adjustment based on the first result corresponding to the target read voltage after the last adjustment and a second mapping function; and the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage after the last adjustment and the predicted read voltage after the next adjustment.

[0275] In some specific embodiments, the operating method of the memory device includes: in the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, adjusting in two opposite directions with a second step size, and in the process of adjusting in each direction, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, performing a statistical analysis showing an upward trend, and determining the first boundary voltage and the second boundary voltage based on the total statistical number being greater than or equal to a preset number; in the process of adjusting in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than a preset threshold, or the smallest first result among multiple first results corresponding to the target read voltage after multiple adjustments is used as a reference value, when the number of remaining multiple first results whose differences from the reference value are less than the preset difference is greater than a preset number, stopping the adjustment and using the adjusted target read voltage corresponding to the smallest first result among the multiple first results as the target valley voltage.

[0276] In some specific embodiments, a method for operating a memory device includes: during a second adjustment of the knee point voltage N times with a second step size, starting from the knee point voltage, adjusting in a first direction with the second step size until a total statistical number of upward trends during the adjustment process in the first direction equals a preset number; and starting from the knee point voltage, adjusting in a second direction opposite to the first direction with the second step size until a total statistical number of upward trends during the adjustment process in the second direction equals a preset number.

[0277] In some specific embodiments, the operating method of the memory device includes: using the adjusted target read voltage corresponding to the total statistical number of times the upward trend is equal to a preset number during the adjustment in the first direction as the first boundary voltage, and using the adjusted target read voltage corresponding to the total statistical number of times the upward trend is equal to the preset number during the adjustment in the second direction as the second boundary voltage; in the process of adjusting in both directions, if the first boundary voltage and the second boundary voltage have been determined, obtaining the first result corresponding to the last adjusted read voltage, the last adjusted read voltage being the average of the first boundary voltage and the second boundary voltage; and using the read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted read voltages as the target valley voltage.

[0278] In some specific embodiments, a memory cell array includes memory cells having multiple storage bits; the multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple levels; and an operating method of the memory device includes: after determining a target valley voltage of at least one codeword at a target level, determining target valley voltages of other levels in the multiple levels except the target level.

[0279] In some specific embodiments, the multiple stages include a first stage and a second stage, and a read voltage of the second stage is lower than a read voltage of the first stage; the operating method of the memory device includes: when the stage corresponding to the determined target valley voltage belongs to the first stage, obtaining a predicted valley voltage of the second stage in the multiple stages and / or predicted valley voltages of the remaining first stages with lower read voltages based on the determined target valley voltage.

[0280] In some specific embodiments, a method for operating a memory device includes: reading stored data of at least one codeword at a first read voltage to obtain a second result; performing a third adjustment on the first read voltage with a third step size to obtain a second read voltage, and reading stored data of at least one codeword at the second read voltage to obtain a third result; performing a logical operation on the second result and the third result to obtain a fourth result; and counting the number of bits in the fourth result indicating that the third result is flipped compared to the second result to obtain the first result.

[0281] In some specific embodiments, a method for operating a memory device includes: a first latch, a second latch, and a third latch; the first latch is configured to store a second result; the second latch is configured to store a third result; and the third latch is configured to store a fourth result.

[0282] In a fifth aspect, an embodiment of the present application provides an operating method for a memory system, comprising: a memory controller in the memory system sends a data acquisition instruction, the data acquisition instruction instructing to obtain a valley voltage; a memory device in the memory system receives the data acquisition instruction, obtains the valley voltage according to the operating method of the memory device of the fourth aspect, and sends information including the valley voltage to the memory controller; the memory controller performs a read operation on the data stored in the memory device according to the valley voltage in the information.

[0283] In some specific embodiments, a memory device in a memory system includes: a memory cell array including a plurality of memory cells, wherein a predetermined number of the memory cells form a codeword; and an operating method of the memory system including: performing a first adjustment M times on a target read voltage of at least one of the codewords with a first step size, and obtaining M first results corresponding to the M read voltages after the M first adjustments; the first result including a number of bits flipped in a read result representing at least one of the codewords at a first read voltage and a second read voltage, wherein the difference between the first read voltage and the second read voltage is less than a predetermined voltage; using a minimum first result among the M first results as an inflection point value, and a read voltage corresponding to the inflection point value as the inflection point voltage; performing a second adjustment N times on the inflection point voltage with a second step size, and obtaining N first results corresponding to the N read voltages after the N second adjustments, wherein the second step size is less than the first step size; and determining a target valley voltage based on the obtained N first results, wherein the target valley voltage is used as a read voltage when performing a read operation on the at least one of the codewords; wherein both M and N are positive integers greater than 1.

[0284] In a sixth aspect, an embodiment of the present application provides an operating method of a memory controller, comprising: performing M first adjustments on a target read voltage of at least one codeword with a first step length, and respectively obtaining M first results corresponding to the M read voltages after the M first adjustments; the first result includes the number of bits flipped in two read results under the first read voltage and the second read voltage of a codeword formed by a preset number of storage cells in at least one memory device, and the difference between the first read voltage and the second read voltage is less than the preset voltage; taking the smallest first result among the M first results as the inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; performing N second adjustments on the inflection point voltage with a second step length, and respectively obtaining N first results corresponding to the N read voltages after the N second adjustments; the second step length is smaller than the first step length; and determining a target valley voltage based on the N first results obtained, the target valley voltage being used as the read voltage when performing a read operation on at least one codeword; wherein M and N are both positive integers greater than 1.

[0285] In some specific embodiments, a method for operating a memory controller of a memory device includes: determining a near-valley threshold value based on a first result corresponding to the at least one codeword at an initial target read voltage before performing M first adjustments on a target read voltage of at least one codeword with a first step length, the near-valley threshold value being used to characterize a maximum value of the first result corresponding to a voltage close to a valley bottom; adjusting the initial target read voltage multiple times until the first result corresponding to the adjusted target read voltage is less than the near-valley threshold value before performing M first adjustments on the target read voltage of the at least one codeword with a first step length; and using the adjusted target read voltage corresponding to the first result being less than the near-valley threshold value as the target read voltage, and performing M first adjustments on the target read voltage with the first step length.

[0286] In some specific embodiments, a method for operating a memory controller of a memory device includes: before performing M first adjustments to a target read voltage of at least one codeword with a first step length, in a process of adjusting an initial target read voltage multiple times, obtaining a next adjusted target read voltage based on the first result corresponding to the target read voltage after the previous adjustment according to the first result corresponding to the adjusted target read voltage being greater than or equal to a near-valley threshold; taking the adjusted target read voltage corresponding to the near-valley threshold when multiple first results corresponding to the adjusted target read voltage are first less than the adjusted target read voltage as a near-valley point voltage; and in the process of performing M first adjustments to the target read voltage with a first step length, starting from the near-valley point voltage, adjusting in two opposite directions with the first step length until the first results corresponding to the adjusted read voltages in both directions are greater than the near-valley threshold.

[0287] In some specific embodiments, a method for operating a memory controller of a memory device includes: in a process of performing M first adjustments on a near-valley voltage with a first step length, starting from the near-valley voltage, adjusting in a first direction with a first step length until a first result corresponding to a target read voltage adjusted in the first direction is greater than a near-valley threshold; and starting from the near-valley voltage, adjusting in a second direction opposite to the first direction with a first step length until a first result corresponding to the target read voltage adjusted in the second direction is greater than the near-valley threshold.

[0288] In some specific embodiments, an operating method of a memory controller of a memory device includes: obtaining a near-valley threshold value based on a first result corresponding to a target read voltage and a first mapping function; wherein the first mapping function is used to characterize the relationship between the near-valley threshold value and the first result corresponding to the target read voltage; obtaining a target read voltage after next adjustment based on the first result corresponding to the target read voltage after the last adjustment and a second mapping function; and the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage after the last adjustment and the predicted read voltage after the next adjustment.

[0289] In some specific embodiments, an operating method of a memory controller of a memory device includes: in a process of performing N second adjustments on the knee point voltage with a second step size, starting from the knee point voltage, adjusting in two opposite directions with a second step size, and in the process of adjusting in each direction, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, performing a statistical analysis showing an upward trend, and determining a first boundary voltage and a second boundary voltage based on the total statistical number being greater than or equal to a preset number; in the process of adjusting in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than a preset threshold, or the smallest first result among multiple first results corresponding to the target read voltage after multiple adjustments is used as a reference value, and when the number of remaining multiple first results whose differences from the reference value are less than the preset difference is greater than a preset number, stopping the adjustment and using the adjusted target read voltage corresponding to the smallest first result among the multiple first results as the target valley voltage.

[0290] In some specific embodiments, a method for operating a memory controller of a memory device includes: in a process of performing N second adjustments to the knee point voltage with a second step size, starting from the knee point voltage, adjusting in a first direction with the second step size until a total statistical number of upward trends during the adjustment process in the first direction equals a preset number; and starting from the knee point voltage, adjusting in a second direction opposite to the first direction with the second step size until a total statistical number of upward trends during the adjustment process in the second direction equals a preset number.

[0291] In some specific embodiments, an operating method of a memory controller of a memory device includes: using an adjusted target read voltage corresponding to a total statistical number of times the upward trend is equal to a preset number during adjustment in a first direction as a first boundary voltage, and using an adjusted target read voltage corresponding to a total statistical number of times the upward trend is equal to a preset number during adjustment in a second direction as a second boundary voltage; in the process of adjustment in both directions, if the first boundary voltage and the second boundary voltage have been determined, obtaining a first result corresponding to the last adjusted read voltage, the last adjusted read voltage being an average of the first boundary voltage and the second boundary voltage; and using a read voltage corresponding to the smallest first result among multiple first results corresponding to all adjusted read voltages as a target valley voltage.

[0292] In some specific embodiments, a memory cell array includes memory cells having multiple storage bits; the multiple storage bits correspond to multiple pages; at least one page corresponds to multiple levels; and an operating method of a memory controller of a memory device includes: after determining a target valley voltage of at least one codeword at a target level, determining valley voltages of targets of other levels in the multiple levels except the target level.

[0293] In some specific embodiments, the multiple stages include a first stage and a second stage, and a read voltage of the second stage is lower than a read voltage of the first stage; the operating method of the memory controller of the memory device includes: when the stage corresponding to the determined target valley voltage belongs to the first stage, obtaining a predicted valley voltage of the second stage in the multiple stages and / or predicted valley voltages of the remaining first stages with lower read voltages based on the determined target valley voltage.

[0294] 17 is an exemplary timing diagram for starting a single-stage read mode operation provided by the present application. DQx can be represented as a data bus signal, and Cycle Type can further represent the type of the data bus signal.

[0295] As shown in FIG17 , the set function command may include, for example, a sub-command (e.g., EFh). Exemplarily, the memory device starts the single-level read mode upon receiving a sub-command EFh. In the single-level read mode, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1 to C2 and three row addresses R1 to R3) between the received sub-commands 00h and 30h. During the read time, the data DATA (e.g., Dn) corresponding to the page of the received address may be cached in the page buffer first, and then the data DATA may be read on demand. It should be noted that, in the above embodiment, when performing a reread operation, the memory device and the memory controller need to frequently transmit (Din / Dout) the data corresponding to a physical page (e.g., Dn), and the transmission of the data takes a long time.

[0296] Figure 18 is a timing diagram for determining a target valley voltage and performing a read operation according to an embodiment of the present application. As shown in Figure 18 , a read command may include, for example, two sub-commands (e.g., 00h and 30h). For example, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. After the memory device receives sub-command 30h, it may first cache the corresponding data DATA (e.g., Dn) in the page of the received address in a page buffer within the read time, and then read the data DATA on demand.

[0297] In an exemplary embodiment, the memory device 104 transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received subcommands 00h and 30h. After receiving subcommand 30h, the memory device 104 receives subcommands EFh and xxh of the data acquisition instruction. Under the instruction of the data acquisition instruction, the memory device 104 acquires the first result corresponding to the codeword at the corresponding read voltage and sends the acquired first result to the memory controller. The memory controller determines a target valley voltage based on the multiple first results corresponding to the multiple different read voltages received from the memory device and performs a read operation on the data stored in the memory device according to the target valley voltage.

[0298] It should be noted that the data acquisition instruction provided in the embodiment of the present application is only an example and should not unduly limit the scope of protection of the present application.

[0299] In some embodiments, the data volume of the first result is less than a preset data volume threshold, for example, the data volume of the first result ranges from 1 byte to 4 bytes. Therefore, in the process of determining the target valley voltage, the amount of data transmitted between the memory device and the memory controller is small and the speed is fast, which is conducive to improving the overall speed of the read operation.

[0300] An embodiment of the present application further provides a storage medium having executable instructions stored thereon. When the executable instructions are executed, the steps of the operating method in the above embodiment of the present application can be implemented.

[0301] In some specific embodiments, the storage medium can be a memory such as Ferromagnetic Random Access Memory (FRAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash Memory, magnetic surface storage, an optical disc, or a Compact Disc Read-Only Memory (CD-ROM); it can also be various devices including one or any combination of the above memory devices.

[0302] In some embodiments, executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0303] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, e.g., in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinating files (e.g., files storing one or more modules, subroutines, or code portions).

[0304] As an example, executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed across multiple sites and interconnected by a communication network.

[0305] In some specific embodiments, referring to Figure 19, Figure 19 is a schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application; wherein, the storage medium includes a first storage medium corresponding to the memory device 104, a second storage medium corresponding to the memory controller 104, and a third storage medium corresponding to the memory system 102; when the executable instruction is executed by the memory device, the first storage medium can be used to implement the steps of the operating method of the memory device described in the above embodiment of the present application; when the executable instruction is executed by the memory controller, the second storage medium can be used to implement the steps of the operating method of the memory controller described in the above embodiment of the present application; when the executable instruction is executed by the memory system, the third storage medium can be used to implement the steps of the operating method of the memory system described in the above embodiment of the present application.

[0306] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0307] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application description and drawings under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A memory device comprising: A memory cell array comprising a plurality of memory cells, a preset number of the memory cells forming a codeword; A peripheral circuit is coupled to the memory cell array and is configured to: performing M first adjustments on a target read voltage of at least one of the codewords with a first step length, and obtaining M first results corresponding to the M read voltages after the M first adjustments, wherein the first results include a number of bits flipped in two read results of the at least one codeword at the first read voltage and the second read voltage, wherein a difference between the first read voltage and the second read voltage is less than a preset voltage; The smallest first result among the M first results is used as the inflection point value, and the read voltage corresponding to the inflection point value is the inflection point voltage; Performing N second adjustments on the knee point voltage with a second step length, and respectively obtaining N first results corresponding to N read voltages after the N second adjustments, wherein the second step length is smaller than the first step length; and determining a target valley voltage according to the N first results obtained, where the target valley voltage is used as a read voltage when performing a read operation on at least one of the codewords; Wherein, both M and N are positive integers greater than 1.

2. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: Before performing a first adjustment M times on the target read voltage of at least one of the codewords with a first step length, determining a near-valley threshold value based on a first result corresponding to at least one of the codewords at the initial target read voltage, the near-valley threshold value being used to represent a maximum value of the first result corresponding to a near-target valley bottom voltage; Before performing the first adjustment M times on the target read voltage of at least one of the code words with the first step length, the initial target read voltage is adjusted multiple times until the adjusted target read voltage is The first result corresponding to the pressing is less than the near-valley threshold; The adjusted target read voltage corresponding to the first result being smaller than the near-valley threshold is used as the target read voltage, and the target read voltage is first adjusted M times with the first step length.

3. The memory device according to claim 2, wherein The peripheral circuit is configured as follows: Before performing the first adjustment M times on the target read voltage of at least one of the codewords with the first step length, in a process of adjusting the initial target read voltage multiple times, according to the first result corresponding to the adjusted target read voltage being greater than or equal to the near-valley threshold, obtaining a next adjusted target read voltage based on the first result corresponding to the last adjusted target read voltage; The first time that the plurality of first results corresponding to the adjusted target read voltage are smaller than the adjusted target read voltage corresponding to the near-valley threshold is used as the near-valley point voltage; In the process of performing M first adjustments on the target read voltage with the first step length, starting from the near-valley point voltage, adjustments are performed in two opposite directions with the first step length until the first results corresponding to the adjusted read voltages in the two directions are both greater than the near-valley threshold.

4. The memory device according to claim 3, wherein The peripheral circuit is configured as follows: In a process of performing M first adjustments on the near-valley point voltage with a first step length, starting from the near-valley point voltage, adjusting in a first direction with the first step length until a first result corresponding to the target read voltage after adjustment in the first direction is greater than the near-valley threshold; Starting from the near-valley point voltage, adjustment is performed in a second direction opposite to the first direction with the first step length until a first result corresponding to the target read voltage adjusted in the second direction is greater than the near-valley threshold.

5. The memory device according to claim 3, wherein The peripheral circuit is configured as follows: Obtaining the near-valley threshold according to the first result corresponding to the target read voltage and a first mapping function; wherein the first mapping function is used to characterize the relationship between the near-valley threshold and the first result corresponding to the target read voltage; According to the first result and the second mapping function corresponding to the target read voltage after the last adjustment, the target read voltage after the next adjustment is obtained; the second mapping function is used to characterize the target read voltage after the last adjustment. The relationship between the first result corresponding to the target read voltage after the adjustment and the predicted read voltage after the next adjustment. The memory device according to claim 1 , wherein: The peripheral circuit is configured as follows: During the process of performing N second adjustments on the knee point voltage with a second step size, starting from the knee point voltage, the adjustment is performed in two opposite directions with the second step size. During the adjustment in each direction, when a first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, a statistical analysis showing an upward trend is performed. If the total number of statistical analyses is greater than or equal to a preset number, the first boundary voltage and the second boundary voltage are determined. During the adjustment process in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than a preset threshold, or if the smallest first result among multiple first results corresponding to the target read voltage after multiple adjustments is used as a reference value, and the number of the remaining multiple first results whose differences from the reference value are less than a preset difference is greater than a preset number, the adjustment is stopped and the adjusted target read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage.

7. The memory device according to claim 6, wherein: The peripheral circuit is configured as follows: During the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, the adjustment is performed in a first direction with the second step size until the total statistical number of times the adjustment shows an upward trend in the first direction is equal to a preset number; starting from the inflection point voltage, the adjustment is performed in a second direction opposite to the first direction with the second step size until the total statistical number of times the adjustment shows an upward trend in the second direction is equal to a preset number.

8. The memory device according to claim 7, wherein The peripheral circuit is configured as follows: During the adjustment in the first direction, the adjusted target read voltage corresponding to the total number of times the upward trend is equal to the preset number is used as the first boundary voltage; and during the adjustment in the second direction, the adjusted target read voltage corresponding to the total number of times the upward trend is equal to the preset number is used as the second boundary voltage; During the adjustment in both directions, if the first boundary voltage and the second boundary voltage have been determined, obtaining a first result corresponding to the read voltage of the last adjustment, where the read voltage of the last adjustment is an average of the first boundary voltage and the second boundary voltage; The read voltage corresponding to the smallest first result among the plurality of first results corresponding to all the adjusted read voltages is used as the target valley voltage.

9. The memory device according to claim 1, wherein The memory cell array includes memory cells with multiple storage bits; the multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple levels; The peripheral circuit is configured as follows: After determining a target valley voltage of at least one of the codewords at a target level, target valley voltages of other levels in the multiple levels except the target level are determined respectively.

10. The memory device according to claim 9, wherein The multiple stages include a first stage and a second stage, wherein a read voltage of the second stage is lower than a read voltage of the first stage; The peripheral circuit is configured as follows: When the stage corresponding to the determined target valley voltage belongs to the first stage, the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower reading voltages are obtained according to the determined target valley voltage.

11. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: Reading stored data of at least one of the codewords at the first read voltage to obtain a second result; performing a third adjustment on the first read voltage with a third step length to obtain the second read voltage, and reading stored data of at least one of the codewords at the second read voltage to obtain a third result; performing a logical operation on the second result and the third result to obtain a fourth result; The first result is obtained by counting the number of bits in the fourth result that represent that the third result is flipped compared with the second result.

12. The memory device according to claim 11, wherein The peripheral circuit includes: a first latch, a second latch, and a third latch; The first latch is configured to: store the second result; The second latch is configured to: store the third result; The third latch is configured to store the fourth result.

13. A memory system comprising: One or more memory devices according to any one of claims 1 to 12; as well as A memory controller is coupled to the memory device and controls the memory device.

14. The memory system according to claim 13, wherein: The memory controller is configured to: send a data acquisition instruction, wherein the data acquisition instruction instructs acquisition of a target valley voltage; The memory device is configured to: receive the data acquisition instruction, acquire a target valley voltage, and send information including the target valley voltage to the memory controller; The memory controller is further configured to perform a read operation on data stored in the memory device according to the target valley voltage in the information.

15. The memory system according to claim 14, wherein: The memory controller is further configured to perform an error correction code decoding operation on a read result of the read operation.

16. A memory controller coupled to at least one memory device, the memory device comprising a plurality of memory cells, a predetermined number of the memory cells forming a codeword; The storage controller includes: The control unit is configured to: performing M first adjustments on a target read voltage of at least one of the codewords with a first step length, and obtaining M first results corresponding to the M read voltages after the M first adjustments, wherein the first results include a number of bits flipped in the read results of the at least one codeword at the first read voltage and the second read voltage; and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage. The smallest first result among the M first results is used as the inflection point value, and the read voltage corresponding to the inflection point value is the inflection point voltage; Performing N second adjustments on the knee point voltage with a second step size, and respectively obtaining N first results corresponding to N read voltages after the N second adjustments, wherein the second step size is smaller than the first step size; and determining a target valley voltage according to the N first results obtained; wherein the target valley voltage is used as a read voltage when performing a read operation on at least one of the codewords; Wherein, both M and N are positive integers greater than 1.

17. The memory controller according to claim 16, wherein: The control unit is configured to: Before performing a first adjustment M times on the target read voltage of at least one of the codewords with a first step length, determining a near-valley threshold value based on a first result corresponding to at least one of the codewords at the initial target read voltage, the near-valley threshold value being used to represent a maximum value of the first result corresponding to a near-target valley bottom voltage; Before performing M first adjustments on the target read voltage of at least one of the codewords with a first step length, adjusting the initial target read voltage multiple times until a first result corresponding to the adjusted target read voltage is less than the near-valley threshold; The adjusted target read voltage corresponding to the first result being smaller than the near-valley threshold is used as the target read voltage, and the target read voltage is first adjusted M times with the first step length.

18. The memory controller according to claim 17, wherein: The control unit is configured to: Before performing the first adjustment M times on the target read voltage of at least one of the codewords with the first step length, in a process of adjusting the initial target read voltage multiple times, according to the first result corresponding to the adjusted target read voltage being greater than or equal to the near-valley threshold, obtaining a next adjusted target read voltage based on the first result corresponding to the last adjusted target read voltage; The first time that the plurality of first results corresponding to the adjusted target read voltage are smaller than the adjusted target read voltage corresponding to the near-valley threshold is used as the near-valley point voltage; In the process of performing M first adjustments on the target read voltage with the first step length, starting from the near-valley point voltage, adjustments are performed in two opposite directions with the first step length until the first results corresponding to the adjusted read voltages in the two directions are both greater than the near-valley threshold.

19. The memory controller according to claim 18, wherein: The control unit is configured to: In a process of performing M first adjustments on the near-valley point voltage with a first step length, starting from the near-valley point voltage, adjusting in a first direction with the first step length until a first result corresponding to the target read voltage after adjustment in the first direction is greater than the near-valley threshold; Starting from the near-valley point voltage, adjustment is performed in a second direction opposite to the first direction with the first step length until a first result corresponding to the target read voltage adjusted in the second direction is greater than the near-valley threshold.

20. The memory controller according to claim 18, wherein The control unit is configured to: Obtaining the near-valley threshold according to the first result corresponding to the target read voltage and a first mapping function; wherein the first mapping function is used to characterize the relationship between the near-valley threshold and the first result corresponding to the target read voltage; The target read voltage after the next adjustment is obtained according to the first result corresponding to the target read voltage after the last adjustment and the second mapping function; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage after the last adjustment and the predicted read voltage after the next adjustment.

21. The memory controller according to claim 16, wherein: The control unit is configured to: During the process of performing N second adjustments on the knee point voltage with a second step size, starting from the knee point voltage, the adjustment is performed in two opposite directions with the second step size. During the adjustment in each direction, when a first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, a statistical analysis showing an upward trend is performed. If the total number of statistical analyses is greater than or equal to a preset number, the first boundary voltage and the second boundary voltage are determined. During the adjustment process in both directions, if the first result corresponding to the target read voltage after one adjustment is lower than the preset threshold, or if the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as the reference value, and the number of the remaining multiple first results whose differences from the reference value are smaller than the preset difference is greater than the preset number, the adjustment is stopped and the multiple first results are The adjusted target read voltage corresponding to the smallest first result is used as the target valley voltage.

22. The memory controller according to claim 21, wherein: The control unit is configured to: During the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, the adjustment is performed in a first direction with the second step size until the total statistical number of times the adjustment shows an upward trend in the first direction is equal to a preset number; starting from the inflection point voltage, the adjustment is performed in a second direction opposite to the first direction with the second step size until the total statistical number of times the adjustment shows an upward trend in the second direction is equal to a preset number.

23. The memory controller according to claim 22, wherein: The control unit is configured to: During the adjustment in the first direction, the adjusted target read voltage corresponding to the total number of times the upward trend is equal to the preset number is used as the first boundary voltage; and during the adjustment in the second direction, the adjusted target read voltage corresponding to the total number of times the upward trend is equal to the preset number is used as the second boundary voltage; During the adjustment in both directions, if the first boundary voltage and the second boundary voltage have been determined, obtaining a first result corresponding to the read voltage of the last adjustment, where the read voltage of the last adjustment is an average of the first boundary voltage and the second boundary voltage; The read voltage corresponding to the smallest first result among the plurality of first results corresponding to all the adjusted read voltages is used as the target valley voltage.

24. The memory controller according to claim 16, wherein: The memory cell array includes a memory cell with a plurality of storage bits; the plurality of storage bits correspond to a plurality of pages; at least one page corresponds to a plurality of levels The control unit is configured to: After determining a target valley voltage of at least one of the codewords at a target level, target valley voltages of other levels in the multiple levels except the target level are determined respectively.

25. The memory controller according to claim 24, wherein: The multiple stages include a first stage and a second stage, wherein a read voltage of the second stage is lower than a read voltage of the first stage; The control unit is configured to: When the stage corresponding to the determined target valley voltage belongs to the first stage, the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower read voltages are generated according to the determined target valley voltage.

26. A method for operating a memory device, comprising: performing M first adjustments on a target read voltage of at least one codeword with a first step length, and obtaining M first results corresponding to the M read voltages after the M first adjustments, wherein the first results include a number of bits flipped in two read results at a first read voltage and a second read voltage representing a codeword formed by a preset number of memory cells in at least one memory device, wherein the difference between the first read voltage and the second read voltage is less than a preset voltage; The smallest first result among the M first results is used as the inflection point value, and the read voltage corresponding to the inflection point value is the inflection point voltage; Performing N second adjustments on the knee point voltage with a second step size, and respectively obtaining N first results corresponding to N read voltages after the N second adjustments; The second step length is smaller than the first step length; and determining a target valley voltage according to the N first results obtained, where the target valley voltage is used as a read voltage when performing a read operation on at least one of the codewords; Wherein, both M and N are positive integers greater than 1.

27. A method for operating a memory system, comprising: A memory controller in the memory system sends a data acquisition instruction, wherein the data acquisition instruction instructs acquisition of a target valley voltage; The memory device in the memory system receives the data acquisition instruction, The operating method of the memory device according to claim 26 , wherein the target valley voltage is acquired, and information including the target valley voltage is sent to the memory controller; The memory controller performs a read operation on data stored in a memory device according to the target valley voltage in the information.

28. A method for operating a memory controller, comprising: performing M first adjustments on a target read voltage of at least one codeword with a first step length, and obtaining M first results corresponding to the M read voltages after the M first adjustments, wherein the first results include a number of bits flipped in read results of a codeword formed by a preset number of memory cells in a memory device of at least one memory system at the first read voltage and at a second read voltage, wherein a difference between the first read voltage and the second read voltage is less than a preset voltage; The smallest first result among the M first results is used as the inflection point value, and the read voltage corresponding to the inflection point value is the inflection point voltage; Performing N second adjustments on the knee point voltage with a second step size, and respectively obtaining N first results corresponding to N read voltages after the N second adjustments; The second step length is smaller than the first step length; and determining a target valley voltage according to the N first results obtained, where the target valley voltage is used as a read voltage when performing a read operation on at least one of the codewords; Wherein, both M and N are positive integers greater than 1.

29. A storage medium having executable instructions stored thereon, wherein when the executable instructions are executed, the steps of the operating method according to any one of claims 26 to 28 can be implemented.

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