Wheel speed detection device and chip system

Abstract

The invention provides a wheel speed detection device and a chip system. The wheel speed detection device comprises a first comparator, a second comparator and a signal analyzer, the first comparator and the second comparator are respectively configured with different reference voltages, and the input end of the first comparator and the input end of the second comparator are used for receiving voltage signals generated by the same wheel speed sensor; and the signal analyzer is used for analyzing the wheel speed information according to the first comparison signal output by the first comparator and the second comparison signal output by the second comparator. Thus, the input signal is subjected to multi-threshold judgment by using a double-comparator structure, so that sensor signals of different current levels can be identified and analyzed uniformly, and compatible processing of sensor signals of multiple protocols is realized. Therefore, the problem that the overall system cost is increased due to hardware redundancy and system complexity increase in a traditional scheme is avoided, and the universality and the integration capacity of the interface module are effectively improved in a low-cost mode.

Description

Technical Field

[0001] This application relates to the automotive field, and more specifically, to a wheel speed detection device and chip system. Background Technology

[0002] Wheel speed sensors, as core sensing elements in modern vehicle active safety systems, play an irreplaceable role in anti-lock braking systems (ABS), electronic stability control (ESC), traction control systems (TCS), and emerging autonomous driving functions. Their core function is to monitor the rotational speed of the wheels in real time and convert mechanical motion into electrical signals recognizable by the electronic control system. Hall effect sensors are the mainstream type; these sensors are based on the principle that changes in magnetic fields cause potential differences. During wheel rotation, they detect changes in the tooth structure of a magnetic target wheel, generating corresponding pulse current signals.

[0003] Different types of wheel speed sensors exhibit diverse communication protocol standards at their signal output ends. However, existing decoding schemes generally suffer from the problem of supporting only a single protocol. Application-Specific Integrated Circuits (ASICs) are typically optimized only for specific protocols. For example, a Hall sensor-specific ASIC mainly focuses on processing the standard square wave protocol, while the AK protocol requires a separate receiver chip for decoding. When a system needs to support multiple types of sensors simultaneously, it is often necessary to use multiple parallel decoding circuits, which not only significantly increases hardware complexity but also raises the overall system cost. Summary of the Invention

[0004] To overcome at least one deficiency in the prior art, this application provides a wheel speed detection device and chip system, specifically including: In a first aspect, this application provides a wheel speed detection device, which includes a first comparator, a second comparator, and a signal analyzer; The first comparator and the second comparator are configured with different reference voltages, and the input terminals of the first comparator and the second comparator are used to receive voltage signals generated by the same wheel speed sensor. The signal parser is used to extract wheel speed information from the first comparison signal output by the first comparator and the second comparison signal output by the second comparator.

[0005] Secondly, this application provides a chip system, including a processor and the aforementioned wheel speed detection device.

[0006] Compared with the prior art, this application has the following beneficial effects: This application provides a wheel speed detection device and chip system. The wheel speed detection device includes a first comparator, a second comparator, and a signal analyzer. The first and second comparators are configured with different reference voltages, and their input terminals are used to receive voltage signals generated by the same wheel speed sensor. The signal analyzer is used to parse wheel speed information from the first comparison signal output by the first comparator and the second comparison signal output by the second comparator. Thus, by using a dual-comparator structure to perform multi-threshold judgment on the input signal, sensor signals of different current levels can be uniformly identified and analyzed, achieving compatible processing of sensor signals from multiple protocols. This avoids the increased overall system cost caused by hardware redundancy and increased system complexity in traditional solutions, effectively improving the versatility and integration capability of the interface module in a low-cost manner. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 A comparative schematic diagram of various wheel speed protocols provided for embodiments of this application; Figure 2 This is a schematic diagram of the overall structure of the wheel speed detection device provided in the embodiments of this application; Figure 3 A schematic diagram illustrating the principle of current signal to voltage signal conversion provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of the signal analyzer provided in the embodiments of this application; Figure 5 A schematic diagram of the input signals of the preprocessing module provided in the embodiments of this application; Figure 6 This is one of the structural schematic diagrams of the preprocessing module provided in the embodiments of this application; Figure 7 This is the second schematic diagram of the preprocessing module provided in the embodiments of this application; Figure 8 A schematic diagram of the working clock provided in the embodiments of this application; Figure 9 This is a schematic diagram of the signal analysis module provided in an embodiment of this application; Figure 10 This is a schematic diagram of state changes provided for an embodiment of this application; Figure 11 This is a connection diagram of the interrupt module provided in an embodiment of this application; Figure 12 This is a schematic diagram of register interaction relationships provided in an embodiment of this application. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of the embodiments of this application (hereinafter referred to as "the embodiments") clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0010] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0011] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0012] In the description of this application, it should be noted that the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0013] Furthermore, it should be noted in the description of this application that, unless otherwise expressly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0014] Based on the above statements, and considering that this embodiment involves multiple wheel speed measurement protocols, to make the following solution easier to understand, we will first combine... Figure 1 This embodiment may involve various wheel speed measurement protocols, which will be explained and described.

[0015] The various wheel speed measurement protocols described here, including the standard square wave protocol, pulse width modulation (PWM) protocol, and AK protocol, will be used as examples for a more intuitive explanation. It should be noted that, based on these protocols, this embodiment divides the output current of the sensor into three levels: high, medium, and low. The high current is 28mA, denoted by the symbol... The medium current is 14mA, as indicated by the symbol. The low current is 7mA, indicated by the symbol. To express.

[0016] The standard square wave protocol is the most basic form of wheel speed output, calculating wheel rotation speed by the number of pulses per unit time. This protocol is simple to implement and low in cost, but its limitations include the inability to provide rotation direction information and relatively weak anti-interference capabilities. The output current is available in two nominal levels: 14mA (medium current) and 7mA (low current). Accurate measurement of the rotation speed is achieved by capturing the period of the pulse signal during decoding.

[0017] The PWM protocol embeds width modulation information into pulse signals, allowing it to measure wheel speed as well as additional information such as rotation direction. Its advantage lies in its good protocol compatibility, making it suitable for various types of wheel speed sensors. However, this protocol requires dedicated decoding circuitry to analyze the pulse duty cycle to obtain valid data. The output current is also available in two nominal levels: a medium current of 14mA and a low current of 7mA. During decoding, both the pulse width and period must be captured simultaneously to achieve accurate identification of speed and direction.

[0018] The AK protocol employs current amplitude modulation technology, using three levels of current variation (7mA, 14mA, and 28mA) to encode and transmit information such as wheel speed, rotation direction, air gap status, and parity check. This protocol boasts strong anti-interference capabilities, making it particularly suitable for complex operating environments with high electromagnetic noise, such as electric vehicles. However, its receiver requires a relatively complex circuit design to convert the current signal into a voltage square wave signal recognizable by the microcontroller. During decoding, the current current level must first be identified, and the timestamp information of the edges must be further analyzed to extract the complete data content. When the wheel is stationary, the AK protocol supports a stationary protocol mode. In this mode, the speed pulse switches to a medium current state, with an interval of approximately 150ms between adjacent pulses, used to feedback the wheel's stationary status to the control system.

[0019] Based on the above descriptions of various wheel speed measurement protocols, in order to address the problem that existing decoding schemes generally support only one protocol, the research process proposed a dedicated integrated chip solution, a solution combining discrete components with a basic microcontroller unit (MCU), and a software decoding solution. When these solutions need to support multiple types of wheel speed sensors, they all result in a significant increase in hardware complexity and system cost.

[0020] First, in application-specific integrated circuit (ASIC) solutions, because the internal protocol decoding logic of the chip is fixed, a single chip can only handle one specific protocol type. Therefore, to be compatible with multiple protocols such as standard square wave, PWM, and AK, a dedicated chip must be configured for each protocol. This parallel deployment not only leads to a significant increase in printed circuit board area and bill of materials costs, but also brings challenges to supply chain management, as different chips may face different supply cycles and substitution risks.

[0021] Secondly, while the solution using discrete components combined with a basic MCU eliminates the reliance on dedicated chips, the different signal conditioning requirements of various protocols, especially complex protocols like the AK protocol, necessitate the design of additional current-to-voltage conversion circuits to adapt to the MCU's input interface. This complicates the front-end circuitry for each channel and makes standardization difficult. Furthermore, the different processing flows required by each protocol (e.g., PWM requires pulse width measurement while the AK protocol involves Manchester encoding parsing) necessitate independent design of corresponding analog front-ends and software logic for each protocol. This results in non-reusable peripheral circuits, further increasing hardware resource consumption and the overall system implementation complexity.

[0022] Finally, even in software decoding solutions, while offering high flexibility, multiple decoding algorithm instances must be run to handle the data structures and decoding rules of different protocols. This necessitates frequent use of high-precision timers to capture edge information, combined with interrupt or DMA mechanisms for data transfer. This approach consumes significant CPU time and memory resources, especially in multi-channel systems where the computational load increases exponentially, necessitating the use of higher-performance MCUs and thus increasing the overall system cost. Furthermore, ensuring real-time performance requires additional hardware auxiliary modules, such as high-speed ADCs or external interrupt controllers, indirectly exacerbating hardware complexity and power consumption.

[0023] Therefore, when faced with the need to support multiple protocols, existing decoding solutions, whether through hardware replication, peripheral expansion, or software overlay, cannot effectively avoid the problems of resource redundancy, circuit complexity, and increased costs.

[0024] Based on the discovery of the aforementioned technical problems, the following technical solutions are proposed through creative effort to solve or improve these problems. It should be noted that the deficiencies in the solutions of the prior art are the result of practical experience and careful research. Therefore, the discovery process of the aforementioned problems and the solutions proposed in the embodiments of this application below should be considered as contributions made to this application during the inventive process, and should not be construed as technical content known to those skilled in the art.

[0025] Therefore, this embodiment provides a wheel speed detection device. For example... Figure 2 As shown, the wheel speed detection device includes a first comparator 12, a second comparator 13, and a signal analyzer 11; The first comparator 12 and the second comparator 13 (hereinafter referred to as dual comparators) are configured with different reference voltages. The input terminals of the first comparator 12 and the second comparator 13 are used to receive the voltage signal generated by the same wheel speed sensor. The signal parser 11 is used to parse wheel speed information from the first comparison signal output by the first comparator 12 and the second comparison signal output by the second comparator 13.

[0026] Thus, unlike existing technologies that rely on dedicated decoding chips or independent external circuits to process specific protocols, the wheel speed detection device in this embodiment uses a first comparator 12 and a second comparator 13 configured with different reference voltages, and both receive voltage signals from the same wheel speed sensor, thereby achieving compatible processing of signals from multiple protocol sensors. This avoids the problem of increased overall system cost caused by hardware redundancy and increased system complexity in traditional solutions, and effectively improves the versatility and integration capability of the interface module in a low-cost manner.

[0027] It should be understood that, considering that most wheel speed sensors directly output current signals, and in this embodiment, the input terminals of the first comparator 12 and the second comparator 13 of the wheel speed detection device are used to receive the voltage signal generated by the same wheel speed sensor. Therefore, an external passive RC converter circuit can be used to convert the current signal output by the wheel speed sensor into a voltage signal, which is then processed by the comparators. Here, the wheel speed sensor refers to a current-type sensor that outputs a standard square wave protocol, PWM protocol, or AK protocol, and its output signal represents speed information in different levels of current.

[0028] Specifically, such as Figure 3 As shown, in practical applications, the current output signal of the wheel speed sensor 14 is transmitted through a resistor. and capacitor A passive RC network is formed to perform current-to-voltage conversion, wherein... Used to convert the current signal (such as 7mA, 14mA, 28mA) output by the sensor into the corresponding voltage signal. Its calculation formula is Because the first comparator 12 and the second comparator 13 are configured with different reference voltages. and ,therefore The value of must ensure that the generated It can effectively cover these two reference voltage thresholds and leave an appropriate margin (usually 5% to 10%) to ensure that the comparator can accurately identify the voltage level corresponding to different current states.

[0029] For the above reference voltage and This can be generated by an internal digital-to-analog converter (DAC). It is used to precisely configure registers to adapt to different sensor specifications or compensate for temperature drift. The configuration must meet the following requirements. Sufficient margin is maintained. Furthermore, for sensors employing standard square wave or PWM protocols and supporting high safety levels such as ASIL D, additional current information may be required; the output current signal in operating mode will not fall below 3.5mA. For such sensors, the first comparator 12 can be multiplexed via registers and parameter configuration to adjust the reference voltage VREFH of the dual comparator module (e.g., 5mA*R0) to monitor the input voltage. If the voltage falls below a set threshold, the sensor fault flag is activated, and an interrupt is generated according to the configuration. In this way, it is possible to monitor whether the input voltage is below a certain set threshold, thereby determining whether the sensor's operating state is abnormal.

[0030] It should also be noted that when using wheel speed sensors that support PWM or standard square wave protocols, since these protocols only involve two current states (e.g., 14mA and 7mA), there is no need to recognize the high current level of 28mA. Therefore, the comparator in the dual comparator that is related to the 28mA current can be selectively turned off to reduce power consumption. At the same time, the subsequent processing logic related to this comparator, such as filtering, XOR operation, and edge detection modules, can also be turned off or put into low-power mode accordingly, thereby further reducing system power consumption and improving overall energy efficiency.

[0031] Furthermore, capacitors The selection of [value] primarily affects the signal's filtering characteristics and response time. A larger [value]... A higher value can enhance the suppression of high-frequency noise, but it will prolong the rise and fall times of the signal, affecting the capture of rapidly changing signals; while a lower value... This improves response speed, but may introduce more noise interference. Therefore, in practical implementation, an adaptive selection can be made based on the specific sensor characteristics, the noise level of the operating environment, and the required signal integrity.

[0032] The voltage signal obtained after the above current is processed by the RC conversion circuit during operation. The input signals are simultaneously fed into the input terminals of the first comparator 12 and the second comparator 13. The two comparators judge the input signals based on their respective reference voltages and output corresponding logic state combinations. For example, under the AK protocol, when... When the current is 7mA, Below and Both comparators output a low level; when At a current of 14mA, Vin is higher than But lower Only the second comparator 13 outputs a high level; while when When the current is 28mA, Higher than Both comparators output a high level. This allows the signal analyzer 11 to accurately identify the communication protocol used by the sensor and the speed and direction information it carries based on the combination of these two comparison signals. Furthermore, as an optional implementation, if the protocol is PWM or a standard square wave, the 28mA comparator can be omitted to save power.

[0033] like Figure 4 As shown, the signal resolver 11 includes a preprocessing module 111 and a signal resolution module 112, and the reference voltage of the first comparator 12 is greater than the reference voltage of the second comparator 13.

[0034] The preprocessing module 111 is used to perform an XOR operation on the first comparison signal and the second comparison signal to obtain a composite signal; and to acquire various edge trigger signals generated by the composite signal and the first comparison signal. The signal parsing module 112 is used to parse wheel speed information from various edge-triggered signals.

[0035] In this embodiment, the preprocessing module 111 of the wheel speed detection device is used to perform an XOR operation on the first comparison signal and the second comparison signal to generate a composite signal, and to obtain various edge trigger signals generated by the composite signal and the first comparison signal. Therefore, the preprocessing module 111 relies on the two digital signals output by the dual comparator module, which are respectively represented as follows: and ,in, Corresponding to the output state of the first comparator 12, The output state corresponding to the second comparison signal, and the combination of the two (00, 01, 11) respectively represent the low current (e.g., 7mA), medium current (e.g., 14mA) and high current (e.g., 28mA) states of the sensor output.

[0036] Specifically, in the application scenario of the AK protocol, in order to achieve independent parsing of Manchester encoded data bits and separate timing and decoding logic, the preprocessing module 111 performs an XOR operation to... and Combined, generating composite signals Its expression is This operational method allows input signals at different current levels to be mapped into composite signals with well-defined logical characteristics. For example: At low current (7mA), ; At medium current (14mA), ; At high current (28mA), .

[0037] thus, The signal can effectively distinguish the current state from the other two states, thus providing a clear logical basis for subsequent edge detection and decoding.

[0038] Preprocessing module 111 is based on the generated composite signal and the first comparison signal (For ease of use with composite signals) To make a comparison, also known as The signal extracts various edge-triggered signals. The signal comes directly from the output of the first comparator 12 and is used to characterize the high current state (28mA), with its rising edge serving as the primary timing trigger event for the speed pulse; while The signal is then used to drive the parsing of Manchester-coded data bits (in the AK protocol's stationary mode, when the wheels are stationary). The signal remains low, failing to provide a valid speed pulse trigger signal, while the sensor outputs a current state (14mA). To achieve effective identification and reporting of stationary states, the following can be enabled: The rising edge of the signal serves as an alternative trigger source; therefore, at this time... The rising edge of the signal will be considered as the timing trigger event of the speed pulse. By synchronously sampling and edge detection of these two signals, multiple independent edge-triggered signals of various types can be generated (such as...). These signals are sent to the signal analysis module 112 as key trigger sources to analyze the wheel speed information.

[0039] During the research, it was found that some sensors directly output current signals, which need to be converted into voltage signals by an external resistor before being sent to a comparator for processing; while other sensors may have built-in first comparator 12 and second comparator 13, which can directly output the digital signal after comparison processing. Therefore, in practical applications, the preprocessing module 111 needs to have the ability to flexibly select the input signal path to adapt to various physical implementation methods.

[0040] In view of this, such as Figure 5 As shown, the preprocessing module 111 includes a first input interface and a second input interface. The preprocessing module 111 is connected to the output terminals of the first comparator 12 and the second comparator 13 through the first input interface; the second input interface is used to connect to the wheel speed sensor 14 equipped with the first comparator 12 and the second comparator 13. The wheel speed detection device also includes a mode configuration register for the preprocessing module 111, which is used to configure the preprocessing module 111 to select between the first input interface and the second input interface.

[0041] Therefore, the preprocessing module 111 is provided with two input interfaces. The first input interface is used to receive the signal after conversion by an external RC circuit and processing by a dual comparator. , The second input interface is used to connect to an external wheel speed sensor 14 that integrates a first comparator 12 and a second comparator 13, thereby directly acquiring its output comparison signal. , In order to achieve switching control between the two input interfaces during the operation of the preprocessing module 111, the wheel speed detection device is further configured with a mode configuration register. The mode configuration register determines which input interface the preprocessing module 111 uses as the currently valid signal source through software configuration.

[0042] In practice, it was found that, due to Signals are products of combinational logic, and their generation depends on the synchronization of the output signals of two comparators. However, in actual circuits, factors such as XOR gate delay, comparator response time differences, and wiring can lead to... The signal produces brief spikes at the edges. In contrast, The signal, as the raw output directly from the comparator, has a shorter path and higher stability. There is an inherent asymmetry between the two in terms of signal path length, propagation delay, and stability characteristics. This difference is particularly pronounced in high-speed or high-noise environments, potentially leading to false triggering of subsequent edge detection and thus affecting the accurate interpretation of wheel speed information.

[0043] In view of this, such as Figure 6 As shown, the preprocessing module 111 includes a filtering unit 1111 and a sampling unit 1112; The filtering unit 1111 is used to perform an XOR operation on the first comparison signal and the second comparison signal to obtain a composite signal; and to filter the composite signal and the first comparison signal, and to transmit the obtained filtered composite signal and the filtered comparison signal to the sampling unit 1112. The sampling unit 1112 is used to sample the filtered composite signal and the filtered comparison signal to obtain various edge trigger signals.

[0044] Therefore, in the wheel speed detection device provided in this embodiment, the filtering unit 1111 in the preprocessing module 111 plays a crucial role in optimizing signal quality. Specifically, the filtering unit 1111 is used to filter composite signals ( ) and the first comparison signal ( Filtering is performed to remove high-frequency noise and signal glitches that may be carried during transmission, thereby improving the stability and accuracy of subsequent processing steps.

[0045] As an optional implementation, the filtering unit 1111 introduces a configurable filtering mechanism, such as an 8th-order FIR filter structure, to... and The signals are filtered separately, and each filtering parameter (such as cutoff frequency and filter coefficients) can be independently configured via registers. Specifically, in practical applications, this can be achieved by... The signal's glitches are subjected to stronger filtering to suppress signal jitter, while also... The signal employs a relatively weak filtering strategy to preserve its timing accuracy at the edges to the greatest extent possible. This asymmetric filtering method enables improved signal quality. While maintaining signal stability, it does not affect The signal is used to ensure the accuracy of velocity pulse timing.

[0046] Furthermore, it should be understood that in the wheel speed detection device provided in this embodiment, the sampling unit 1112 is an important component of the preprocessing module 111, and its core function is to synchronously sample the filtered composite signal and the first comparison signal to extract various edge trigger signals that can be used for subsequent decoding.

[0047] like Figure 7 As shown, when the preprocessing module 111 provides a first input interface and a second input interface, the preprocessing module 111 further includes an interface selection unit 1114 and a protocol selection unit 1113. The interface selection unit 1114 is used to select the signal from the first input interface or the second input interface for processing based on the mode configuration information in the mode configuration register. The protocol selection unit 1113 is used to selectively process the first comparison signal and the second comparison signal based on the configuration information provided by the user in the protocol selection register.

[0048] like Figure 8 As shown, the filtered Signals and The signal is input to sampling unit 1112 and synchronously sampled under the drive of the working clock provided by the functional clock divider module. This working clock is generated from the processor's main clock via frequency division logic, and its frequency can be flexibly configured in the registers according to the timing requirements of different protocols, for example, within the range of 1-2MHz, thereby ensuring sufficient time resolution for signal variations under different protocols. The filtered signal is then sampled using this clock. and Periodic sampling of the signal can effectively eliminate metastability problems caused by signal asynchrony, improve signal stability, and ensure its consistency in the internal clock domain of the module.

[0049] Specifically, based on signal synchronization, sampling unit 1112 further identifies and captures rising and falling edge events in the signal, thereby generating multiple independent edge-triggered signals, including but not limited to: the rising edge of the first comparison signal (represented as...). The falling edge of the first comparison signal (represented as) The rising edge of a composite signal (represented as) ) and the falling edge of the composite signal (represented as These multiple edge-triggered signals serve as key timestamp information, driving the start, stop, and latch operations of the subsequent counting unit 1121, and also providing precise triggering conditions for state machine transitions in the subsequent decoding unit 1122.

[0050] like Figure 9 As shown, the signal analysis module 112 includes a counting unit 1121 and a decoding unit 1122; The decoding unit 1122 is used to decode the wheel speed information based on the counting results of the counting unit 1121 for various edge-triggered signals.

[0051] In this embodiment, the wheel speed detection device supports wheel speed sensors 14 with multiple protocols, including standard square wave protocol, PWM protocol and AK protocol. The wheel speed detection device also includes a protocol selection register of the counting unit 1121 and multiple counting registers provided for multiple protocols. The counting unit 1121 is used to determine the target protocol from multiple protocols based on the configuration information in the protocol selection register; According to the target protocol, a target edge trigger signal is selected from multiple edge trigger signals, and a target count register corresponding to the target protocol is selected from multiple count registers; The counting unit 1121 is also used to write the statistical results of the target edge trigger signal into the target counting register.

[0052] The counting unit 1121, as a key hardware module for achieving multi-protocol compatible decoding, is designed to adapt to various mainstream wheel speed sensor 14 output protocols, including standard square wave protocol, PWM protocol, and AK protocol. To meet the differentiated requirements of different protocols for signal feature extraction, the counting unit 1121 adopts a configurable and multiplexed hardware architecture. Through the coordinated operation of the protocol selection register and multiple dedicated counting registers, it achieves flexible processing and efficient statistics of various edge-triggered signals.

[0053] During operation, the counting unit 1121 first identifies the specific communication protocol used by the wheel speed sensor 14 to be parsed, based on the information configured in the protocol selection register. This protocol selection information is written by external software through register configuration and guides the counting unit 1121 in selecting the correct signal processing logic and register resources in subsequent operations. After determining the target protocol, the counting unit 1121 filters out the target edge trigger signal suitable for the current protocol from various edge trigger signals according to the protocol characteristics, and selects the target counting register corresponding to the current protocol from multiple counting registers to store the corresponding count value. It should be noted that multiple counting registers can be shared and reused by multiple protocols, or partially reused according to protocol characteristics, or each protocol may correspond to a dedicated counting register.

[0054] For example, the multiple counting registers in this embodiment can specifically be three sets of counting registers with different bit widths: a wheel speed counter (T, 24 bits), a high-level counter (t, 18 bits), and an AK decoding counter (tdec, 12 bits). Each counter undertakes a different functional role and is dynamically enabled according to the selected protocol. Specifically, the wheel speed counter is shared by the AK protocol, the PWM protocol, and the standard square wave protocol; the high-level counter is shared by the AK protocol and the PWM protocol; and the AK decoding counter is exclusively used by the AK protocol.

[0055] Under standard square wave or PWM protocols, the main components used are a wheel speed counter T and a high-level counter t. T measures the period, and t measures the pulse width (duty cycle). Both are based on... As a start signal, the T value is in the next Latching, while the value of t is in Time-locked.

[0056] Under the AK protocol, in addition to the wheel speed counter T, a high-level counter t and an AK decoding counter tdec are also enabled. The wheel speed counter T is still used to measure the speed pulse period, but... The high-level counter t is used to measure the duration of the high level, serving as the time reference for Manchester decoding; the AK decoding counter tdec is used to measure the transition edge interval within the bit interval, determined by the falling edge of the velocity pulse (e.g., ...). Start, and in each The current count value is reset and latched on the transition edge.

[0057] Furthermore, in this implementation, to meet the requirement of counting the total number of wheel speed pulses within a given time period, the counting unit also provides an edge-triggered accumulation mode. In this mode, the wheel speed counter T is multiplexed as an accumulator to record the number of wheel speed pulses received within a specified duration. Specifically, when the register is configured in this functional mode, different trigger signals are selected according to the protocol type used, as detailed below: For both standard square wave and PWM protocols, the wheel speed counter T is configured by... rising edge of the signal ( Trigger count; For the AK protocol, the trigger counting is divided into two types. In non-stationary protocol mode, the wheel speed counter T is configured by... rising edge of the signal ( Trigger counting; when in static protocol mode, the wheel speed counter T is configured by... rising edge of the signal ( Trigger count.

[0058] Meanwhile, the wheel speed detection device also provides a dedicated timer / counter for the edge-triggered accumulation mode, which is only enabled in this function mode and used to set a specified duration. This timer / counter counts based on the system clock; when its count reaches the specified duration, it indicates that the given time window has ended. At this time, the wheel speed counter T latches its current accumulated value, which is the total number of wheel speed pulses accumulated within that time period. This latched value can be read through a register, and the interrupt module can be configured to send an interrupt notification to the processor to inform the CPU of the wheel speed pulse statistics for the current time period.

[0059] Therefore, the design of the counting unit 1121 fully considers the signal feature extraction requirements of different protocols, and realizes dynamic scheduling and function multiplexing of hardware resources through register configuration. This structure not only improves the system's adaptability to various wheel speed sensor 14 protocols, but also reduces the computational burden on the processor, thereby reducing the overall system complexity and power consumption. In addition, each counter integrates an error detection mechanism, such as generating a timeout error flag when the count overflows, further enhancing the robustness and reliability of the device in complex electromagnetic environments.

[0060] Taking the AK protocol as an example, when the target protocol is the AK protocol, the decoding unit 1122 implements the decoding operation of the AK protocol through a hardware state machine.

[0061] The decoding unit 1122 is used to obtain the duration of the composite signal from the counting unit 1121 when the first comparison signal generates a falling edge; and wait for the composite signal to generate a transition edge; When the composite signal has a transition edge, the transition time interval of the composite signal is obtained from the counting unit 1121; If the transition time interval is equal to the duration, it is determined to be a valid Manchester encoded edge, and the wheel speed information is decoded. If the transition time interval is half the duration, then continue to wait for the next transition edge of the composite signal; Once the next transition edge of the composite signal is detected, the transition time interval of the next transition edge is obtained from the counting unit 1121; If the transition time interval of the next transition edge is half the duration, it is determined to be a valid Manchester-coded edge, and the wheel speed information is decoded.

[0062] It should be understood that the hardware state machine here specifically refers to a logical structure based on a finite state transition mechanism. Its purpose is to automatically determine the current decoding stage based on various edge-triggered signals and their time intervals, and to execute corresponding data parsing and error detection actions according to preset state transition rules. This hardware state machine includes eight functional states: IDLE, START, TOGGLE, WAIT, TOGGLE2, DECODER, ERROR, and TIMEOUT.

[0063] Specifically, such as Figure 10 As shown, when the target protocol is the AK protocol, the falling edge of the velocity pulse (usually...) The signal triggers the hardware state machine to enter the START state, at which point the high-level counter t in the counter module begins to latch the time base value. That is, the duration of the current velocity pulse is measured.

[0064] In the START state, the state machine waits for input from... The signal's rising edge trigger condition. Once detected... Upon the signal transition edge, the system enters the TOGGLE state, and the time interval between the transition edge occurrences is recorded by the AK decoding counter tdec. Based on this, the state machine will use the AK decoding counter tdec and the time base value... The relationship between the time interval and the reference value is used to determine whether the transition edge meets the validity criteria of Manchester encoding: if the time interval is equal to the reference value, it is determined to be a valid transition edge, and the system enters the DECODER state to parse out the corresponding data bit ("0" or "1"); if the time interval is half of the reference value, it is considered a valid transition edge. If the current transition edge is a compensating transition edge, the state machine enters the WAIT state to wait for the next transition edge.

[0065] Continue monitoring in WAIT state The signal transitions again. Once a new transition edge is detected, the state machine enters the TOGGLE2 state and records the time interval of the transition edge again via the AK decoding counter. If the time interval at this time is also half of the reference value, it is considered that the transition edge has completed the double-edge characteristic compensation required for Manchester encoding, and the state machine then enters the DECODER state to complete the final parsing of the data bits.

[0066] Conversely, if a time interval is detected in the TOGGLE or TOGGLE2 state that is neither equal to the reference value nor half of the reference value, then... If the error occurs, the state machine will enter the ERROR state, indicating that there is a format or timing abnormality in the current decoding process, and triggering the corresponding error flag and diagnostic process.

[0067] Furthermore, if the expected transition edge is not detected in time during the entire decoding cycle, for example, due to sensor communication interruption or signal loss, causing the wheel speed counter T to exceed the preset maximum allowable cycle value, the state machine will enter the TIMEOUT state, generate a timeout exception flag, and notify the upper-level control module to respond to the fault. Thus, this hardware state machine, through rigorous state division and transition rules, can effectively identify different types of Manchester encoding patterns, while possessing strong fault tolerance and real-time response characteristics, thereby ensuring the reliability and accuracy of the decoding process.

[0068] For example, in practical applications, if the wheel speed sensor 14 uses the AK protocol to output a data stream with Manchester encoding, where each bit contains two edge transitions, then the hardware state machine will enter the START state on the first falling edge and latch the time base value. Then, upon the arrival of the first transition edge, it enters the TOGGLE state and determines whether the transition edge falls on the time base value. Half of it. If this is indeed the case, the state machine enters the WAIT state to wait for the second transition edge, and then confirms that it also occurred at the time base value. Halfway through the time, it enters the DECODER state to complete the data bit parsing. This demonstrates the state machine's ability to adapt to Manchester encoding characteristics and also showcases its ability to maintain stable communication in complex electromagnetic environments.

[0069] Research has found that in traditional wheel speed sensor signal decoding schemes, especially those relying on software decoding or general peripherals to acquire wheel speed data, the processor often needs to continuously check the status of relevant registers through a polling mechanism to determine whether a valid round of wheel speed information acquisition has been completed. This mechanism not only consumes a large amount of computing resources but may also cause delays in the response of critical control tasks, affecting the overall real-time performance of the system.

[0070] In view of this, such as Figure 11 As shown, the wheel speed detection device also includes an interrupt module 113; Interrupt module 113 is used to send a notification to the connected processor to read wheel speed information via an interrupt.

[0071] Therefore, after the wheel speed detection device completes the signal analysis from the wheel speed sensor 14 and outputs corresponding comparison signals through the first comparator 12 and the second comparator 13, the wheel speed information is extracted by the signal analyzer 11. This information is stored in an internal register, triggering the interrupt module 113 to generate an interrupt request. The function of the interrupt module 113 is to proactively notify the connected processor to read relevant data and status information in a timely manner when a specific event occurs (e.g., wheel speed count is valid, decoding error, timeout exception, etc.), rather than relying on the processor to periodically query whether the data is ready. Thus, the processor only intervenes when there is indeed data to read or when there is an abnormal situation, thereby significantly reducing unnecessary polling operations and improving the utilization efficiency of system resources.

[0072] like Figure 12 As shown, since the registers of the preprocessing module 111, signal parsing module 112, and interrupt module 113 all provide corresponding registers for users to configure and for the processor to read, the figure intuitively shows the interaction details between these modules and registers.

[0073] In summary, the wheel speed detection device provided in this embodiment achieves compatibility processing for three mainstream wheel speed sensor protocols: standard square wave, PWM, and AK. It eliminates the need to configure independent external decoding chips or dedicated circuits for different protocols, thereby significantly improving the system's protocol adaptability and development flexibility.

[0074] Secondly, by highly integrating functions such as signal conditioning, protocol parsing, and error diagnosis into the wheel speed detection device, and requiring only a simple external RC circuit to achieve current-to-voltage conversion, not only is the bill of materials cost reduced, but the printed circuit board area occupied is also reduced, further improving the system's integration and reliability.

[0075] At the same time, the core decoding function is implemented using hardware logic, which avoids the high consumption of processor resources by traditional software decoding schemes, significantly saves processor computing power, and reserves sufficient resource space for more complex control tasks.

[0076] Furthermore, regarding signal processing stability and security, the built-in filtering unit 1111, hysteresis comparison, and hardware state machine mechanism effectively enhance the anti-interference capability in complex electromagnetic environments. Simultaneously, the introduction of abundant error detection flags strengthens the system's diagnostic capabilities and fault response mechanisms, meeting the high requirements of functional safety levels (such as ASIL D). Finally, the wheel speed detection device adopts a modular design and standard register interface, allowing for flexible portability to different platforms. This facilitates rapid deployment and reuse within the vehicle control system, improving development efficiency and system scalability.

[0077] Based on the wheel speed detection device provided in the above embodiments, this embodiment also provides a chip system, which includes the wheel speed detection device and processor in the above embodiments.

[0078] This can be understood as achieving efficient acquisition, analysis, and processing of signals from various types of wheel speed sensors by encapsulating a wheel speed detection device with multi-protocol compatibility and a processor within a single chip. This chip system not only inherits the technical advantages of the aforementioned wheel speed detection device in terms of protocol adaptability, hardware resource utilization, and decoding efficiency, but also further enhances the system's security and diagnostic coverage.

[0079] In this embodiment, the chip system includes a processor and multiple parallel-configured wheel speed detection devices. Each wheel speed detection device is connected to a different wheel speed sensor 14 and independently performs signal conditioning, comparison, preprocessing, and decoding operations according to its own protocol characteristics (such as standard square wave, PWM, or AK). Furthermore, the chip system introduces a multi-module comparison and checking mechanism. This involves enabling a built-in comparison logic unit through register configuration to periodically or event-drivenly read the register data within each wheel speed detection device. The comparison logic unit performs consistency analysis on the acquired data. If a discrepancy is found between the wheel speed count values ​​or decoding results corresponding to different modules, a potential fault is identified.

[0080] For example, when multiple wheel speed detection devices are simultaneously connected to the wheel speed sensors 14 of the four wheels of the same vehicle, the wheel speed values ​​collected by each channel should maintain consistency within a reasonable range under normal circumstances. If a module's output wheel speed information becomes inconsistent with other modules due to external interference, hardware failure, or communication anomaly, the comparison logic unit will first set the global fault flag; then, it will record the identified problematic module number in a specific register; finally, it will decide whether to send an interrupt request to the processor according to the user-preconfigured interrupt policy, thereby notifying the upper-level control system to take timely countermeasures.

[0081] It's worth noting that the chip system can specifically be an MCU. Here, the MCU refers to an embedded control unit whose core architecture, in addition to the processor and wheel speed detection device mentioned above, can also include memory resources (such as Flash and RAM), timer / counter modules, communication interfaces, and various dedicated peripheral modules. In this architecture, the wheel speed detection device, as one of the configurable hardware functional modules, is directly integrated into the MCU's on-chip system and interacts with the processor via a standard bus interface.

[0082] The processor may be an integrated circuit chip with signal processing capabilities, and may include one or more processing cores (e.g., a single-core processor or a multi-core processor). By way of example only, the processor described above may include a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), an Application Specific Instruction-set Processor (ASIP), a Graphics Processing Unit (GPU), a Physics Processing Unit (PPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a controller, a microcontroller unit, a Reduced Instruction Set Computing (RISC) computer, or a microprocessor, or any combination thereof.

[0083] The above descriptions are merely various embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A wheel speed detection device, characterized in that, The wheel speed detection device includes a first comparator, a second comparator, and a signal analyzer; The first comparator and the second comparator are configured with different reference voltages, and the input terminals of the first comparator and the second comparator are used to receive voltage signals generated by the same wheel speed sensor. The signal parser is used to extract wheel speed information from the first comparison signal output by the first comparator and the second comparison signal output by the second comparator.

2. The wheel speed detection device according to claim 1, characterized in that, The reference voltage of the first comparator is greater than the reference voltage of the second comparator, and the signal parser includes a preprocessing module and a signal parsing module; The preprocessing module is used to perform an XOR operation on the first comparison signal and the second comparison signal to obtain a composite signal; and to acquire various edge trigger signals generated by the composite signal and the first comparison signal. The signal parsing module is used to parse the wheel speed information from the various edge-triggered signals.

3. The wheel speed detection device according to claim 2, characterized in that, The preprocessing module includes a filtering unit and a sampling unit; The filtering unit is used to perform an XOR operation on the first comparison signal and the second comparison signal to obtain a composite signal; and to filter the composite signal and the first comparison signal, and transmit the resulting filtered composite signal and the filtered comparison signal to the sampling unit. The sampling unit is used to sample the filtered composite signal and the filtered comparison signal to obtain the various edge trigger signals.

4. The wheel speed detection device according to claim 2, characterized in that, The preprocessing module includes a first input interface and a second input interface. The preprocessing module is connected to the output terminals of the first comparator and the second comparator through the first input interface. The second input interface is used to connect to a wheel speed sensor equipped with the first comparator and the second comparator. The wheel speed detection device also includes a mode configuration register for the preprocessing module, which is used to configure the preprocessing module to select between the first input interface and the second input interface.

5. The wheel speed detection device according to claim 2, characterized in that, The signal analysis module includes a counting unit and a decoding unit; The decoding unit is used to decode the wheel speed information based on the counting results of the counting unit on the various edge-triggered signals.

6. The wheel speed detection device according to claim 5, characterized in that, The wheel speed detection device supports wheel speed sensors with multiple protocols, and the wheel speed detection device also includes a protocol selection register of the counting unit and multiple counting registers provided for the multiple protocols; The counting unit is used to determine the target protocol from the multiple protocols based on the configuration information in the protocol selection register. According to the target protocol, a target edge trigger signal is selected from the plurality of edge trigger signals, and a target count register corresponding to the target protocol is selected from the plurality of count registers; The counting unit is also used to write the statistical results of the target's various edge-triggered signals into the target counting register.

7. The wheel speed detection device according to claim 6, characterized in that, The various protocols include the standard square wave protocol, the PWM protocol, and the AK protocol.

8. The wheel speed detection device according to claim 7, characterized in that, When the target protocol is the AK protocol, the decoding unit is used to obtain the duration of the composite signal from the counting unit when the first comparison signal generates a falling edge; and wait for the composite signal to generate a transition edge; Once the composite signal has a transition edge, the transition time interval of the composite signal is obtained from the counting unit; If the transition time interval is equal to the duration, it is determined to be a valid Manchester encoded edge, and the wheel speed information is decoded. If the transition time interval is half of the duration, then continue to wait for the next transition edge of the composite signal; Once the next transition edge of the composite signal is detected, the transition time interval of the next transition edge is obtained from the counting unit; If the transition time interval of the next transition edge is half of the duration, it is determined to be a valid Manchester encoded edge, and the wheel speed information is decoded.

9. The wheel speed detection device according to claim 1, characterized in that, The wheel speed detection device also includes an interrupt module; The interrupt module is used to send a notification to the connected processor to read the wheel speed information via an interrupt.

10. A chip system, characterized in that, It includes a processor and the wheel speed detection device according to any one of claims 1-9.

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