Switching value output system and method based on PCI bus

Abstract

The invention relates to a switching value output system and method based on a PCI bus, and the system comprises a circuit board, the circuit board is provided with a CPCI connector as an onboard connector, a signal and a power supply definition are defined according to a PCI standard, an FPGA chip is used as a control core of a main control unit, and PCI communication is completed by using a hardware description language; the input end of the main control unit is connected with the power supply unit through a PCI bus and a CPCI connector and is used for inputting; the main control unit is also connected with the debugging unit and is used for programming a hardware program of the main control unit; the main control unit is also connected with the OC output unit and is used for providing an output command to the OC output unit for execution by the main control unit; and the main control unit is also connected with the state monitoring unit, so that the state monitoring unit transmits the output recovery data to the main control unit. According to the invention, PCI bus communication can be completed by means of a customized platform, and switching value OC output and state monitoring are supported.

Description

Technical Field

[0001] This invention belongs to the field of PCI bus implementation technology of hardware description language, and relates to a switch output system and method, especially a switch output system and method based on PCI bus. Background Technology

[0002] The PCI bus, which emerged in the 1990s, is an excellent bus designed for multimedia technology. Its high performance, burst transmission, and plug-and-play capabilities have led to its widespread adoption, making it the de facto standard computer bus. Due to the PCI bus's prevalence and widespread use, both domestic and international companies are actively developing products based on the PCI bus interface, resulting in significant advancements in PCI bus technology.

[0003] There are two common ways to implement PCI interfaces: based on dedicated PCI interface bridge chips and based on FPGA soft cores.

[0004] (1) PCI interface bridge chip-based approach

[0005] Dedicated PCI interface bridge chips are relatively simple to use; their main function is to control the PCI protocol layer and related logic. However, the chip is fixed, lacking flexibility and configurability, directly impacting the overall system performance. Furthermore, they, along with the required configuration chips, occupy considerable board space. In addition, using dedicated chips often only utilizes a portion of the PCI interface functionality, resulting in some resource waste.

[0006] (2) Implementation based on FPGA soft core

[0007] The FPGA-based soft-core implementation uses a hardware programming language to implement the PCI bus at its underlying level. It leverages mature and proven hardware logic encapsulation. It is simple and convenient to use, with various configurations easily achievable without needing to understand the specifics of the PCI specification; only the IP core's usage needs to be known. Taking Xilinx as an example, its PCI IP core configuration interface is simple, efficient, and reliable. However, since most PCI IP cores are currently implemented by foreign manufacturers, their hardware program application is limited by the device model and manufacturer used, making them incompatible with some domestically designed FPGAs.

[0008] Therefore, this invention proposes a switching output system and method based on the PCI bus.

[0009] A search revealed no publicly available literature of the same or similar prior art as this invention. Summary of the Invention

[0010] The purpose of this invention is to overcome the shortcomings of the prior art and provide a PCI bus-based switch output system and method that can achieve PCI bus communication through a customized platform and support switch OC output and status monitoring functions.

[0011] The present invention solves its practical problem by adopting the following technical solution:

[0012] A PCI bus-based digital output system includes a circuit board with a CPCI connector as an onboard connector. The system defines signals and power supply according to the PCI standard, uses an FPGA chip as the control core of the main control unit, and uses a hardware description language to complete PCI communication.

[0013] The input terminal of the main control unit is connected to the power supply unit via a PCI bus and a CPCI connector for input.

[0014] The input terminal of the main control unit is connected to the clock unit to provide a reference clock for the main control unit;

[0015] The main control unit is also connected to the debugging unit for burning the main control unit hardware program;

[0016] The main control unit is also connected to the OC output unit, which is used to provide output commands from the main control unit to the OC output unit for execution.

[0017] The main control unit is also connected to the status monitoring unit, which is used for the status monitoring unit to transmit the output data back to the main control unit, and the main control unit to send the status display command to the status monitoring unit for execution.

[0018] Furthermore, the main control unit includes: an FPGA chip, a Flash module, a PCI bus-related logic module, a state machine, and a user logic module; the output of the Flash module is connected to the FPGA for storing hardware programs; the FPGA chip is used to run the hardware logic; the PCI bus-related logic module is connected to the state machine via a local bus for PCI bus timing control; the state machine is connected to the user logic module for transmitting read and write commands; the user logic module is connected to a status monitoring unit for sending status display commands to the status monitoring unit for execution; the status monitoring unit is connected to an OC output unit for the status monitoring unit to collect status signals from the output unit.

[0019] Furthermore, the user logic unit is connected to the debugging console via an OC output unit and a CPCI connector, and is used to convert output commands into OC output signals and transmit them to the debugging console.

[0020] Furthermore, the PCI bus-related logic modules are connected to the test bench via the PCI bus and CPCI connector for PCI communication between the main control unit and the test bench.

[0021] Furthermore, the debugging console is connected to the rear-output debugging board and is used to transmit the OC output signal to the rear-output debugging board, which then displays the output.

[0022] Furthermore, the debugging console is connected to a keyboard, mouse, and monitor, and is used to connect the keyboard, mouse, and monitor peripherals to the CPCI motherboard.

[0023] Furthermore, the debugging console is connected to the CPCI motherboard, which is used by the CPCI motherboard as a master device to connect to the PCI bus, and also provides peripheral interfaces for keyboard, mouse and monitor.

[0024] Furthermore, the rear-end debugging board is connected to the output channel of the digital output module via a CPCI connector and a debugging platform; the keyboard, mouse, and monitor are connected to the CPCI motherboard interface via the debugging platform. The CPCI motherboard and the digital output module are connected to the PCI bus via CPCI connectors, and respectively serve as the master and slave devices of the PCI bus.

[0025] A method for digital output based on a PCI bus includes the following steps:

[0026] Step 1: Upon initial power-on, the hardware program is downloaded to the FLASH memory of the main control unit via the debugging unit for hardening.

[0027] Step 2: During operation, after the DC power supply is powered on normally, it provides 28V DC power for output testing to the subsequent debugging board. The debugging platform powers the CPCI motherboard, which completes initialization and enters the Windows XP operating system, loading peripherals such as the keyboard, mouse, and monitor. At the same time, the debugging platform provides 5V DC power to the power supply unit of the digital output module. The power supply unit converts the 5V power to 3.3V, 1.8V, 1.2V, and 1.0V and provides them to the main control unit, clock unit, OC output unit, status monitoring unit, and debugging unit.

[0028] Step 3: After the clock unit is powered on, a 25MHz clock signal is provided to the dedicated clock pin of the FPGA as the reference clock for the main control unit.

[0029] Step 4: After the OC output unit is powered on, it waits for the output signal provided by the main control unit before outputting anything. The status monitoring unit collects the output status and sends it to the main control unit. Initially, all output statuses are high-level signals, indicating no external output.

[0030] Step 5: After the main control unit is powered on, the FPGA uses an active configuration method to load the program stored in the external FLASH.

[0031] Furthermore, the FPGA's internal program processing method in step 5 is as follows:

[0032] First, the unit is initialized, including software reset and register reset; the PCI device enumeration responds to the configuration operation of the PCI master device, reports information such as vendor ID, device ID, instruction, and status, and records the allocated read and write operation base address;

[0033] In the CPCI motherboard's operating system, a write operation is performed, sending the address and data to the designated register of the main control unit;

[0034] The main control unit sets the number in the specified register to a specific frequency for output, and the corresponding pin provides a high or low level output to the subsequent debugging board and status monitoring unit according to the set frequency.

[0035] The status monitoring unit provides the collected signals to the main control unit. The main control unit performs digital filtering on the collected signals, compares the filtered data with the data in the specified register, and reports its own status to the CPCI motherboard via PCI. At the same time, it outputs the status monitoring signal and the clock heartbeat signal to the status monitoring unit.

[0036] The indicator lights on the subsequent debugging board will turn on and off according to the output signal.

[0037] Advantages and beneficial effects of the present invention:

[0038] 1. This invention proposes a PCI bus-based switch output system and method, which uses the FPGA in the main control unit to implement the PCI bus, eliminating the need for a bridge chip and occupying less PCB space;

[0039] 2. This invention develops PCI bus functionality in FPGA based on actual needs, optimizes configuration, and consumes minimal FPGA resources;

[0040] 3. This invention uses a hardware programming language and can be implemented on chips from any manufacturer, without being dependent on a hardware platform. Attached Figure Description

[0041] Figure 1 This is a typical environmental architecture diagram of the PCI bus-based digital output system of the present invention;

[0042] Figure 2 This is a flowchart of the processing of the present invention. Detailed Implementation

[0043] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings:

[0044] A PCI bus-based digital output system includes a circuit board with a CPCI connector as an onboard connector. The system defines signals and power supply according to the PCI standard, uses an FPGA chip as the control core of the main control unit, and uses a hardware description language to complete PCI communication.

[0045] The input terminal of the main control unit is connected to the power supply unit via a PCI bus and a CPCI connector for input.

[0046] The input terminal of the main control unit is connected to the clock unit to provide a reference clock for the main control unit;

[0047] The main control unit is also connected to the debugging unit for burning the main control unit hardware program;

[0048] The main control unit is also connected to the OC output unit, which is used to provide output commands from the main control unit to the OC output unit for execution.

[0049] The main control unit is also connected to the status monitoring unit, which is used for the status monitoring unit to transmit the output data back to the main control unit, and the main control unit to send the status display command to the status monitoring unit for execution.

[0050] In this embodiment, the circuit board has a 6U CPCI structure, and the power supply for the circuit board is input through a CPCI connector.

[0051] In this embodiment, the FPGA chip is a PH1A100SFG676I7 type FPGA chip.

[0052] In this embodiment, the main control unit includes: an FPGA chip, a Flash module, a PCI bus-related logic module, a state machine, and a user logic module; the output of the Flash module is connected to the FPGA for storing hardware programs; the FPGA chip is used to run hardware logic; the PCI bus-related logic module is connected to the state machine via a local bus for PCI bus timing control; the state machine is connected to the user logic module for transmitting read and write commands; the user logic module is connected to a status monitoring unit for sending status display commands to the status monitoring unit for execution; the status monitoring unit is connected to an OC output unit for the status monitoring unit to collect status signals from the output unit.

[0053] In this embodiment, the user logic unit is connected to the debugging console via an OC output unit and a CPCI connector, and is used to convert output commands into OC output signals and transmit them to the debugging console;

[0054] In this embodiment, the PCI bus-related logic module is connected to the test bench via the PCI bus and CPCI connector for PCI communication between the main control unit and the test bench;

[0055] In this embodiment, the debugging console is connected to the rear-output debugging board and is used to transmit the OC output signal to the rear-output debugging board, which then displays the output.

[0056] In this embodiment, the debugging console is connected to a keyboard, mouse, and monitor, and is used to connect the keyboard, mouse, and monitor peripherals to the CPCI motherboard;

[0057] In this embodiment, the debugging console is connected to the CPCI motherboard, which is used to connect the CPCI motherboard as a master device to the PCI bus, and also provides peripheral interfaces for keyboard, mouse and monitor.

[0058] In this embodiment, the rear-output debugging board is connected to the output channel of the digital output module via a CPCI connector and a debugging platform; the keyboard, mouse, and monitor are connected to the CPCI motherboard interface via the debugging platform. The CPCI motherboard and the digital output module are connected to the PCI bus via CPCI connectors, and respectively serve as the master and slave devices of the PCI bus.

[0059] In this embodiment, the power supply unit consists of a power supply module and peripheral circuitry.

[0060] In this embodiment, the clock unit consists of a crystal oscillator and peripheral circuitry.

[0061] In this embodiment, the debugging unit consists of a JTAG interface.

[0062] In this embodiment, the OC output unit consists of a Darlington optocoupler and peripheral circuitry.

[0063] In this embodiment, the status monitoring unit consists of a transistor optocoupler and peripheral circuitry.

[0064] The functions and roles of each component within the system of this invention are further explained below:

[0065] like Figure 1 As shown, it implements circuits for OC output, status monitoring, and PCI bus. It includes a circuit board with an FPGA as its core, coupled with a Flash chip, optocoupler, and crystal oscillator to realize PCI bus function, OC output function, and status monitoring function.

[0066] The circuit board has a 6U CPCI structure, and the platform power supply is +5V through the CPCI connector on the baseboard.

[0067] The FPGA chip is a PH1A100SFG676I7 type FPGA chip;

[0068] The main control unit mainly consists of an FPGA, configuration Flash memory, and related peripheral circuits. Its main function is to implement all control logic operations and store related programs.

[0069] The main function of the power supply unit is to convert the 5V provided by the PCI bus into various voltage levels required by devices such as FPGAs and optocouplers.

[0070] The clock unit is a 25MHz crystal oscillator output to the dedicated clock pin of the FPGA. The clock signal is latched by the FPGA's PLL and converted into the on-chip clock for PCI, UART, system, etc. The clock signals and data are synchronized using mechanisms such as buffering and handshaking.

[0071] The debugging unit uses NSiP83086V, which enables the unit to communicate with the outside world via RS422 for debugging, testing and monitoring. The RS422 uses an on-board connector and is not brought out to the motherboard connector.

[0072] The OC output unit uses the Darlington optocoupler XNG452, which is a high-voltage optocoupler composed of a light-emitting diode and a Darlington transistor, providing two outputs: low-level or high-impedance state.

[0073] The status monitoring unit uses the XN817 optocoupler, which is composed of a light-emitting diode and a phototransistor. It re-samples the output OC status back to the FPGA to determine whether the output is correct, and at the same time provides response indications for clock heartbeat, PCI bus operation, bus error, etc.

[0074] A method for digital output based on a PCI bus includes the following steps:

[0075] Step 1: Upon initial power-on, the hardware program is downloaded to the FLASH memory of the main control unit via the debugging unit for hardening.

[0076] Step 2: During operation, after the DC power supply is powered on normally, it provides 28V DC power for output testing to the subsequent debugging board. The debugging platform powers the CPCI motherboard, which completes initialization and enters the Windows XP operating system, loading peripherals such as the keyboard, mouse, and monitor. At the same time, the debugging platform provides 5V DC power to the power supply unit of the digital output module. The power supply unit converts the 5V power to 3.3V, 1.8V, 1.2V, and 1.0V and provides them to the main control unit, clock unit, OC output unit, status monitoring unit, and debugging unit.

[0077] Step 3: After the clock unit is powered on, a 25MHz clock signal is provided to the dedicated clock pin of the FPGA as the reference clock for the main control unit.

[0078] Step 4: After the OC output unit is powered on, it waits for the output signal provided by the main control unit before outputting anything. The status monitoring unit collects the output status and sends it to the main control unit. Initially, all output statuses are high-level signals, indicating no external output.

[0079] Step 5: After the main control unit is powered on, the FPGA uses an active configuration method to load the program stored in the external FLASH.

[0080] The FPGA's internal program logic in step 5, such as Figure 2 As shown.

[0081] First, the unit is initialized, including software reset and register reset; the PCI device enumeration responds to the configuration operation of the PCI master device, reports information such as vendor ID, device ID, instruction, and status, and records the allocated read and write operation base address;

[0082] In the CPCI motherboard's operating system, a write operation is performed, sending the address and data to the designated register of the main control unit;

[0083] The main control unit sets the number in the specified register to a specific frequency for output, and the corresponding pin provides a high or low level output to the subsequent debugging board and status monitoring unit according to the set frequency.

[0084] The status monitoring unit provides the collected signals to the main control unit. The main control unit performs digital filtering on the collected signals, compares the filtered data with the data in the specified register, and reports its own status to the CPCI motherboard via PCI. At the same time, it outputs the status monitoring signal and the clock heartbeat signal to the status monitoring unit.

[0085] The indicator lights on the subsequent debugging board will turn on and off according to the output signal.

[0086] In summary, the PCI bus-based digital output system and method of the present invention can realize PCI bus functions by relying on a customized standard platform, and can support digital OC output function and status monitoring function.

[0087] The working principle of the present invention is:

[0088] This invention implements a PCI bus switch output system and method based on FPGA using hardware logic language. It implements the PCI protocol using FPGA hardware logic, specifically by using pure hardware logic language to implement the PCI timing and related logic operations to achieve protocol conversion. This approach allows for free modification of the PCI bus performance and configuration, enabling the porting of mature hardware logic to any chip with sufficient resources, without being limited by chip manufacturers. Furthermore, the program can be upgraded according to usage requirements without modifying the PCB or cutting down the hardware to save resources.

[0089] In addition to the basic functions of a general-purpose PCI board, this system also has functions such as OC output, automatic detection, and PCI bus fault diagnosis.

[0090] It should be emphasized that the embodiments described in this invention are illustrative rather than limiting. Therefore, this invention includes, but is not limited to, the embodiments described in the specific implementation. Any other implementations derived by those skilled in the art based on the technical solutions of this invention are also within the scope of protection of this invention.

Claims

1. A PCI bus-based digital output system, characterized in that: The circuit board includes a CPCI connector as an onboard connector. The signal and power definitions are based on the PCI standard. The FPGA chip is used as the control core of the main control unit, and the PCI communication is completed using a hardware description language. The input terminal of the main control unit is connected to the power supply unit via a PCI bus and a CPCI connector for input. The input terminal of the main control unit is connected to the clock unit to provide a reference clock for the main control unit; The main control unit is also connected to the debugging unit for burning the main control unit hardware program; The main control unit is also connected to the OC output unit, which is used to provide output commands from the main control unit to the OC output unit for execution. The main control unit is also connected to the status monitoring unit, which is used for the status monitoring unit to transmit the output data back to the main control unit, and the main control unit to send the status display command to the status monitoring unit for execution.

2. The PCI bus-based digital output system according to claim 1, characterized in that: The main control unit includes: an FPGA chip, a Flash module, a PCI bus-related logic module, a state machine, and a user logic module. The output of the Flash module is connected to the FPGA for storing hardware programs. The FPGA chip is used to run the hardware logic. The PCI bus-related logic module is connected to the state machine via a local bus for PCI bus timing control. The state machine is connected to the user logic module for transmitting read and write commands. The user logic module is connected to a status monitoring unit for sending status display commands to the status monitoring unit for execution. The status monitoring unit is connected to an OC output unit for the status monitoring unit to collect status signals from the output unit.

3. The PCI bus-based digital output system according to claim 1, characterized in that: The user logic unit is connected to the debugging console via an OC output unit and a CPCI connector, and is used to convert output commands into OC output signals and transmit them to the debugging console.

4. The PCI bus-based digital output system according to claim 1, characterized in that: The PCI bus-related logic modules are connected to the test bench via the PCI bus and CPCI connector for PCI communication between the main control unit and the test bench.

5. A PCI bus-based digital output system according to claim 1, characterized in that: The debugging platform is connected to the rear-output debugging board and is used to transmit the OC output signal to the rear-output debugging board, which then displays the output.

6. The PCI bus-based digital output system according to claim 1, characterized in that: The debugging console is connected to a keyboard, mouse, and monitor, and is used to connect the keyboard, mouse, and monitor peripherals to the CPCI motherboard.

7. A PCI bus-based digital output system according to claim 1, characterized in that: The debugging platform is connected to the CPCI motherboard, which is used by the CPCI motherboard as a master device to connect to the PCI bus, and also provides peripheral interfaces for keyboard, mouse and monitor.

8. A PCI bus-based digital output system according to claim 1, characterized in that: The rear-end debugging board is connected to the output channel of the digital output module via a CPCI connector and a debugging platform. The keyboard, mouse, and monitor are connected to the interface of the CPCI motherboard via the debugging platform. The CPCI motherboard and the digital output module are connected to the PCI bus via CPCI connectors and serve as the master and slave devices of the PCI bus, respectively.

9. A method for digital output based on a PCI bus, characterized in that: Includes the following steps: Step 1: Upon initial power-on, the hardware program is downloaded to the FLASH memory of the main control unit via the debugging unit for hardening. Step 2: During operation, after the DC power supply is powered on normally, it provides 28V DC power for output testing to the subsequent debugging board. The debugging platform powers the CPCI motherboard, which completes initialization and enters the Windows XP operating system, loading peripherals such as the keyboard, mouse, and monitor. At the same time, the debugging platform provides 5V DC power to the power supply unit of the digital output module. The power supply unit converts the 5V power to 3.3V, 1.8V, 1.2V, and 1.0V and provides them to the main control unit, clock unit, OC output unit, status monitoring unit, and debugging unit. Step 3: After the clock unit is powered on, a 25MHz clock signal is provided to the dedicated clock pin of the FPGA as the reference clock for the main control unit. Step 4: After the OC output unit is powered on, it waits for the output signal provided by the main control unit before outputting; the status monitoring unit collects the output status and sends it to the main control unit. Initially, the output status is all high-level signals, indicating that there is no external output. Step 5: After the main control unit is powered on, the FPGA uses an active configuration method to load the program stored in the external FLASH.

10. A method for switching output based on a PCI bus according to claim 9, characterized in that: The FPGA internal program processing method in step 5 is as follows: First, the unit is initialized, including software reset and register reset; the PCI device enumeration responds to the configuration operation of the PCI master device, reports information such as vendor ID, device ID, instruction, and status, and records the allocated read and write operation base address; In the CPCI motherboard's operating system, a write operation is performed, sending the address and data to the designated register of the main control unit; The main control unit sets the number in the specified register to a specific frequency for output, and the corresponding pin provides a high or low level output to the subsequent debugging board and status monitoring unit according to the set frequency. The status monitoring unit provides the collected signals to the main control unit. The main control unit performs digital filtering on the collected signals, compares the filtered data with the data in the specified register, and reports its own status to the CPCI motherboard via PCI. At the same time, it outputs the status monitoring signal and the clock heartbeat signal to the status monitoring unit. The indicator lights on the subsequent debugging board will turn on and off according to the output signal.

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