High-voltage LDO applied to battery management system

Abstract

The invention discloses a high-voltage LDO (Low Dropout Regulator) applied to a battery management system. The high-voltage LDO has two working modes of high performance and low power consumption. In the low-power-consumption working mode, the high-voltage LDO comprises a pre-voltage-stabilizing module, a band-gap reference circuit, a first-stage error amplifier, a buffer module, an off-chip power tube and a feedback circuit. In the high-performance working mode, the high-voltage LDO further comprises a second-stage error amplifier and an on-chip power tube. The ultra-wide voltage input range is supported, and the two working modes of high performance and low power consumption can be selected; in a high-performance working mode, all circuit structures of the high-voltage LDO are integrated in a chip, and the high-voltage LDO is designed without an off-chip capacitor and can supply power to the interior of the chip or supply power to the exterior of the chip; in the low-power-consumption working mode, power is supplied to the outside of the chip by driving the off-chip power tube; in a high-performance and low-power-consumption working mode, the pre-voltage-stabilizing module, the band-gap reference circuit, the first-stage error amplifier, the buffer module and the feedback circuit can be reused as common parts.

Description

Technical Field

[0001] This invention belongs to the field of battery management technology, and specifically relates to a high-voltage LDO applied to a battery management system. Background Technology

[0002] With the rapid development of new energy technologies, Battery Management Systems (BMS) are being driven by policies, technologies, market demand, and infrastructure construction in fields such as new energy vehicles and renewable energy storage, showing a very optimistic development prospect. New energy vehicles, in particular, will play an increasingly important role in future transportation. The Battery Monitoring Integrated Circuit (BMIC) is a major and critical component of the BMS, capable of monitoring battery status, ensuring safety and performance, and extending battery life. As a crucial component of the chip, the power management system provides stable power voltage support for the normal operation of other modules within the chip, and its design directly affects the operating status of other modules in the BMS. Especially in systems supporting multiple batteries connected in series, the power management system needs to achieve high efficiency, low noise, and reliable energy conversion under extreme voltage fluctuations, harsh environments, and safety constraints. Therefore, a high-voltage LDO (Low Dropout Voltage Regulator) supporting a wide input range is a more reasonable solution to these problems.

[0003] Figure 1 This is a common connection method for the LDO pins and off-chip board level circuits of mainstream battery management systems (BMS) from major companies in similar application scenarios. For example... Figure 1 As shown, this LDO has three main pins: VDRV, VREG, and GND. VDRV is the driver pin, used to drive the base of the external NPN transistor Q1. VREG is the feedback pin, also the pin for outputting a stable voltage. Internally, this pin is connected to the input of the operational amplifier via a negative feedback loop, providing a stable operating voltage. GND is the ground pin. The collector of the NPN transistor Q1 is connected to a 100Ω resistor, then directly to the external battery voltage VBAT. Simultaneously, a 0.1μF capacitor is connected to ground. The capacitor C_load and resistor R_load represent the equivalent impedance of the simulated load.

[0004] Currently, there is a considerable body of literature that presents relevant research on high-pressure LDOs.

[0005] The LDO designed in reference 1, “Sakolski O., Poongodan PK, Vanselow F., et al. A Feedforward Compensated High Voltage Linear Regulator With Fast Response, High-Current Siinking Capability[J]. IEEE Solid-State Circuits Letters, 2020,3: 114-117”, has a very high input voltage of 70V and a strong current-carrying capability (100mA). Due to its novel and simple circuit structure, the overall chip area is only 0.15mm². The LDO without external capacitor designed in reference 2, "Cheng Li, A high-performance LDO without external capacitor [J], Microelectronics & Computer, 2017, 34(10): 119-122", has a static current of only 50uA when the maximum load current reaches 100mA. Since it does not require external capacitors to help stabilize the system, it has a wider range of applications. The wide input range LDO designed in reference 3, "Wei X., Liu W., Zhang Z., et al. A Wide Input Voltage Range LDO with Fast Transient Response [C]. 2023 6th International Conference on Electronics Technology (ICET) Chengdu, China: IEEE, 2023:114-119", has an input voltage range of 8V~45V and a maximum load current of 50mA, which meets the requirements of power chips with wide input range and certain driving capability in multi-cell series battery management systems.

[0006] However, the high-voltage LDO described in the above literature has the following problems: Although the LDO designed in Reference 1 has a high input voltage, its output voltage is also very high, reaching 66V. The overall application of the LDO is limited to power supply of the high-voltage side circuit, which does not meet the application requirements of high input voltage and low output voltage; moreover, with a maximum load current of 100mA, its quiescent current reaches 288μA, which does not meet the application requirements of low quiescent power consumption.

[0007] Although the LDO without external capacitors designed in Reference 2 meets the design requirements of ultra-low power consumption, its input voltage is only 1.2V ~ 2V, which does not meet the requirement of a wide input voltage range.

[0008] The wide input range LDO designed in Reference 3 does not mention the static power consumption of the circuit in the original text, and requires a 3μF off-chip capacitor to help stabilize the circuit system, which limits its application range. Summary of the Invention

[0009] To address the aforementioned problems in the prior art, this invention provides a high-voltage LDO applied to a battery management system. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a high-voltage LDO for use in a battery management system, wherein the high-voltage LDO has two operating modes: high performance and low power consumption; wherein, In low-power operation mode, the high-voltage LDO includes a pre-regulator module, a bandgap reference circuit, a first-stage error amplifier, a buffer module, an off-chip power transistor, and a feedback circuit; wherein, The system includes: a pre-regulator module to provide the internal operating voltage; a bandgap reference circuit to generate a reference voltage under the internal operating voltage; a first-stage error amplifier to compare and amplify the first output sampling voltage with the reference voltage under the internal operating voltage to obtain the first-stage error amplification signal; wherein the first-stage error amplifier has high DC gain characteristics; a buffer module to enhance the driving capability of the first-stage error amplifier under both internal and external operating voltages, and to split the low-frequency pole at the connection point when the first-stage error amplifier and the external power transistor are directly connected into two high-frequency poles, facilitating frequency compensation for the entire high-voltage LDO; and a feedback circuit to act as a feedback loop between the first-stage error amplifier and the external power transistor, stabilizing the output voltage generated at the load output terminal based on the first-stage error amplification signal, and providing the first output sampling voltage for the first-stage error amplifier. In high-performance operating mode, the high-voltage LDO also includes a second-stage error amplifier and an on-chip power transistor; wherein, The second-stage error amplifier compares and amplifies the second output sampling voltage and the first error amplification signal under the internal operating voltage to obtain the second-stage error amplification signal. The first-stage and second-stage error amplifiers work together to give the entire high-voltage LDO high DC gain and wide bandwidth characteristics. The buffer module enhances the driving capability of the second-stage error amplifier under both internal and external operating voltages and splits the low-frequency pole at the connection point (when the second-stage error amplifier and the on-chip power transistor are directly connected) into two high-frequency poles, facilitating frequency compensation for the entire high-voltage LDO. The feedback circuit serves as a feedback loop between the first-stage error amplifier and the on-chip power transistor, and between the second-stage error amplifier and the on-chip power transistor, stabilizing the output voltage generated at the load output based on the second-stage error amplification signal and providing the second output sampling voltage to the second-stage error amplifier.

[0010] In one embodiment of the present invention, the bandgap reference circuit includes transistors Q11 to Q13, resistors R11 to R19, a trimming resistor R_Trim, transistor NM11, transistors PM10 to PM19, and a differential amplifier OA; wherein, The emitter of transistor Q11 is connected to one end of resistor R11. The base of transistor Q11 is connected to the base of transistor Q12, one end of resistor R17, and the source of transistor NM11. The collector of transistor Q11 is connected to one end of resistor R12 and the negative input terminal of differential amplifier OA. The emitter of transistor Q12 is connected to the other end of resistor R11, the collector of transistor Q13, and the base of transistor Q12. The collector of transistor Q12 is connected to one end of resistor R13 and the non-inverting input terminal of differential amplifier OA. The emitter of transistor Q13 is connected to resistor R14. One end of resistor R12 is connected to the gate of transistor PM17 and the gate of transistor PM18. The other end of resistor R12 is connected to the other end of resistor R13, the source of transistor PM11, the source of transistor PM12, and the source of transistor PM14. The other end of resistor R14 is connected to one end of the trimming resistor R_Trim. The other end of trimming resistor R_Trim is connected to one end of resistor R15, the drain of transistor PM17, and the drain of transistor PM19. The other end of resistor R15, one end of resistor R19, the drain of transistor PM16, and the drain of transistor PM18 are all connected to... Grounded, one end of resistor R16 is connected to the drain of transistor PM10, the gate of transistor PM11, the gate of transistor PM12, and the gate of transistor PM14; the other end of resistor R16 is connected to the drain of transistor NM11, the gate of transistor PM10, the gate of transistor PM13, and the gate of transistor PM15; the gate of transistor PM12 is connected to the gate of transistor PM13; the gates of transistor PM14 and PM15 are connected; the gate of transistor NM11 is connected to the output terminal of differential amplifier OA; the other end of resistor R17 is connected to... One end of resistor R18 is connected to the gate of transistor PM16. The other end of resistor R18 is connected to the other end of resistor R19 and the gate of transistor PM19. The drain of transistor PM11 is connected to the source of transistor PM10. The drain of transistor PM12 is connected to the source of transistor PM13. The drain of transistor PM13 is connected to the source of transistor PM16 and the source of transistor PM17. The drain of transistor PM14 is connected to the source of transistor PM15. The drain of transistor PM15 is connected to the source of transistor PM18 and the source of transistor PM19.

[0011] In one embodiment of the present invention, the feedback circuit includes a first adjustable variable resistor structure RT1, a second adjustable variable resistor structure RT2, resistors R1 and R2, switch J1, and switch J2; wherein, One end of the first adjustable resistor structure RT1 is connected to one end of the second adjustable resistor structure RT2 and the on-chip power transistor. The other end of the first adjustable resistor structure RT1 is connected to one end of switch J1. The other end of the second adjustable resistor structure RT2 is connected to one end of switch J2. The other end of switch J1 is connected to the other end of switch J2, one end of resistor R1, and the second-stage error amplifier. The other end of resistor R1 is connected to one end of resistor R2 and the first-stage error amplifier. The other end of resistor R2 is grounded. By controlling the on and off states of switches J1 and J2, a feedback loop is formed between the first-stage error amplifier and the external power transistor in low-power operating mode, and a feedback loop is formed between the first-stage error amplifier and the on-chip power transistor, and between the second-stage error amplifier and the on-chip power transistor in high-performance operating mode.

[0012] In one embodiment of the present invention, the first adjustable variable resistor structure RT1 includes a plurality of resistors and a plurality of NMOS transistors. By controlling the on and off states of all NMOS transistors, resistors are selectively connected to change the feedback coefficient of the feedback circuit.

[0013] In one embodiment of the present invention, the second adjustable resistor structure RT2 is based on the first adjustable resistor structure RT1, with an NPN transistor connected to a diode added at the input terminal, so as to weaken the negative temperature change characteristics of the output voltage of the high voltage LDO in the low power consumption operating mode.

[0014] In one embodiment of the present invention, the off-chip power transistor is an NPN transistor. The base of the NPN transistor is connected to the output terminal of the buffer module, the collector of the NPN transistor is connected to an external power supply that provides an external operating voltage through a resistor, and the emitter of the NPN transistor is connected to the load circuit.

[0015] In one embodiment of the present invention, the on-chip power transistor is an NMOS transistor. The gate of the NMOS transistor is connected to the output terminal of the buffer module, the source of the NMOS transistor is connected to the feedback circuit, and the drain of the NMOS transistor is connected to an external power supply that provides the external operating voltage.

[0016] In one embodiment of the present invention, the second-stage error amplifier is short-circuited in low-power operating mode via switch S1, so that the first-stage error amplifier and the buffer module are directly connected. In high-performance operating mode, the second-stage error amplifier is connected, so that the first-stage error amplifier, the second-stage error amplifier, and the buffer module are connected in sequence.

[0017] In one embodiment of the present invention, by selecting switch T1, connection to an external power transistor is selected in low-power operating mode, and connection to an on-chip power transistor is selected in high-performance operating mode.

[0018] In one embodiment of the present invention, the control signals for switches J1, J2, S1, and selection switch T1 are all provided by an off-chip MCU. The off-chip MCU generates corresponding control signals according to the requirements of the high-voltage LDO for high-performance operating mode and low-power operating mode.

[0019] The beneficial effects of this invention are: This invention proposes a high-voltage LDO for battery management systems, supporting an ultra-wide input voltage range of 15V to 80V and offering two operating modes: high performance and low power consumption. Both modes support adjustable output voltages of 3.3V and 5.0V. In high-performance mode, the entire circuitry of the high-voltage LDO is integrated on-chip, eliminating the need for external capacitors. It can power internal or external modules, supporting a maximum load of 50mA, thus solving the problem of power supply coordination in battery management systems and demonstrating strong applicability. In low-power mode, stable power supply to external modules is achieved by driving an external power transistor. The low-power mode also supports a maximum output load current of 50mA, while consuming less than 5μA of quiescent current internally. In both high-performance and low-power modes, the pre-regulator module, bandgap reference circuit, first-stage error amplifier, buffer module, and feedback circuit can be reused as common parts, saving chip design area. In summary, this invention solves many limitations of current high-voltage LDOs, such as insufficient input voltage range, low static power consumption, and the need for external capacitors to help stabilize the system. The designed high-voltage LDO supports a wider input voltage range and lower static power consumption, supports power supply for both on-chip and off-chip modules, and has an adjustable output voltage. It combines high-performance and low-power operating modes to better meet the power supply design requirements in battery management systems, making it more practical and expanding its application scope.

[0020] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the common connection method between LDO pins and off-chip circuits used in existing battery management systems; Figure 2 This is a schematic diagram of a high-voltage LDO applied to a battery management system provided in an embodiment of the present invention; Figure 3 This is a specific circuit diagram of the bandgap reference circuit in a high-voltage LDO applied to a battery management system, provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the segmented compensation effect of the bandgap reference circuit provided in an embodiment of the present invention; Figure 5This is a schematic diagram showing the change of the bandgap reference output voltage as a function of temperature in the bandgap reference circuit provided in this embodiment of the invention; Figure 6 This is a schematic diagram of the feedback circuit in the high-performance operating mode provided in the embodiments of the present invention; Figure 7 This is a schematic diagram of the feedback circuit in the low-power operating mode provided in the embodiment of the present invention; Figure 8 This is a simplified circuit diagram of a high-voltage LDO applied to a battery management system in high-performance operating mode, as provided in an embodiment of the present invention. Figure 9 This is a simplified circuit diagram of a high-voltage LDO applied to a battery management system in a low-power operating mode, as provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of the simulation results of a high-voltage LDO applied to a battery management system over a wide input voltage range, provided by an embodiment of the present invention. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0023] Please see Figure 1 This invention provides a high-voltage LDO for use in a battery management system, wherein the high-voltage LDO has two operating modes: high performance and low power consumption; wherein, In low-power operation mode, the high-voltage LDO includes a pre-regulation module, a bandgap reference circuit, a first-stage error amplifier, a buffer module, an off-chip power transistor, and a feedback circuit; among which... The system includes: a pre-regulator module to provide the internal operating voltage; a bandgap reference circuit to generate a reference voltage under the internal operating voltage; a first-stage error amplifier to compare and amplify the first output sampling voltage and the reference voltage under the internal operating voltage to obtain the first-stage error amplification signal; the first-stage error amplifier has high DC gain characteristics; a buffer module to enhance the driving capability of the first-stage error amplifier under both internal and external operating voltages, and to split the low-frequency pole at the connection point when the first-stage error amplifier and the external power transistor are directly connected into two high-frequency poles, facilitating frequency compensation for the entire high-voltage LDO; and a feedback circuit to act as a feedback loop between the first-stage error amplifier and the external power transistor, stabilizing the output voltage generated at the load output terminal based on the first-stage error amplification signal, and providing the first output sampling voltage for the first-stage error amplifier. In high-performance operating mode, the high-voltage LDO also includes a second-stage error amplifier and on-chip power transistors; among which, The second-stage error amplifier compares and amplifies the second output sampling voltage and the first error amplification signal under the internal operating voltage to obtain the second-stage error amplification signal. The first-stage and second-stage error amplifiers work together to give the entire high-voltage LDO high DC gain and wide bandwidth characteristics. The buffer module enhances the driving capability of the second-stage error amplifier under both internal and external operating voltages and splits the low-frequency pole at the connection point (if the second-stage error amplifier and the on-chip power transistor are directly connected) into two high-frequency poles, facilitating frequency compensation for the entire high-voltage LDO. The feedback circuit serves as a feedback loop between the first-stage error amplifier and the on-chip power transistor, and between the second-stage error amplifier and the on-chip power transistor, stabilizing the output voltage generated at the load output based on the second-stage error amplification signal and providing the second output sampling voltage for the second-stage error amplifier.

[0024] Next, each part will be introduced in detail.

[0025] like Figure 2 As shown, the external chip of this embodiment of the invention utilizes existing... Figure 1 The circuit structure shown uses discrete components that work in conjunction with the chip in the application, where the NPN transistor Q1 is an off-chip power transistor. Figure 2 The gray dashed box in the middle shows the internal modules of the chip, including: pre-regulator module, bandgap reference circuit, first-stage error amplifier EA1, second-stage error amplifier EA2, buffer module, on-chip power transistor HV_NM0, and feedback circuit.

[0026] The pre-regulator module consists of a low-precision bandgap reference and a low-precision LDO, directly connected to an external power supply connected in series to provide the external operating voltage VBAT. It outputs a relatively low internal operating voltage VDD to power other low-voltage modules within the chip, such as the bandgap reference circuit, the first-stage error amplifier EA1, the second-stage error amplifier EA2, and the buffer module. The bandgap reference circuit provides a precise reference voltage. The first-stage error amplifier EA1 internally forms a folded cascode operational amplifier to provide high DC gain, i.e., it has high DC gain characteristics. The second-stage error amplifier EA2 internally consists of a five-transistor OTA (Operational Voltage Regulator). The operational transconductance amplifier (ECA) provides a large bandwidth, i.e., it has a wide bandwidth characteristic. The first-stage error amplifier EA1 and the second-stage error amplifier EA2 work together to give the entire high-voltage LDO high DC gain and wide bandwidth characteristics. The buffer module is an internally dynamically biased super source follower. Due to its small input transistor size and extremely small output impedance, it can split the low-frequency pole between the original error amplifier and the power transistor into two high-frequency poles, thereby facilitating frequency compensation and achieving stable system operation. At the same time, the buffer module in this embodiment is powered by two power supplies, which reduces the use of high-voltage devices and increases the output voltage range. The feedback network composed of RT1, RT2, R1, and R2 forms a negative feedback stable output voltage.

[0027] The bandgap reference circuit of the present invention is as follows: Figure 3 As shown, it includes transistors Q11 to Q13, resistors R11 to R19, adjustment resistor R_Trim, transistor NM11, transistors PM10 to PM19, and differential amplifier OA; among which, The emitter of transistor Q11 is connected to one end of resistor R11. The base of transistor Q11 is connected to the base of transistor Q12, one end of resistor R17, and the source of transistor NM11. The collector of transistor Q11 is connected to one end of resistor R12 and the negative input terminal of differential amplifier OA. The emitter of transistor Q12 is connected to the other end of resistor R11, the collector of transistor Q13, and the base of transistor Q12. The collector of transistor Q12 is connected to one end of resistor R13 and the non-inverting input terminal of differential amplifier OA. The emitter of transistor Q13 is connected to one end of resistor R14. The gate of transistor PM17 and the gate of transistor PM18 are connected. The other end of resistor R12 is connected to the other end of resistor R13, the source of transistor PM11, the source of transistor PM12, and the source of transistor PM14. The other end of resistor R14 is connected to one end of the trimming resistor R_Trim. The other end of the trimming resistor R_Trim is connected to one end of resistor R15, the drain of transistor PM17, and the drain of transistor PM19. The other end of resistor R15, one end of resistor R19, the drain of transistor PM16, and the drain of transistor PM18 are all connected to... Ground, one end of resistor R16 is connected to the drain of transistor PM10, the gate of transistor PM11, the gate of transistor PM12, and the gate of transistor PM14; the other end of resistor R16 is connected to the drain of transistor NM11, the gate of transistor PM10, the gate of transistor PM13, and the gate of transistor PM15; the gate of transistor PM12 is connected to the gate of transistor PM13; the gates of transistor PM14 and PM15 are connected; the gate of transistor NM11 is connected to the output terminal of differential amplifier OA; the other end of resistor R17 is connected to... One end of resistor R18 is connected to the gate of transistor PM16. The other end of resistor R18 is connected to the other end of resistor R19 and the gate of transistor PM19. The drain of transistor PM11 is connected to the source of transistor PM10. The drain of transistor PM12 is connected to the source of transistor PM13. The drain of transistor PM13 is connected to the source of transistor PM16 and the source of transistor PM17. The drain of transistor PM14 is connected to the source of transistor PM15. The drain of transistor PM15 is connected to the source of transistor PM18 and the source of transistor PM19.

[0028] Figure 3The designed bandgap reference circuit, with its bandgap reference output voltage VBG, can not only provide a high-precision bandgap reference voltage as a reference voltage for the first-stage error amplifier, but also provide a bandgap voltage reference for other modules in the battery management system, such as the ADC (Analog-Digital Converter). The ADC requires a 2.5V bandgap reference voltage with a temperature drift coefficient of less than 5ppm / ℃, while the output voltage of a conventional voltage-mode bandgap reference is around 1.25V. Bandgap reference voltages higher than 1.25V need to be generated through a current-mode bandgap reference. However, the current-mode bandgap reference has an additional current branch compared to the voltage-mode bandgap reference, resulting in higher static power consumption. Therefore, this invention proposes... Figure 3 The bandgap reference circuit shown uses a diode-connected transistor in the voltage-mode bandgap reference. Figure 3 The transistor Q13 in the circuit enables a 2.5V reference voltage to be output even with a bandgap reference in a voltage-mode architecture, reducing the circuit's static power consumption. The temperature drift coefficient of an uncompensated bandgap reference is typically above 10ppm / ℃. The purpose of high-order compensation is to correct the uncompensated output reference voltage's temperature-dependent curve from an approximately downward-opening parabola to a curve with more uniformly distributed extreme points within the same temperature range. The more extreme points and the more uniform their distribution, the "flatter" the reference voltage curve, resulting in a smaller temperature drift coefficient. Segmented compensation is one type of high-order compensation method; the more segmented points in the compensation, the better the compensation effect. Generally, segmented compensation circuits work by biasing the static operating point of the differential pair transistors in the subthreshold region and using dynamic adjustment to continuously adjust the compensation current I_COM based on the change in the positive temperature coefficient voltage VPTAT, achieving high-order compensation of the bandgap reference output voltage VBG and reducing the temperature drift coefficient of the reference voltage. VL and VH are the compensation segmentation points set based on the first-order compensation results, and their voltages hardly change with temperature; VPTAT is the positive temperature coefficient voltage. When the positive temperature coefficient voltage VPTAT is between VL and VH, the compensation current I_COM is almost zero; however, when the positive temperature coefficient voltage VPTAT is less than VL or greater than VH, the compensation current I_COM changes exponentially with temperature, quickly exceeding the uncompensated bandgap reference output voltage VBG (approximately a quadratic function), thus raising the voltage that was originally reduced in the low and high temperature regions. The effect of segmented compensation is as follows: Figure 4 As shown, Figure 4 The horizontal axis represents temperature, and the vertical axis represents the bandgap reference output voltage VBG: the gray dashed line is the curve of the uncompensated bandgap reference voltage VBG changing with temperature, approximately a downward-opening parabola; the black dashed line is the VBG voltage curve after piecewise compensation at two segmented points. At temperatures b and c, the positive temperature coefficient voltage VPATA is equal to VL and VH, respectively. In this embodiment of the invention... Figure 3 In this circuit, by biasing the quiescent operating points of the differential pair transistors PM16~PM19 near the cutoff region, when the temperature is below point a or above point d, the rate of increase of the compensation current slows down, and the trend of the bandgap reference output voltage VBG reverts to being dominated by the uncompensated circuit, with the voltage showing a decreasing trend to the left of point a and to the right of point d. Thus, by simply changing the quiescent operating points of the input differential pair transistors, two more extreme points can be added to the bandgap reference output voltage VBG within the same temperature range, such as... Figure 4 As shown by the solid black line, this achieves a lower temperature drift coefficient. And to achieve this... Figure 4 The effect of the solid black line in the middle shows that segmented compensation requires setting four segmented compensation points. Therefore, the design of this embodiment saves the static current consumption of the two compensation branches composed of PM16, PM17, and PM18, PM19 respectively, further reducing power consumption and saving chip area. The bandgap reference output voltage VBG of the bandgap reference circuit of this invention changes with temperature at a typical process corner as follows: Figure 5 As shown, the temperature drift coefficient at this time is 0.9 ppm / ℃. Figure 5 The horizontal axis represents temperature, and the vertical axis represents the bandgap reference output voltage VBG.

[0029] The bandgap reference circuit designed in this invention achieves segmented compensation, reaching a compensation effect that would otherwise require more complex compensation circuits, higher power consumption, and larger area. Furthermore, while achieving an ultra-low temperature drift coefficient, it saves chip area and further reduces system power consumption. The ingenious use of the diode-connected NPN transistor Q13 reduces the output voltage temperature drift coefficient of the proposed high-voltage LDO in low-power operating mode, effectively mitigating the negative temperature characteristic of the base-emitter voltage of the off-chip NPN transistor Q1. Simultaneously, it improves the output voltage compared to the traditional voltage-mode bandgap reference. Moreover, the voltage-mode architecture provides the required bandgap reference voltage for the system, representing a novel low-power design.

[0030] The feedback circuit in the embodiments of the present invention is as follows: Figure 2 As shown, it includes a first adjustable variable resistor structure RT1, a second adjustable variable resistor structure RT2, resistors R1 and R2, switch J1, and switch J2; wherein, One end of the first adjustable resistor structure RT1 is connected to one end of the second adjustable resistor structure RT2 and the on-chip power transistor. The other end of the first adjustable resistor structure RT1 is connected to one end of switch J1. The other end of the second adjustable resistor structure RT2 is connected to one end of switch J2. The other end of switch J1 is connected to the other end of switch J2, one end of resistor R1, and the second-stage error amplifier. The other end of resistor R1 is connected to one end of resistor R2 and the first-stage error amplifier. The other end of resistor R2 is grounded. By controlling the on and off states of switches J1 and J2, a feedback loop is formed between the first-stage error amplifier and the off-chip power transistor in the low-power operating mode. In the high-performance operating mode, feedback loops are formed between the first-stage error amplifier and the on-chip power transistor, and between the second-stage error amplifier and the on-chip power transistor.

[0031] The first adjustable variable resistor structure RT1 in this embodiment of the invention is as follows: Figure 6 As shown, the circuit includes several resistors and several NMOS transistors. Resistors are selectively connected by controlling the on / off state of all NMOS transistors to change the feedback coefficient of the feedback circuit. For example, Figure 6 In this control scheme: if NMOS transistor NM21 is turned on, resistor R21 is connected, and resistor R22 is not connected; if NMOS transistor NM21 is turned off and NMOS transistor NM22 is turned on, both resistors R21 and R22 are connected. Similar control methods can be used to connect different combinations of resistors to change the feedback coefficient of the feedback circuit.

[0032] The second adjustable variable resistance structure RT2 in this embodiment of the invention is as follows: Figure 7 As shown, based on the first adjustable resistor structure RT1, an NPN transistor connected to a diode is added to the input terminal, such as... Figure 7 The transistor Q0 in the middle is used to reduce the negative temperature variation characteristics of the output voltage of the high-voltage LDO in low-power operation mode.

[0033] In this embodiment of the invention, the off-chip power transistor is an NPN type transistor, such as... Figure 2 In this embodiment, an NPN transistor Q1 is used as the power transistor. The base of Q1 is connected to the output of the buffer module, the collector is connected to an external power supply providing the external operating voltage via a resistor, and the emitter is connected to the load circuit. NPN transistors are used externally as power transistors in this embodiment. They offer suitable quiescent current and a large load current capability, along with fast response speed. Furthermore, their external placement provides excellent heat dissipation.

[0034] In this embodiment of the invention, the on-chip power transistor is an NMOS transistor, such as... Figure 2In the circuit, the gate of NMOS transistor HV_NM0 is connected to the output of the buffer module, the source of NMOS transistor HV_NM0 is connected to the feedback circuit, and the drain of NMOS transistor HV_NM0 is connected to the external power supply providing the external operating voltage. This embodiment of the invention uses an NMOS transistor as the power transistor on-chip. NMOS transistors have very low quiescent current and suitable load current capability; at the same time, because they are integrated inside the chip, the cost of the entire circuit is reduced.

[0035] In this embodiment of the invention, switch S1 selects to short-circuit the second-stage error amplifier in low-power operation mode, directly connecting the first-stage error amplifier and the buffer module. In high-performance operation mode, it selects to connect the second-stage error amplifier, connecting the first-stage error amplifier, the second-stage error amplifier, and the buffer module sequentially. In this embodiment of the invention, switch T1 selects to connect to an external power transistor in low-power operation mode and to an internal power transistor in high-performance operation mode. The control signals for switches J1, J2, S1, and T1 are all provided by an external MCU (Microcontroller Unit). The external MCU generates corresponding control signals based on the high-voltage LDO's requirements for high-performance and low-power operation modes. Typically, combining the two operation modes sacrifices some chip area and power consumption. However, this embodiment of the invention effectively reduces chip area by multiplexing the pre-regulator module, bandgap reference circuit, first-stage error amplifier, buffer module, and feedback circuit in both operation modes.

[0036] Through the circuit design described above, the high-voltage LDO proposed in this invention supports two operating modes: a high-performance operating mode and a low-power operating mode. Specifically: In high-performance operating mode, both the first-stage error amplifier EA1 and the second-stage error amplifier EA2 in Figure 2 are operational. Simultaneously, switch S1 is open, and the output of the second-stage error amplifier EA2 is connected to the input of the buffer module. Selector switch T1 is connected to point 2, and the output of the buffer module is connected to the gate of the on-chip power transistor HV_NM0. Switch S2 is closed, the VDRV drive port is short-circuited to ground, and the external power transistor Q1 is turned off. Switch J1 is closed, and switch J2 is open. The feedback circuit in high-performance operating mode is composed of the first adjustable variable resistor structure RT1, resistor R1, and resistor R2. A simplified structure in high-performance operating mode is shown below. Figure 8 As shown in the figure. This LDO structure is a dual-loop LDO. Unlike ordinary LDOs, this LDO has both high DC gain and large bandwidth, ensuring high accuracy and fast load switching response.

[0037] In low-power operating mode, Figure 2The second-stage error amplifier module EA2 is not working. Simultaneously, switch S1 is closed, and the output of the first-stage error amplifier EA1 is directly connected to the input of the buffer module. Selector switch T1 is connected to point 1, and the output of the buffer module is connected to the VDRV drive port, i.e., the base of the external power transistor Q1. Switch J1 is open, and switch J2 is closed. The feedback circuit in low-power mode consists of the second adjustable variable resistor structure RT2 and resistor R2. The structure in low-power mode is as follows: Figure 9 As shown.

[0038] As shown above, in high-performance operating mode, the high-voltage LDO proposed in this invention is a dual-loop LDO without external capacitors. In this mode, the LDO can power other modules in the Battery Management System (BMS) and also supply power externally through the VREG feedback port. Simulation results show that the maximum load current reaches 50mA, and the static current is controlled within 55μA. Furthermore, it can be controlled by control signals provided by the external MCU. Figure 6 The on / off state of the NMOS transistor is controlled to change the feedback coefficient of the feedback circuit, achieving an adjustable output voltage of 3.3V / 5.0V, which offers excellent application convenience. Due to the structural advantages of its dual-loop LDO, in addition to the high accuracy and fast load switching response brought by high DC gain and large bandwidth, the naturally generated zero that follows the dominant pole also greatly reduces the difficulty and cost of frequency compensation.

[0039] In low-power operation mode, the high-voltage LDO proposed in this invention uses an off-chip NPN transistor Q1 as the power transistor, and can also be controlled by a control signal provided by an off-chip MCU. Figure 7 The on / off state of the NMOS transistor is controlled to change the feedback coefficient of the feedback network, thereby achieving an adjustable output voltage of 3.3V / 5.0V. In this mode, it can supply power externally, and simulation results show that with a maximum load current of 50mA, only 3.5μA of quiescent current is consumed internally. Because it uses an external NPN transistor Q1 as the power transistor, the heat generation problem under heavy load is effectively solved. Also, due to the inherent characteristics of the external NPN transistor Q1, its base-emitter voltage VBE exhibits a negative temperature characteristic with changes in external temperature. Therefore, this invention specifically incorporates a diode-connected NPN transistor Q0 in the feedback circuit to mitigate the negative temperature characteristic of the circuit's output voltage to some extent.

[0040] The simulation results of this invention in low-power operating mode with an input voltage range of 0~80V are as follows: Figure 10 As shown. Figure 10 In the right-hand graph, the horizontal axis represents the battery voltage of the external power source. Figure 1In the diagram, VBAT is the vertical axis, representing the output voltage of the high-voltage LDO set to 5V output mode. Figure 10 As shown in the diagram on the right, the high-voltage LDO can operate normally when the battery voltage rises to approximately 7.6V. The LDO can operate normally within the range of 7.6V to 80V, verifying that the high-voltage LDO proposed in this invention is an LDO that supports a wide input voltage range. Figure 10 The different colors in the left-hand diagram indicate that the above conclusions hold true under different process angles and operating temperatures during manufacturing. Therefore, it can be concluded that the high-voltage LDO proposed in this invention can stably establish a normal output voltage across a wide input range of 7.6V to 80V, under conditions of full process angles and -40℃ to 85℃.

[0041] In summary, the high-voltage LDO proposed in this embodiment of the invention for use in battery management systems supports an ultra-wide voltage input range of 15V to 80V and offers two selectable operating modes: high performance and low power consumption. Both modes support adjustable output voltages of 3.3V and 5.0V. In high-performance mode, the entire circuit structure of the high-voltage LDO is integrated on-chip, eliminating the need for external capacitors. It can power internal or external modules, supporting a maximum load of 50mA, thus solving the problem of power supply coordination difficulties in battery management systems and demonstrating strong applicability. In low-power mode, stable power supply to external modules is achieved by driving an external power transistor. The low-power mode also supports a maximum output load current of 50mA, while consuming less than 5μA of quiescent current internally. In both high-performance and low-power modes, the pre-regulator module, bandgap reference circuit, first-stage error amplifier, buffer module, and feedback circuit can be reused as common parts, saving chip design area. In summary, this invention solves many limitations of current high-voltage LDOs, such as insufficient input voltage range, low static power consumption, and the need for external capacitors to help stabilize the system. The designed high-voltage LDO supports a wider input voltage range and lower static power consumption, supports power supply for both on-chip and off-chip modules, and has an adjustable output voltage. It combines high-performance and low-power operating modes to better meet the power supply design requirements in battery management systems, making it more practical and expanding its application scope.

[0042] It should be noted that the embodiments of the present invention propose to support an ultra-wide voltage input range of 15V~80V and consume less than 5μA of static current on the chip in low-power operating mode. The difference between these and the simulation results is due to the consideration of the possible impact on actual manufacturing.

[0043] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0044] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0045] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-voltage LDO for use in a battery management system, characterized in that, The high-voltage LDO has two operating modes: high performance and low power consumption; among them... In low-power operation mode, the high-voltage LDO includes a pre-regulator module, a bandgap reference circuit, a first-stage error amplifier, a buffer module, an off-chip power transistor, and a feedback circuit; wherein, The system includes: a pre-regulator module to provide the internal operating voltage; a bandgap reference circuit to generate a reference voltage under the internal operating voltage; a first-stage error amplifier to compare and amplify the first output sampling voltage with the reference voltage under the internal operating voltage to obtain the first-stage error amplification signal; wherein the first-stage error amplifier has high DC gain characteristics; a buffer module to enhance the driving capability of the first-stage error amplifier under both internal and external operating voltages, and to split the low-frequency pole at the connection point when the first-stage error amplifier and the external power transistor are directly connected into two high-frequency poles, facilitating frequency compensation for the entire high-voltage LDO; and a feedback circuit to act as a feedback loop between the first-stage error amplifier and the external power transistor, stabilizing the output voltage generated at the load output terminal based on the first-stage error amplification signal, and providing the first output sampling voltage for the first-stage error amplifier. In high-performance operating mode, the high-voltage LDO also includes a second-stage error amplifier and an on-chip power transistor; wherein, The second-stage error amplifier compares and amplifies the second output sampling voltage and the first error amplification signal under the internal operating voltage to obtain the second-stage error amplification signal. The first-stage and second-stage error amplifiers work together to give the entire high-voltage LDO high DC gain and wide bandwidth characteristics. The buffer module enhances the driving capability of the second-stage error amplifier under both internal and external operating voltages and splits the low-frequency pole at the connection point (when the second-stage error amplifier and the on-chip power transistor are directly connected) into two high-frequency poles, facilitating frequency compensation for the entire high-voltage LDO. The feedback circuit serves as a feedback loop between the first-stage error amplifier and the on-chip power transistor, and between the second-stage error amplifier and the on-chip power transistor, stabilizing the output voltage generated at the load output based on the second-stage error amplification signal and providing the second output sampling voltage to the second-stage error amplifier.

2. The high-voltage LDO applied to a battery management system according to claim 1, characterized in that, The bandgap reference circuit includes transistors Q11 to Q13, resistors R11 to R19, adjustment resistor R_Trim, transistor NM11, transistors PM10 to PM19, and differential amplifier OA; among which, The emitter of transistor Q11 is connected to one end of resistor R11. The base of transistor Q11 is connected to the base of transistor Q12, one end of resistor R17, and the source of transistor NM11. The collector of transistor Q11 is connected to one end of resistor R12 and the negative input terminal of differential amplifier OA. The emitter of transistor Q12 is connected to the other end of resistor R11, the collector of transistor Q13, and the base of transistor Q12. The collector of transistor Q12 is connected to one end of resistor R13 and the non-inverting input terminal of differential amplifier OA. The emitter of transistor Q13 is connected to resistor R14. One end of resistor R12 is connected to the gate of transistor PM17 and the gate of transistor PM18. The other end of resistor R12 is connected to the other end of resistor R13, the source of transistor PM11, the source of transistor PM12, and the source of transistor PM14. The other end of resistor R14 is connected to one end of the trimming resistor R_Trim. The other end of trimming resistor R_Trim is connected to one end of resistor R15, the drain of transistor PM17, and the drain of transistor PM19. The other end of resistor R15, one end of resistor R19, the drain of transistor PM16, and the drain of transistor PM18 are all connected to... Grounded, one end of resistor R16 is connected to the drain of transistor PM10, the gate of transistor PM11, the gate of transistor PM12, and the gate of transistor PM14; the other end of resistor R16 is connected to the drain of transistor NM11, the gate of transistor PM10, the gate of transistor PM13, and the gate of transistor PM15; the gate of transistor PM12 is connected to the gate of transistor PM13; the gates of transistor PM14 and PM15 are connected; the gate of transistor NM11 is connected to the output terminal of differential amplifier OA; the other end of resistor R17 is connected to... One end of resistor R18 is connected to the gate of transistor PM16. The other end of resistor R18 is connected to the other end of resistor R19 and the gate of transistor PM19. The drain of transistor PM11 is connected to the source of transistor PM10. The drain of transistor PM12 is connected to the source of transistor PM13. The drain of transistor PM13 is connected to the source of transistor PM16 and the source of transistor PM17. The drain of transistor PM14 is connected to the source of transistor PM15. The drain of transistor PM15 is connected to the source of transistor PM18 and the source of transistor PM19.

3. The high-voltage LDO applied to a battery management system according to claim 1, characterized in that, The feedback circuit includes a first adjustable variable resistor structure RT1, a second adjustable variable resistor structure RT2, resistors R1 and R2, switch J1, and switch J2; wherein, One end of the first adjustable resistor structure RT1 is connected to one end of the second adjustable resistor structure RT2 and the on-chip power transistor. The other end of the first adjustable resistor structure RT1 is connected to one end of switch J1. The other end of the second adjustable resistor structure RT2 is connected to one end of switch J2. The other end of switch J1 is connected to the other end of switch J2, one end of resistor R1, and the second-stage error amplifier. The other end of resistor R1 is connected to one end of resistor R2 and the first-stage error amplifier. The other end of resistor R2 is grounded. By controlling the on and off states of switches J1 and J2, a feedback loop is formed between the first-stage error amplifier and the external power transistor in low-power operating mode, and a feedback loop is formed between the first-stage error amplifier and the on-chip power transistor, and between the second-stage error amplifier and the on-chip power transistor in high-performance operating mode.

4. The high-voltage LDO applied to a battery management system according to claim 3, characterized in that, The first adjustable resistor structure RT1 includes several resistors and several NMOS transistors. By controlling the on and off states of all NMOS transistors, resistors are selectively connected to change the feedback coefficient of the feedback circuit.

5. The high-voltage LDO applied to a battery management system according to claim 4, characterized in that, The second adjustable resistor structure RT2 is based on the first adjustable resistor structure RT1, with an additional NPN transistor connected to a diode at the input terminal to reduce the negative temperature variation characteristics of the output voltage of the high-voltage LDO in low-power operation mode.

6. The high-voltage LDO applied to a battery management system according to claim 1, characterized in that, The external power transistor is an NPN transistor. The base of the NPN transistor is connected to the output terminal of the buffer module. The collector of the NPN transistor is connected to the external power supply that provides the external operating voltage through a resistor. The emitter of the NPN transistor is connected to the load circuit.

7. The high-voltage LDO applied to a battery management system according to claim 1, characterized in that, The on-chip power transistor is an NMOS transistor. The gate of the NMOS transistor is connected to the output terminal of the buffer module, the source of the NMOS transistor is connected to the feedback circuit, and the drain of the NMOS transistor is connected to the external power supply that provides the external operating voltage.

8. The high-voltage LDO applied to a battery management system according to claim 3, characterized in that, By using switch S1, the second-stage error amplifier is short-circuited in low-power operating mode, allowing the first-stage error amplifier and the buffer module to be directly connected. In high-performance operating mode, the second-stage error amplifier is connected, allowing the first-stage error amplifier, the second-stage error amplifier, and the buffer module to be connected in sequence.

9. The high-voltage LDO applied to a battery management system according to claim 8, characterized in that, By selecting switch T1, you can choose to connect to the external power transistor in low-power operation mode and to connect to the internal power transistor in high-performance operation mode.

10. The high-voltage LDO applied to a battery management system according to claim 9, characterized in that, The control signals for switches J1, J2, S1, and selector switch T1 are all provided by an external MCU. The external MCU generates corresponding control signals based on the high-performance and low-power operating modes required by the high-voltage LDO.

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