Multi-board card interconnected computing system and firmware management method for multi-board card interconnected devices

Abstract

The application discloses a multi-board card interconnection computing system and a firmware management method of a multi-board card interconnection device, and relates to the computer field.The multi-board card interconnection device is connected with multiple board cards, is used for dividing the multiple board cards into multiple levels according to board card functions of the multiple board cards, generating multiple board card sub-codes according to board card models contained by board cards of different levels, and generating a board card code according to the multiple board card sub-codes; and the system initialization component is connected with the multi-board card interconnection device, is used for determining hardware configuration information of the multi-board card interconnection device according to the board card code, and performing firmware management on the multi-board card interconnection device according to the hardware configuration information.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computers, and in particular to a multi-board card interconnected computing system and a firmware management method of a multi-board card interconnected device. BACKGROUND

[0002] In order to improve the utilization rate of the board card, save the development cycle and development cost, one board card is often applied to multiple configurations. The problem brought by this is how to distinguish multiple configurations and different configurations. The conventional design often matches different FW (Firmware) under different configurations to realize the different functions of each port under different configurations. This also brings a certain amount of work to the FW management.

[0003] In the related art, one board card is often applied to multiple configurations, but the existing technology is difficult to distinguish multiple configurations of the board card and different configurations of the settings brought by different configurations, resulting in difficult firmware management. At present, no effective solution has been proposed. SUMMARY

[0004] The present application provides a multi-board card interconnected computing system and a firmware management method of a multi-board card interconnected device to at least solve the problem in the related art that one board card is often applied to multiple configurations, but the existing technology is difficult to distinguish multiple configurations of the board card and different configurations of the settings brought by different configurations, resulting in difficult firmware management.

[0005] The present application provides a multi-board card interconnected computing system, comprising: a multi-board card interconnected device connected with multiple board cards, configured to divide the multiple board cards into multiple levels according to board card functions of the multiple board cards, generate multiple board card sub-codes according to board card models contained by board cards of different levels, and generate a board card code according to the multiple board card sub-codes; and a system initialization component connected with the multi-board card interconnected device, configured to determine hardware configuration information of the multi-board card interconnected device according to the board card code, and perform firmware management on the multi-board card interconnected device according to the hardware configuration information.

[0006] In one exemplary embodiment, the system initialization component comprises a processor configured to: read the board card code from the multi-board card interconnected device when the computing system starts; determine power-on timing of the multiple board cards according to the board card code; and control the multiple board cards to be powered on in sequence according to the power-on timing.

[0007] In an example embodiment, the system initialization component includes a firmware booting module configured to: read the board card codes from the multi-board interconnection device in the case that the power-on of the plurality of board cards is completed; match the hardware configuration information in the preset configuration data according to the board card codes, wherein the preset configuration data is used to indicate the mapping relationship between the plurality of board card codes and the plurality of hardware configuration information; and load a target firmware version to the plurality of board cards according to the hardware configuration information, wherein the target firmware version corresponds to the hardware configuration information.

[0008] In an example embodiment, the system initialization component includes a controller configured to: read the board card codes from the multi-board interconnection device in the case that the power-on of the plurality of board cards is completed; monitor the in-place state and the running state of the plurality of board cards according to the board card codes; and generate first abnormal information of a target board card in the case that the in-place state or the running state of the target board card is abnormal.

[0009] In an example embodiment, the controller is connected with the firmware booting module and the processor, and is further configured to: read the hardware connection state and the configuration information of the plurality of board cards from the processor, wherein the power-on sequence is determined according to the hardware connection state and the configuration information; read the version information of the target firmware version from the firmware booting module; and verify the version information according to the hardware connection state and the configuration information.

[0010] In an example embodiment, the controller is further configured to: send a firmware update instruction to the firmware booting module in the case that the version information fails to pass the verification, wherein the firmware update instruction is used to instruct the firmware booting module to reload firmware to the plurality of board cards.

[0011] In an example embodiment, the controller is further configured to: monitor running data of a plurality of components of the computing system, wherein the plurality of components at least include: the multi-board interconnection device, the processor, the firmware booting module, and the running data includes at least one of: running temperature, power supply voltage, and power supply state; and generate second abnormal information of a target component in the case that the running data of the target component is abnormal.

[0012] In an example embodiment, the multi-board interconnection device includes: a Peripheral Component Interconnect Express (PCIe) port connected with the firmware booting module, and configured to connect a PCIe device to the multi-board interconnection device, wherein the plurality of board cards include the PCIe device.

[0013] In an example embodiment, the PCIe port includes N high-bit ports and N low-bit ports, and the PCIe port is further configured to determine the first identification bit and the second identification bit according to the number and type of the plurality of PCIe devices connected to the PCIe port, and send the first identification bit and the second identification bit to the firmware boot module, wherein N is a positive integer, and the first identification bit and the second identification bit are used to determine the bandwidth information of the PCIe port.

[0014] In an example embodiment, the multi-board interconnection device is further configured to, in a case where a change in the plurality of boards connected to the multi-board interconnection device is detected, detect the board models of the changed plurality of boards, and regenerate the board code according to the board models of the changed plurality of boards; and send the updated board code to the system initialization component to instruct the system initialization component to update the firmware versions of the changed plurality of boards according to the updated board code.

[0015] In an example embodiment, the computing system further includes a standby power rail configured to provide power to the computing system in a case where the computing system is in a powered-off state, so that the multi-board interconnection device identifies the board models of the plurality of boards and generates the plurality of board sub-codes and the board code according to the board models of the boards at different levels.

[0016] The application also provides a firmware management method of a multi-board interconnection device, applied to the above-mentioned multi-board interconnection computing system, including: dividing the plurality of boards connected to the multi-board interconnection device into a plurality of levels according to the board functions of the plurality of boards, generating a plurality of board sub-codes according to the board models contained by the boards at different levels, and generating a board code according to the plurality of board sub-codes; determining hardware configuration information of the multi-board interconnection device according to the board code, and performing firmware management on the multi-board interconnection device according to the hardware configuration information.

[0017] In an example embodiment, determining the hardware configuration information of the multi-board interconnection device according to the board code, and performing firmware management on the multi-board interconnection device according to the hardware configuration information includes: reading the board code from the multi-board interconnection device when the computing system starts; determining the power-on sequence of the plurality of boards according to the board code; and controlling the plurality of boards to be powered on in sequence according to the power-on sequence.

[0018] In an example embodiment, after the plurality of board cards are sequentially powered on according to the power-on timing, the method further comprises: matching the hardware configuration information in preset configuration data according to the board card coding, wherein the preset configuration data is used to indicate a mapping relationship between a plurality of the board card coding and a plurality of the hardware configuration information; and loading a target firmware version to the plurality of board cards according to the hardware configuration information, wherein the target firmware version corresponds to the hardware configuration information.

[0019] In an example embodiment, after the plurality of board cards are sequentially powered on according to the power-on timing, the method further comprises: monitoring in-place states and running states of the plurality of board cards according to the board card coding; and generating first abnormal information of a target board card in a case that the in-place state or the running state of the target board card is abnormal.

[0020] In an example embodiment, after the plurality of board cards are sequentially powered on according to the power-on timing, the method further comprises: obtaining hardware connection states and configuration information of the plurality of board cards, and obtaining version information of the target firmware version, wherein the power-on timing is determined according to the hardware connection states and the configuration information; and verifying the version information according to the hardware connection states and the configuration information.

[0021] In an example embodiment, after the version information is verified according to the hardware connection states and the configuration information, the method further comprises: in a case that the version information fails to pass the verification, issuing a firmware update instruction to a firmware booting module to instruct the firmware booting module to reload firmware to the plurality of board cards.

[0022] The present application also provides an electronic device, comprising: a memory configured to store a computer program; and a processor configured to execute the computer program to implement the steps of the firmware management method of any one of the above multi-board interconnection devices.

[0023] The present application also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the firmware management method of any one of the above multi-board interconnection devices.

[0024] The present application also provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps of the firmware management method of any one of the above multi-board interconnection devices.

[0025] According to the application, a multi-board card interconnected computing system is provided, comprising a multi-board card interconnection device and a system initialization component. The multi-board card interconnection device is connected with a plurality of board cards, and the board cards are divided into a plurality of levels according to the functions of the board cards, and then the board card sub-codes are automatically generated according to the specific board card models contained in the board cards of different levels, and then the board card codes are generated, and the codes are realized by identifying the characteristics of different board cards; the system initialization component is connected to the multi-board card interconnection device, and the hardware configuration information of the multi-board card interconnection device is determined according to the board card codes, and the firmware management of the multi-board card interconnection device is realized. According to the above system, the board cards are coded and managed according to the functions of the board cards, the board card configuration information is accurately identified according to the coding information, and the firmware management of the board cards is realized, so as to solve the problem that in the related art, one board card is often applied to multiple configurations, but the existing technology is difficult to distinguish the multiple configurations of the board card and the different configurations brought by different configurations, resulting in the difficulty of firmware management. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0027] Figure 1 is a hardware structure block diagram of a multi-board card interconnected computing system according to an embodiment of the present application;

[0028] Figure 2 is a structure block diagram of a multi-board card interconnected computing system according to an embodiment of the present application;

[0029] Figure 3 is a configuration block diagram of SKU ID according to an embodiment of the present application;

[0030] Figure 4 is a SKU ID identification flowchart according to an embodiment of the present application;

[0031] Figure 5 is a PCIe X16 port structure diagram according to an embodiment of the present application;

[0032] Figure 6 is a firmware management method flowchart of a multi-board card interconnection device according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] With reference to the drawings and the specific embodiments described below, the principles of the present application will be better understood.

[0034] It should be noted that, in the description of the present application, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article, or apparatus that includes a list of elements not only includes those elements, but also includes other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "first", "second", etc. in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0035] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0036] In conjunction with the specific application environment architecture or specific hardware architecture on which the firmware management method for multi-board card interconnection equipment depends, the specific application environment architecture or specific hardware architecture is described here.

[0037] The method embodiments provided in the embodiments of the present application can be executed in a multi-board card interconnected computing system or similar computing device. Taking the execution on a multi-board card interconnected computing system as an example, Figure 1 is a hardware structure block diagram of a multi-board card interconnected computing system according to an embodiment of the present application. As Figure 1 shown, the multi-board card interconnected computing system can include one or more (only one is shown in Figure 1 ) processor 102 (the processor 102 can include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned multi-board card interconnected computing system can further include a transmission device 106 for communication function and an input and output device 108. Those skilled in the art can understand that Figure 1 the structure shown is only schematic, which does not limit the structure of the above-mentioned multi-board card interconnected computing system. For example, the multi-board card interconnected computing system can further include more or less components than Figure 1 shown, or have a different configuration from Figure 1 shown.

[0038] The memory 104 can be used to store computer programs, such as software programs of application software and modules, such as a computer program corresponding to the starting method of the operating system in the embodiments of the present application. The processor 102 performs various functional applications and data processing, that is, implements the above method, by running the computer programs stored in the memory 104. The memory 104 can include a high-speed random access memory, and can also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory 104 can further include a memory remotely arranged with respect to the processor 102, which can be connected to the computer terminal through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0039] The transmission device 106 is used to receive or send data via a network. Specific examples of the above network can include a wireless network provided by a communication provider of a multi-board interconnected computing system. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC) which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, RF) module used for wireless communication with the Internet.

[0040] In the embodiments, a multi-board interconnected computing system is provided, Figure 2 is a structural block diagram of a multi-board interconnected computing system according to the embodiments of the present application, as Figure 2 shown, the system includes:

[0041] The multi-board interconnection device 22 is connected with the plurality of boards 23, and is used to divide the plurality of boards into a plurality of levels according to board functions of the plurality of boards, generate a plurality of board sub-codes according to board models contained in boards of different levels, and generate a board code according to the plurality of board sub-codes.

[0042] It should be noted that the multi-board interconnection device refers to a device or system in a computer system for facilitating high-speed communication and data exchange between a plurality of functional boards. The core of such a device is its ability to effectively manage the interconnection between a plurality of boards (such as GPU (Graphics Processing Unit, a microprocessor specially designed for processing graphics and image data) acceleration cards, network interface cards, storage expansion cards, etc.), ensuring their cooperative work and improving the overall performance and efficiency of the system.

[0043] At the technical level, multi-board interconnect devices typically rely on high-speed network protocols such as PCI Express (PCIe), InfiniBand, and Ethernet to enable communication between boards. This involves not only physical connectors and slots, but also complex electrical design, signal integrity analysis, and the software and firmware used to configure, manage, and monitor these boards.

[0044] It's worth noting that multi-board interconnect devices are widely used in related technical fields, especially in high-performance computing (HPC), data centers, cloud computing, artificial intelligence (AI), and machine learning. This architecture, by distributing computing, storage, networking, and acceleration functions across multiple boards and enabling high-speed interconnection between them, can significantly improve the overall performance and flexibility of the system. Below are several specific application examples of multi-board interconnect devices to demonstrate the role of multi-board interconnect device systems in real-world scenarios:

[0045] 1. AI Servers: AI servers typically handle massive amounts of data and complex computational tasks, therefore they often employ multi-board interconnect architectures to enhance computing and data processing capabilities. For example, in the DGX system, multiple GPU boards are connected to the switch board (SW board) via high-speed interconnect technologies such as PCIe, enabling direct communication between GPUs and greatly improving the efficiency of parallel computing. Simultaneously, the storage board connects to the motherboard via PCIe, providing high-speed NVMe storage, while the network board is responsible for connecting to external networks, providing the necessary bandwidth.

[0046] 2. Hyperscale Data Centers: In hyperscale data centers, server clusters need to handle a large number of data communication and computing tasks. Multi-board interconnect devices can include network boards (such as 100G / 200G / 400G Ethernet cards), storage boards (such as NVMe-over-Fabrics storage expansion), and compute acceleration boards (such as FPGA or ASIC accelerators). These boards are interconnected with the motherboard and other servers via high-speed networks such as RDMA (Remote Direct Memory Access) to form a large-scale, high-efficiency computing and storage network.

[0047] 3. Cloud Computing Platform: Cloud computing platforms need to provide scalable computing and storage resources. Multi-board interconnect devices can include various types of boards, such as high-performance computing boards, elastic storage boards, and virtualized network boards. Servers in a cloud computing architecture can dynamically add or remove these boards, dynamically adjusting resource allocation according to tenant needs. This flexibility enables cloud service providers to respond quickly to changing computing demands while maintaining high efficiency and cost-effectiveness.

[0048] 4、HPC cluster: In HPC (High-Performance Computing) clusters, multi-board interconnection devices are used to improve the processing speed of compute-intensive tasks. For example, an HPC system may contain multiple GPU-accelerated and high-performance network boards, which are interconnected through PCIe and high-speed networks such as InfiniBand or high-speed Ethernet, enabling efficient data transmission between compute nodes. This architecture can provide maximum computing performance with minimal latency, making it ideal for high-precision scientific computing applications such as large-scale simulations, weather forecasting, and genomics.

[0049] As can be seen from the above examples, multi-board interconnection devices can provide highly customized high-performance computing, storage, and network resources in specific applications in different fields, meeting the needs of various complex scenarios. The advantage of this architecture is its flexibility, scalability, and efficient resource management, allowing system designers to flexibly configure and optimize hardware resources according to actual workloads and performance requirements.

[0050] It should be noted that in the embodiments of the present application, the multi-board interconnection device, as the core of the multi-board interconnection computing system, not only provides high-performance computing resources and high-speed data transmission capabilities, but also has intelligent identification and configuration functions. It can analyze the type information of each board card, such as GPU acceleration cards, network interface cards, and storage expansion cards, and generate a unique board card code. This coding mechanism ensures that even in the case of frequent exchange between board cards, the system can quickly and accurately identify the type and function of each board card.

[0051] In an optional embodiment, the board cards connected to the multi-board interconnection device are divided into three levels, the first level board card is the mainboard, the second level board card is the Switch board and other master control chips, and the third level board card is the most peripheral board card, such as GPU board card, etc.

[0052] Note that the first level board card is the center of the entire system, which contains the main computing resources such as CPU, BIOS, BMC, memory slot, etc. The SKU ID (Stock Keeping Unit Identifier, a code used to uniquely identify a specific product configuration) on the motherboard is usually reserved for future expansion and has no practical application at present, but it ensures enough flexibility to adapt to future configuration changes. The second level board card mainly undertakes tasks such as data exchange, signal processing or control logic, for example, the Switch board, which is responsible for managing the routing and bandwidth allocation of high-speed interconnection signals such as PCIe. In AI systems, this may include specialized chips such as FPGAs, ASICs, etc. for accelerating data processing. The SKU ID of the second level board card is used to distinguish different master chip types or vendors. The third level board card is usually hardware directly facing specific functions or applications, such as GPU board for graphics rendering and AI computing acceleration. The SKU ID of these board cards is used to distinguish the expansion type or chassis height configuration.

[0053] Note that the classification connection means that each board card will be connected to the corresponding interface or bus according to its level. In a multi-board interconnection device, each level has a corresponding connection point, such as PCIe slot, SATA (Serial ATA, a computer bus interface standard) interface, etc. The board card can access the system and communicate with other board cards or system components through these connection points. This design not only ensures the flexibility of hardware configuration, but also maintains the clarity and scalability of system structure, which is a key strategy for building complex systems.

[0054] The system initialization component 24 is connected with the multi-board interconnection device, and is used for determining hardware configuration information of the multi-board interconnection device according to the board card code, and performing firmware management on the multi-board interconnection device according to the hardware configuration information.

[0055] Through the above system, the multi-board card interconnection equipment establishes connection with multiple board cards, classifies the board cards according to multiple levels of the multi-board card interconnection equipment first, then generates board card sub-codes according to the board card models of the board cards of different levels, and further generates board card codes, and the codes are realized by identifying the characteristics of different board cards; the system initialization component is connected to the multi-board card interconnection equipment, and the hardware configuration information of the multi-board card interconnection equipment is determined according to the board card codes, and the firmware management of the multi-board card interconnection equipment is realized. By using the above system, the board cards are managed according to the functions of the board cards, the configuration information of the board cards is accurately identified according to the code information, and the firmware management of the board cards is realized, thereby solving the problem that in the related art, one board card is often applied to multiple configurations, but the existing technology is difficult to distinguish the multiple configurations of the board card and the different configurations brought by different configurations, resulting in difficult firmware management.

[0056] In one example embodiment, the system initialization component includes a processor configured to: read the board card codes from the multi-board card interconnection equipment when the computing system starts; determine the power-on sequence of the multiple board cards according to the board card codes; and control the multiple board cards to be powered on in sequence according to the power-on sequence.

[0057] The system initialization component essentially contains a processor (such as a Complex Programming logic device (CPLD)). The processor reads the board card codes from the multi-board card interconnection equipment immediately after the system starts, then analyzes the codes, determines the power-on sequence of the multiple board cards, and ensures orderly power supply. Based on the developed sequence, the processor accurately controls each board card to be powered on in sequence, realizing smooth startup of the system.

[0058] It should be noted that the decision of the power-on sequence is based on the functional priority of the board card, the power supply demand, and the dependency relationship with other hardware components. For example, the processor may preferentially start the power management module, then the system main board, and then the GPU acceleration card or network interface card with heavy load, which not only ensures the orderly startup of the system, but also reduces the power burden in the startup process and improves the running stability of the whole machine.

[0059] It should be noted that the processor controls the power-on in sequence through direct or indirect ways. It may directly issue control signals to the power management circuit of each board card, or indirectly convey commands through the multi-board card interconnection equipment. Regardless of which way, the goal is to ensure that each board card is powered at the right time, avoiding unnecessary energy waste, and also reducing the hardware risk in the startup process.

[0060] The implementation of this mechanism significantly enhances the stability and reliability of the multi-board card interconnection system, providing a solid foundation for the computing system in the startup phase.

[0061] Optionally, the system initialization component includes a firmware boot module configured to: read the board card code from the multi-board interconnection device when power-on of the plurality of board cards is completed; match the hardware configuration information in the preset configuration data according to the board card code, wherein the preset configuration data is used to indicate a mapping relationship between a plurality of board card codes and a plurality of hardware configuration information; and load a target firmware version into the plurality of board cards according to the hardware configuration information, wherein the target firmware version corresponds to the hardware configuration information.

[0062] The system initialization component further includes a firmware boot module (BIOS, Basic Input Output System) configured to obtain the board card code from the multi-board interconnection device immediately after power-on of each board card is completed. Subsequently, the module determines the hardware configuration information that matches the board card code based on the mapping relationship in the preset configuration data. Finally, the target firmware version is accurately deployed to each board card according to the hardware configuration information, ensuring that the version matches the hardware configuration.

[0063] It should be noted that the firmware boot module is responsible for loading and booting the firmware at system startup. The module first ensures that each board card has completed power-on, and then accesses the board card code in the multi-board interconnection device. The code is essentially a series of numbers or letters, each of which corresponds to the unique identification of a specific board card in the system, containing key information such as board card model, function, and interface configuration.

[0064] It should be noted that the mapping data describes a one-to-one correspondence between the board card code and the corresponding hardware configuration information, ensuring that the module can accurately identify the hardware requirements of each board card. This mapping relationship may be stored in the SPI memory, NVRAM (Non-Volatile Random Access Memory), or the internal database of the system initialization component, facilitating quick lookup and matching.

[0065] It should be noted that the SPI memory is a memory chip that uses the Serial Peripheral Interface (SPI) for communication.

[0066] The loading of the target firmware version is the final task of the firmware boot module. The module retrieves the firmware version matching the hardware configuration information from the storage and loads it into the corresponding board card. The selection of the firmware version needs to ensure complete adaptation to the hardware characteristics of the board card, avoiding system failures caused by incompatible or incorrectly configured versions. The loading process may involve steps such as data transmission, decompression, verification, and writing of the firmware, ensuring that the firmware is lossless and correctly deployed on the board card.

[0067] Through this embodiment, the flexibility and maintainability of the multi-board interconnection system are greatly improved through automated configuration and firmware version management, reducing the risk of errors during hardware updates or software maintenance. The intelligent decision-making of the firmware boot module ensures the accuracy and efficiency of the system startup process.

[0068] Optionally, the system initialization component includes a controller for reading the board card codes from the multi-board interconnection device when the power-on of the multiple board cards is complete, monitoring the in-place state and running state of the multiple board cards according to the board card codes, and generating first abnormal information of a target board card if the in-place state or running state of the target board card is abnormal.

[0069] In an optional embodiment, the system initialization component further includes a controller (BMC, Baseboard Management Controller) that reads the board card codes from the multi-board interconnection device after ensuring that all board cards have completed power-on. Then, according to the codes, it continuously monitors the in-place state and running state of each board card, achieving real-time tracking of the hardware condition. Once it finds that the in-place state or running state of a specific board card, i.e., the target board card, is abnormal, it immediately generates abnormal information for quick identification and response to system failures.

[0070] It should be noted that the controller, as an important component of the system initialization component, is not only responsible for the loading and booting of hardware configuration, but also undertakes the monitoring and fault detection tasks during system operation. In this embodiment, the controller can identify and locate each board card by reading the board card codes from the multi-board interconnection device after the system starts. The board card code is a unique identifier used to identify and distinguish various types of hardware in the system, which helps to achieve accurate monitoring of the board card.

[0071] It should be noted that the monitoring process continuously detects the in-place state and running state of each board card through the controller to ensure that the system hardware runs at the expected health level. The in-place state reflects whether the board card has been correctly inserted and connected to the system, while the running state relates to the performance parameters, temperature, voltage and current of the board card, which are used to evaluate whether the hardware is working normally. This monitoring mechanism provides real-time hardware health reports for the system, which helps to prevent potential failures and ensures stable operation of the system.

[0072] In summary, the controller builds an intelligent and responsive system monitoring and fault detection platform by reading the board card code and continuously monitoring the hardware state, greatly improving the reliability of the computing system and ensuring the stability of the hardware and the security of the data under high-intensity computing tasks.

[0073] Optionally, the controller, connected with the firmware boot module and the processor, is further configured to: read the hardware connection state and configuration information of the plurality of board cards from the processor, wherein the power-on sequence is determined according to the hardware connection state and the configuration information; read the version information of the target firmware version from the firmware boot module; and verify the version information according to the hardware connection state and the configuration information.

[0074] In this embodiment, the controller first reads the connection state and configuration details of the plurality of board cards from the processor to ensure that the power-on sequence is consistent with the actual situation of the hardware. Then, the controller queries the information of the target firmware version from the firmware boot module, compares the hardware state and configuration, verifies the appropriateness of the firmware version, and ensures the stability and security of the system operation.

[0075] It should be noted that the version information of the target firmware version includes the version number, compatibility list, function description and known problems of the firmware. The controller reads this information and compares it with the hardware connection state and configuration information obtained from the processor to perform version verification. This process includes checking whether the firmware version supports the current hardware configuration, whether it matches the hardware performance, and whether there are compatibility problems with the current configuration, etc., aiming to prevent system failure or performance degradation caused by improper selection of firmware version.

[0076] Optionally, the controller is further configured to: in the case that the version information fails to pass the verification, send a firmware update instruction to the firmware boot module, wherein the firmware update instruction is used to instruct the firmware boot module to reload the firmware to the plurality of board cards.

[0077] When the firmware version information fails to meet the verification standard, an update instruction is immediately sent to the firmware boot module to instruct the module to reload the firmware to each board card, ensuring the high coordination of hardware and software.

[0078] It should be noted that the firmware update process involves multiple steps, including file transfer, decompression, integrity verification, writing to hardware, and reboot verification. Before updating the firmware, the module performs a comprehensive check on the new firmware version to ensure it is compatible with the board hardware and free of viruses or errors. During the update process, the module also monitors the board's power status to prevent firmware corruption or hardware failure caused by power outages during the update. After the update is complete, the system reboots, and the firmware boot module performs version verification again to ensure successful firmware update and normal hardware operation.

[0079] This mechanism demonstrates the crucial role of the controller in hardware and software management within multi-board interconnect systems. Through an automated firmware update process, the controller can promptly correct software configuration issues, eliminate hardware compatibility obstacles, and ensure the computing system maintains high efficiency and stability even in the face of hardware changes or new firmware versions. This is one of the key technologies in modern computing system design for achieving dynamic hardware configuration and seamless firmware upgrades.

[0080] Optionally, the controller is further configured to: monitor the operating data of multiple components of the computing system, wherein the multiple components include at least: the multi-board interconnect device, the processor, the firmware boot module, and the operating data includes at least one of the following: operating temperature, power supply voltage, and power status; and generate second abnormal information of the target component when abnormal operating data of a target component is detected among the multiple components.

[0081] In this embodiment, the controller also undertakes the task of data monitoring, closely monitoring the status of multiple components in the computing system, including multi-board interconnect devices, processors, firmware boot modules, etc. The monitored indicators include key data such as operating temperature, power supply voltage, and power status. If the operating data of any component, such as the target component, deviates from the normal range, abnormal information is immediately generated to prompt the system to pay attention to and repair potential fault points.

[0082] It's important to note that monitoring operational data is a crucial responsibility of the controller, ensuring the computing system's hardware components are in a healthy working state. The controller periodically collects and analyzes operational data from each component. For example, operating temperature reflects whether the hardware is overheating, supply voltage indicates the stability of the power supply, and power status provides information on the component's power supply status, including power-on, standby, and power-off states. This data is essential for assessing the real-time operating status of the hardware, predicting potential failure points, and maintaining overall system stability.

[0083] Through this monitoring mechanism, the controller's proactive monitoring and fault warning capabilities during system operation are demonstrated, which is the foundation for long-term stable operation of the computing system. Through continuous data collection and analysis, the controller can detect and address potential hardware problems in advance, reducing system maintenance costs and improving system availability and user satisfaction.

[0084] Optionally, the multi-board card interconnection device comprises a PCIe port connected with the firmware boot module, used to connect a PCIe device to the multi-board card interconnection device, wherein the plurality of board cards comprises the PCIe device.

[0085] The multi-board card interconnection device integrates a PCIe port and is directly connected with the firmware boot module. Its function is to provide a connection point for PCIe devices, enabling these devices to be connected to the multi-board card interconnection architecture of the system, wherein the plurality of board cards that constitute the system contain these PCIe devices.

[0086] It should be noted that the PCIe port, i.e. Peripheral Component Interconnect Express port, is a high-speed expansion bus interface in modern computer systems, widely used to connect various high-performance devices such as graphics processors, network adapters, and storage controllers to the motherboard. In servers and AI systems, the high-speed data transmission capability of the PCIe port makes it the preferred interface for connecting high-speed peripherals and accelerators, significantly improving the overall performance of the system and meeting the needs of large-scale data processing and high-concurrency computing.

[0087] In this embodiment, the firmware boot module is directly connected with the PCIe port in the multi-board card interconnection device, which can directly read and configure the status and firmware of the PCIe device, enhancing the management and control capabilities of the system for PCIe devices.

[0088] In summary, the integration of the PCIe port in the multi-board card interconnection device not only simplifies hardware connections, but also directly facilitates the interaction between the firmware boot module and PCIe devices, providing a solid foundation for implementing system-level device management and firmware updates. This design is an indispensable part of building high-performance and high-reliability servers and AI systems, helping to improve the scalability and maintenance efficiency of the system.

[0089] Optionally, the PCIe port comprises N high-bit ports and N low-bit ports, and the PCIe port is further configured to determine first identification bits corresponding to the N high-bit ports and second identification bits corresponding to the N low-bit ports according to the number and type of the plurality of PCIe devices connected, and send the first identification bits and the second identification bits to the firmware boot module, wherein N is a positive integer, and the first identification bits and the second identification bits are used to determine the bandwidth information of the PCIe port.

[0090] The PCIe ports are divided into high and low types, and the total number reaches 2N bits, N representing a positive integer, and the design allows the ports to flexibly adapt to different numbers and types of PCIe device connections. The ports have intelligent recognition function, can determine the first identification bit and the second identification bit according to the number and type of the connected devices, and then transmit the two identification bit information to the firmware boot module, for determining the bandwidth information of the PCIe port, and ensuring efficient communication and reasonable allocation of resources between devices.

[0091] In the embodiment, the ports are not limited to traditional single signal paths, but are innovatively divided into high and low ports, which together constitute a 2N-bit composite port. Such a design allows the ports to automatically adjust the signal path according to the number and type of the actually connected PCIe devices, to realize dynamic allocation of bandwidth and meet the different bandwidth requirements of different types of devices.

[0092] Optionally, the multi-board card interconnection device is further configured to: in a case where it is detected that the plurality of board cards connected to the multi-board card interconnection device changes, detect the board card models of the changed plurality of board cards, and regenerate board card codes according to the board card models of the changed plurality of board cards; and send the updated board card codes to the system initialization component to instruct the system initialization component to update the firmware versions of the changed plurality of board cards according to the updated board card codes.

[0093] The multi-board card interconnection device has dynamic monitoring and adaptation functions. Once it senses that the connected board card array changes, it immediately starts a process to analyze the type of the newly connected component, and then reconstructs the board card coding system according to the updated hardware configuration. After this dynamic coding update, the system automatically transmits the new code to the system initialization component, which guides it to accurately match and update the firmware version of the corresponding board card according to the latest code information, ensures that all component firmware in the system is synchronized with the current hardware environment, optimizes the overall performance, and reduces the instability caused by mismatched firmware versions.

[0094] The system initialization component, as the core control unit in the server startup process, is responsible for loading and configuring firmware to ensure that hardware components can be initialized as expected. In the embodiment, it intelligently identifies the specific type and function of each board card according to the dynamically updated board card codes provided by the multi-board card interconnection device, thereby loading the most suitable firmware version to complete the individual initialization and configuration of the hardware components and improve the overall response speed and processing efficiency of the system.

[0095] This mechanism is particularly important in high-dynamic, high-load server environments, such as AI computing nodes or cloud computing data centers, where hardware configurations may be frequently adjusted to adapt to different computing tasks or load requirements. By dynamically monitoring and instantaneously updating the firmware version, the system can seamlessly adapt to hardware changes, avoiding system restarts or performance degradation caused by configuration updates, and providing users with continuous and stable computing services.

[0096] Optionally, the computing system further comprises: a standby power rail, configured to provide power for the computing system in the case that the computing system is in a powered-off state, so that the multi-board card interconnection device identifies the board card models of the plurality of board cards and generates the plurality of board card sub-codes and the board card code according to the board card models of the different levels of board cards.

[0097] The computing system integrates the key component of the standby power rail, so that even in the case of system power-off, the important components in the system (such as the multi-board card interconnection device) can be continuously powered, ensuring that the multi-board card interconnection device can continuously identify the connected board card categories, and then automatically generate detailed board card sub-codes and comprehensive board card codes according to the identified board card models, laying a foundation for fast initialization and firmware matching after system power-on.

[0098] The standby power rail, specifically, is a circuit designed to provide low-power power to specific and necessary components in the system when the system is inactive or completely shut down. These components usually include the memory part that stores system state information, the clock circuit, and the control chip responsible for firmware management and hardware monitoring, such as BMC (Baseboard Management Controller). In the embodiments of the present application, the standby power rail ensures that even if the server is completely powered off, the multi-board card interconnection device can use this low-power power to continuously monitor and identify the board card models connected to the system, providing accurate configuration information for subsequent system startup.

[0099] In the case that the system needs to perform hot plug operation, or the system must be frequently started and stopped within a short period of time. Through the continuous power supply of the standby power rail, the multi-board card interconnection device can immediately identify the board card changes without waiting for the system to be completely powered on, generate the corresponding code, and then speed up the firmware update and system initialization process, significantly improving the availability and response speed of the server.

[0100] Obviously, the above-described embodiments are only part of the embodiments of the present application, not all. In order to better understand the above method, the above process is described in combination with the following embodiments, but not used to limit the technical solutions of the embodiments of the present application, specifically:

[0101] In one optional embodiment, this application performs hierarchical management of the board according to its functional application. SKU_ID is defined as an 8-bit [0:7] data, and [5:7] is defined as the first-level board SKUID (i.e., board sub-code). In the default state, [0:7] are all pull-up in the first-level board and designed to be all 1s. The current motherboard segment SKU ID is RSV. [2:4] is defined as the second-level board SKU ID. This ID can be used to distinguish the main control chip type. According to the rules, the corresponding PIN can be pulled down. [0:1] is defined as the third-level board SKU ID, which can be used to distinguish the expansion type (such as GPU or UBB platform) or the chassis height configuration (6U or 4U).

[0102] While sending the board_ID and SKU ID to the CPLD, BIOS, and BMC through the I / O expander chip, BP_ID0 / ID1 is defined in each PCIeport, and pull-up and pull-down processing is performed according to rules in the downlink configuration. Combined with some BP (Board Presence) presence logic PINs, bandwidth allocation and silkscreen display are performed under different configurations.

[0103] The following combination Figure 3 A supplementary explanation of the structure of SKU_ID (i.e., the board code mentioned above) is provided, such as... Figure 3 As shown, Figure 3 The configuration block diagram for SKU_ID is shown below:

[0104] To facilitate identification of different model configurations, the motherboard (MB) adds an 8-bit SKU ID and connects it to the BMC, BIOS, and MB's CPLD respectively, so that different logic processing can be performed according to different model configurations.

[0105] 1. Based on the system hierarchy, the boards are divided into three levels;

[0106] 2. Each level is divided according to function, and one level may contain 1-2 motherboards;

[0107] 3. The first level is the motherboard. All ID pins are pulled up on the motherboard and connected to the BMC, BIOS and CPLD. The entry method is not limited to GPIO or through the I2C gpio expander chip.

[0108] 4. SKU ID[5:7] is used for RSV functionality on the motherboard, but it is not currently in practical application.

[0109] 5、The second level is applied according to the AI model, and is mostly a SW board (Switch board, mainly responsible for data routing and switching) or an RT board (Router board, similar to the switch board, but more focused on network signal routing and processing), occupying [2:4] in the SKU ID, which is mainly used to distinguish the manufacturer type of the functional board card to support the diversified manufacturer demand of the current SW (Switch) chip and RT (Router) chip;

[0110] 6、The third level is often the most peripheral board card for multi-system interconnection. For AI models, the third level SKU ID is mostly used to indicate the GPU board card model, which can be used to identify the GPU BOX and UBB (Universal Baseboard, an OCP specification defined OAM baseboard) BOX, and the product division of different model heights;

[0111] 7、Further, if it is a UBB model application, a UBB SKU ID design can be added to the third level to identify different manufacturer UBB and OAM (OCP Accelerator Module, a modular hardware standard designed for accelerated computing tasks) types.

[0112] Correspondingly, based on the SKU ID coding design shown in Figure 3 The application also provides an optional SKU ID identification process, as shown in Figure 4 , including the following steps:

[0113] 1、After the system is powered on, the BMC and the CPLD start to read the SKU ID;

[0114] 2、Combined with the board ID, the CPLD performs power-on sequence guidance for different SKU configurations;

[0115] 3、The BMC compares the configuration information under the SKU ID with the read machine information, and reports abnormal information;

[0116] 4、BIOS waits for a boot signal, and after receiving the boot signal, reads the SKU ID, and guides and starts according to the corresponding configuration of the SKU ID.

[0117] According to another optional embodiment of the present application, while the board_ID, SKU ID is sent to the CPLD, BIOS and BMC through the I / O expander chip, the BP_ID0 / ID1 (i.e. the first identification bit and the second identification bit described above) in each PCIe port is defined, and the up and down pull processing is performed according to the rules in the downlink configuration, combined with the in-place logic PIN of some BP, to perform bandwidth allocation and silk screen display under different configurations.

[0118] The following describes the embodiment by taking a complete PCIe X16 port as an example, and the specific implementation block diagram is as shown in Figure 5

[0119] 1. Each PCIe x16 PORT is divided into high 8 bits (equivalent to the above N high bit ports, and N is 8 in the embodiment) and low 8 bits (equivalent to the above N low bit ports), and each group of X8 signals has two ID bits [0:1];

[0120] 2. At the motherboard end, each ID PIN is pulled down and then connected to the CPU I / O expander chip through the MOS flip-flop;

[0121] 3. In the default state, the BP ID corresponding to each PCIe x16 PORT is 1111;

[0122] 4. According to the device type of the device end, there may be X16 devices, uplink X8 and downlink empty connection, downlink X8 and uplink empty connection, and X8 configured as two X2;

[0123] 5. There are also cases that the BIOS cannot recognize, a PCIe x8 has both the case of being configured as 2 NVMe BP and the case of 2 NVMe M.2, at this time, the in-place ID of the corresponding device needs to be added to assist identification and configuration.

[0124] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0125] The embodiment of the present application also provides a firmware management method of a multi-board interconnection device, applied to the above-mentioned multi-board interconnection computing system, Figure 6 is a firmware management method of a multi-board interconnection device according to the embodiment of the present application, as shown in Figure 6 The method comprises the following steps:

[0126] ​Step S602, according to the card function of the plurality of cards connected to the multi-card interconnection device, the plurality of cards are divided into a plurality of levels, a plurality of card sub-codes are generated according to the card models contained in the cards of different levels, and a card code is generated according to the plurality of card sub-codes;

[0127] Step S604, according to the card code, the hardware configuration information of the multi-card interconnection device is determined, and the firmware management of the multi-card interconnection device is performed according to the hardware configuration information.

[0128] Through the above method, the multi-card interconnection device can automatically generate a card code for the access of multiple types of cards, which realizes the identification of the characteristics of different cards, and then determines the hardware configuration information of the multi-card interconnection device according to the card code, so as to realize accurate firmware management strategy and optimize system running state; By using the above scheme, the card is coded and managed according to the function of the card, the card configuration information is accurately identified according to the coding information, and the firmware management of the card is performed, thereby solving the problem that in the related art, one card is often applied to multiple configurations, but the existing technology is difficult to distinguish the multiple configurations of the card and the different configurations caused by different configurations, resulting in difficulty in firmware management.

[0129] Optionally, according to the card code, the hardware configuration information of the multi-card interconnection device is determined, and the firmware management of the multi-card interconnection device is performed according to the hardware configuration information, including: when the computing system starts, the card code is read from the multi-card interconnection device; according to the card code, the power-on sequence of the plurality of cards is determined; according to the power-on sequence, the plurality of cards are controlled to be powered on in sequence.

[0130] At the moment when the computing system starts, the card code information of the multi-card interconnection device is read, and the code determines the power-on sequence of each card in the entire system; the system controls the cards to be powered on in sequence, ensuring the smoothness and optimization of the hardware initialization process.

[0131] Server startup means that the system wakes up from a silent state and enters an initialization process, at which time the card code of the multi-card interconnection device becomes critical. The code information is stored in the device and contains a comprehensive description of all connected cards. From the code, the system can parse the type, quantity and level information of each card. This process is undoubtedly the initial stage of the system identifying its hardware configuration, providing a basis for subsequent resource allocation and firmware management.

[0132] The power-on sequence is a hardware initialization strategy based on board coding, which specifies the power-on order of each board in a multi-board interconnection device. In complex systems, different boards may have different requirements for power supply and initialization. A reasonable power-on sequence can avoid power supply conflicts during power-on and reduce the risk of hardware failure. For example, power-on the underlying infrastructure board such as the power management board or network interface board first, and then start the upper-layer compute-intensive GPU acceleration card or storage device. Such a timing arrangement can ensure the rational use of system resources and the orderly initialization of hardware.

[0133] Controlling the boards to power on in sequence is part of the initialization firmware management of a computing system, which relies on the power-on sequence strategy. Through firmware or BIOS programs, the system can accurately control the power state of each board in a predetermined order, ensuring smooth transition of hardware components to the working state. This mechanism not only improves the startup efficiency of the server, but also reduces hardware compatibility problems caused by improper power-on sequence, providing a guarantee for the stability and security of system operation.

[0134] Optionally, after controlling the multiple boards to power on in sequence according to the power-on sequence, the method further includes: matching the hardware configuration information in the preset configuration data according to the board coding, wherein the preset configuration data is used to indicate the mapping relationship between multiple board codings and multiple hardware configuration information; and loading a target firmware version to the multiple boards according to the hardware configuration information, wherein the target firmware version corresponds to the hardware configuration information.

[0135] After controlling the boards to power on in sequence according to the power-on sequence, the system further acts to find matching hardware configuration information in the preset configuration data according to the board coding; then, according to the configuration information, accurately load the target firmware version that matches to each board, ensuring perfect fit between firmware and hardware.

[0136] It should be noted that the preset configuration data records the correspondence between different board codings and corresponding hardware configuration information. This data set is usually pre-formulated by the designer or maintainer of the system to guide the server to quickly identify and load the correct firmware version according to the current hardware layout when starting. In the configuration data, the board coding serves as an index, and the hardware configuration information describes the function, type, quantity, and level of the board in detail, providing a basis for firmware loading decisions.

[0137] This embodiment embodies the intelligence and automation of firmware management of the computing system. Through the combination of board card coding and preset configuration data, the system can automatically identify the current hardware environment, load the most suitable firmware version, reduce the need for manual intervention, and improve the efficiency of system startup and configuration. In AI servers and high-performance computing platforms, this mechanism is particularly important, as it allows the system to flexibly adapt to changing hardware configurations, ensuring that the correct firmware version is started under any configuration, maximizing the use of hardware resources and meeting the needs of high-performance computing.

[0138] Optionally, after the multiple board cards are sequentially powered on according to the power-on sequence, the method further comprises: monitoring the in-place state and running state of the multiple board cards according to the board card coding; and generating first abnormal information of a target board card if the in-place state or running state of the target board card is abnormal.

[0139] After each board card is started according to the power-on sequence, the system continues to operate and uses board card coding to monitor the state of these board cards in real time, covering the in-place state and running performance. If the state of any board card deviates from the normal state, the system generates an abnormal report immediately and identifies the problem board card, facilitating quick positioning and repair.

[0140] It should be noted that the board card coding is not only an indicator of hardware configuration at startup, but also a key to real-time monitoring of hardware state. Through coding, the system can track each board card, whether it is a computing card, a storage card, or a network interface card, its actual position in the device (in-place state) and working condition (running state). This function is crucial for maintaining the stable operation of servers, especially in large-scale AI cluster environments, as it can immediately detect and report any hardware problems that may affect performance or security.

[0141] Optionally, after the multiple board cards are sequentially powered on according to the power-on sequence, the method further comprises: obtaining hardware connection state and configuration information of the multiple board cards, and obtaining version information of the target firmware version, wherein the power-on sequence is determined according to the hardware connection state and the configuration information; and verifying the version information according to the hardware connection state and the configuration information.

[0142] After each board card is started according to the power-on sequence, the system further obtains hardware connection state, configuration details, and version information of the currently loaded firmware. Based on the collected hardware state and configuration data, the system verifies the firmware version information to ensure that the hardware and firmware version match correctly.

[0143] It is to be noted that the hardware connection state relates to the actual connection status of each board card in the server, which explicitly indicates the physical connection state between the board cards and the mainboard, including whether to be connected, the type of connection (such as PCIe, SATA, etc.), and the stability of the connection. This information is crucial for firmware configuration during system initialization, which guides the firmware to correctly identify and interact with hardware resources, avoiding initialization failure or performance problems caused by connection problems.

[0144] Optionally, after verifying the version information according to the hardware connection state and the configuration information, the method further includes: in the case that the version information fails to pass the verification, issuing a firmware update instruction to a firmware boot module to instruct the firmware boot module to reload firmware to the plurality of board cards.

[0145] After the version information fails to pass the verification, the system immediately takes action to send an update instruction to the firmware boot module to instruct it to reload firmware to each board card, ensuring the matching of hardware and firmware versions and stable operation of the system.

[0146] Through this embodiment, the system can realize automatic monitoring and updating of firmware versions, reducing the need for manual intervention and improving the level of automated management and maintenance of the server. In large-scale clusters and cloud environments, the implementation of this mechanism greatly reduces the system downtime caused by firmware version problems, improves the operation and maintenance efficiency, and has important significance for guaranteeing business continuity and user data security.

[0147] Embodiments of the present application also provide an electronic device comprising a memory and a processor, the memory storing a computer program, and the processor being configured to run the computer program to perform the steps in any of the above-mentioned firmware management method embodiments for a multi-board interconnection device.

[0148] Embodiments of the present application also provide a computer readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above-mentioned firmware management method embodiments for a multi-board interconnection device when running.

[0149] In an exemplary embodiment, the above-mentioned computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic or optical disk, and various media that can store computer programs.

[0150] The embodiment of the present application further provides a computer program product, which comprises a computer program, and the computer program realizes the steps in the method for managing firmware of the multi-board interconnection device when executed by a processor.

[0151] The embodiment of the present application further provides another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program realizes the steps in the method for managing firmware of the multi-board interconnection device when executed by a processor.

[0152] Those skilled in the art can further understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0153] The above describes in detail the method for managing firmware of a multi-board interconnection system and a multi-board interconnection device provided by the present application. The principles and implementation manners of the present application are described by applying specific examples in the present text. The above description of the embodiments is only applicable to help understand the method of the present application and its core idea. It should be pointed out that those skilled in the art can make some improvements and modifications to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A multi-board card-interconnected computing system, comprising: The system comprises: A multi-board card interconnection device connected with a plurality of board cards, configured to divide the plurality of board cards into a plurality of levels according to board card functions of the plurality of board cards, generate a plurality of board card sub-codes according to board card models contained in board cards of different levels, and generate a board card code according to the plurality of board card sub-codes; A system initialization component connected with the multi-board card interconnection device, configured to determine hardware configuration information of the multi-board card interconnection device according to the board card code, and perform firmware management on the multi-board card interconnection device according to the hardware configuration information; The system initialization component comprises a processor, which is configured to: read the board card code from the multi-board card interconnection device when the computing system starts; determine power-on timing of the plurality of board cards according to the board card code; control the plurality of board cards to be powered on in sequence according to the power-on timing. The system initialization component comprises a firmware booting module, which is configured to: read the board card code from the multi-board card interconnection device when the plurality of board cards are powered on; match the hardware configuration information in preset configuration data according to the board card code, wherein the preset configuration data is used to indicate a mapping relationship between a plurality of the board card codes and a plurality of the hardware configuration information; load a target firmware version to the plurality of board cards according to the hardware configuration information, wherein the target firmware version corresponds to the hardware configuration information.

2. The multi-board card interconnected computing system of claim 1, wherein, The system initialization component comprises a controller, which is configured to: read the board card code from the multi-board card interconnection device when the plurality of board cards are powered on; monitor in-place states and running states of the plurality of board cards according to the board card code; generate first abnormal information of a target board card when the in-place state or the running state of the target board card is abnormal.

3. The multi-board card interconnected computing system of claim 2, wherein, The controller is connected with the firmware booting module and the processor, and is further configured to: read hardware connection states and configuration information of the plurality of board cards from the processor, wherein the power-on timing is determined according to the hardware connection states and the configuration information; read version information of the target firmware version from the firmware booting module; verify the version information according to the hardware connection states and the configuration information.

4. The multi-board card interconnected computing system of claim 3, wherein, The controller is further configured to: send a firmware update instruction to the firmware booting module when the version information fails to pass the verification, wherein the firmware update instruction is used to instruct the firmware booting module to reload firmware to the plurality of board cards.

5. The multi-board card interconnected computing system of claim 2, wherein, The controller is further configured to: monitor running data of a plurality of components of the computing system, wherein the plurality of components at least include the multi-board card interconnection device, the processor, and the firmware booting module, and the running data at least includes running temperature, power supply voltage, and power supply state; generate second abnormal information of a target component when it is monitored that the running data of the target component is abnormal.

6. The multi-board card interconnected computing system of claim 1, wherein, The multi-board card interconnection device comprises: PCIe ports connected with the firmware booting module, used to connect PCIe devices to the multi-board interconnection device, wherein the plurality of boards comprises the PCIe devices.

7. The multi-board card interconnected computing system of claim 6, wherein, The PCIe ports comprise N high-bit ports and N low-bit ports, and the PCIe ports are further used to: determine first identification bits corresponding to the N high-bit ports and second identification bits corresponding to the N low-bit ports according to the number and type of the plurality of connected PCIe devices, and send the first identification bits and the second identification bits to the firmware booting module, wherein N is a positive integer, and the first identification bits and the second identification bits are used to determine bandwidth information of the PCIe ports.

8. The multi-board card interconnected computing system of claim 1, wherein, The multi-board interconnection device is further used to: In the case that the plurality of boards connected to the multi-board interconnection device changes, detect the board models of the changed plurality of boards, and regenerate board codes according to the board models of the changed plurality of boards; send the updated board codes to the system initialization component to instruct the system initialization component to update the firmware versions of the changed plurality of boards according to the updated board codes.

9. The multi-board card interconnected computing system of claim 1, wherein, The computing system further comprises: a standby power rail used to provide power for the computing system in the case that the computing system is in a powered-off state, so that the multi-board interconnection device identifies the board models of the plurality of boards and generates the plurality of board sub-codes and the board codes according to the board models of the boards of different levels.

10. A method for managing firmware of a multi-board card interconnect device, the method comprising: The application is applied to the multi-board interconnection computing system of any one of claims 1 to 9, comprising: dividing the plurality of boards connected to the multi-board interconnection device into a plurality of levels according to the board functions of the plurality of boards, generating a plurality of board sub-codes according to the board models contained by the boards of different levels, and generating a board code according to the plurality of board sub-codes; determining hardware configuration information of the multi-board interconnection device according to the board code, and performing firmware management on the multi-board interconnection device according to the hardware configuration information; wherein determining the hardware configuration information of the multi-board interconnection device according to the board code and performing firmware management on the multi-board interconnection device according to the hardware configuration information comprises: reading the board code from the multi-board interconnection device when the computing system starts; determining power-on sequences of the plurality of boards according to the board code; controlling the plurality of boards to be powered on in sequence according to the power-on sequences; wherein after controlling the plurality of boards to be powered on in sequence according to the power-on sequences, the method further comprises: matching the hardware configuration information in the preset configuration data according to the board code, wherein the preset configuration data is used to indicate the mapping relationship between a plurality of board codes and a plurality of hardware configuration information; loading a target firmware version to the plurality of boards according to the hardware configuration information, wherein the target firmware version corresponds to the hardware configuration information.

11. The method of claim 10, wherein: after controlling the plurality of boards to be powered on in sequence according to the power-on sequences, the method further comprises: According to the board card code, the in-place state and the running state of the plurality of board cards are monitored. In a case where the in-place state or the running state of a target board card in the plurality of board cards is abnormal, first abnormal information of the target board card is generated.

12. The method of claim 11, wherein: After the plurality of board cards are sequentially powered on according to the power-on timing, the method further comprises: Obtaining hardware connection state and configuration information of the plurality of board cards, and obtaining version information of a target firmware version, wherein the power-on timing is determined according to the hardware connection state and the configuration information; According to the hardware connection state and the configuration information, the version information is verified.

13. The method of claim 12, wherein: After the hardware connection state and the configuration information are verified, the method further comprises: In a case where the version information fails to pass the verification, a firmware update instruction is issued to a firmware booting module to instruct the firmware booting module to reload firmware to the plurality of board cards.

14. A computer readable storage medium, characterized in that, The computer readable storage medium stores a computer program, wherein the computer program is executed by a processor to implement the steps of the method of any one of claims 10 to 13.

15. An electronic device, comprising: including: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the method of any one of claims 10 to 13.

16. A computer program product comprising a computer program, characterized in that, The computer program is executed by a processor to implement the steps of the method of any one of claims 10 to 13.

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