A BMC chip and electronic device

Abstract

The application provides a BMC chip and an electronic device, and relates to the technical field of computers.A BMC chip comprises a network interconnection bus, a main processor connected with the network interconnection bus based on an AXI interface or an AHB interface, a storage resource system, all modules in the storage resource system being connected with the network interconnection bus based on the AXI interface or the AHB interface, a first peripheral system, all modules in the first peripheral system being connected with the network interconnection bus based on the AXI interface or the AHB interface, a second peripheral system, data bandwidth required by the second peripheral system being smaller than data bandwidth required by the first peripheral system, all modules in the second peripheral system being connected with the network interconnection bus based on an APB interface or an AHB interface, and a security system, all modules of the security system being connected with the network interconnection bus based on the AHB interface.Thus, the data interaction efficiency can be improved, and the system delay can be reduced.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more particularly to a BMC chip and electronic device. Background Technology

[0002] With the development of integrated circuit technology, the functions of system-on-chip (SoC) chips such as baseboard management controller (BMC) chips are becoming increasingly complex, requiring the connection of a large number of master and slave devices. These master and slave devices differ significantly in terms of function, operation mode, data bandwidth and real-time requirements. As the central hub for module interconnection, the performance of the system bus directly determines the overall efficiency of the SoC system.

[0003] Currently, Advanced Microcontroller Bus Architecture (AMBA) is primarily used to meet the multi-user, high-performance, and low-power requirements of SoC systems. AMBA-compatible on-chip network interconnect (IP) cores, such as the CoreLink NIC400, can achieve interconnection between various master-slave devices through flexible topologies, building an efficient and low-power communication architecture. However, maximizing bus bandwidth utilization to improve overall system data interaction bandwidth and reduce latency remains a pressing technical challenge.

[0004] In related technologies, the data interaction bandwidth is mainly increased by increasing the overall operating frequency or expanding the bus width of the overall interface. However, the former will significantly increase the power consumption of the chip and make timing difficult to converge; the latter will increase the difficulty of back-end layout and routing, and also cause timing convergence problems, and may also reduce the overall operating frequency. Summary of the Invention

[0005] This application provides a BMC chip and an electronic device to at least solve the above-mentioned technical problems existing in the prior art.

[0006] According to a first aspect of this application, a BMC chip is provided, the chip comprising: a network interconnect bus; a main processor connected to the network interconnect bus via an AXI interface or an AHB interface; a storage resource system, wherein all modules in the storage resource system are connected to the network interconnect bus via an AXI interface or an AHB interface; a first peripheral system, wherein all modules in the first peripheral system are connected to the network interconnect bus via an AXI interface or an AHB interface; a second peripheral system, wherein the data bandwidth required by the second peripheral system is less than that required by the first peripheral system, and all modules in the second peripheral system are connected to the network interconnect bus via an APB interface or an AHB interface; and a security system, wherein all modules in the security system are connected to the network interconnect bus via an AHB interface; wherein the AHB interface and the APB interface are divided into multiple groups, each group comprising multiple modules, all groups being configured with corresponding bus bandwidth, and the multiple modules within each group sharing the bus bandwidth of that group.

[0007] In one embodiment, the storage resource system includes at least one of a DDR module, an SRAM module, and a ROM module.

[0008] In one possible implementation, the first peripheral system includes at least one of a USB module, a VGA module, an EMAC module, a PCIe module, an H2B module, an MCTP module, and an SD module.

[0009] In one embodiment, the second peripheral system includes a first peripheral unit and a second peripheral unit; the processing latency required by the first peripheral unit is greater than the processing latency required by the second peripheral unit.

[0010] In one possible implementation, all modules in the first peripheral unit are connected to the network interconnect bus via the APB interface; all modules in the second peripheral unit are connected to the network interconnect bus via the AHB interface.

[0011] In one possible implementation, the first peripheral unit includes at least one of an I2C module, a UART module, an ADC module, a WDT module, a GPIO module, and an I2S module; the second peripheral unit includes at least one of an LPC module, a QSPI module, an I3C module, a PECI module, a PTC module, and an ESPI module.

[0012] In one embodiment, the security system includes at least one of a hash algorithm module, a symmetric encryption / decryption module, an asymmetric encryption / decryption module, and a secure boot module.

[0013] In one embodiment, the APB interface is divided into 6 groups, each group containing up to 16 modules, and only one module in each group can use the bus bandwidth of that group at any given time.

[0014] In one embodiment, the AHB interface is divided into 10 groups, each group containing up to 16 modules, and only one module in each group can use the bus bandwidth of that group at any given time.

[0015] In one embodiment, the DDR module in the storage resource system is connected to the network interconnect bus via a first AXI interface, wherein the data width of the first AXI interface is 64 bits or 128 bits.

[0016] In one possible implementation, the PCIe module in the first peripheral system is connected to the network interconnect bus via a second AXI interface, wherein the data width of the second AXI interface is 64 bits.

[0017] In one embodiment, the main processor is connected to the network interconnect bus via a third AXI interface, the third AXI interface having a data width of 128 bits.

[0018] In one possible implementation, apart from the DDR module in the storage resource system, the PCIe module in the first peripheral system, and the main processor, the data bit width of the AXI interface corresponding to the other modules is 32 bits.

[0019] In one embodiment, the CDAS of the main processor is configured in a first mode, which supports concurrent access to multiple modules, and different IDs are required to access different modules; the CDAS of other modules connected to the network interconnect bus, in addition to the main processor, are configured in a second mode, which allows access to only one module at a time.

[0020] In one embodiment, a BMC chip further includes: an internal data processing system connected to the network interconnect bus via an AXI interface; and a DMA system connected to the network interconnect bus via an AHB interface.

[0021] In one possible implementation, the internal data processing system includes a JPEG module; the DMA system includes a DMAC module.

[0022] In one embodiment, a BMC chip further includes a coprocessor connected to the network interconnect bus via an assisted interconnect bus.

[0023] In one possible implementation, the coprocessor is connected to the assist interconnect bus via an AXI interface or an AHB interface; the assist interconnect bus is connected to the network interconnect bus via an AXI interface or an AHB interface.

[0024] In one possible implementation, the network interconnect bus is an AMBA protocol-compatible interconnect bus.

[0025] According to a second aspect of this disclosure, an electronic device is provided, the electronic device including the BMC chip described in this disclosure.

[0026] This application discloses a BMC chip and electronic device. The BMC chip groups AHB and APB interfaces and allocates independent bus bandwidth to each group, allowing different modules to share bandwidth resources according to their data bandwidth requirements. This grouping and bandwidth allocation strategy effectively avoids bandwidth contention, significantly improves data interaction efficiency, and reduces system latency. Simultaneously, different modules select appropriate interface types based on their data bandwidth needs. For example, the main processor, storage resource system, and first peripheral system with high bandwidth requirements use AXI or AHB interfaces, while the second peripheral system with low bandwidth requirements uses APB or AHB interfaces, further optimizing system performance and power consumption management. Furthermore, the network interconnect bus design enhances system flexibility and scalability, facilitating future system upgrades and module replacements.

[0027] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0028] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which:

[0029] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0030] Figure 1 A schematic diagram of the structure of a BMC chip according to an embodiment of this application is shown;

[0031] Figure 2 This application illustrates a schematic diagram of the internal interconnection structure of a BMC chip according to an embodiment of the present application. Figure 1 ;

[0032] Figure 3 This application illustrates a schematic diagram of the internal interconnection structure of a BMC chip according to an embodiment of the present application. Figure 2 . Detailed Implementation

[0033] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] Figure 1 A schematic diagram of the structure of a BMC chip according to an embodiment of this application is shown, as follows: Figure 1 As shown, a BMC chip includes:

[0035] Network interconnect bus;

[0036] The main processor is connected to the network interconnect bus via an AXI or AHB interface.

[0037] The storage resource system, in which all modules are connected to the network interconnect bus based on the AXI or AHB interface;

[0038] The first peripheral system, in which all modules are connected to the network interconnect bus based on the AXI or AHB interface;

[0039] The second peripheral system requires less data bandwidth than the first peripheral system. All modules in the second peripheral system are connected to the network interconnect bus based on the APB interface or AHB interface.

[0040] The security system's modules are all connected to the network interconnect bus via the AHB interface.

[0041] The AHB and APB interfaces are divided into multiple groups, each containing multiple modules. All groups are configured with corresponding bus bandwidth, and the multiple modules within each group share the bus bandwidth of that group.

[0042] In this embodiment, the BMC chip design aims to achieve a balance between performance, area, and power consumption. The realization of this goal depends on the differentiated design of the interfaces of different modules. First, based on the functions and access permissions of all modules in the BMC chip, all modules in the BMC chip are classified to obtain the main processor, storage resource system, first peripheral system, second peripheral system, and security system.

[0043] The main processor can be a central processing unit (CPU) or a graphics processing unit (GPU). As the core of the SoC chip to implement various functions, the main processor has the highest data access permission and can access all functional modules except for some modules in the security system. At the same time, the main processor needs to handle a large number of tasks simultaneously, so it is necessary to ensure high total data bandwidth, high concurrency processing, and low data transmission latency, thereby improving the performance of the main processor.

[0044] Storage resource systems include, for example Figure 1 The system includes at least one of the following: Double Data Rate (DDR) module, Static Random Access Memory (SRAM) module, and Read Only Memory (ROM) module. The storage resource system is used for data storage and retrieval and is the system with the highest bandwidth for data processing and data exchange. This includes all modules in the first peripheral system, all modules in the security system, some modules in the second peripheral system, and... Figure 1 The Direct Memory Access Controller (DMAC) module in the system has access rights to the storage resource system and generally needs to access it frequently and at high speed, so it is necessary to prioritize data bandwidth.

[0045] The first peripheral system includes Figure 1 At least one module in the External high-speed system, and all modules in the first peripheral system, have data access permissions only for data interaction with the Double Data Rate Synchronous Dynamic Random Access Memory (DDR) in the main processor and storage resource system. The data access path is relatively simple, but the required data bandwidth is high. That is, all modules in the first peripheral system require high data interaction speeds; the first peripheral system can also be called a high-speed peripheral system. It is important to emphasize that each module in the first peripheral system has an independent interface connected to the network interconnect bus. Figure 1 The only arrow in the diagram connecting to the network interconnect bus is simply to illustrate the classification information.

[0046] The second peripheral system includes Figure 1At least one module in the External low-speed (APB) and External low-speed (AHB) systems only has access to interact with the main processor and DMAC. The data access path is relatively simple, requiring lower data bandwidth and lower latency. In other words, all modules in the second peripheral system require low data interaction speeds; therefore, the second peripheral system can also be called a low-speed peripheral system. It is important to emphasize that each module in the second peripheral system has an independent interface connected to the network interconnect bus. Figure 1 The only arrow in the diagram connecting to the network interconnect bus is simply to illustrate the classification information.

[0047] Security systems, including such Figure 1 The security system in AHB (Automatic Bootloader) is at least one module. It's a special functional system with two main functions: firstly, it needs to verify the processor system's boot firmware, operating before the CPU boots; secondly, for security reasons related to the BMC chip, access permissions for the security system need to be restricted, typically allowing only the main processor access to certain units. Furthermore, the security system requires special design in the BMC chip's backend to enhance security. Therefore, modules within the security system are usually processed together during chip placement and routing. Thus, its access permissions include: the main processor accessing certain units within the security system, and the security system accessing SRAM and DDR memory for verifying the processor system's boot firmware.

[0048] In this embodiment, it is also necessary to determine the interface corresponding to each module based on the bandwidth and latency characteristics required by the module. The interfaces in this application include the Advanced Peripheral Bus (APB) interface, the Advanced High-performance Bus (AHB) interface, and the Advanced eXtensible Interface (AXI) under the AMBA bus. Specifically, the APB interface is a low-speed interface designed to minimize resource consumption; the AHB interface is a medium-speed interface used to balance area, power consumption, and performance; and the AXI interface is a high-speed interface used to achieve high bandwidth and low latency.

[0049] The main processor needs to ensure high total data bandwidth, high concurrency processing, and low data transmission latency. Therefore, the main processor needs to be connected to the network interconnect bus based on the AXI interface or AHB interface.

[0050] Storage resource systems typically require frequent and high-speed access, necessitating priority in ensuring data bandwidth. Therefore, all modules within a storage resource system are connected to the network interconnect bus via AXI or AHB interfaces.

[0051] The first peripheral system requires high data bandwidth; therefore, all modules in the first peripheral system are connected to the network interconnect bus based on the AXI or AHB interface.

[0052] The second peripheral system requires less data bandwidth than the first peripheral system and has lower requirements for data access latency. Therefore, all modules in the second peripheral system are connected to the network interconnect bus based on the APB or AHB interface.

[0053] Security systems have high requirements for data access latency; therefore, all modules of the security system are connected to the network interconnect bus based on the AHB interface.

[0054] In this embodiment, the AHB and APB interfaces are divided into multiple groups, each group containing multiple modules. All groups are configured with corresponding bus bandwidth, and the multiple modules within each group share the bus bandwidth of that group. The core logic of the grouping is to categorize low-speed or medium-speed modules with similar functions and data interaction requirements, so that these modules can share the bus bandwidth of the corresponding group.

[0055] In this application, by grouping the AHB and APB interfaces and allocating independent bus bandwidth to each group, different modules can share bandwidth resources according to their data bandwidth requirements. This grouping and bandwidth allocation strategy effectively avoids bandwidth contention, significantly improves data interaction efficiency, and reduces system latency. Simultaneously, different modules select appropriate interface types based on their data bandwidth requirements; for example, the main processor, storage resource system, and first peripheral system with high bandwidth requirements use AXI or AHB interfaces, while the second peripheral system with low bandwidth requirements uses APB or AHB interfaces, further optimizing system performance and power consumption management. Furthermore, the network interconnect bus design enhances system flexibility and scalability, facilitating future system upgrades and module replacements.

[0056] In another embodiment, the first peripheral system includes at least one of the following: a Universal Serial Bus (USB) module, a Video Graphics Array (VGA) data receiving and processing module, an Ethernet Media Access Controller (EMAC) module, a Peripheral Component Interconnect Express (PCIe) module, a Host-to-BMC (H2B) module, a Management Component Transport Protocol (MCTP) module, and an SD card interface (SD) module.

[0057] In another embodiment, the second peripheral system includes a first peripheral unit and a second peripheral unit; the processing latency required by the first peripheral unit is greater than that required by the second peripheral unit. That is, both the first and second peripheral units have low data bandwidth requirements, but the first peripheral unit has low latency requirements for data access and processing, and is not sensitive to latency, meaning it can accept longer latency periods; the second peripheral unit has high real-time requirements for data access and processing, meaning it cannot accept longer latency periods. The first peripheral unit includes... Figure 1 External low-speed: at least one module in the APB; the second peripheral unit includes Figure 1 External low-speed: at least one module in AHB.

[0058] In another embodiment, all modules in the first peripheral unit are connected to the network interconnect bus via the APB interface; all modules in the second peripheral unit are connected to the network interconnect bus via the AHB interface. The first peripheral unit has low requirements for data access and processing latency, is not sensitive to latency, and can accept longer delays; therefore, all modules in the first peripheral unit are connected to the network interconnect bus via the APB interface. The second peripheral unit has high requirements for real-time data access and processing, and cannot accept longer delays; therefore, all modules in the second peripheral unit are connected to the network interconnect bus via the AHB interface.

[0059] In another embodiment, the first peripheral unit includes at least one of the following: an Inter-Integrated Circuit module, a Universal Asynchronous Receiver / Transmitter (UART) module, an Analog-to-Digital Converter (ADC) module, a Watchdog Timer (WDT) module, a General-Purpose Input / Output (GPIO) module, and an Inter-IC Sound (I2S) module.

[0060] In another embodiment, the second peripheral unit includes at least one of the following: a Low Pin Count (LPC) module, a Quad Serial Peripheral Interface (QSPI) module, an Improved Inter-Integrated Circuit (I3C) module, a Platform Environment Control Interface (PECI) module, a Pulse Width Modulation and Tachocontroller (PTC) module, and an Enhanced Serial Peripheral Interface (ESPI).

[0061] In another embodiment, the security system includes at least one of a hash algorithm module, a symmetric encryption / decryption module, an asymmetric encryption / decryption module, and a secure boot module. The asymmetric encryption / decryption module may include an Elliptic Curve Cryptography (ECC) algorithm and a Rivest-Shamir-Adleman (RSA) algorithm; therefore, the asymmetric encryption / decryption module may also be referred to as an ECC / SA module.

[0062] In another embodiment, the APB interface is divided into 6 groups, each group containing up to 16 modules, and only one module in each group can use the bus bandwidth of that group at any given time.

[0063] In this embodiment, before grouping the APB and AHB interfaces, we will first introduce the principle of optimizing the performance, area, and power consumption of the bus interconnect structure through interface grouping. The bus interconnect structure can be divided into three categories:

[0064] Category 1: Shared address bus and shared data buses (SASD). This combination of a shared address bus and a bidirectional read / write data bus allows each channel to be used by only one master and one slave device. When a master device sends address information to a slave device, other master devices cannot occupy the address bus. This structure results in significant latency and low processing bandwidth.

[0065] Category 2: Multiple address buses and multiple data buses (MAMD). This combines a dedicated address bus with dedicated read and write data channels, allowing multiple master and slave devices to occupy each channel. This parallel access mechanism effectively improves data throughput and reduces access latency. While MAMD maximizes interconnect performance, it correspondingly increases design complexity, area, and power consumption.

[0066] Category 3: Hybrid Address / Data Channel Interconnect, which is a hybrid of "multiple address / data channels" and "shared address / data channels." The interconnect structure of this bus contains both dedicated address / data channels and shared address / data channels. Theoretically, this type of bus structure can meet the needs of various functional modules with different bandwidth requirements. Therefore, this application uses this bus structure for interconnection. However, how to group and configure the interconnects to achieve the highest performance, minimum area, and minimum power consumption is a crucial issue.

[0067] In this embodiment, the APB interface can be divided into 6 groups, each group containing up to 16 modules. Only one module in each group can use the bus bandwidth of that group at any given time.

[0068] In one example, the APB interface can be grouped as shown in Table 1 below:

[0069] Table 1

[0070]

[0071] Here, master represents the host interface, master_peci represents the host interface of the PECI module, and so on for other interfaces, which will not be elaborated here; n represents the existence of n modules with the same function. For example, master_I3C_n represents the existence of n I3C host interfaces. The value of n is set according to the actual usage requirements, but it must meet the requirement that each group of APB interfaces has a maximum of 16 modules, that is, the total number of n plus the number of other modules does not exceed 16.

[0072] In another embodiment, the AHB interface is divided into 10 groups, each group containing up to 16 modules, and only one module in each group can use the bus bandwidth of that group at any given time.

[0073] In one example, the AHB interface can be grouped as shown in Table 2 below:

[0074] Table 2

[0075]

[0076] Here, master represents the host interface, slave represents the slave interface, master_eccsra is the host interface of the eccsra unit, and other interfaces follow the same pattern, which will not be elaborated here; n represents the existence of n units with the same function. For example, master_sd_n represents the existence of n SD host interfaces, and the value of n is set according to the actual bandwidth requirements.

[0077] In another embodiment, the DDR module in the storage resource system is connected to the network interconnect bus via a first AXI interface, which has a data width of 64 bits or 128 bits. The AXI interface offers the highest bandwidth and lowest latency. During interface allocation and configuration, interfaces with high bandwidth and real-time requirements are set to AXI interfaces, and the data interface width is appropriately increased to achieve high performance and low latency. Therefore, for a DDR module, the data width of its corresponding AXI interface can be 64 bits or 128 bits.

[0078] In another embodiment, the PCIe module in the first peripheral system is connected to the network interconnect bus via a second AXI interface, the second AXI interface having a data width of 64 bits. For the PCIe module, the corresponding AXI interface can have a data width of 64 bits.

[0079] In another embodiment, the main processor connects to the network interconnect bus via a third AXI interface, which has a data width of 128 bits. For the main processor, the corresponding AXI interface can have a data width of 128 bits.

[0080] In another embodiment, except for the DDR module in the storage resource system, the PCIe module in the first peripheral system, and the main processor, the data width of the AXI interfaces for other modules is 32 bits. That is, the data width of all AXI interfaces except for the first, second, and third AXI interfaces is 32 bits. It is important to emphasize that all AXI modules are independent and not grouped to achieve the highest performance and concurrency characteristics.

[0081] In another embodiment, the CDAS of the main processor is configured in a first mode, which supports concurrent access to multiple modules, and different IDs are required to access different modules; the CDAS of other modules connected to the network interconnect bus, apart from the main processor, are configured in a second mode, which allows access to only one module at a time.

[0082] In this embodiment, the first mode can be slave_per_id, and the second mode can be single_slave. The CDAS of the main processor is configured in the first mode to ensure concurrent access and high-performance processing of the main processor. The CDAS of other modules connected to the network interconnect bus are configured in the second mode to reduce the risk of bus deadlock.

[0083] In another embodiment, a BMC chip further includes:

[0084] The internal data processing system is connected to the network interconnection bus based on the AXI interface.

[0085] The DMA system connects to the network interconnect bus based on the AHB interface.

[0086] In this embodiment, the internal data processing system includes, for example, Figure 1 The Joint Photographic Experts Group (JPEG) module shown is used for internal data processing and has high requirements for data bandwidth and latency. Its access permissions include access by the main processor for data interaction and access to DDR memory by the internal data processing system. Because of the high bandwidth and latency requirements of the internal data processing system, it is connected to the network interconnect bus via an AXI interface.

[0087] In this embodiment, the DMA system includes, for example, Figure 1The DMAC module shown is a DMA system that facilitates data exchange between internal memory, external memory, and internal functional modules. It achieves high-speed data transfer and connects to multiple systems. Its access permissions include data interaction with the main processor, the first peripheral system, and the second peripheral system. The DMA system has a complex data access path and requires high data bandwidth; therefore, it connects to the network interconnect bus based on the AHB interface.

[0088] In another embodiment, a BMC chip further includes:

[0089] The coprocessor is connected to the network interconnect bus via the co-connect bus.

[0090] In this embodiment, the coprocessor, similar to the main processor, needs to ensure high total data bandwidth, high concurrency processing, and low data transmission latency. Therefore, the coprocessor needs to connect to the network interconnect bus via an AXI or AHB interface. The auxiliary interconnect bus also needs to ensure high total data bandwidth, high concurrency processing, and low data transmission latency; therefore, the auxiliary interconnect bus connects to the network interconnect bus via an AXI or AHB interface.

[0091] In another embodiment, the network interconnect bus is an AMBA protocol-compliant interconnect bus. The AMBA protocol can meet the SoC system's requirements for multi-user, high-performance, and low-power consumption.

[0092] Figure 2 This application illustrates a schematic diagram of the internal interconnection structure of a BMC chip according to an embodiment of the present application. Figure 1 ,like Figure 2 As shown, the main processor and PCIe module, etc. (in order to reduce...) Figure 2 The complexity of the module (not shown in other modules) is directly connected to multiple corresponding AHB groups (AHB_group0-AHB_group9). This indicates that the main processor and PCIe can directly access these AHB groups to perform data read and write operations, making it the main control and data initiation point in the system. Through its connection with the AHB groups, it dominates some data transmission and module interaction.

[0093] Some AHB groups (such as AHB_group6 and AHB_group9) are not directly connected to APB groups, but are connected to APB groups (APB_group0~APB_group5) through a switch. The switch here acts as a bus exchange and routing mechanism. It can guide access requests from AHB groups to different APB groups according to certain rules or control signals, realizing a more flexible interconnection between the AHB bus and the APB bus, and enabling data exchange between modules of different bus types.

[0094] Through this bus interconnect architecture, the chip can rationally allocate bus resources according to the performance requirements of different modules, which not only ensures the data transmission efficiency of high-performance modules, but also effectively manages the communication of peripheral modules, thus realizing efficient and orderly data interaction and control between various modules within the chip.

[0095] It should be emphasized that, due to the complexity of the connections, a diagram is attached for clearer representation. Figure 2 Only interconnection relationships other than DDR access relationships are listed. For DDR access relationships, please refer to the appendix. Figure 3 .

[0096] Figure 3 This application illustrates a schematic diagram of the internal interconnection structure of a BMC chip according to an embodiment of the present application. Figure 2 ,like Figure 2 As shown, DDR, as a storage resource, is connected to AHB groups AHB_group0 through AHB_group9. This means that each AHB group can interact with DDR, such as reading data from or writing data to DDR. The AHB bus has high performance and is suitable for connecting modules with certain requirements for data transfer speed and bandwidth. Through its connection with DDR, the modules connected to each AHB group can efficiently access the data stored in DDR to meet their own computing and storage needs, thereby ensuring the overall efficient operation of the chip.

[0097] This application has the following technical effects:

[0098] 1. Enables any master interface to access its corresponding slave interface via a maximum of two levels of switches. Reduces latency during internal interconnection.

[0099] 2. Grouping reduces the access paths between different groups, thus reducing area and power consumption.

[0100] 3. The main processor uses multiple independent channels to connect to other interface switches, without other interfaces competing for the main processor's performance and priority.

[0101] 4. The network hierarchy is simplified, the clock frequency of some routing and switching systems is reduced, and the data bandwidth of some routing and switching systems is reduced.

[0102] According to embodiments of this application, this application also provides an electronic device that includes a BMC chip according to this disclosure.

[0103] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0104] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0105] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A BMC chip, characterized in that, The chip includes: Network interconnect bus; The main processor is connected to the network interconnect bus via an AXI interface or an AHB interface. A storage resource system, wherein all modules in the storage resource system are connected to the network interconnect bus based on an AXI interface or an AHB interface; The first peripheral system, in which all modules are connected to the network interconnect bus via an AXI or AHB interface; The second peripheral system requires less data bandwidth than the first peripheral system. All modules in the second peripheral system are connected to the network interconnect bus based on the APB interface or AHB interface. The security system, in which all modules are connected to the network interconnect bus via an AHB interface; The AHB and APB interfaces are divided into multiple groups, each containing multiple modules. All groups are configured with corresponding bus bandwidth, and the multiple modules within each group share the bus bandwidth of that group. The second peripheral system includes a first peripheral unit and a second peripheral unit; the processing latency required by the first peripheral unit is greater than the processing latency required by the second peripheral unit. In this configuration, all modules in the first peripheral unit are connected to the network interconnect bus via the APB interface; all modules in the second peripheral unit are connected to the network interconnect bus via the AHB interface. The APB interface is divided into 6 groups, each group containing up to 16 modules. Only one module in each group can use the bus bandwidth of that group at any given time. The AHB interface is divided into 10 groups, each group containing up to 16 modules. Only one module in each group can use the bus bandwidth of that group at any given time. The DDR module in the storage resource system is connected to the network interconnect bus based on the first AXI interface, and the data bit width of the first AXI interface is 64 bits or 128 bits. In this system, the PCIe module in the first peripheral system is connected to the network interconnect bus based on the second AXI interface, and the data width of the second AXI interface is 64 bits. The main processor is connected to the network interconnect bus via a third AXI interface, and the data width of the third AXI interface is 128 bits. Except for the DDR module in the storage resource system, the PCIe module in the first peripheral system, and the main processor, the data width of the AXI interface corresponding to the other modules is 32 bits.

2. The chip according to claim 1, characterized in that, The storage resource system includes at least one of a DDR module, an SRAM module, and a ROM module.

3. The chip according to claim 1, characterized in that, The first peripheral system includes at least one of a USB module, a VGA module, an EMAC module, a PCIe module, an H2B module, an MCTP module, and an SD module.

4. The chip according to claim 1, characterized in that, The first peripheral unit includes at least one of an I2C module, a UART module, an ADC module, a WDT module, a GPIO module, and an I2S module; the second peripheral unit includes at least one of an LPC module, a QSPI module, an I3C module, a PECI module, a PTC module, and an ESPI module.

5. The chip according to claim 1, characterized in that, The security system includes at least one of a hash algorithm module, a symmetric encryption / decryption module, an asymmetric encryption / decryption module, and a secure boot module.

6. The chip according to claim 1, characterized in that, The CDAS of the main processor is configured in a first mode, which supports concurrent access to multiple modules. Different IDs are required to access different modules. Apart from the main processor, the CDAS of all other modules connected to the network interconnect bus are configured in a second mode, which allows access to only one module at a time.

7. The chip according to claim 1, characterized in that, Also includes: An internal data processing system, which is connected to the network interconnect bus via an AXI interface; A DMA system, which is connected to the network interconnect bus via an AHB interface.

8. The chip according to claim 7, characterized in that, The internal data processing system includes a JPEG module; the DMA system includes a DMAC module.

9. The chip according to claim 1, characterized in that, Also includes: A coprocessor, which is connected to the network interconnect bus via a cooperating interconnect bus.

10. The chip according to claim 9, characterized in that, The coprocessor is connected to the cooperating interconnect bus via an AXI interface or an AHB interface; the cooperating interconnect bus is connected to the network interconnect bus via an AXI interface or an AHB interface.

11. The chip according to claim 1, characterized in that, The network interconnect bus is an AMBA protocol-compatible interconnect bus.

12. An electronic device, characterized in that, The electronic device includes a BMC chip according to any one of claims 1-11.

Images