Chip backend module hierarchical structure diagram construction method and system and related device

Abstract

The application provides a chip back-end module hierarchical structure diagram construction method, system and related equipment, the method comprises the following steps: traversing all modules of the chip back-end to obtain module set data containing different hierarchical modules; in the module set data, the non-top-level modules are screened out to obtain a top-level module set; each module in the top-level module set is given an initial field; in the top-level module set, whether the next-level module relationship information contained by each module is empty is judged in turn, if not, the additional field is given to each next-level module corresponding to the module according to the initial field; the step is repeated until each module has a field; the module set data is arranged according to the field possessed by each module, and a module hierarchical structure diagram is output. The hierarchical analysis process is flexible and simple enough, which is beneficial to improving the chip back-end design efficiency.

Description

TECHNICAL FIELD

[0001] The present application is suitable for the chip digital back-end technical field, and particularly relates to a chip back-end module hierarchy structure diagram construction method and system and related equipment. BACKGROUND

[0002] A chip is usually composed of many different modules, and there is a relatively close connection relationship and hierarchical relationship between the modules. Different module hierarchies affect the configuration, combination and optimization of the modules, so it is particularly important to quickly sort the module hierarchies between the chip modules and obtain the structure diagram in the chip digital back-end field.

[0003] In the prior art, in order to obtain the module hierarchy of the modules, the port connection relationship in the register transfer level (RTL) code is usually sorted, and the principle is as shown in Figure 1 The port (dark part) is sorted layer by layer from top to bottom or from bottom to top, and the chip module having a connection relationship with the port is found through the port, and finally the module hierarchy data of all the modules is obtained.

[0004] However, the register transfer level code relied on in the above scheme has quality requirements. This code generally requires the basic design of the whole chip, and the instantiation relationship of each module needs to be determined, which requires a certain design progress of the chip digital back-end. On the other hand, the sorting of the register transfer level code also needs commercial code analysis tools, and the complex code content will increase the reading and analysis difficulty in the analysis tools. Due to the above problems, the existing module hierarchy analysis method is not flexible enough, and it is not conducive to the addition, deletion and modification of the modules in the back-end design during the analysis process. In addition, the code dependency path is long, and it is relatively difficult to be used for early design and evaluation of the chip digital back-end project. SUMMARY

[0005] The present application provides a chip back-end module hierarchy structure diagram construction method, system and related equipment, which aims to solve the technical problems of complex analysis and difficult progress control caused by the dependence of the register transfer level code in the existing chip back-end module hierarchy structure.

[0006] To solve the above technical problems, in a first aspect, the present application provides a chip back-end module hierarchy structure diagram construction method, which comprises the following steps:

[0007] S101, all modules of the chip back-end are traversed to obtain module set data containing different level modules, wherein each module has next level module relationship information of the next level module corresponding thereto;

[0008] S102, filtering the non-top-level modules in the module set data according to the next-level module relationship information to obtain a top-level module set;

[0009] S103, assigning an initial field to each module in the top-level module set;

[0010] S104, in the top-level module set, judging whether the next-level module relationship information contained in each module is empty: if not, assigning an additional field to each next-level module corresponding to the module according to the initial field; repeating the step until each module in the module set data except the modules contained in the top-level module set has the additional field;

[0011] S105, arranging the module set data according to the initial field or the additional field possessed by each module in the module set data, and outputting to obtain a module hierarchical structure diagram.

[0012] Further, in step S103, the initial field in the form of a numerical value is assigned to each module in the top-level module set in a numerical value increasing manner, and the initial field is a positive integer.

[0013] Further, define Ln to represent the level of the module, where n is the level number, the module in the top-level module set is L1 level, and the number of next-level modules that can be contained by each module in the top-level module set is h, h = 2, and step S104 includes the following sub-steps:

[0014] S1041, traversing the modules in the top-level module set according to the numerical value of the initial field;

[0015] S1042, taking the module at Ln level as a parent module, determining the level Ln+1 of the child module of the parent module according to the level Ln of the parent module, and judging whether the next-level module relationship information possessed by the parent module is empty:

[0016] If yes, h = 2, and return to step S1041;

[0017] If not, go to step S1043;

[0018] S1043, assigning the additional field to each child module of the current parent module according to the following relationship formula (1):

[0019] (1);

[0020] Wherein, value(Ln+1) represents the additional field, value(Ln) represents the initial field or the additional field contained in the parent module, j represents the jth sub-module of the parent module being assigned a field; starting from j = 1, sequentially assigning a field to each sub-module, j = j + 1;

[0021] S1044, Ln = Ln + 1, h = h + 1, return to step S1042.

[0022] Further, in step S105, the initial field or the additional field possessed by each module in the module set data is set as numerical data, all the modules in the module set data are sorted according to the numerical data from small to large, and the sorting result is output as the module hierarchical structure diagram.

[0023] Further, step S101 further comprises:

[0024] The next-level module relationship information of each module is set based on the chip connection relationship.

[0025] Further, the initial field and the additional field are stored in the form of a dictionary.

[0026] Further, in step S105, the module information, level, and the initial field or the additional field possessed by all the modules are output as entries of the module hierarchical structure diagram.

[0027] In a second aspect, the present application further provides a system for constructing a chip backend module hierarchical structure diagram, comprising:

[0028] A traversal unit is configured to traverse all the modules of the chip backend to obtain module set data containing different level modules, wherein each module has next-level module relationship information of a next-level module corresponding thereto;

[0029] A screening unit is configured to screen non-top-level modules in the module set data according to the next-level module relationship information to obtain a top-level module set.

[0030] An initialization unit is configured to assign an initial field to each module in the top-level module set.

[0031] an assignment unit, configured to judge whether the next-level module relationship information contained in each of the modules in the top module set is empty in sequence: if not, an additional field is assigned to each next-level module corresponding to the module according to the initial field; the execution is repeated until each of the modules in the module set data except the modules contained in the top module set has the additional field;

[0032] an output unit, configured to arrange the module set data according to the initial field or the additional field possessed by each of the modules in the module set data, and output a module hierarchical structure diagram.

[0033] In a third aspect, the present application also provides a computer device, comprising a memory, a processor, and a chip backend module hierarchical structure diagram construction program stored in the memory and executable on the processor, and the processor implements the steps in the chip backend module hierarchical structure diagram construction method according to any one of the above embodiments when executing the chip backend module hierarchical structure diagram construction program.

[0034] In a fourth aspect, the present application also provides a computer readable storage medium, which stores a chip backend module hierarchical structure diagram construction program, and the chip backend module hierarchical structure diagram construction program implements the steps in the chip backend module hierarchical structure diagram construction method according to any one of the above embodiments when executed by a processor.

[0035] The present application has the advantages that a chip backend module hierarchical structure diagram construction method based on module assignment is provided, the method processes the field assignment size relationship of multi-level modules with hierarchical structure in a traversal manner by obtaining the inherent connection relationship of each module, and the hierarchical structure diagram can be quickly sorted according to the hierarchical relationship of the modules in the chip backend according to the field assignment between different levels, the process does not depend on the register transfer level code and does not require the chip design progress, the hierarchical analysis process is flexible and simple enough, and the chip backend design efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a structural schematic diagram of the module hierarchy in the existing chip structure;

[0037] Figure 2 is a step flow block diagram of the chip backend module hierarchical structure diagram construction method provided by the embodiment of the present application;

[0038] Figure 3 is a chip backend module hierarchical structure diagram provided by the embodiment of the present application;

[0039] Figure 4is a structural schematic diagram of a chip back-end module hierarchical structure construction system provided by an embodiment of the present application.

[0040] Figure 5 is a structural schematic diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0042] Referring to Figure 2 , Figure 2 is a step flow block diagram of a construction method of a chip back-end module hierarchical structure provided by an embodiment of the present application, and the construction method comprises the following steps.

[0043] S101, all modules of a chip back-end are traversed to obtain module set data containing different hierarchical modules, wherein each module has next-level module relationship information of a next-level module corresponding thereto.

[0044] Step S101 further comprises:

[0045] The next-level module relationship information of each module is set based on a chip connection relationship. In an embodiment of the present application, the next-level module relationship information is existing data, which is obtained based on the respective connection relationship of the modules. It can be understood that, in the chip back-end design, since multiple levels of modules can be included, and the connection between different modules has not been completed (the method of the present embodiment is applied to the chip digital back-end design stage), therefore, if each module only contains the relationship information of the next-level module corresponding thereto, it is insufficient to constitute the hierarchical relationship of the entire chip structure.

[0046] In step S101, the next-level module relationship information can be represented by a certain data structure, for example, in a first-level module, the second-level modules connected thereto are listed in the form of a data list of a list, and on the basis of such relationship information, the hierarchical relationship of the first-level module to the multiple second-level modules can be determined.

[0047] S102, according to the next-level module relationship information, non-top-level modules in the module set data are screened out to obtain a top-level module set.

[0048] For example Figure 1As shown, the L1 level module does not belong to any submodule of any module, and belongs to the top-level module, so it is not contained by the next level module relationship information of any module, and the non-top-level module refers to all modules other than the top-level module, which must have a next level module containing it. Specifically, for the module set data obtained in step S101, it contains the set relationship of different modules and their next level modules. However, in the chip back-end design, there are also common next level module designs between different modules, so it is necessary to screen the set elements by subtracting the sets, and further remove all set elements of non-top-level module names (the top-level module does not belong to any submodule of any module, and is the initial hierarchical structure in the chip back-end design). Therefore, the subtraction of different sets can screen out the top-level module which is not a set element. In this way, the set data containing only the top-level module can be obtained.

[0049] S103, assigning an initial field to each module in the top-level module set.

[0050] In step S103, the initial field in the form of a numerical value is assigned to each module in the top-level module set in a numerical value increasing manner, and the initial field is a positive integer. For example, for a plurality of top-level modules, the initial fields assigned thereto are 1, 2, 3, and the like in turn. The numerical value increasing manner can also adopt an arithmetic sequence manner, which can be determined according to actual needs.

[0051] S104, in the top-level module set, it is judged in turn whether the next level module relationship information contained by each module is empty: if not, an additional field is assigned to each next level module corresponding to the module according to the initial field; the step is repeated until each module in the module set data other than the modules contained in the top-level module set has the additional field.

[0052] In the embodiment of the application, the top-level module set obtained based on the above steps is actually equivalent to the root node of the multi-way tree, and in order to better represent the hierarchical relationship between different modules, the other secondary modules having a hierarchical structure relationship with the top-level module are subjected to certain assignment processing based on the initial field information of the top-level module. By assigning a field having a numerical relationship, the direction of the hierarchical structure can be easily identified. It can be understood that if the next level module relationship information contained by the module is empty, it means that the module is a root node and does not need to be further traversed to the next level, but is traversed to the same level module.

[0053] Specifically, define Ln to represent the level of the module, where n is the level number, the modules in the top module set are L1 level, the number of the next level modules that each of the modules in the top module set can contain is h, h = 2, and step S104 includes the following sub-steps:

[0054] S1041, traverse the modules in the top module set according to the value size of the initial field;

[0055] S1042, take the module at the Ln level as a parent module, determine the level Ln+1 of the child module of the parent module according to the level Ln of the parent module, and judge whether the next level module relationship information possessed by the parent module is empty:

[0056] If yes, make h = 2, and return to step S1041;

[0057] If no, go to step S1043;

[0058] S1043, assign the additional field to each of the child modules of the current parent module according to the following relationship (1):

[0059] (1);

[0060] Wherein, value(Ln+1) represents the additional field, value(Ln) represents the initial field or the additional field contained by the parent module, and j represents the field assigned to the jth child module of the parent module; starting from j = 1, the field is sequentially assigned to each of the child modules, and j = j + 1 is made;

[0061] S1044, make Ln = Ln + 1, h = h + 1, and return to step S1042.

[0062] Exemplarily, the field assignment process of the embodiment of the application is explained by the following numerical examples:

[0063] Suppose that the top module at the L1 level contains 2, and in the initial field assignment stage, they are respectively assigned with the initial fields of 1 and 2; the traversal order is performed according to the order from small to large of the fields, that is, starting from the top module with the initial field of 1;

[0064] For the top module 1, according to the existing next level module relationship information, it can be determined that the child module at the L2 level contains 2, and then through the above steps, the additional fields assigned to the two child modules are respectively 1.01 and 1.02;

[0065] Furthermore, by analyzing the two modules with field data of 1.01 and 1.02 respectively, it was found that the next-level module set of the module with field 1.01 was empty, indicating that no field assignment processing was needed for the next level of this module; while for the next-level module set of the module with field 1.02, analysis revealed that its L3 level sub-modules contained two. Therefore, through the above steps, the additional fields assigned to these two sub-modules were 1.0201 and 1.0202 respectively.

[0066] After all submodules in top-level module 1 have been assigned values, return to the traversal steps to assign values ​​to the submodules in top-level module 2; and so on, so that all modules can be assigned certain numerical fields.

[0067] The initial field and the additional fields are stored in dictionary form. Dictionary-style data is beneficial for storage and analysis.

[0068] S105. Arrange the module set data according to the initial field or the additional field of each module in the module set data, and output the module hierarchy structure diagram.

[0069] In step S105, the initial field or the additional field of each module in the module set data is taken as numerical data, and all the modules in the module set data are sorted in ascending order of the numerical data, and the sorting result is output as the module hierarchy structure diagram.

[0070] Based on the field data of each module obtained from the above steps, after converting them into pure numerical values, they exhibit a certain numerical order. Specifically, the numerical values ​​of modules in the L1 level are the smallest, while the numerical values ​​of modules in the L2 level have more non-zero digits and increase sequentially, thus allowing the module hierarchy diagram to be arranged according to the actual hierarchical relationship. In one possible implementation, when converting fields into numerical values, the numerical value of the L1 level (initial field) is used as the integer part, and the numerical values ​​after the L1 level (additional fields) are used as the decimal part. This clearly shows the numerical order and the hierarchical relationship of the fields (numerical values ​​with a hierarchical structure have the same first n fields).

[0071] In step S105, the module information, hierarchy, and initial or additional fields of all the modules are output as entries in the module hierarchy structure diagram. The module hierarchy structure diagram provided in this embodiment of the invention is as follows: Figure 3 As shown, where, Figure 3 Field A in the dictionary contains raw data stored as a dictionary. Figure 3The field data of the middle B is converted into a floating point value form, and for a chip digital back-end design, the value size relationship shown in the module hierarchical structure diagram can obviously reflect the hierarchical relationship of a hardened module of the chip, and the data in the form of a diagram is also conducive to module progress query, lib library configuration and other chip digital back-end design processes.

[0072] The method has the advantages that the inherent connection relationship of each module is obtained, the field assignment size relationship processing is performed on the multi-level modules with hierarchical structure in a traversal manner, the hierarchical structure diagram is obtained according to the field assignment between different levels, and the hierarchical relationship of the modules in the chip back-end is quickly sorted out, the process does not depend on the register transfer level code and does not require the chip design progress, the hierarchical analysis process is flexible and simple, and the chip back-end design efficiency is improved.

[0073] The embodiment of the application further provides a chip back-end module hierarchical structure diagram construction system 200, please refer to Figure 4 , Figure 4 The embodiment of the application provides a chip back-end module hierarchical structure diagram construction system, which comprises:

[0074] The traversal unit 201 is used for traversing all modules of the chip back-end to obtain module set data containing different level modules, wherein each module has next level module relationship information of a corresponding next level module;

[0075] The screening unit 202 is used for screening non-top level modules in the module set data according to the next level module relationship information to obtain a top level module set;

[0076] The initialization unit 203 is used for assigning an initial field to each module in the top level module set;

[0077] The assignment unit 204 is used for sequentially judging whether the next level module relationship information contained in each module in the top level module set is empty: if not, assigning an additional field to each next level module corresponding to the module according to the initial field; and repeating the execution until each module in the module set data except the modules contained in the top level module set has the additional field;

[0078] The output unit 205 is used for arranging the module set data according to the initial field or the additional field of each module in the module set data and outputting a module hierarchical structure diagram.

[0079] The chip backend module hierarchical structure diagram construction system 200 can implement the steps in the chip backend module hierarchical structure diagram construction method in the above embodiment and achieve the same technical effects. For details, refer to the description in the above embodiment, which will not be repeated here.

[0080] The embodiment of the present application further provides a computer device, please refer to Figure 5 , Figure 5 is a structural schematic diagram of the computer device provided by the embodiment of the present application, the computer device 300 comprises a memory 302, a processor 301 and a chip backend module hierarchical structure diagram construction program stored in the memory 302 and capable of running on the processor 301.

[0081] The processor 301 invokes the chip backend module hierarchical structure diagram construction program stored in the memory 302 to execute the steps in the chip backend module hierarchical structure diagram construction method provided by the embodiment of the present application, please combine Figure 1 , specifically comprising the following steps:

[0082] S101, all modules of the chip backend are traversed to obtain module set data containing different hierarchical modules, wherein each module has next-level module relationship information of the next-level module corresponding thereto.

[0083] Step S101 further comprises:

[0084] The next-level module relationship information of each module is set based on the chip connection relationship.

[0085] S102, S102, according to the next-level module relationship information, the non-top-level modules in the module set data are screened out to obtain a top-level module set.

[0086] S103, an initial field is given to each module in the top-level module set.

[0087] In step S103, the initial field in the form of a numerical value is given to each module in the top-level module set in the form of numerical value increment, and the initial field is a positive integer.

[0088] S104, in the top-level module set, it is judged whether the next-level module relationship information contained by each module is empty: if not, an additional field is given to each next-level module corresponding to the module according to the initial field; repeat the step until each module in the module set data except the modules contained in the top-level module set has the additional field.

[0089] define Ln to represent the level of the module, where n is the level number, the module in the top module set is L1 level, the number of the next level modules that each module in the top module set can contain is h, h = 2, step S104 includes the following sub-steps:

[0090] S1041, traverse the modules in the top module set according to the numerical value of the initial field:

[0091] S1042, take the module at Ln level as a parent module, determine the level Ln+1 of the child module of the parent module according to the level Ln of the parent module, and judge whether the next level module relationship information possessed by the parent module is empty:

[0092] If yes, make h = 2 and return to step S1041;

[0093] If no, go to step S1043;

[0094] S1043, assign the additional field to each child module of the current parent module according to the following relationship (1):

[0095] (1);

[0096] Wherein, value(Ln+1) represents the additional field, value(Ln) represents the initial field or the additional field contained by the parent module, j represents the field assigned to the jth child module of the parent module; starting from j = 1, sequentially assign the field to each child module, and make j = j + 1;

[0097] S1044, make Ln = Ln + 1, h = h + 1, and return to step S1042.

[0098] The initial field and the additional field are stored in the form of a dictionary.

[0099] S105, arrange the module set data according to the initial field or the additional field possessed by each module in the module set data, and output the obtained module level structure diagram.

[0100] In step S105, the initial field or the additional field possessed by each module in the module set data is set as numerical data, all the modules in the module set data are sorted according to the order from small to large of the numerical data, and the sorting result is output as the module level structure diagram.

[0101] In step S105, the module information, the hierarchy, and the initial field or the additional field of all the modules are output as entries of the module hierarchy diagram.

[0102] The computer device 300 provided by the embodiment of the present application can realize the steps in the method for constructing the chip backend module hierarchy diagram, and can realize the same technical effects. For details, refer to the description in the above embodiment, which will not be repeated here.

[0103] The embodiment of the present application also provides a computer readable storage medium, which stores a program for constructing a chip backend module hierarchy diagram. The program is executed by a processor to realize each process and step in the method for constructing the chip backend module hierarchy diagram provided by the embodiment of the present application, and can realize the same technical effects. To avoid repetition, details will not be repeated here.

[0104] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by a program for constructing a chip backend module hierarchy diagram to instruct related hardware (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to complete. The program can be stored in a computer readable storage medium. When the program is executed, it can include the processes of the above-mentioned embodiment of each method. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0105] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusions, so that processes, methods, articles, or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed, or include elements inherent to such processes, methods, articles, or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article, or device that includes the element.

[0106] The embodiments of the present application are described above in combination with the drawings, and the disclosed are only the preferred embodiments of the present application, but the present application is not limited to the above-mentioned specific embodiments. The above-mentioned specific embodiments are only illustrative, but not restrictive. Those skilled in the art can make many equivalent changes under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims, which all belong to the protection of the present application.

Claims

1. A method for constructing a chip back-end module hierarchical structure diagram, characterized in that, The construction method includes the following steps: S101. Traverse all modules of the chip backend to obtain module set data containing modules of different levels, wherein each module has the relationship information of the next level module of its corresponding next level module; S102. Based on the next-level module relationship information, the non-top-level modules in the module set data are filtered out to obtain the top-level module set; S103. Assign an initial field to each module in the top-level module set; S104. In the top-level module set, determine in turn whether the next-level module relationship information contained in each module is empty: if not, assign an additional field to each next-level module corresponding to the module according to the initial field; repeat this step until every other module in the module set data except the modules contained in the top-level module set has the additional field. S105. Arrange the module set data according to the initial field or the additional field of each module in the module set data, and output the module hierarchy structure diagram.

2. The method for constructing a chip back-end module hierarchical structure diagram according to claim 1, characterized in that, In step S103, each module in the top-level module set is assigned an initial field in numerical form, where the initial field is a positive integer, in an incrementing manner.

3. The method for constructing the chip back-end module hierarchical structure diagram according to claim 2, characterized in that, Define Ln to represent the hierarchy of the module, where n is the number of levels. The modules in the top-level module set are at level L1. Each module in the top-level module set can accommodate h lower-level modules, where h = 2. Step S104 includes the following sub-steps: S1041. Traverse the modules in the top-level module set according to the value of the initial field; S1042. Taking the module at level Ln as the parent module, determine the level Ln+1 of its child modules based on the level Ln of the parent module, and determine whether the next-level module relationship information of the parent module is empty: If so, set h = 2 and return to step S1041; If not, proceed to step S1043; S1043. Assign the additional field to each of the child modules of the current parent module according to the following relation (1): （1）； Wherein, value(Ln+1) represents the additional field, value(Ln) represents the initial field or the additional field contained in the parent module, and j represents the field assigned to the j-th sub-module of the parent module; starting from j = 1, when assigning fields to each sub-module in sequence, j = j + 1; S1044. Set Ln = Ln + 1 and h = h + 1, then return to step S1042.

4. The method for constructing the chip back-end module hierarchical structure diagram according to claim 3, characterized in that, In step S105, the initial field or the additional field of each module in the module set data is set as numerical data, and all the modules in the module set data are sorted in ascending order of the numerical data, and the sorting result is output as the module hierarchy diagram.

5. The method for constructing a chip back-end module hierarchical structure diagram according to claim 1, characterized in that, Step S101 also includes: The relationship information of the next-level modules of each module is set based on the chip connection relationship.

6. The method for constructing a chip back-end module hierarchical structure diagram according to claim 3, characterized in that, The initial field and the additional field are stored in dictionary form.

7. The method for constructing the chip back-end module hierarchical structure diagram according to claim 3, characterized in that, In step S105, the module information, hierarchy, and initial or additional fields of all the modules are output as entries in the module hierarchy structure diagram.

8. A system for constructing a chip back-end module hierarchical structure diagram, characterized in that, include: The traversal unit is used to traverse all modules on the back end of the chip to obtain module set data containing modules at different levels, wherein each module has the relationship information of the next level module of its corresponding next level module; The filtering and reduction unit is used to filter and reduce the non-top-level modules in the module set data according to the next-level module relationship information to obtain the top-level module set; An initialization unit is used to assign an initial field to each module in the top-level module set; The assignment unit is used to sequentially determine whether the relationship information of the next-level modules contained in each of the top-level modules is empty in the top-level module set; if not, then assign an additional field to each of the next-level modules corresponding to the module according to the initial field; repeat the process until every other module in the module set data except the modules contained in the top-level module set has the additional field; The output unit is used to arrange the module set data according to the initial field or the additional field of each module in the module set data, and output a module hierarchy structure diagram.

9. A computer device, characterized in that, include: The method for constructing a chip back-end module hierarchy diagram includes a memory, a processor, and a chip back-end module hierarchy diagram construction program stored on the memory and executable on the processor. When the processor executes the chip back-end module hierarchy diagram construction program, it implements the steps in the chip back-end module hierarchy diagram construction method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program for constructing a chip back-end module hierarchy diagram. When the program for constructing the chip back-end module hierarchy diagram is executed by a processor, it implements the steps in the method for constructing a chip back-end module hierarchy diagram as described in any one of claims 1-7.

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