Bmc-based trusted computing method, server, storage medium and electronic device

Abstract

The embodiment of the application provides a kind of based on BMC's trusted computing method, server, storage medium and electronic equipment, it is related to computer technical field, method is applied to server, the host board card of server includes: host, BMC chip, method includes: host determines to be encrypted data, to be encrypted data is packaged as target data, and the target data is transmitted to the BMC chip;Host issues operation instruction to the BMC chip, and the operation instruction is used to indicate that target data is carried out trusted computing;The BMC chip is encapsulated according to the operation instruction to the target data, and obtains the trusted service package after encapsulation;The BMC chip carries out trusted computing according to the trusted service package, and obtains first calculation result;The first calculation result is encapsulated, and trusted service result package is obtained;The BMC chip feeds back the trusted service result package to the host.Just like this, trusted computing is realized by BMC chip, and the security and trusted computing performance are improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a trusted computing method, server, storage medium and electronic device based on BMC (Baseboard Management Controller). Background Technology

[0002] With the development of the internet, the importance of servers in terms of computing power has become increasingly prominent. Major server manufacturers have expanded the manageability of their servers on their hardware platforms and iterated and enhanced the ease of use in server management in new hardware versions. The BMC chip, as an independent management subsystem on the server motherboard, is responsible for hardware monitoring, remote management, and fault diagnosis. In terms of hardware, the BMC chip has evolved from a simple circuit to a complex and independent SoC (System on Chip) system, including an embedded processor, memory, flash memory, and peripheral input / output (I / O). Currently, network security, especially access security, protocol security, and data security, is receiving significant attention. The development of domestically produced servers is becoming increasingly sophisticated. With the advancement of big data, cloud computing, and AI technologies, the server market demands higher security from servers, ensuring data confidentiality and integrity, guaranteeing the legitimacy of access, and ensuring that the information services provided are not interrupted, preventing network paralysis.

[0003] Currently, trusted computing implementation schemes include: Figure 1 As shown, the motherboard includes various core components such as the BMC chip, server host, storage devices, and TPM (Trusted Platform Module) chip. When the server host is connected to an external TPM chip, a series of trusted computing processes are initiated during the boot process. The TPM chip first performs an integrity check on the server's BIOS (Basic Input / Output System), comparing the current BIOS hash value with the BIOS baseline hash value. If they match, the system can continue booting; otherwise, the system boots up. Regarding encrypted data transmission, the server encrypts data via the TPM chip, transmitting data in ciphertext form over the network. In the data storage stage, the TPM chip encrypts sensitive data on the server's hard drive, storing the encrypted data on the physical medium.

[0004] However, implementing trusted computing through TPM chips presents the following problems:

[0005] 1. Performance: External TPM chips typically connect to the motherboard via a specific bus (such as LPC (Low Pin Count bus)). This type of bus has a limited data transfer rate, which can become a performance bottleneck when the server performs large amounts of data encryption, decryption, or integrity verification, leading to a decrease in data processing speed. Furthermore, since the TPM chip is an external device independent of the server's main processor, trusted computing operations require data interaction and instruction transmission between the main processor and the TPM chip, introducing additional processing latency and affecting the overall system response speed.

[0006] 2. Security: As an independent hardware device, the external TPM chip is vulnerable to side-channel attacks (such as power consumption analysis) due to its PCB traces and packaging. Furthermore, some low-end models lack anti-tampering protection. If the security measures in the server's environment are inadequate, the TPM chip may be physically attacked, such as being disassembled, tampered with, or implanted with malicious hardware. The key may also be physically extracted, posing a significant security risk. Summary of the Invention

[0007] This application provides a trusted computing method, server, storage medium, and electronic device based on BMC, to at least solve the above-mentioned technical problems existing in the prior art.

[0008] The technical solution of this application embodiment is implemented as follows:

[0009] In a first aspect, embodiments of this application provide a trusted computing method based on a BMC chip. The method is applied to a server, where the server's host board includes a host and a BMC chip, the host being connected to the BMC chip. The method includes:

[0010] The host determines the data to be encrypted, encapsulates the data to be encrypted into target data, and transmits the target data to the BMC chip;

[0011] The host sends an operation command to the BMC chip, the operation command being used to instruct the target data to be subjected to trusted computation.

[0012] The BMC chip encapsulates the target data according to the operation instructions to obtain the encapsulated trusted service packet;

[0013] The BMC chip performs trusted computation based on the trusted service package to obtain a first computation result; the first computation result is then encapsulated to obtain a trusted service result package.

[0014] The BMC chip feeds back the trusted service result packet to the host.

[0015] Secondly, embodiments of this application provide a server, wherein the host board of the server includes: a host and a BMC chip, and the host is connected to the BMC chip;

[0016] The host is used to determine the data to be encrypted, encapsulate the data to be encrypted into target data, and transmit the target data to the BMC chip;

[0017] An operation instruction is issued to the BMC chip, the operation instruction being used to instruct the target data to be subjected to trusted computation;

[0018] The BMC chip is used to encapsulate the target data according to the operation instructions to obtain the encapsulated trusted service packet;

[0019] Trusted computation is performed based on the trusted service package to obtain a first computation result; the first computation result is then encapsulated to obtain a trusted service result package.

[0020] The trusted service result package is fed back to the host.

[0021] Thirdly, embodiments of this application provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform any of the trusted computing methods described above.

[0022] Fourthly, embodiments of this application provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the trusted computing method according to any one of the claims.

[0023] The embodiments of this application have the following beneficial effects:

[0024] The trusted computing method, server, storage medium, and electronic device provided in this application are applied to a server. The server's host board includes a host and a BMC chip, with the host connected to the BMC chip. The method includes: the host determining data to be encrypted, encapsulating the data to be encrypted into target data, and transmitting the target data to the BMC chip; the host issuing an operation instruction to the BMC chip, the operation instruction indicating trusted computing on the target data; the BMC chip encapsulating the target data according to the operation instruction to obtain an encapsulated trusted service packet; the BMC chip performing trusted computing based on the trusted service packet to obtain a first calculation result; encapsulating the first calculation result to obtain a trusted service result packet; and the BMC chip feeding back the trusted service result packet to the host. Thus, trusted computing is implemented by the BMC chip, improving security and trusted computing performance.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of a trusted computing implementation device in a related technology, provided in an embodiment of this application.

[0027] Figure 2 A flowchart illustrating a trusted computing method based on BMC provided in this application embodiment;

[0028] Figure 3 This is a schematic diagram of the structure of a trusted computing implementation device provided in an embodiment of this application;

[0029] Figure 4 A schematic diagram of a cryptographic service processing method for trusted computing provided in this application embodiment;

[0030] Figure 5 This application provides a schematic diagram of a trusted computing startup service process according to an embodiment of the present application.

[0031] Figure 6 A schematic diagram of a BMC-side cache data linked list area and a business data area provided in an embodiment of this application;

[0032] Figure 7 This is a schematic diagram of the structure of a trusted data packet provided in an embodiment of this application;

[0033] Figure 8 This application provides a schematic diagram of a network isolation structure for internal and external network servers.

[0034] Figure 9 A schematic diagram illustrating a trusted log management system provided in an embodiment of this application;

[0035] Figure 10 This application provides a schematic diagram of the structure of a server according to an embodiment of the present application.

[0036] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0037] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0039] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0041] Figure 2 A flowchart illustrating a trusted computing method based on BMC provided in this application embodiment; as shown Figure 2 As shown, the method is applied to a server, the server's host board includes: a host and a BMC chip, the host being connected to the BMC chip; the method includes:

[0042] Step 201: The host determines the data to be encrypted, encapsulates the data to be encrypted into target data, and transmits the target data to the BMC chip;

[0043] Step 202: The host sends an operation command to the BMC chip, the operation command being used to instruct the target data to be subjected to trusted computation;

[0044] Step 203: The BMC chip encapsulates the target data according to the operation instructions to obtain the encapsulated trusted service packet;

[0045] Step 204: The BMC chip performs trusted computation based on the trusted service package to obtain a first computation result; the first computation result is encapsulated to obtain a trusted service result package;

[0046] Step 205: The BMC chip sends the trusted service result packet back to the host.

[0047] Thus, in this embodiment of the application, the BMC chip is used to implement the Root of Trust (RoT) as the server host, which solves the pain points such as high resource consumption, large performance loss and strong supply chain dependence caused by implementing the root of trust with an external TPM chip.

[0048] In some embodiments, the BMC chip includes: an internal cache;

[0049] Encapsulating the data to be encrypted into target data and transmitting the target data to the BMC chip includes:

[0050] The data to be encrypted is encapsulated into a PCIe frame, which is then used as the target data.

[0051] The internal cache memory address space is accessed through the PCIe interface to transmit the PCIe frame to the internal cache of the BMC chip.

[0052] The internal cache may include DDR (Double Data Rate Synchronous Dynamic Random Access Memory) and / or SRAM (Static Random Access Memory), which can be used to store temporary data.

[0053] Here, the BMC chip and the host can communicate via the PCIE (Peripheral Component Interconnect Express) interface. Encapsulation into a PCIE frame means that the data to be encrypted is packaged into a frame according to the PCIE protocol format, which is used as the target data for transmission through the bus.

[0054] The BMC chip has a dedicated cache (such as DDR or SRAM) inside. Data is written to a specific address in the internal cache via the PCIe bus so that the BMC chip can perform subsequent encryption processing on the data.

[0055] The specific address can be negotiated between the host and the BMC chip. For example, the host sends a write request to the CPU of the BMC chip, and the CPU responds with a currently writable cache address to inform the host to write the data to that address. In this way, the BMC chip can know about the data writing in real time, and the host can also successfully send the data to the BMC chip and inform it of the write address.

[0056] In some embodiments, the BMC chip further includes: a CPU (Central Processing Unit), an encryption / decryption system, and a SEMG (Signal Event Management Register).

[0057] The BMC chip encapsulates the target data according to the operation instructions to obtain an encapsulated trusted service packet, including:

[0058] The CPU encapsulates the received operation instructions into a descriptor and caches it in its internal cache;

[0059] The CPU configures the SEMG to inform the SEMG of the descriptor and the cache address of the target data;

[0060] The SEMG reads the descriptor and the target data according to the cache address, and encapsulates the descriptor and the target data into a trusted service packet; the descriptor is saved to the header of the trusted service packet.

[0061] Here, the cache address can include: the cache address of the descriptor and the cache address of the target data (i.e., the PCIe frame).

[0062] After receiving an operation instruction, the CPU can first parse the instruction and obtain a descriptor based on the parsing result. This descriptor can include relevant information about the target data, such as the data location, length, type, and the type of encryption / decryption operation to be performed, as well as the algorithm used for encryption / decryption (such as hash, symmetric encryption / decryption, asymmetric operation, etc.). Then, these descriptors are cached in the internal cache.

[0063] SEMG stands for Signal Event Management Register, used for secure encryption management. To enable SEMG to access descriptors and target data in the cache, the CPU can configure SEMG to specify the cache address. This configuration is typically achieved by writing cache address information to specific registers or memory regions, similar to memory mapping, which associates physical memory addresses with hardware control registers for accurate reading.

[0064] SEMG can read the descriptor and target data based on the cache address and encapsulate them into a trusted service packet. The descriptor is saved in the header of the trusted service packet, while the target data becomes the content of the packet.

[0065] In some embodiments, the BMC chip performs trusted computation based on the trusted service package to obtain a first computation result, including:

[0066] The SEMG sends the trusted service packet to the encryption / decryption system;

[0067] The encryption / decryption system calls the corresponding processing core according to the header information of the trusted service packet, and uses the processing core to perform encryption / decryption operations on the target data in the trusted service packet to obtain the first calculation result;

[0068] The encryption / decryption system includes at least one processing core, and the encryption / decryption operation involves one or more processing cores.

[0069] Here, the encryption / decryption system has at least one processing core, such as Figure 3 As shown, it can include hash algorithm kernels, symmetric algorithm kernels, and asymmetric algorithm kernels;

[0070] The service scheduling module of the encryption / decryption system reads the header information of trusted service packets to obtain descriptors, and then determines the encryption / decryption core to be invoked and processes it. The core can be a hardware module specifically designed to execute encryption or decryption algorithms. The specific calculation process is not limited here; it's easy to understand that each core can perform various required encryption / decryption calculations.

[0071] Therefore, using a hardware encryption / decryption core for processing is faster and more secure than software encryption. Furthermore, since encryption and decryption operations are performed internally within the BMC chip, the risk of data exposure is reduced, while simultaneously improving system efficiency and data processing security. Moreover, the parallel processing capability of the core allows for more efficient encryption and decryption of large amounts of data, enhancing overall system performance.

[0072] In some embodiments, the BMC chip feeds back the trusted service result packet to the host, including:

[0073] The encryption / decryption system sends the trusted service result packet back to SEMG;

[0074] The SEMG splits the trusted service result packet to obtain valid data;

[0075] The SEMG writes the valid data back to the internal cache and informs the CPU;

[0076] The CPU sends a notification message to the host, so that the host can read the valid data from the internal cache according to the notification message.

[0077] Here, after the trusted computing operation is completed, the generated trusted business result packet is fed back to SEMG by the encryption and decryption system. SEMG is responsible for security processing. After receiving the trusted business result packet, it deconstructs the contents of the packet and extracts the valid data part. This valid data is the final data after encryption and decryption processing and will be written back to the internal cache for subsequent processing.

[0078] Once valid data is written to the cache, SEMG informs the CPU, which then sends a notification to the host, informing them of the cache address and that the data processing is complete. The host then reads the valid data from the BMC chip's internal cache based on the notification.

[0079] This not only ensures the speed and accuracy of encryption and decryption operations, but also enhances the overall security of the system, avoiding the risk of sensitive data being leaked during transmission or processing.

[0080] like Figure 3 The diagram illustrates the structure of a trusted computing implementation device applied to a server. The server's motherboard includes a host, a BMC chip, and components such as BMC-Flash and BIOS-Flash. The BMC chip plays a crucial role in the entire system, serving as the root of trust for the server host.

[0081] The BMC chip contains:

[0082] Bus 1 plays a crucial role in data transmission, acting as a bridge for data flow between various components.

[0083] The CPU is used to interact with the host, BIOS flash memory, etc., and to configure SEMG, etc.

[0084] Internal cache, used to provide efficient data caching services, such as SRAM and DDR;

[0085] SEMG is used to implement secure processing such as trusted service flow classification and packet encapsulation for delivery.

[0086] An encryption / decryption system used for encryption and decryption operations related to trusted computing.

[0087] The BMC chip may also include:

[0088] The memory section provides storage space, such as ROM;

[0089] The SPI interface is used to enable serial communication between the chip and external devices.

[0090] The PCIe interface provides a high-speed, low-latency channel, greatly improving data transmission efficiency.

[0091] The encryption / decryption system is primarily used for data authentication, verification, encryption, and decryption operations to ensure data integrity, legitimacy, and security. The encryption / decryption system may include:

[0092] The system includes a buffer for two types of trusted data packets (trusted management packets and trusted service packets) (management packet SRAM and service packet SRAM), multiple processing cores, an OTP (One-Time Programmable) module for key and parameter storage, and a service scheduling module.

[0093] The multiple computational cores may include, but are not limited to: hash algorithm cores, symmetric algorithm cores, and asymmetric algorithm cores.

[0094] With the above devices, when the host has data that needs to be processed by trusted computation (such as hashing, symmetric encryption / decryption, and asymmetric operations), the BMC chip can complete the task.

[0095] The following provides an example of cryptographic business processing in trusted computing, such as... Figure 4 As shown. After the BMC and server host have completed secure boot, assuming the server host (hereinafter referred to as the host) has data that needs to be encrypted / decrypted, hashed, or signed using an asymmetric algorithm, for example, data A, data B, and data C need to be processed using symmetric, hash, and asymmetric algorithms respectively, corresponding to SM4, SM3, and SM2, the following steps can be used:

[0096] 1. The host encapsulates data A, data B, and data C into a PCIe frame and accesses the memory address space of the BMC chip through the PCIe interface to transfer data A, data B, and data C to the BMC's internal cache respectively.

[0097] For example, if the host and CPU negotiate and determine the cache addresses to be written to: DDR space a, b, c, then data A, data B, and data C will be transferred to DDR space a, b, c inside the BMC respectively;

[0098] 2. The host needs to perform algorithmic operations on data A, data B, and data C. It issues operation instructions to the CPU of the BMC chip to instruct the BMC chip to perform SM4 encryption, SM3 hashing, and SM2 signature operations on data A, data B, and data C respectively.

[0099] 3. The CPU encapsulates the operation instructions into descriptors and caches them in consecutive addresses in DDR (let's say addr_A, addr_B, addr_C), and configures the SEMG register to inform the SEMG register;

[0100] Here, the specific operation instructions can be received by the CPU, and then the CPU encapsulates the operation instructions into descriptors and caches them in consecutive addresses in DDR;

[0101] 4. SEMG reads the descriptor and the data to be processed (i.e., data A, data B, and data C), encapsulates them into trusted service packets (let's say pack_A, pack_B, and pack_C) and sends them to the encryption / decryption system;

[0102] 5. The encryption / decryption system determines the algorithm type based on the header information of the trusted service packet, calls the operation core corresponding to the algorithm type to perform SM4 encryption, SM3 hashing, and SM2 signature operations on the data pack_A, pack_B, and pack_C respectively, and after obtaining the operation results, encapsulates the operation results into trusted service result packets (assumed to be pack_A0, pack_B0, and pack_C0) and returns them to SEMG;

[0103] 6. SEMG splits pack_A0, pack_B0, and pack_C0, writes the valid data portion of the pack back to DDR according to the agreement, and notifies the CPU of the BMC chip;

[0104] 7. The CPU notifies the host to read back the calculation results, completing the cryptographic calculation of data A, data B, and data C.

[0105] It should be noted that the encryption, signature and other algorithms described above are only examples. In actual applications, various algorithms are designed according to the requirements, and no limitations are made here.

[0106] In some embodiments, the server's motherboard further includes a BIOS flash memory; the method further includes booting the server's motherboard.

[0107] The hostboard card used to start the server includes:

[0108] The BMC chip obtains the image file of the boot firmware from the BIOS flash memory through the SPI interface and saves the image file to the internal cache of the BMC chip;

[0109] The BMC chip encapsulates the image file to obtain an encapsulated trusted management package;

[0110] The BMC chip performs trusted computation based on the trusted management package to obtain a second computation result; and feeds back the second computation result to the host.

[0111] In some embodiments, the BMC chip further includes: a CPU, an encryption / decryption system, and a SEMG;

[0112] The BMC chip obtains the boot firmware image file from the BIOS flash memory via the SPI interface and saves the image file to the BMC chip's internal cache; including:

[0113] The CPU obtains the boot firmware image file from the BIOS flash memory via the SPI interface and saves the image file to the internal cache of the BMC chip;

[0114] Accordingly, the BMC chip encapsulates the image file to obtain an encapsulated trusted management package, including:

[0115] The SEMG encapsulates the image file to obtain the encapsulated Trusted Management Package;

[0116] Accordingly, the BMC chip performs trusted computation based on the trusted management package to obtain a second computation result; the second computation result is then fed back to the host, including:

[0117] The SEMG sends the Trusted Management Packet to the encryption / decryption system;

[0118] The encryption / decryption system performs trusted computation based on the trusted management packet to obtain a second computation result; and writes the second computation result back to the SEMG.

[0119] The SEMG parses the second calculation result to obtain the BIOS boot data, writes the BIOS boot data back to the internal cache, and informs the CPU.

[0120] The CPU informs the host of the cache address of the BIOS boot data, so that the host can read the BIOS boot data according to the cache address.

[0121] Here, combined Figure 3 The structure of the server motherboard shown is provided as a specific example to illustrate the process of booting the server motherboard, such as... Figure 5 As shown, the startup process includes the following steps:

[0122] 1. The server motherboard is powered on, and the Flash memory reset is successful;

[0123] Here, the server motherboard is powered on, the BMC-Flash and BIOS-Flash are reset, and the BMC chip is powered on.

[0124] Among them, BMC-Flash is the flash memory area that stores the BMC firmware; BIOS-Flash is the flash memory area that stores the host BIOS firmware.

[0125] 2. The BMC chip executes the secure boot process;

[0126] 3. The CPU determines whether the BMC chip has booted successfully and safely. If successful, proceed to step 4; otherwise, booting fails.

[0127] Here, the BMC chip can move the BMC-Flash boot firmware image to memory via SPI0 and execute the secure boot process. The secure boot process of BMC is a general operation and will not be described in detail.

[0128] Once the BMC chip has successfully booted, it can actively measure the host BIOS program (BIOS_image) in the BIOS-Flash.

[0129] 4. The CPU reads the host boot firmware image file from the BIOS-Flash and verifies it;

[0130] Here, the server's specific software performs symmetric encryption on the BIOS boot data to obtain ciphertext (denoted as BIOS_EN0); performs hash calculation on the ciphertext to obtain a ciphertext digest value (denoted as BIOS_D0); and signs the ciphertext digest value to obtain a signature value (denoted as BIOS_S0). The above three parts are then packaged into a host boot firmware image file to be verified (denoted as BIOS_image).

[0131] Therefore, the BIOS_image read by the CPU = (BIOS_EN0) + verification base values ​​(BIOS_D0, BIOS_S0); BIOSboot represents the firmware program executed when the host starts up, responsible for loading the operating system. BIOS_image represents the packaged firmware data, containing the encrypted BIOS program and its verification information.

[0132] The CPU can read the BIOS_image into its internal cache, such as DDR, via the SPI (Serial Peripheral Interface) 1 interface; DDR is Dynamic Random Access Memory, used to store temporary data.

[0133] 5. The CPU caches the BIOS_image in its internal cache (such as DDR), and informs the SEMG of the cache address through configuration. The SEMG reads the BIOS_image and encapsulates it into a trusted management packet.

[0134] Here, the CPU can move BIOS_EN0, BIOS_D0, and BIOS_S0 to the internal cache through the built-in DMA (Direct Memory Access). SEMG assembles the final trusted management packet according to the configuration and trusted management packet header, and sends the trusted management packet to the encryption and decryption system.

[0135] SEMG stands for Signal Event Management Register, which is responsible for the generation and verification of trusted management packets.

[0136] 6. SEMG distributes the Trusted Management Package to the encryption / decryption system for trusted computing;

[0137] 7. The encryption / decryption system performs trusted calculations based on the trusted management packet to verify the firmware hash value and signature, and obtains the BIOS boot data after completion.

[0138] Specifically, SEMG performs trusted computing based on the Trusted Management Package, including:

[0139] Identify the valid information in the header of the Trusted Management Packet, determine the required algorithm (such as SM3, SHA algorithm, etc.), call the corresponding computing core to perform digest operation on BIOS_image, obtain the digest value (denoted as BIOS_D1), and compare it with the digest baseline value BIOS_D0 in the Trusted Management Packet;

[0140] If the comparison fails, it indicates that the host BIOS verification has failed, and the boot process is interrupted;

[0141] The comparison is successful. Proceed to the next step: verify the signature value BIOS_S0 using the asymmetric encryption algorithm (such as SM2 or ECC) indicated in the packet header.

[0142] If the signature verification fails, it means that the BIOS verification has failed; if the signature verification passes, it means that the BIOS data encrypted by the host is trustworthy. The BIOS boot data can be obtained by decrypting BIOS_EN0 using a symmetric algorithm (such as SM4 or AES) selected from the packet header information.

[0143] 8. The encryption / decryption system encapsulates the decrypted BIOS boot data to obtain a trusted management packet and returns it to SEMG;

[0144] 9. SEMG analyzes and responds to the trusted management packet, writes the BIOS boot data back to DDR, and notifies the CPU via an interrupt;

[0145] 10. The CPU responds to the interrupt, reads SEMG, and confirms that the BIOS boot data verification is successful; and the CPU controls the CPLD (Complex Programmable Logic Device) to power on the host and release the host reset.

[0146] 11. The host reads the BIOS boot data and uses it to boot the host operating system.

[0147] Here, the host can read the BIOS boot data in the cache through the PCIe interface and boot the host to complete the operating system startup.

[0148] In this way, the above process enables the trusted boot of the host, which is undertaken by the BMC chip. The above process ensures the integrity and legitimacy of the host boot firmware; performs proactive measurement to monitor and measure critical parts of the system in real time; provides trusted cryptographic services for the entire system to ensure the security of password-related operations; and provides network isolation services to effectively prevent the penetration of network-level security threats, thus comprehensively protecting the security and stable operation of the server host.

[0149] In some embodiments, the internal cache of the BMC chip uses a data linked list structure to manage trusted data packets, and each node in the data linked list corresponds to an independent trusted data packet.

[0150] The descriptors of the data linked list include:

[0151] The first identifier is used to point to the physical address of the trusted data packet in the DDR of the BMC chip, supporting contiguous or discrete storage;

[0152] The second identifier is used to indicate the size of the trusted data packet;

[0153] A status flag bit, the status flag bit being used to indicate at least one of the following: a verification flag bit, an algorithm type, or access control;

[0154] The descriptors are linked in a circular queue managed by head and tail pointers, supporting multiple (e.g., N, where N is greater than or equal to 1) trusted data packets concurrently.

[0155] The trusted data packets are stored in either a continuous or discrete manner.

[0156] Here, a business data linked list structure is provided, which allows the system to manage trusted data packets through a continuous data linked list numbered 0-N. The trusted data packets can be specifically divided into trusted management packets and trusted business packets according to their packet types, and are stored continuously in the DDR buffer of the BMC chip.

[0157] like Figure 6 The diagram illustrates a DDR cache area for a BMC chip, including a data list area and a service data area. Each data list node corresponds to an independent trusted data packet instance, and the trusted data packet includes a data body corresponding to the trusted data packet header.

[0158] The descriptor fields in the linked list include:

[0159] Bufptr (first identifier): points to the physical address of the data packet in BMC DDR, supporting contiguous or discrete storage;

[0160] Length (second identifier): Data packet size (in bytes), supporting a dynamic range of 0-256MB;

[0161] Status (status flags) includes, but is not limited to: verification flags, algorithm type, and access control.

[0162] The descriptors are linked in a circular queue managed by head and tail pointers, supporting multiple data packets concurrently.

[0163] Here, business data packets can utilize elastic storage, supporting continuous storage mode. Continuous storage improves data read / write efficiency and is suitable for high-throughput scenarios such as batch firmware updates and batch encryption of sensitive data. Discrete storage mode is also supported, optimizing memory utilization and adapting to fragmented data scenarios such as real-time log collection. Specific limitations are not specified.

[0164] In some embodiments, the types of trusted data packets include: trusted service packets and trusted management packets;

[0165] The trusted data packet includes a header and valid data. The header includes: control information, authentication data, and algorithm parameters.

[0166] The control information is used to indicate at least one of the following: packet type, data type, packet length, write-back address, and algorithm type.

[0167] The existence of the authentication data is determined based on the control information and is used to provide baseline value data.

[0168] The algorithm parameters are used to provide the necessary parameter data for the algorithm to run.

[0169] Here, the service data packets can be divided into trusted data packets and trusted service packets.

[0170] The Trusted Management Package is used for non-high-speed cryptographic algorithm services, such as secure boot on the host side and firmware updates.

[0171] The trusted service package is used for high-speed cryptographic algorithm services on the host side, such as high-speed encryption and decryption.

[0172] Specifically, the structure of a trusted data packet is as follows: Figure 7 As shown, it consists of a header and valid data.

[0173] The header section includes: control information, authentication data, and algorithm parameters;

[0174] Control information is used to indicate necessary control information such as packet type, data type, packet length, write-back address, and algorithm type;

[0175] The existence of authentication data depends on the control information, and mainly consists of verifiable baseline data such as hash base values ​​and signature values.

[0176] Algorithm parameters are the necessary parameter data for the algorithm to run.

[0177] Trusted data packets are encapsulated in the SEMG of the BMC chip, possessing the ability to aggregate multiple algorithm operations. Taking the BMC chip's BIOS boot verification process as an example, this process assumes that hash operations, asymmetric signature verification, and symmetric decryption operations are performed sequentially. The encrypted BIOS boot digest base value is compared, the signature value is verified, and after verifying integrity and legality, decryption is performed to obtain the BIOS boot. During this process, the BMC chip's CPU needs to configure three algorithm startup processes, assuming they are hash, asymmetric, and symmetric algorithms respectively. The SEMG can encapsulate these three algorithm types and their order into a trusted management packet and distribute it to the encryption / decryption system for execution. The encapsulation operation is entirely completed by hardware without software intervention, eliminating software-level scheduling overhead and reducing the BMC chip's CPU configuration operation from three times to one time, maximizing the release of BMC chip CPU performance.

[0178] In some embodiments, if the server is applied to an internal / external network structure, and the server is an internal network server, the method further includes:

[0179] The host of the external network server receives network data packets;

[0180] The host of the external network server transmits the network data packets to the internal cache of the BMC chip of the external network server and sends transmission instructions to the BMC chip of the external network server.

[0181] After the BMC chip of the external network server performs trusted computation, it transmits the data to the internal network server.

[0182] or,

[0183] After receiving the network data packet, the host of the external network server sends it to the internal cache of the BMC chip of the external network server and sends a transmission command to the BMC chip of the external network server.

[0184] The BMC chip of the external network server performs a trusted calculation on the network data packet according to the transmission instruction to obtain the original network data packet.

[0185] In some embodiments, if the server is applied to an internal / external network structure, and the server is an internal network server, the method further includes:

[0186] After receiving the network data packet, the host of the intranet server sends it to the internal cache of the BMC chip of the intranet server and sends a transmission command to the BMC chip of the intranet server.

[0187] The BMC chip of the intranet server performs a trusted calculation on the network data packet according to the transmission instruction to obtain the original network data packet;

[0188] or,

[0189] The host of the intranet server receives network data packets;

[0190] The host of the intranet server transmits the network data packets to the internal cache of the BMC chip of the intranet server and sends transmission instructions to the BMC chip of the intranet server.

[0191] After the BMC chip of the intranet server performs trusted computation, it transmits the data to the extranet server.

[0192] Here, a design for network isolation between internal and external servers is presented, as shown by the solid line in Figure 8. The process includes:

[0193] 1. Network data packets (denoted as pack_A0) from the external network enter the host of the external server (hereinafter referred to as the external host) through the INF0 interface.

[0194] 2. After being processed by the external host, the transmission instructions for the network data packets are sent to the BMC chip of the external server (hereinafter referred to as the external BMC).

[0195] 3. The external network BMC receives transmission commands and network data packets from the external network host and stores the network data packets in the internal cache of the BMC chip, for example, the RX cache area denoted as DDR0.

[0196] 4. The external network BMC performs trust calculations on network data packets;

[0197] Specifically, the external BMC reads the network data packets to be processed through SEMG and inputs the data packets into the encryption / decryption subsystem for symmetric algorithm encryption. After symmetric algorithm encryption, the encryption / decryption subsystem obtains Encry_A1. It calculates the digest value of Encry_A1 (denoted as Hash_A1) and signs Hash_A1 to obtain the signature value (denoted as Sign_A1). Encry_A1, Hash_A1, and Sign_A1 are packaged into a new network data packet (denoted as pack_B0) and sent to the internal network server through the INF1 interface.

[0198] 5. The intranet server receives and processes data;

[0199] 6. When the host of the intranet server (hereinafter referred to as the intranet host) receives pack_B0, it sends it to the internal cache of the BMC chip of the intranet server (hereinafter referred to as the intranet BMC), for example, the RX cache area of ​​DDR1, and issues a transmission command.

[0200] After receiving the instruction, the internal CPU calls SEMG to read the network data packet pack_B0 and transmits it to the encryption / decryption system for hash processing to obtain a digest value (denoted as Hash_B1). It then compares Hash_A1 and Hash_B1 to see if they match. If they do not match, the packet is dropped. If they match, the signature is verified. If the signature verification is successful, Encry_A1 is decrypted to obtain the original network data packet pack_A0.

[0201] 7. The raw network data packet pack_A0 is output from the INF0 interface of the internal network server.

[0202] like Figure 8 The section shown by the dashed line illustrates the internal network data packet processing flow, which includes:

[0203] 1. Network data packets pack_B0 from the intranet enter the intranet through the INF0 interface;

[0204] 2. After processing by the intranet host, the network packet transmission command is sent to the intranet BMC;

[0205] 3. The intranet BMC receives transmission commands and network data packets from intranet hosts and stores them in the RX cache area of ​​the intranet BMC DDR1;

[0206] 4. The intranet BMC performs trusted calculations on network data packets;

[0207] Specifically, the internal BMC reads the network packet to be processed through SEMG, processes it, and inputs it into the encryption and decryption system for symmetric algorithm encryption to obtain Encry_B1. The digest value Hash_B1 of Encry_B1 is calculated, and Hash_B1 is signed to obtain Sign_B1. Encry_B1, Hash_B1, and Sign_B1 are packaged into a new network data packet (denoted as pack_B1) and sent to the external server through the INF1 interface.

[0208] 5. The external network server receives and processes data packets;

[0209] 6. The external server receives pack_B1, sends it to the internal buffer of the external BMC (Dedicated to DDR0 TX), and issues an instruction. After receiving the instruction, the CPU of the external BMC calls SEMG to read the network packet pack_B1 and transmits it to the algorithm subsystem for hash processing to obtain the digest value Hash_A1. It then compares Hash_A1 and Hash_B1 to see if they match. If they do not match, the packet is dropped. If they match, the signature is verified. After successful signature verification, Encry_B1 is decrypted to obtain the original network data packet pack_B0.

[0210] 7. Output the data packet pack_B0 from the INF1 interface of the external network server.

[0211] It should be noted that in the diagram, BMC_bus represents the bus in the BMC; INF1, BMC_CPU, DDR1, and INF0, which are connected to the internal network BMC, belong to the devices in the internal network BMC; correspondingly, INF1, BMC_CPU, DDR0, and INF0, which are connected to the external network BMC, belong to the devices in the external network BMC. For the sake of visual representation of the external network host, external network BMC, internal network host, and internal network BMC, BMC_CPU, DDR, and INF are not drawn within the BMC, but their meaning is not difficult to understand. The specific structure of the BMC can be found in the diagram. Figure 3 The BMC chip shown.

[0212] In some embodiments, the server's hostboard further includes: BMC flash memory, and the method further includes:

[0213] After the BMC chip is started, a host encrypted log storage area is created in the BMC flash memory, a structured log template is defined, and a dedicated audit key is generated;

[0214] During the server operation phase, the BMC chip records at least one log and stores it in the host encrypted log storage area of ​​the BMC flash memory;

[0215] The BMC chip records at least one log entry, including:

[0216] When the host BIOS firmware is loaded and verified, the BMC chip records the access address range and data verification value of the interface when reading the BIOS image file; when performing hash verification, the BMC chip records the calculated hash value, the pre-stored base value, and the comparison result; when performing digital signature verification, the BMC chip records the public key information used, the signature algorithm, and the signature verification result; when triggering a decryption operation, the BMC chip records the key handle and the encryption mode.

[0217] After the operating system runs, the BMC chip calculates a hash value for each host log entry, uses the hash value of the previous log entry as input for chained expansion, and constructs an irreversible hash chain; and signs each host log entry, appending the signature value to the end of the log to complete the signature encapsulation.

[0218] Specifically, the structured log template includes core fields such as timestamp, event type (verification / password operation), operation object, algorithm identifier, and operation result.

[0219] Combination Figure 9 As shown in Figure 9, an example of log management is provided. In this embodiment of the application, the log management process may include multiple stages:

[0220] 1. Initialize the audit log;

[0221] After BMC starts, a host encrypted log storage area is created in BMC Flash, a structured log template is defined, including core fields such as timestamp, event type (verification / password operation), operation object, algorithm identifier, operation result, etc., and a unique audit key is generated.

[0222] 2. Trusted verification event logs, including:

[0223] During the host BIOS firmware loading and verification phase, when the BMC reads the BIOS image, it records the access address range and data check value of the SPI interface; when performing hash verification, it records the calculated hash value, the pre-stored base value and the comparison result; when performing digital signature verification, it records the public key information used, the signature algorithm and the signature verification result; and when triggering the decryption operation, it records the key handle, encryption mode, etc.

[0224] 3. Log security processing: After the operating system starts, it calculates a hash value (SM3 or other digest algorithm) for each host log, uses the hash value of the previous log as input to expand in a chain, and builds an irreversible hash chain; it signs each host log entry (SM2 or other asymmetric algorithm), and appends the signature value to the end of the log to complete the signature encapsulation;

[0225] 4. Secure storage and rolling updates: Use SM4 or other symmetric algorithms, encrypt logs with an audit key, and write them to BMC-Flash; trigger rolling updates after reaching a threshold (e.g., threshold is M records, M is greater than or equal to 1).

[0226] 5. Access Control and Auditing: Authorized security administrators on the client side can verify the integrity of the log hash chain and view the complete log.

[0227] Thus, this application provides a server host log management method based on a BMC chip. The client can directly read the log management area in the BMC Flash to obtain the host's logs. Through the closed-loop design of log acquisition → password protection → distributed storage → access control, the entire process from hardware operation to password verification is traceable and non-repudiable, meeting the core requirements of security auditing.

[0228] Figure 10 This application provides a schematic diagram of the structure of a server according to an embodiment of the present application; as shown below. Figure 10 As shown, the server's host board includes: a host and a BMC chip, with the host connected to the BMC chip;

[0229] The host is used to determine the data to be encrypted, encapsulate the data to be encrypted into target data, and transmit the target data to the BMC chip;

[0230] An operation instruction is issued to the BMC chip, the operation instruction being used to instruct the target data to be subjected to trusted computation;

[0231] The BMC chip is used to encapsulate the target data according to the operation instructions to obtain the encapsulated trusted service packet;

[0232] Trusted computation is performed based on the trusted service package to obtain a first computation result; the first computation result is then encapsulated to obtain a trusted service result package.

[0233] The trusted service result package is fed back to the host.

[0234] In some embodiments, the BMC chip includes: an internal cache;

[0235] The host is used to encapsulate the data to be encrypted into a PCIE frame, which is then used as the target data.

[0236] The internal cache memory address space is accessed through the PCIe interface to transmit the PCIe frame to the internal cache of the BMC chip.

[0237] In some embodiments, the BMC chip further includes: a CPU, an encryption / decryption system, and a SEMG;

[0238] The CPU is used to encapsulate the received operation instructions into a descriptor and cache them in the internal cache;

[0239] By configuring the SEMG, the cache address of the descriptor and the target data can be informed to the SEMG;

[0240] The SEMG is used to read the descriptor and the target data according to the cache address, and encapsulate the descriptor and the target data into a trusted service packet; the descriptor is saved to the header of the trusted service packet.

[0241] In some embodiments, the SEMG is used to send the trusted service packet to an encryption / decryption system;

[0242] The encryption / decryption system is used to call the corresponding computing core according to the header information of the trusted service packet, and use the computing core to perform encryption / decryption operations on the target data in the trusted service packet to obtain a first calculation result;

[0243] The encryption / decryption system includes at least one processing core, and the encryption / decryption operation involves one or more processing cores.

[0244] In some embodiments, the encryption / decryption system is used to send the trusted service result packet back to SEMG;

[0245] The SEMG is used to split the trusted service result packet to obtain valid data; write the valid data back to the internal cache and inform the CPU;

[0246] The CPU is configured to send a notification message to the host, so that the host can read the valid data from the internal cache according to the notification message.

[0247] In some embodiments, the server's motherboard further includes: BIOS flash memory;

[0248] The BMC chip is also used to obtain the image file of the boot firmware from the BIOS flash memory through the SPI interface and save the image file to the internal cache of the BMC chip;

[0249] The image file is encapsulated to obtain the encapsulated trusted management package;

[0250] Trusted computation is performed based on the trusted management package to obtain a second computation result; the second computation result is then fed back to the host.

[0251] In some embodiments, the BMC chip further includes: a CPU, an encryption / decryption system, and a SEMG;

[0252] The CPU is used to obtain the image file of the boot firmware from the BIOS flash memory via the SPI interface and save the image file to the internal cache of the BMC chip;

[0253] Accordingly, the SEMG is used to encapsulate the image file to obtain an encapsulated trusted management package;

[0254] as well as,

[0255] The SEMG is used to send the Trusted Management Packet to the encryption / decryption system;

[0256] The encryption / decryption system is used to perform trusted computation based on the trusted management packet to obtain a second computation result; and to write the second computation result back to the SEMG.

[0257] The SEMG is used to parse the second calculation result, obtain the BIOS boot data for the firmware program, write the BIOS boot data back to the internal cache, and inform the CPU.

[0258] The CPU is used to inform the host of the cache address of the BIOS boot data, so that the host can read the BIOS boot data according to the cache address.

[0259] In some embodiments, the internal cache of the BMC chip uses a data linked list structure to manage trusted data packets, and each node in the data linked list corresponds to an independent trusted data packet.

[0260] The descriptors of the data linked list include:

[0261] The first identifier is used to point to the physical address of the trusted data packet in the internal cache of the BMC chip;

[0262] A second identifier is used to indicate the size of the trusted data packet;

[0263] Status flags are used to indicate at least one of the following: verification flag, algorithm type, or access control;

[0264] The descriptors are linked lists and managed in a circular queue using head and tail pointers, supporting the concurrent processing of multiple trusted data packets; the service data packets are stored in either a continuous or discrete manner.

[0265] In some embodiments, the types of trusted data packets include: trusted service packets and trusted management packets;

[0266] The trusted data packet includes: a header and valid data, wherein the header includes: control information, authentication data, and algorithm parameters;

[0267] The control information is used to indicate at least one of the following: packet type, data type, packet length, write-back address, and algorithm type.

[0268] The existence of the authentication data is determined based on the control information and is used to provide baseline value data.

[0269] The algorithm parameters are used to provide the necessary parameter data for the algorithm to run.

[0270] In some embodiments, if the server is applied to an internal and external network structure, and the server is an external network server, the host of the external network server is used to receive network data packets from the external network; transmit the network data packets to the internal cache of the BMC chip of the external network server, and issue transmission instructions to the BMC chip of the external network server;

[0271] The BMC chip of the external network server is used to perform trusted calculations on the network data packets according to the transmission instructions, and then transmit the network data packets to the internal network server.

[0272] or,

[0273] The host of the external network server is used to receive network data packets from the internal network server, send them to the internal cache of the BMC chip of the external network server, and send transmission instructions to the BMC chip of the external network server.

[0274] The BMC chip of the external network server is used to perform trusted calculations on the network data packets according to the transmission instructions to obtain the original network data packets.

[0275] In some embodiments, if the server is applied to an internal and external network structure, and the server is an internal network server, the host of the internal network server is used to receive network data packets from the external network, send them to the internal cache of the BMC chip of the internal network server, and send transmission instructions to the BMC chip of the internal network server.

[0276] The BMC chip of the intranet server is used to perform trusted calculations on the network data packets according to the transmission instructions to obtain the original network data packets;

[0277] or,

[0278] The host of the intranet server is used to receive network data packets; transmit the network data packets to the internal cache of the BMC chip of the intranet server; and issue transmission instructions to the BMC chip of the intranet server.

[0279] The BMC chip of the intranet server is used to perform trusted calculations on the network data packets according to the transmission instructions, and then transmit the network data packets to the extranet server.

[0280] In some embodiments, the host board of the server further includes: BMC flash memory. After the BMC chip is started, the BMC chip is also used to create a host encrypted log storage area in the BMC flash memory, define a structured log template, and generate a dedicated audit key.

[0281] During the server operation phase, at least one log entry is recorded and stored in the host encrypted log storage area of ​​the BMC flash memory;

[0282] The BMC chip records at least one log entry, including:

[0283] When the host BIOS firmware is loaded and verified, the BMC chip records the access address range and data verification value of the SPI interface when reading the BIOS image file; when performing hash verification, the BMC chip records the calculated hash value, the pre-stored base value, and the comparison result; when performing digital signature verification, the BMC chip records the public key information used, the signature algorithm, and the signature verification result; when triggering a decryption operation, the BMC chip records the key handle and the encryption mode.

[0284] After the operating system runs, the BMC chip calculates a hash value for each host log entry, uses the hash value of the previous log entry as input for chained expansion, and constructs an irreversible hash chain; and signs each host log entry, appending the signature value to the end of the log to complete the signature encapsulation.

[0285] It is understood that, when implementing the corresponding BMC-based trusted computing method, the BMC-based trusted computing device provided in the above embodiments can allocate the above processing to different program modules as needed to complete all or part of the processing described above. Furthermore, the device and the corresponding method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0286] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a BMC-based trusted computing method.

[0287] This application provides a computer-readable storage medium storing executable instructions. When the executable instructions are executed by a processor, the processor will execute the trusted computing method based on BMC provided in this application.

[0288] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0289] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0290] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0291] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0292] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application; as shown below. Figure 11 As shown, the electronic device 110 includes a processor 1101 and a memory 1102 communicatively connected to the processor 1101; the memory 1102 stores instructions executable by the processor 1101. The instructions are executed by the processor 1101 to enable the processor 1101 to perform a trusted computing method.

[0293] The electronic devices provided in the above embodiments and the corresponding embodiments of the trusted computing method based on BMC belong to the same concept. For details of their implementation process, please refer to the method embodiments, which will not be repeated here.

[0294] In practical applications, the electronic device 110 may further include at least one network interface 1103. The various components of the electronic device 110 are coupled together via a bus system 1104. It is understood that the bus system 1104 is used to realize communication between these components. In addition to a data bus, the bus system 1104 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 11 All buses are labeled as bus system 1104. The number of processors 1101 can be at least one, and the number of memories 1102 can be at least one. The network interface 1103 is used for wired or wireless communication between the electronic device 110 and other devices.

[0295] The memory 1102 in this embodiment is used to store various types of data to support the operation of the electronic device 110.

[0296] The methods disclosed in the embodiments of this application can be applied to processor 1101, or implemented by processor 1101. Processor 1101 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 1101 or by instructions in the form of software. The processor 1101 may be a general-purpose processor, a digital signal processor (DSP, DiGital Signal Processor), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 1101 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 1102. Processor 1101 reads the information in memory 1102 and, in conjunction with its hardware, completes the steps of the aforementioned trusted computing method based on BMC.

[0297] In some embodiments, the electronic device 110 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0298] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0299] In the above description, the term "some embodiments" refers to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0300] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in this application is for the purpose of describing embodiments of this application only and is not intended to be limiting of this application.

[0301] It should be understood that in the various embodiments of this application, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0302] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0303] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A trusted computing method based on BMC, characterized in that, The method is applied to a server, wherein the server's host board includes: a host and a motherboard management controller (BMC) chip, the host being connected to the BMC chip, and the method includes: The host determines the data to be encrypted, encapsulates the data to be encrypted into target data, and transmits the target data to the BMC chip; The host sends an operation command to the BMC chip, the operation command being used to instruct the target data to be subjected to trusted computation. The BMC chip encapsulates the target data according to the operation instructions to obtain the encapsulated trusted service packet; The BMC chip performs trusted computation based on the trusted service package to obtain a first computation result; the first computation result is then encapsulated to obtain a trusted service result package. The BMC chip feeds back the trusted service result packet to the host. The server's motherboard also includes a BIOS flash memory; the method further includes booting the server's motherboard. The hostboard card used to start the server includes: The BMC chip obtains the image file of the boot firmware from the BIOS flash memory through the SPI interface and saves the image file to the internal cache of the BMC chip; The BMC chip encapsulates the image file to obtain an encapsulated trusted management package; The BMC chip performs trusted computation based on the trusted management package to obtain a second computation result; and feeds the second computation result back to the host. The BMC chip also includes: a CPU, an encryption / decryption system, and an SEMG; The BMC chip obtains the boot firmware image file from the BIOS flash memory via the SPI interface and saves the image file to the BMC chip's internal cache; including: The CPU obtains the boot firmware image file from the BIOS flash memory via the SPI interface and saves the image file to the internal cache of the BMC chip; Accordingly, the BMC chip encapsulates the image file to obtain an encapsulated trusted management package, including: The SEMG encapsulates the image file to obtain the encapsulated Trusted Management Package; Accordingly, the BMC chip performs trusted computation based on the trusted management package to obtain a second computation result; the second computation result is then fed back to the host, including: The SEMG sends the Trusted Management Packet to the encryption / decryption system; The encryption / decryption system performs trusted computation based on the trusted management packet to obtain a second computation result; and writes the second computation result back to the SEMG. The SEMG parses the second calculation result to obtain the BIOS boot data for the firmware program, writes the BIOS boot data back to the internal cache, and informs the CPU. The CPU informs the host of the cache address of the BIOS boot data, so that the host can read the BIOS boot data according to the cache address.

2. The method according to claim 1, characterized in that, The BMC chip includes: an internal cache; Encapsulating the data to be encrypted into target data and transmitting the target data to the BMC chip includes: The data to be encrypted is encapsulated into a high-speed serial computer extended bus standard PCIe frame, which is used as the target data; The internal cache memory address space is accessed through the PCIe interface to transmit the PCIe frame to the internal cache of the BMC chip.

3. The method according to claim 1 or 2, characterized in that, The BMC chip also includes: a central processing unit (CPU), an encryption / decryption system, and a signal event management register (SEMG); The step of encapsulating the target data according to the operation instructions to obtain the encapsulated trusted service package includes: The CPU encapsulates the received operation instructions into a descriptor and caches it in its internal cache; The CPU configures the SEMG to inform the SEMG of the descriptor and the cache address of the target data; The SEMG reads the descriptor and the target data according to the cache address, and encapsulates the descriptor and the target data into a trusted service packet; the descriptor is saved to the header of the trusted service packet.

4. The method according to claim 3, characterized in that, The BMC chip performs trusted computation based on the trusted service packet to obtain a first computation result, including: The SEMG sends the trusted service packet to the encryption / decryption system; The encryption / decryption system calls the corresponding processing core according to the header information of the trusted service packet, and uses the processing core to perform encryption / decryption operations on the target data in the trusted service packet to obtain the first calculation result; The encryption / decryption system includes at least one processing core, and the encryption / decryption operation involves one or more processing cores.

5. The method according to claim 3, characterized in that, The BMC chip feeds back the trusted service result packet to the host, including: The encryption / decryption system sends the trusted service result packet back to SEMG; The SEMG splits the trusted service result packet to obtain valid data; The SEMG writes the valid data back to the internal cache and informs the CPU; The CPU sends a notification message to the host, so that the host can read the valid data from the internal cache according to the notification message.

6. The method according to claim 2, characterized in that, The internal cache of the BMC chip uses a data linked list structure to manage trusted data packets, and each node in the data linked list corresponds to an independent trusted data packet. The descriptors of the data linked list include: The first identifier is used to point to the physical address of the trusted data packet in the internal cache of the BMC chip; A second identifier is used to indicate the size of the trusted data packet; Status flags are used to indicate at least one of the following: verification flag, algorithm type, or access control; The descriptor is in the form of a linked list, and a circular queue is implemented through head and tail pointers to support the concurrent storage of multiple trusted data packets; the trusted data packets adopt a continuous or discrete storage mode.

7. The method according to claim 6, characterized in that, The types of trusted data packets include: trusted service packets and trusted management packets; The trusted data packet includes: a header and valid data, wherein the header includes: control information, authentication data, and algorithm parameters; The control information is used to indicate at least one of the following: packet type, data type, packet length, write-back address, and algorithm type; The existence of the authentication data is determined based on the control information and is used to provide baseline value data. The algorithm parameters are used to provide the necessary parameter data for the algorithm to run.

8. The method according to claim 1, characterized in that, If the server is used in an internal / external network structure, and the server acts as an external network server, the method further includes: The host of the external network server receives network data packets from the external network; The host of the external network server transmits the network data packets to the internal cache of the BMC chip of the external network server and sends transmission instructions to the BMC chip of the external network server. The BMC chip of the external network server performs a trusted calculation on the network data packet according to the transmission instruction, and then transmits the network data packet to the internal network server. or, After receiving network data packets from the internal network server, the host of the external network server sends them to the internal cache of the BMC chip of the external network server and sends a transmission command to the BMC chip of the external network server. The BMC chip of the external network server performs a trusted calculation on the network data packet according to the transmission instruction to obtain the original network data packet.

9. The method according to claim 1, characterized in that, If the server is used in an internal / external network structure, and the server is an internal network server, the method further includes: After receiving network data packets from the external network, the host of the intranet server sends them to the internal cache of the BMC chip of the intranet server and sends a transmission command to the BMC chip of the intranet server. The BMC chip of the intranet server performs a trusted calculation on the network data packet according to the transmission instruction to obtain the original network data packet; or, The host of the intranet server receives network data packets; The host of the intranet server transmits the network data packets to the internal cache of the BMC chip of the intranet server and sends transmission instructions to the BMC chip of the intranet server. The BMC chip of the intranet server performs a trusted calculation on the network data packet according to the transmission instruction, and then transmits the network data packet to the external network server.

10. The method according to claim 1, characterized in that, The server's motherboard also includes: BMC flash memory, and the method further includes: After the BMC chip is started, a host encrypted log storage area is created in the BMC flash memory, a structured log template is defined, and a dedicated audit key is generated. During the server operation phase, the BMC chip records at least one log and stores it in the host encrypted log storage area of ​​the BMC flash memory; The BMC chip records at least one log entry, including: When the host BIOS firmware is loaded and verified, the BMC chip records the access address range and data verification value of the interface when reading the BIOS image file; when performing hash verification, the BMC chip records the calculated hash value, the pre-stored base value, and the comparison result; when performing digital signature verification, the BMC chip records the public key information used, the signature algorithm, and the signature verification result; when triggering a decryption operation, the BMC chip records the key handle and the encryption mode. After the operating system runs, the BMC chip calculates a hash value for each host log entry, uses the hash value of the previous log entry as input for chained expansion, and constructs an irreversible hash chain; and signs each host log entry, appending the signature value to the end of the log to complete the signature encapsulation.

11. A server, characterized in that, The server's host board includes: a host and a BMC chip, with the host connected to the BMC chip; The host is used to determine the data to be encrypted, encapsulate the data to be encrypted into target data, and transmit the target data to the BMC chip; An operation instruction is issued to the BMC chip, the operation instruction being used to instruct the target data to be subjected to trusted computation; The BMC chip is used to encapsulate the target data according to the operation instructions to obtain the encapsulated trusted service packet; Trusted computation is performed based on the trusted service package to obtain a first computation result; the first computation result is then encapsulated to obtain a trusted service result package. The trusted service result packet is fed back to the host. The server's motherboard also includes: BIOS flash memory; The BMC chip is also used to obtain the image file of the boot firmware from the BIOS flash memory through the SPI interface and save the image file to the internal cache of the BMC chip; The image file is encapsulated to obtain the encapsulated trusted management package; Trusted computation is performed based on the trusted management package to obtain a second computation result; the second computation result is then fed back to the host. The BMC chip also includes: a CPU, an encryption / decryption system, and an SEMG; The CPU is used to obtain the image file of the boot firmware from the BIOS flash memory via the SPI interface and save the image file to the internal cache of the BMC chip; Accordingly, the SEMG is used to encapsulate the image file to obtain an encapsulated trusted management package; as well as, The SEMG is used to send the Trusted Management Packet to the encryption / decryption system; The encryption / decryption system is used to perform trusted computation based on the trusted management packet to obtain a second computation result; and to write the second computation result back to the SEMG. The SEMG is used to parse the second calculation result, obtain the BIOS boot data for the firmware program, write the BIOS boot data back to the internal cache, and inform the CPU. The CPU is used to inform the host of the cache address of the BIOS boot data, so that the host can read the BIOS boot data according to the cache address.

12. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the trusted computing method according to any one of claims 1 to 10.

13. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the trusted computing method according to any one of claims 1 to 10.

Images