Decoding system and physical layout for simulated neural memory in deep learning artificial neural networks

Abstract

Decoding systems and physical layouts for simulated neural memory in deep learning artificial neural networks. Disclosed are various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders, and various types of physical layout designs for simulating non-volatile flash memory arrays in nervous systems. The invention discloses a sharing and segmentation implementation scheme of a high voltage row decoder.

Description

[0001] This application is a divisional application of the patent application filed on November 17, 2019, with international application number PCT / US2019 / 061900, Chinese application number 201980095856.2, entitled "Decoding system and physical layout for analog neural memory in deep learning artificial neural networks".

[0002] Priority Statement

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 840,318, filed April 29, 2019, entitled “DECODING SYSTEM AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK”, and U.S. Patent Application No. 16 / 503,355, filed July 3, 2019, entitled “DECODING SYSTEM AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK”. Technical Field

[0004] This invention discloses an improved decoding system and physical layout for analog neural memory systems utilizing non-volatile memory cells. Background Technology

[0005] Artificial neural networks mimic biological neural networks (the central nervous system of animals, especially the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are often unknown. Artificial neural networks typically consist of interconnected layers of "neurons" that exchange messages with each other.

[0006] Figure 1 An artificial neural network is illustrated, where circles represent the inputs or layers of neurons. Connections (called synapses) are indicated by arrows and have numerical weights that can be adjusted empirically. This allows the neural network to adapt to its inputs and learn. Typically, a neural network consists of layers with multiple inputs. There are usually one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions individually or collectively based on the data received from the synapses.

[0007] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of sufficient hardware technology. Real-world neural networks rely on a large number of synapses to achieve high connectivity between neurons, i.e., very high computational parallelism. In principle, such complexity can be achieved using digital supercomputers or dedicated clusters of graphics processing units. However, compared to biological networks, these methods are generally energy inefficient, in addition to being costly, as biological networks consume less energy primarily due to their ability to perform low-precision analog calculations. CMOS analog circuits have been used in artificial neural networks, but most CMOS-implemented synapses are excessively large due to the need for a large number of neurons and synapses.

[0008] The applicant previously disclosed an artificial (simulated) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application 15 / 594,439 (published as U.S. Patent Publication 2017 / 0337466), which is incorporated herein by reference. The non-volatile memory array operates as a simulated neural memory. The neural network device includes a plurality of first synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a plurality of first neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each memory cell includes: spaced-apart source and drain regions formed in a semiconductor substrate, wherein a channel region extends between the source and drain regions; a floating gate disposed over and insulated from a first portion of the channel region; and a non-floating gate disposed over and insulated from a second portion of the channel region. Each memory cell is configured to store weight values ​​corresponding to a plurality of electrons on the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values ​​to generate the first plurality of outputs.

[0009] Every non-volatile memory cell used in an analog neural memory system must be erased and programmed to maintain a very specific and precise amount of charge (i.e., the number of electrons) in the floating gate. For example, each floating gate must hold one of N distinct values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0010] One challenge in vector-matrix multiplication (VMM) systems is the ability to select specific cells or groups of cells for erase, program, and read operations, or in some cases, the entire array of cells. A related challenge is improving the use of physical space within the semiconductor die without sacrificing functionality.

[0011] What is needed is an improved decoding system and physical layout for analog neural memory systems that utilize non-volatile memory cells. Summary of the Invention

[0012] This invention discloses an improved decoding system and physical layout for analog neural memory systems utilizing non-volatile memory cells. Attached Figure Description

[0013] Figure 1 A schematic diagram illustrating an existing artificial neural network.

[0014] Figure 2 This illustrates a split-gate flash memory cell from the prior art.

[0015] Figure 3 This illustrates another prior art split-gate flash memory cell.

[0016] Figure 4 This illustrates another prior art split-gate flash memory cell.

[0017] Figure 5 This illustrates another prior art split-gate flash memory cell.

[0018] Figure 6 This illustrates another prior art split-gate flash memory cell.

[0019] Figure 7 This illustrates a stacked gate flash memory cell from the prior art.

[0020] Figure 8 This is a schematic diagram illustrating different layers of an exemplary artificial neural network using one or more non-volatile memory arrays.

[0021] Figure 9 A block diagram illustrating the vector-matrix multiplication system is provided.

[0022] Figure 10 A block diagram illustrating an exemplary artificial neural network using one or more vector-matrix multiplication systems is provided.

[0023] Figure 11 Another implementation scheme of the vector-matrix multiplication system is shown.

[0024] Figure 12 Another implementation scheme of the vector-matrix multiplication system is shown.

[0025] Figure 13 Another implementation scheme of the vector-matrix multiplication system is shown.

[0026] Figure 14 Another implementation scheme of the vector-matrix multiplication system is shown.

[0027] Figure 15 Another implementation scheme of the vector-matrix multiplication system is shown.

[0028] Figure 16 This illustrates a prior art long short-term memory system.

[0029] Figure 17 An exemplary cell used in a long short-term memory system is shown.

[0030] Figure 18 Show Figure 17 An implementation of an exemplary unit.

[0031] Figure 19 Show Figure 17 Another implementation of the exemplary unit.

[0032] Figure 20 This illustrates a prior art gate-controlled recursive cell system.

[0033] Figure 21 An exemplary cell used in a gate-controlled recursive cell system is shown.

[0034] Figure 22 Show Figure 21 An implementation of an exemplary unit.

[0035] Figure 23 Show Figure 21 Another implementation of the exemplary unit.

[0036] Figure 24 Another implementation scheme of the vector-matrix multiplication system is shown.

[0037] Figure 25 Another implementation scheme of the vector-matrix multiplication system is shown.

[0038] Figure 26 Another implementation scheme of the vector-matrix multiplication system is shown.

[0039] Figure 27 Another implementation scheme of the vector-matrix multiplication system is shown.

[0040] Figure 28 Another implementation scheme of the vector-matrix multiplication system is shown.

[0041] Figure 29 Another implementation scheme of the vector-matrix multiplication system is shown.

[0042] Figure 30 Another implementation scheme of the vector-matrix multiplication system is shown.

[0043] Figure 31 Another implementation scheme of the vector-matrix multiplication system is shown.

[0044] Figure 32Another implementation scheme of the vector-matrix multiplication system is shown.

[0045] Figure 33 An exemplary block diagram of a vector-matrix multiplication system is shown.

[0046] Figure 34 An exemplary decoding implementation scheme for a vector-matrix multiplication system is shown.

[0047] Figure 35 Another exemplary decoding implementation of the vector-matrix multiplication system is shown.

[0048] Figure 36 An example line decoder is shown.

[0049] Figure 37 Another exemplary decoding implementation of the vector-matrix multiplication system is shown.

[0050] Figure 38 Another exemplary decoding implementation of the vector-matrix multiplication system is shown.

[0051] Figure 39 Another exemplary decoding implementation of the vector-matrix multiplication system is shown.

[0052] Figure 40 An implementation of a low-voltage line decoder is shown.

[0053] Figure 41 An embodiment of a combined low-voltage line decoder and control gate decoder is shown.

[0054] Figure 42 An implementation of a bitline decoder is shown.

[0055] Figure 43 The vector-matrix multiplication system and input block are shown.

[0056] Figure 44 A multiplexer is shown for receiving output from an array and providing input to one or more arrays in a multiplexed manner.

[0057] Figure 45A and Figure 45B An exemplary layout of a vector-matrix multiplication system is shown.

[0058] Figure 46 An exemplary layout of a vector-matrix multiplication system is shown.

[0059] Figure 47 The diagram shows a word line decoder circuit, a source line decoder circuit, and a high-voltage level shifter for use with a vector multiplier matrix.

[0060] Figure 48The erase gate decoder circuit, control gate decoder circuit, source line decoder circuit, and high voltage level shifter are shown for use with a vector multiplier matrix.

[0061] Figure 49 Another implementation of a word line driver for use with a vector multiplier matrix is ​​shown.

[0062] Figure 50 Another implementation of a word line driver for use with a vector multiplier matrix is ​​shown.

[0063] Figure 51 Another exemplary decoding implementation of the vector-matrix multiplication system is shown. Detailed Implementation

[0064] The artificial neural network of this invention utilizes a combination of CMOS technology and non-volatile memory arrays.

[0065] Non-volatile memory cells

[0066] Digital nonvolatile memory is well known. For example, U.S. Patent 5,029,130 ​​(“130 Patent”), which is incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which is a type of flash memory cell. Such memory cells 210 in… Figure 2 As shown in the figure. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controlling the conductivity of) a second portion of the channel region 18, and a second portion extending upward and located over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line terminal 24 is coupled to the drain region 16.

[0067] The memory cell 210 is erased by applying a high positive voltage to the word line terminal 22 (where electrons are removed from the floating gate), which causes electrons on the floating gate 20 to tunnel from the floating gate 20 to the word line terminal 22 through the intermediate insulator via Fowler-Nordheim tunneling.

[0068] Memory cell 210 is programmed by applying a positive voltage to word line terminal 22 and a positive voltage to source region 14 (where electrons are placed on the floating gate). Electron current flows from source region 14 (source line terminal) to drain region 16. When electrons reach the gap between word line terminal 22 and floating gate 20, they accelerate and become heated. Due to electrostatic attraction from floating gate 20, some heated electrons are injected into floating gate 20 through gate oxide.

[0069] Memory cell 210 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (which connects the portion of channel region 18 below the word line terminal). If the floating gate 20 is positively charged (i.e., electrons are erased), the portion of channel region 18 below the floating gate 20 is also turned on, and current flows through channel region 18, which is sensed as an erased state or a "1" state. If the floating gate 20 is negatively charged (i.e., programmed electronically), the portion of channel region below the floating gate 20 is mostly or completely turned off, and current does not flow (or very little current) through channel region 18, which is sensed as a programmed state or a "0" state.

[0070] Table 1 shows the typical voltage range that can be applied to the terminals of memory cell 110 for performing read, erase, and program operations:

[0071] Table 1: Figure 2 Operation of flash memory cell 210

[0072] WL BL SL Read 1 0.5-3V 0.1-2V 0V Read 2 0.5-3V 0-2V 2-0.1V erase Approximately 11-13V 0V 0V programming 1V-2V 1-3μA 9-10V

[0073] "Read 1" is the read mode where the cell current is output on the bit line. "Read 2" is the read mode where the cell current is output on the source line terminal.

[0074] Figure 3 The memory cell 310 is shown, which is related to Figure 2 The memory cell 210 is similar, but with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, at a low or negative voltage (e.g., 0V / -8V) during erasure, and at a low or medium voltage (e.g., 0V / 2.5V) during reading. Other terminals are similar. Figure 2 That kind of bias.

[0075] Figure 4A quad-gate memory cell 410 is shown, comprising a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating gates, meaning they are electrically connected to or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0076] Table 2 shows the typical voltage range that can be applied to the terminals of memory cell 310 for performing read, erase, and program operations:

[0077] Table 2: Figure 4 Operation of flash memory cell 410

[0078] WL / SG BL CG EG SL Read 1 0.5-2V 0.1-2V 0-2.6V 0-2.6V 0V Read 2 0.5-2V 0-2V 0-2.6V 0-2.6V 2-0.1V erase -0.5V / 0V 0V 0V / -8V 8-12V 0V programming 1V 1μA 8-11V 4.5-9V 4.5-5V

[0079] "Read 1" is the read mode where the cell current is output on the bit line. "Read 2" is the read mode where the cell current is output on the source line terminal.

[0080] Figure 5 Memory cell 510 is shown, except that it does not have the erase gate EG terminal. Memory cell 510 is similar to... Figure 4 The memory cell 410 is similar. Erasure is performed by biasing the substrate 18 to a high voltage and the control gate CG terminal 28 to a low voltage or a negative voltage. Alternatively, erasure is performed by biasing the word line terminal 22 to a positive voltage and the control gate terminal 28 to a negative voltage. Programming and reading are similar. Figure 4 As it is.

[0081] Figure 6 A tri-gate memory cell 610 is shown, which is another type of flash memory cell. Memory cell 610 and... Figure 4 The memory cell 410 is identical to the memory cell 610, except that the memory cell 610 does not have a separate control gate terminal. Except that no control gate bias is applied, the erase operation (erasing via the erase gate terminal) and read operation are similar. Figure 4 The programming operation is performed without a control gate bias, and as a result, a higher voltage must be applied to the source line terminals during the programming operation to compensate for the lack of a control gate bias.

[0082] Table 3 shows the typical voltage range that can be applied to the terminals of memory cell 610 for performing read, erase, and program operations:

[0083] Table 3: Figure 6 Operation of flash memory cell 610

[0084] WL / SG BL EG SL Read 1 0.5-2.2V 0.1-2V 0-2.6V 0V Read 2 0.5-2.2V 0-2V 0-2.6V 2-0.1V erase -0.5V / 0V 0V 11.5V 0V programming 1V 2-3μA 4.5V 7-9V

[0085] "Read 1" is the read mode where the cell current is output on the bit line. "Read 2" is the read mode where the cell current is output on the source line terminal.

[0086] Figure 7 The stacked gate memory cell 710 is shown, which is another type of flash memory cell. Memory cell 710 and... Figure 2 The memory cell 210 is similar, except that the floating gate 20 extends over the entire channel region 18, and the control gate terminal 22 (which will be coupled to the word line here) extends over the floating gate 20, separated by an insulating layer (not shown). Erase, program, and read operations operate in a manner similar to those previously described for memory cell 210.

[0087] Table 4 shows the typical voltage ranges that can be applied to the terminals of memory cell 710 and substrate 12 to perform read, erase, and program operations:

[0088] Table 4: Figure 7 Operation of flash memory cell 710

[0089] CG BL SL substrate Read 1 0-5V 0.1–2V 0-2V 0V Read 2 0.5-2V 0-2V 2-0.1V 0V erase -8 to -10V / 0V FLT FLT 8-10V / 15-20V programming 8-12V 3-5V / 0V 0V / 3-5V 0V

[0090] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output at the source line terminal. Optionally, in an array comprising rows and columns of memory cells 210, 310, 410, 510, 610, or 710, the source line can be coupled to a row of memory cells or two adjacent rows of memory cells. That is, the source line terminal can be shared by memory cells in adjacent rows.

[0091] To utilize memory arrays comprising one of the aforementioned types of non-volatile memory cells in artificial neural networks, two modifications were made. First, the circuitry was configured such that each memory cell could be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as explained further below. Second, continuous (simulated) programming of the memory cells was provided.

[0092] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state independently with minimal interference to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be continuously changed from a fully programmed state to a fully erased state and vice versa, independently with minimal interference to other memory cells. This means that the cell storage device is analog, or at least can store one discrete value from many discrete values ​​(such as 16 or 64 different values), which allows for very precise and individual tuning of all cells in the memory array, and makes the memory array ideal for storing and fine-tuning the synaptic weights of neural networks.

[0093] The methods and apparatus described herein can be applied to other non-volatile memory technologies, such as, but not limited to, SONOS (silicon-oxide-nitride-oxide-silicon, with charge trapped in the nitride), MONOS (metal-oxide-nitride-oxide-silicon, with metal charge trapped in the nitride), ReRAM (resistive RAM), PCM (phase-change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), OTP (double- or multi-layer programmable at one time), and CeRAM (associated electron RAM). The methods and apparatus described herein can also be applied to volatile memory technologies for neural networks, such as, but not limited to, SRAM, DRAM, and volatile synaptic cells.

[0094] Neural networks using non-volatile memory cell arrays

[0095] Figure 8 This conceptually illustrates a non-limiting example of a neural network using a non-volatile memory array in this embodiment. This example uses a non-volatile memory array neural network for a facial recognition application, but any other suitable application can also be implemented using a neural network based on a non-volatile memory array.

[0096] In this example, S0 is the input layer, which is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with 5-bit precision per pixel). The synapse CB1 from the input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in others, and scans the input image with a 3x3 pixel overlapping filter (kernel), shifting the filter by one pixel (or more than one pixel depending on the model). Specifically, the values ​​of nine pixels in a 3x3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these nine input values ​​are multiplied by appropriate weights, and after summing the output of this multiplication, a single output value is determined by the first synapse of CB1 to generate the pixels of one of the feature maps in layer C1. The 3x3 filter is then shifted one pixel to the right within the input layer S0 (i.e., adding a column of three pixels to the right and releasing a column of three pixels to the left), thereby providing the nine pixel values ​​from this newly positioned filter to synapse CB1, where they are multiplied by the same weights and the second single output value is determined by the associated synapse. This process continues until the 3x3 filter scans all three colors and all bits (precision values) across the entire 32x32 pixel image of the input layer S0. This process is then repeated using different sets of weights to generate different feature maps for C1 until all feature maps for layer C1 are computed.

[0097] At layer C1, in this example, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array. Therefore, in this example, layer C1 consists of a 16-layer two-dimensional array (remember that the layers and arrays referred to in this article are logical relationships, not necessarily physical relationships; that is, the array does not have to be oriented as a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one set of sixteen different groups of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as boundary recognition. For example, the first map (generated using the first weight recombination, shared for all scans used to generate the first map) can recognize circular edges, the second map (generated using the second weight recombination, different from the first weight recombination) can recognize rectangular edges, or the aspect ratio of certain features, and so on.

[0098] Before transitioning from layer C1 to layer S1, activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. The purpose of the pooling function is to average the neighboring locations (or, alternatively, use a max function) to, for example, reduce the dependence on edge locations and reduce the data size before moving to the next stage. At layer S1, there are 16 15x15 feature maps (i.e., sixteen different arrays, each 15x15 pixels). The synapse CB2 from layer S1 to layer C2 scans the map in S1 using a 4x4 filter, where the filter is shifted by 1 pixel. At layer C2, there are 22 12x12 feature maps. Before transitioning from layer C2 to layer S2, activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. At layer S2, there are 22 6x6 feature maps. An activation function (pooling) is applied to the synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each mapping in layer S2 via a corresponding synapse in CB3. There are 64 neurons in layer C3. The synapse CB4 from layer C3 to the output layer S3 completely connects C3 to S3, meaning each neuron in layer C3 is connected to every neuron in layer S3. The output at S3 comprises 10 neurons, with the highest-output neuron determining the class. For example, this output could indicate the recognition or classification of the content of the original image.

[0099] Synapses for each layer are implemented using an array or a portion of an array of non-volatile memory cells.

[0100] Figure 9 The diagram shows a block diagram of a system that could be used for this purpose. The vector-matrix multiplication (VMM) system 32 includes non-volatile memory cells and serves as synapses between layers (such as...) Figure 6 (CB1, CB2, CB3, and CB4 in the original text). Specifically, the VMM system 32 includes a VMM array 33 having non-volatile memory cells arranged in rows and columns, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the corresponding inputs of the non-volatile memory cell array 33. The inputs to the VMM array 33 may come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the outputs of the VMM array 33. Alternatively, the bit line decoder 36 may decode the outputs of the VMM array 33.

[0101] The VMM array 33 serves two purposes. First, it stores weights that will be used by the VMM system 32. Second, the VMM array 33 efficiently multiplies the inputs with the weights stored in the VMM array 33 and adds them together at each output line (source line or bit line) to produce an output that will serve as the input to the next layer or the final layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic circuits and is also highly efficient due to its in-situ memory computation.

[0102] The output of VMM array 33 is provided to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of VMM array 33 to create a single value for the convolution. Differential summer 38 is arranged to perform the summation of both the positive and negative weight inputs to output a single value.

[0103] The output values ​​of the difference summer 38 are then summed and provided to the activation function circuit 39, which corrects the output. The activation function circuit 39 can provide a sigmoid, tanh, ReLU function, or any other nonlinear function. The corrected output value of the activation function circuit 39 becomes the next layer's (e.g., Figure 8 The elements of the feature map of layer C1 are then applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the VMM array 33 constitutes multiple synapses (which receive their input from existing neuron layers or from input layers such as an image database), and the summer 38 and activation function circuit 39 constitute multiple neurons.

[0104] Figure 9 The inputs to the VMM system 32 (WLx, EGx, CGx, and optional BLx and SLx) can be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter (PAC) may be required to convert the pulses to the appropriate input analog level), or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog level); the outputs can be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog level to digital bits).

[0105] Figure 10 A block diagram illustrating the use of a multi-layer VMM system 32 (here labeled VMM systems 32a, 32b, 32c, 32d, and 32e). For example... Figure 10As shown, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be voltage or current. The first-level input D / A conversion can be accomplished by using a function or LUT (lookup table) of appropriate analog levels of the matrix multiplier that maps Inputx to the input VMM system 32a. Input conversion can also be accomplished by an analog-to-analog (A / A) converter to convert an external analog input into a mapped analog input to the input VMM system 32a. Input conversion can also be accomplished by a digital-to-digital pulse (D / P) converter to convert an external digital input into one or more digital pulses mapped to the input VMM system 32a.

[0106] The output generated by the input VMM system 32a is provided as input to the next VMM system (hidden level 1) 32b, which in turn generates the output provided as input to the next VMM system (hidden level 2) 32c, and so on. The layers of VMM system 32 serve as different layers of synapses and neurons in a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be an independent physical non-volatile memory array, or multiple VMM systems can utilize different portions of the same non-volatile memory array, or multiple VMM systems can utilize overlapping portions of the same physical non-volatile memory system. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time-division multiplexed for different portions of its array or neurons. Figure 10 The example shown contains five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will recognize that this is merely exemplary, and conversely, a system may include more than two hidden layers and more than two fully connected layers.

[0107] VMM array

[0108] Figure 11 The neuronal VMM array 1100 is shown, which is particularly suitable for Figure 3 The memory cell 310 shown serves as a synapse and component for neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (at the top of the array). Alternatively, another reference array may be placed at the bottom.

[0109] In VMM array 1100, control gate lines (such as control gate line 1103) extend vertically (therefore, reference array 1102 is orthogonal to control gate line 1103 in the row direction), and erase gate lines (such as erase gate line 1104) extend horizontally. Here, the inputs of VMM array 1100 are set on control gate lines (CG0, CG1, CG2, CG3), and the outputs of VMM array 1100 appear on source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summation function of all currents from the memory cells connected to that particular source line.

[0110] As described herein with respect to neural networks, the non-volatile memory cells of the VMM array 1100 (i.e., the flash memory of the VMM array 1100) are preferably configured to operate in the subthreshold region.

[0111] In weak inversion, the non-volatile reference memory cell and non-volatile memory cell described in this paper are biased:

[0112] Ids = Io * e (Vg-Vth) / nVt =w*Io*e (Vg) / nVt ,

[0113] Where w = e (-Vth) / nVt

[0114] Where Ids is the drain-to-source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k*T / q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1 + (Cdep / Cox), where Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at the gate voltage equal to the threshold voltage, and Io is related to (Wt / L)*u*Cox*(n-1)*Vt 2 Proportional, where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0115] For I-to-V logarithmic converters that use memory cells (such as reference memory cells or peripheral memory cells) or transistors to convert input current Ids to input voltage Vg:

[0116] Vg = n * Vt * log[Ids / wp * Io]

[0117] Here, wp refers to the w in the reference memory cell or the peripheral memory cell.

[0118] For a memory array used as a VMM array for vector matrix multipliers, the output current is:

[0119] Iout = wa * Io * e (Vg) / nVt ,Right now

[0120] Iout = (wa / wp) * Iin = W * Iin

[0121] W = e (Vthp-Vtha) / nVt

[0122] Iin = wp * Io * e (Vg) / nVt

[0123] Here, wa = w for each memory cell in the memory array.

[0124] Word lines or control gates can be used as inputs to memory cells that accept input voltages.

[0125] Alternatively, the non-volatile memory cells of the VMM array described herein can be configured to operate in a linear region:

[0126] Ids=β*(Vgs-Vth)*Vds;β=u*Cox*Wt / L,

[0127] Wα(Vgs-Vth),

[0128] This means that the weight W in the linear region is proportional to (Vgs-Vth).

[0129] Word lines, control gates, bit lines, or source lines can be used as inputs to memory cells operating in a linear region. Bit lines or source lines can be used as outputs to memory cells.

[0130] For an I-to-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor or resistor operating in the linear region can be used to linearly convert the input / output current into the input / output voltage.

[0131] Alternatively, the flash memory cells of the VMM array described herein can be configured to operate in a saturation region:

[0132] Ids = 1 / 2 * β * (Vgs - Vth) 2 β=u*Cox*Wt / L

[0133] Wα(Vgs-Vth) 2 This means that the weight W is related to (Vgs-Vth). 2 proportional

[0134] Word lines, control gates, or erase gates can be used as inputs to memory cells operating in saturation regions. Bit lines or source lines can be used as outputs of output neurons.

[0135] Alternatively, the memory cells of the VMM array described herein can be used in all regions or combinations thereof (subthreshold, linear, or saturated regions).

[0136] U.S. Patent Application 15 / 826,345 describes Figure 9 Other embodiments of the VMM array 32 are described herein, and this application is incorporated herein by reference. As described herein, source lines or bit lines can be used as neuron outputs (current summation outputs).

[0137] Figure 12 This illustrates a neuronal VMM array 1200, which is particularly suitable for... Figure 2 The memory cell 210 shown serves as a synapse between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of first non-volatile reference memory cells, and a reference array 1202 of second non-volatile reference memory cells. The reference arrays 1201 and 1202, arranged along the column direction of the array, are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected via a multiplexer 1214 (partially shown) through which current inputs flow. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0138] Memory array 1203 serves two purposes. First, it stores the weights used by VMM array 1200 on their respective memory cells. Second, memory array 1203 efficiently multiplies the inputs (i.e., the current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1201 and 1202 convert into input voltages to provide to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1203, and then sums all the results (memory cell currents) to produce an output on the corresponding bit lines (BL0-BLN), which will be the input to the next layer or the final layer. By performing multiplication and addition functions, memory array 1203 eliminates the need for separate multiplication and addition logic circuits and is also highly efficient. Here, voltage inputs are provided on word lines (WL0, WL1, WL2, and WL3), and the output appears on the corresponding bit lines (BL0-BLN) during read (inference) operations. The current placed on each bit line in the bit lines BL0-BLN performs a summation function of the currents from all non-volatile memory cells connected to that particular bit line.

[0139] Table 5 shows the operating voltages used for the VMM array 1200. The columns in the table indicate the voltage applied to the word line for the selected cell, the word line for the unselected cell, the bit line for the selected cell, the bit line for the unselected cell, the source line for the selected cell, and the source line for the unselected cell, where FLT indicates floating, i.e., no voltage is applied. The rows indicate read, erase, and program operations.

[0140] Table 5: Figure 12 Operation of VMM array 1200

[0141] WL WL - Not selected BL BL - Not Selected SL SL - Not selected Read 0.5-3.5V -0.5V / 0V 0.1-2V (Ineuron) 0.6V-2V / FLT 0V 0V erase Approximately 5-13V 0V 0V 0V 0V 0V programming 1V-2V -0.5V / 0V 0.1-3uA Vinh approximately 2.5V 4-10V 0-1V / FLT

[0142] Figure 13 This illustrates a neuronal VMM array 1300, which is particularly suitable for... Figure 2The memory cell 210 shown serves as a synapse and component for neurons between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of first non-volatile reference memory cells, and a reference array 1302 of second non-volatile reference memory cells. Reference arrays 1301 and 1302 extend in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that in the VMM array 1300, word lines extend in the vertical direction. Here, inputs are set on word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on source lines (SL0, SL1) during read operations. The current placed on each source line performs a summation function of all currents from the memory cells connected to that particular source line.

[0143] Table 6 shows the operating voltages used for the VMM array 1300. The columns in the table indicate the voltage applied to the word line for the selected cell, the word line for the unselected cell, the bit line for the selected cell, the bit line for the unselected cell, the source line for the selected cell, and the source line for the unselected cell. The rows indicate read, erase, and program operations.

[0144] Table 6: Figure 13 Operation of VMM array 1300

[0145]

[0146] Figure 14 The diagram shows a neuronal VMM array 1400, which is particularly suitable for... Figure 3 The memory cell 310 shown serves as a synapse and component for neurons between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of first non-volatile reference memory cells, and a reference array 1402 of second non-volatile reference memory cells. Reference arrays 1401 and 1402 are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected via a multiplexer 1412 (partially shown), through which current inputs flow via BLR0, BLR1, BLR2, and BLR3. Each multiplexer 1412 includes a corresponding multiplexer 1405 and a common-source cascode transistor 1404 to ensure a constant voltage on the bit lines (such as BLRO) of each of the first and second non-volatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0147] Memory array 1403 serves two purposes. First, it stores weights that will be used by VMM array 1400. Second, memory array 1403 efficiently multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1401 and 1402 convert into input voltages to be provided to control gates CG0, CG1, CG2, and CG3) by the weights stored in the memory array, and then sums all the results (cell currents) to produce an output that appears on BL0-BLN and will be the input to the next layer or the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly efficient. Here, the inputs are provided on control gate lines (CG0, CG1, CG2, and CG3), and the outputs appear on bit lines (BL0–BLN) during read operations. The currents placed on each bit line perform a summation function of all currents from the memory cells connected to that particular bit line.

[0148] The VMM array 1400 implements unidirectional tuning for the non-volatile memory cells in the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge is reached on the floating gate. This can be performed, for example, using the precise programming techniques described below. If too much charge is placed on the floating gate (causing an incorrect value to be stored in the cell), the cell must be erased, and the sequence of partial programming operations must restart. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (this is called page erasure), and thereafter, each cell is partially programmed until the desired charge is reached on the floating gate.

[0149] Table 7 shows the operating voltages used for the VMM array 1400. The columns in the table indicate the voltage applied to the word lines for the selected cell, the word lines for the unselected cell, the bit lines for the selected cell, the bit lines for the unselected cell, the control gate for the selected cell, the control gate for the unselected cell in the same sector as the selected cell, the control gate for the unselected cell in a different sector from the selected cell, the erase gate for the selected cell, the erase gate for the unselected cell, the source line for the selected cell, and the source line for the unselected cell. The rows indicate read, erase, and program operations.

[0150] Table 7: Figure 14 Operation of VMM array 1400

[0151]

[0152] Figure 15 This illustrates a neuronal VMM array 1500, which is particularly suitable for... Figure 3The memory cell 310 shown serves as a synapse and component for neurons between the input layer and the next layer. The VMM array 1500 includes a memory array 1503 of non-volatile memory cells, a reference array 1501 of first non-volatile reference memory cells, and a reference array 1502 of second non-volatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1500 is similar to the VMM array 1400, except that the VMM array 1500 implements bidirectional tuning, where each individual cell can be completely erased, partially programmed, and partially erased as needed to achieve the desired amount of charge on the floating gate due to the use of individual EG lines. As shown in the figure, reference arrays 1501 and 1502 convert the input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to memory cells in the row direction (through the operation of reference cells connected via diodes of multiplexer 1514). Current outputs (neurons) are in bit lines BL0-BLN, where each bit line sums all currents from non-volatile memory cells connected to that particular bit line.

[0153] Table 8 shows the operating voltages used for the VMM array 1500. The columns in the table indicate the voltage applied to the word lines for the selected cell, the word lines for the unselected cell, the bit lines for the selected cell, the bit lines for the unselected cell, the control gate for the selected cell, the control gate for the unselected cell in the same sector as the selected cell, the control gate for the unselected cell in a different sector from the selected cell, the erase gate for the selected cell, the erase gate for the unselected cell, the source line for the selected cell, and the source line for the unselected cell. The rows indicate read, erase, and program operations.

[0154] Table 8: Figure 15 Operation of VMM array 1500

[0155]

[0156] Figure 24 The diagram shows a neuronal VMM array 2400, which is particularly suitable for... Figure 2 The memory unit 210 shown serves as a synapse and component for neurons between the input layer and the next layer. In the VMM array 2400, the inputs are INPUT0...., INPUT... N At bit lines BL0,...BL respectively N The data is received and outputs OUTPUT1, OUTPUT2, OUTPUT3 and OUTPUT4 are generated on source lines SL0, SL1, SL2 and SL3 respectively.

[0157] Figure 25 This illustrates a neuronal VMM array 2500, which is particularly suitable for... Figure 2 The memory unit 210 shown serves as a synapse and component for neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0,...OUTPUT N In the bit lines BL0,…,BL N Generate above.

[0158] Figure 26 The diagram shows a neuronal VMM array 2600, which is particularly suitable for... Figure 2 The memory unit 210 shown serves as a synapse and component for neurons between the input layer and the next layer. In this example, the inputs are INPUT0,…,INPUT M On the word lines WL0, ..., WL respectively M The data is received and outputs OUTPUT0,...OUTPUT. N In the bit lines BL0,…,BL N Generate above.

[0159] Figure 27 The diagram shows a neuronal VMM array 2700, which is particularly suitable for... Figure 3 The memory unit 310 shown serves as a synapse and component for neurons between the input layer and the next layer. In this example, the inputs are INPUT0,…,INPUT M On the word lines WL0, ..., WL respectively M The data is received and outputs OUTPUT0,...OUTPUT. N In the bit lines BL0,…,BL N Generate above.

[0160] Figure 28 The diagram shows a neuronal VMM array 2800, which is particularly suitable for... Figure 4 The memory unit 410 shown serves as a synapse and component for neurons between the input layer and the next layer. In this example, the inputs are INPUT0,…,INPUT n On the vertical control grid lines CG0, ..., CG N The data is received, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0161] Figure 29The diagram shows a neuronal VMM array 2900, which is particularly suitable for... Figure 4 The memory unit 410 shown serves as a synapse and component for neurons between the input layer and the next layer. In this example, input INPUT0 is connected to INPUT... N They are received on the gates of bit line control gates 2901-1, 2901-2 to 2901-(N-1) and 2901-N, respectively, and these gates are coupled to bit lines BL0 to BL0, respectively. N Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0162] Figure 30 This illustrates a neuronal VMM array 3000, which is particularly suitable for... Figure 3 The memory unit 310 shown Figure 5 The memory cell 510 shown and Figure 7 The memory unit 710 shown serves as a synapse and component for neurons between the input layer and the next layer. In this example, the inputs are INPUT0,…,INPUT M In the word lines WL0,…,WL M The data is received and output as OUTPUT0, ..., OUTPUT. N On bit lines BL0, ..., BL respectively N Generate above.

[0163] Figure 31 The neuronal VMM array 3100 is shown, which is particularly suitable for Figure 3 The memory unit 310 shown Figure 5 The memory cell 510 shown and Figure 7 The memory unit 710 shown serves as a synapse and component for neurons between the input layer and the next layer. In this example, input INPUT0 is connected to INPUT... M In control grid lines CG0 to CG M The data is received. Outputs OUTPUT0, ..., OUTPUT N On the vertical source lines SL0, ..., SL respectively N The above is generated, where each source line SL i The source line is coupled to all memory cells in column i.

[0164] Figure 32 The diagram shows a neuronal VMM array 3200, which is particularly suitable for... Figure 3 The memory unit 310 shown Figure 5 The memory cell 510 shown and Figure 7The memory unit 710 shown serves as a synapse and component for neurons between the input layer and the next layer. In this example, input INPUT0 is connected to INPUT... M In control grid lines CG0 to CG M The data is received. Outputs OUTPUT0, ..., OUTPUT N On the vertical position lines BL0, ..., BL respectively N Generate on, where each bit line BL i Bit lines coupled to all memory cells in column i.

[0165] Long Short-Term Memory

[0166] Existing technologies include a concept known as Long Short-Term Memory (LSTM). LSTM cells are commonly used in neural networks. LSTM allows neural networks to remember information for predetermined arbitrary time intervals and use that information in subsequent operations. A typical LSTM cell includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval at which information is remembered in the LSTM. Virtual Memory Models (VMMs) are particularly useful in LSTM cells.

[0167] Figure 16 An exemplary LSTM 1600 is illustrated. This example LSTM 1600 includes cells 1601, 1602, 1603, and 1604. Cell 1601 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 1602 receives an input vector x1, an output vector (hidden state) h0 from cell 1601, and a cell state c0 from cell 1601. 0， The unit 1603 receives the input vector x2, the output vector (hidden state) h1 from unit 1602, and the cell state c1 from unit 1602, and generates the output vector h2 and the cell state vector c2. Unit 1604 receives the input vector x3, the output vector (hidden state) h2 from unit 1603, and the cell state c2 from unit 1603, and generates the output vector h3. Additional units can be used, and the four-unit LSTM is only an example.

[0168] Figure 17 Showing what can be used Figure 16 An exemplary specific implementation of LSTM cell 1700 in cells 1601, 1602, 1603 and 1604 is provided. LSTM cell 1700 receives input vector x(t), cell state vector c(t-1) from the previous cell and output vector h(t-1) from the previous cell, and generates cell state vector c(t) and output vector h(t).

[0169] LSTM unit 1700 includes sigmoid function devices 1701, 1702, and 1703, each applying a number between 0 and 1 to control the number of times each component of the input vector is allowed to pass through to the output vector. LSTM unit 1700 also includes tanh devices 1704 and 1705 for applying the hyperbolic tangent function to the input vector, multiplier devices 1706, 1707, and 1708 for multiplying two vectors together, and adder device 1709 for adding two vectors together. The output vector h(t) can be provided to the next LSTM unit in the system, or it can be accessed for other purposes.

[0170] Figure 18 LSTM unit 1800 is shown, which is an example of a specific implementation of LSTM unit 1700. For the reader's convenience, the same numbering is used in LSTM unit 1800 as in LSTM unit 1700. Sigmoid function devices 1701, 1702, and 1703, and tanh device 1704 each include multiple VMM arrays 1801 and activation circuit blocks 1802. Thus, it can be seen that VMM arrays are particularly useful in LSTM units used in certain neural network systems. Multiplier devices 1706, 1707, and 1708, and adder device 1709 are implemented digitally or analogically. Activation function block 1802 can be implemented digitally or analogously.

[0171] Alternative forms of the LSTM unit 1800 (and another example of a specific implementation of the LSTM unit 1700) are in Figure 19 As shown in [the image]. Figure 19 In this context, sigmoid function devices 1701, 1702, and 1703, as well as tanh device 1704, share the same physical hardware (VMM array 1901 and activation function block 1902) in a time-division multiplexing manner. The LSTM unit 1900 also includes a multiplier device 1903 for multiplying two vectors together, an adder device 1908 for adding two vectors together, a tanh device 1705 (which includes an activation circuit block 1902), a register 1907 for storing the value i(t) when the value i(t) is output from the sigmoid function block 1902, a register 1904 for storing the value f(t)*c(t-1) when it is output from the multiplier device 1903 via multiplexer 1910, a register 1905 for storing the value i(t)*u(t) when it is output from the multiplier device 1903 via multiplexer 1910, a register 1906 for storing the value o(t)*c~(t) when it is output from the multiplier device 1903 via multiplexer 1910, and a multiplexer 1909.

[0172] LSTM unit 1800 includes multiple sets of VMM arrays 1801 and corresponding activation function blocks 1802, while LSTM unit 1900 includes only one set of VMM arrays 1901 and activation function blocks 1902, which are used to represent multiple layers in an implementation of LSTM unit 1900. LSTM unit 1900 will require less space than LSTM unit 1800 because it only needs 1 / 4 of the space for VMMs and activation function blocks compared to LSTM unit 1800.

[0173] It is also understandable that an LSTM cell will typically consist of multiple VMM arrays, each requiring functionality provided by certain circuit blocks outside the VMM array (such as summer and activation circuit blocks, and high-voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be inefficient to some extent.

[0174] Gate control recursive unit

[0175] A simulated VMM implementation can be used in gated recurrent unit (GRU) systems. A GRU is the gated mechanism in a recurrent neural network. A GRU is similar to an LSTM, but a GRU unit typically contains fewer components than an LSTM unit.

[0176] Figure 20 An exemplary GRU 2000 is shown. This example GRU 2000 includes units 2001, 2002, 2003, and 2004. Unit 2001 receives an input vector x0 and generates an output vector h0. Unit 2002 receives an input vector x1, the output vector h0 from unit 2001, and generates an output vector h1. Unit 2003 receives an input vector x2 and the output vector (hidden state) h1 from unit 2002, and generates an output vector h2. Unit 2004 receives an input vector x3 and the output vector (hidden state) h2 from unit 2003, and generates an output vector h3. Additional units may be used, and this four-unit GRU is merely an example.

[0177] Figure 21 Showing what can be used Figure 20Exemplary specific implementations of GRU unit 2100 of units 2001, 2002, 2003, and 2004. GRU unit 2100 receives an input vector x(t) and an output vector h(t-1) from a previous GRU unit, and generates an output vector h(t). GRU unit 2100 includes sigmoid function devices 2101 and 2102, each applying a number between 0 and 1 to the components from the output vector h(t-1) and the input vector x(t). GRU unit 2100 also includes a tanh device 2103 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 2104, 2105, and 2106 for multiplying two vectors together, an adder device 2107 for adding two vectors together, and a complementary device 2108 for subtracting the input from 1 to generate the output.

[0178] Figure 22 GRU unit 2200 is shown as an example of a specific implementation of GRU unit 2100. For the reader's convenience, GRU unit 2200 uses the same numbering as GRU unit 2100. Figure 22 As shown, sigmoid function devices 2101 and 2102 and tanh device 2103 each include multiple VMM arrays 2201 and activation function blocks 2202. Therefore, it can be seen that VMM arrays are particularly useful in GRU units used in certain neural network systems. Multiplier devices 2104, 2105, and 2106, adder device 2107, and complement device 2108 are implemented digitally or analogically. Activation function blocks 2202 can be implemented digitally or analogously.

[0179] Alternative forms of GRU unit 2200 (and another example of a specific implementation of GRU unit 2300) in Figure 23 As shown in [the image]. Figure 23 In this configuration, the GRU unit 2300 utilizes a VMM array 2301 and an activation function block 2302. When this activation function block is configured as a sigmoid function, a number between 0 and 1 is applied to control the number of times each component of the input vector is allowed to reach the output vector. Figure 23In this context, sigmoid function devices 2101 and 2102 and tanh device 2103 share the same physical hardware (VMM array 2301 and activation function block 2302) in a time-division multiplexing manner. GRU unit 2300 also includes a multiplier device 2303 for multiplying two vectors together, an adder device 2305 for adding two vectors together, a complement device 2309 for subtracting the input from 1 to generate the output, a multiplexer 2304, a register 2306 for holding the value h(t-1)*r(t) when it is output from the multiplier device 2303 through the multiplexer 2304, a register 2307 for holding the value h(t-1)*z(t) when it is output from the multiplier device 2303 through the multiplexer 2304, and a register 2308 for holding the value h^(t)*(1-z(t)) when it is output from the multiplier device 2303 through the multiplexer 2304.

[0180] GRU unit 2200 includes multiple sets of VMM arrays 2201 and activation function blocks 2202, while GRU unit 2300 includes only one set of VMM arrays 2301 and activation function blocks 2302, which are used to represent multiple layers in an implementation of GRU unit 2300. GRU unit 2300 will require less space than GRU unit 2200 because GRU unit 2300 only needs 1 / 3 of its space for VMMs and activation function blocks compared to GRU unit 2200.

[0181] It is also understandable that a GRU system would typically include multiple VMM arrays, each requiring functionality provided by certain circuit blocks outside the VMM array itself (such as summer and activation circuit blocks, and high-voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be inefficient to some extent.

[0182] The input to a VMM array can be analog, binary, or digital (in which case a DAC is needed to convert the digital bits to the appropriate analog input level), and the output can be analog, binary, or digital (in which case an output ADC is needed to convert the output analog level to digital bits).

[0183] For each memory cell in the VMM array, each weight W can be implemented by a single memory cell, a differential cell, or a hybrid memory cell (the average of two cells). In the case of differential cells, two memory cells are needed to implement the weight W as a differential weight (W = W+ – W-). In the case of two hybrid memory cells, two memory cells are needed to implement the weight W as the average of two cells.

[0184] Decoding system and physical layout implementation scheme for VMM arrays

[0185] Figures 33-51 Various decoding systems and physical layouts for VMM arrays are disclosed, which are compatible with previously known decoding systems. Figures 2-7 Any of the memory cell types described or used in conjunction with other non-volatile memory cells.

[0186] Figure 33 VMM system 3300 is shown. VMM system 3300 includes VMM array 3301 (which may be based on any of the previously discussed VMM array designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100 and 3200 or other VMM designs), low-voltage row decoder 3302, high-voltage row decoder 3303, column decoder 3304, column driver 3305, control logic unit 3306, bias circuit 3307, neuron output circuit block 3308, input VMM circuit block 3309, algorithm controller 3310, high-voltage generator block 3311, analog circuit block 3315, and control logic unit 3316.

[0187] Input circuit block 3309 serves as an interface from external input to the input terminals of memory array 3301. Input circuit block 3309 may include, but is not limited to, a DAC (digital-to-analog converter), DPC (digital-to-pulse converter), APC (analog-to-pulse converter), IVC (current-to-voltage converter), AAC (analog-to-analog converter, such as a voltage-to-voltage scaler), or FAC (frequency-to-analog converter). Neuron output block 3308 serves as an interface from memory array output to an external interface (not shown). Neuron output block 3308 may include, but is not limited to, an ADC (analog-to-digital converter), APC (analog-to-pulse converter), DPC (digital-to-analog converter), IVC (current-to-voltage converter), or IFC (current-to-frequency converter). Neuron output block 3308 may include, but is not limited to, activation functions, normalization circuitry, and / or rescaling circuitry.

[0188] The low-voltage line decoder 3302 provides a bias voltage for read and program operations, and provides a decoding signal for the high-voltage line decoder 3303. The high-voltage line decoder 3303 provides a high-voltage bias signal for program and erase operations.

[0189] The algorithm controller 3310 provides control functions for bit lines during programming, verification, and erasure operations.

[0190] The high voltage generator block 3311 includes a charge pump 3312, a charge pump regulator 3313, and a high voltage generation circuit 3314 that provides multiple voltages required for various programming, erasing, programming verification, and reading operations.

[0191] Figure 34 The VMM system 3400 is shown, which is particularly suitable for use with... Figure 4 It is used with a memory cell of the type shown as memory cell 410. VMM system 3400 includes VMM arrays 3401, 3402, 3402, and 3404 (each of which may be based on any of the aforementioned VMM array designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, and 31000 or other VMM array designs); low-voltage row decoders 3405, 3406, 3407, and 3408; a shared high-voltage row decoder 3409; word lines or word input lines 3411, 3412, 3413, and 3414; bit lines 3421, 3422, 3423, and 3424; control gate line 3432; source line 3434; and erase gate line 3434. The shared high-voltage line decoder 3409 provides control gate lines 3432, source lines 3434, and erase gate lines 3434. In this arrangement, word lines 3411, 3412, 3413, and 3414, and bit lines 3421, 3422, 3423, and 3424 are parallel to each other. In one embodiment, the word lines and bit lines are arranged vertically. The control gate lines 3432, source lines 3434, and erase gate lines 3436 are parallel to each other and arranged horizontally, thus perpendicular to the word lines or word input lines 3411, 3412, 3413, and 3414, and the bit lines 3421, 3422, 3423, and 3424.

[0192] In the VMM system 3400, VMM arrays 3401, 3402, 3403, and 3404 share control gate line 3432, source line 3434, erase gate line 3436, and high-voltage row decoder 3409. However, each of the arrays has its own low-voltage row decoder, such that low-voltage row decoder 3405 is used with VMM array 3401; low-voltage row decoder 3406 is used with VMM array 3402; low-voltage row decoder 3407 is used with VMM array 3403; and low-voltage row decoder 3408 is used with VMM array 3404. Advantageous of this arrangement is that word lines 3411, 3412, 3413, and 3414 are arranged vertically, allowing word line 3411 to be routed only to VMM array 3401, word line 3412 only to VMM array 3402, word line 3413 only to VMM array 3403, and word line 3414 only to VMM array 3404. This would be highly inefficient with a conventional layout, where word lines are arranged horizontally for multiple VMM arrays sharing the same high-voltage decoder and the same high-voltage decoding lines.

[0193] Figure 35 The VMM system 3500 is shown, which is particularly suitable for use with... Figure 4 This is used with memory cells of the type shown as memory cell 410. The VMM system 3500 is similar. Figure 33 The VMM system 3500 differs from the VMM system 3300 in that it includes separate word lines and low-voltage line decoders for read and program operations.

[0194] VMM system 3500 includes VMM arrays 3501, 3502, 3503 and 3504 (each of which can be based on any of the aforementioned VMM designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100 and 3200 or other VMM array designs). The system includes: low-voltage read line decoders 3505, 3506, 3507, and 3508; a shared low-voltage programmable line decoder 3530; a shared high-voltage line decoder 3509; read word lines or word input lines 3511, 3512, 3513, and 3514; a programmable pre-decoding line line 3515; bit lines 3521, 3522, 3523, and 3524; control gate line 3532; source line 3533; and erase gate line 3535. The shared high-voltage line decoder 3509 provides control gate line 3532, source line 3533, and erase gate line 3535. In this layout, the read word lines or word input lines 3511, 3512, 3513, and 3514, the programmable pre-decoding line line 3515, and the bit lines 3521, 3522, 3523, and 3524 are parallel to each other and arranged vertically. The control gate line 3532, source line 3533, and erase gate line 3535 are parallel to each other and arranged horizontally, and therefore perpendicular to the read word lines or word input lines 3511, 3512, 3513, and 3514, the programming pre-decoding row line 3515, and the bit lines 3521, 3522, 3523, and 3524. In this VMM system 3500, the low-voltage programmable row decoder 3530 is shared across multiple VMM arrays.

[0195] In the VMM system 3500, VMM arrays 3501, 3502, 3503, and 3504 share control gate line 3532, source line 3533, erase gate line 3535, and high-voltage row decoder 3509. However, each VMM array has its own low-voltage read row decoder, such that low-voltage read row decoder 3505 is used with VMM array 3501; low-voltage read row decoder 3506 is used with VMM array 3502; low-voltage read row decoder 3507 is used with VMM array 3503; and low-voltage read row decoder 3508 is used with VMM array 3504. The advantage of this layout is that the read word lines or word input lines 3511, 3512, 3513, and 3514 are arranged vertically, so that word line 3511 can be routed only to VMM array 3501, word line 3512 only to VMM array 3502, word line 3513 only to VMM array 3503, and word line 3514 only to VMM array 3504. This would be very inefficient with a conventional layout, in which word lines are arranged horizontally for multiple arrays sharing the same high-voltage decoder and the same high-voltage decoding lines. Notably, the programming pre-decoding line 3515 can be connected to any of the VMM arrays 3501, 3502, 3503, and 3504 via a low-voltage programming line decoder 3530, allowing cells in one or more of those VMM arrays to be programmed at once.

[0196] Figure 36Additional details regarding certain aspects of the VMM system 3500 are shown, specifically details regarding low-voltage row decoders 3505, 3506, 3507, and 3508, exemplified as low-voltage row decoder 3600. The low-voltage read row decoder 3600 includes multiple switches, such as the exemplary switches shown, to selectively couple word lines to cell rows in VMM arrays 3601, 3602, 3603, and 3604, respectively. The low-voltage programmable decoder 3630 includes exemplary NAND gates 3631 and 3632, PMOS transistors 3633 and 3635, and NMOS transistors 3636 and 3636, configured as shown. NAND gates 3631 and 3632 receive the programming pre-decoding row line XP 3615 as input. During programming operations, the switch Sp (which may be a CMOS multiplexer or another type of switch) in the low-voltage read row decoders 3605, 3606, 3607, and 3608 is closed, so the programming word line Wlp0-n is coupled to the word line in the array to apply the voltage for programming. During read operations, the read word line or word input line 3611, 3612, 3613, and 3614 are selectively coupled to apply voltage to the word line terminals of one or more rows in arrays 3601, 3602, 3603, and 3604 using the Sr switch (closed) (which may be a CMOS multiplexer or another type of switch) within the low-voltage read row decoders 3605, 3606, 3607, and 3608.

[0197] Figure 37 The VMM system 3700 is shown, which is particularly suitable for use with... Figure 4The memory cells shown as type 410 are used together. The VMM system 3700 includes VMM arrays 3701, 3702, 3703, and 3704 (each of which may be based on any of the aforementioned VMM designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, and 3100 or other VMM array designs); low Voltage line decoders 3705, 3706, 3707, and 3708; local high-voltage line decoders 3709 and 3710; global high-voltage line decoder 3730; word lines 3711, 3712, 3713, and 3714; bit lines 3721, 3722, 3723, and 3724; high-voltage and / or low-voltage (HV / LV) pre-decoding lines 3732, source lines 3733, and erase gate lines 3734. The shared global high-voltage line decoder 3730 provides HV / LV pre-decoding lines 3732, source lines 3733, and erase gate lines 3734. In this layout, word lines 3711, 3712, 3713, and 3714, and bit lines 3721, 3722, 3723, and 3724 are parallel to each other and arranged in the vertical direction. HV / LV pre-decoding line 3732, source line 3733, and erase gate line 3734 are parallel to each other and arranged horizontally, and therefore perpendicular to word lines 3711, 3712, 3713, and 3714 and bit lines 3721, 3722, 3723, and 3724. HV / LV pre-decoding line 3732 is input to local high-voltage decoders 3709 and 3710. Local high-voltage decoder 3709 outputs local control gate lines for VMM arrays 3701 and 3702. Local high-voltage decoder 3710 outputs local control gate lines for VMM arrays 3703 and 3704. In another embodiment, local high-voltage decoders 3709 and 3710 may provide local source lines for VMM arrays 3701 / 3702 and VMM arrays 3703 / 3704, respectively. In another embodiment, local high-voltage decoders 3709 and 3710 may provide local erase gate lines for VMM arrays 3701 / 3702 and VMM arrays 3703 / 3704, respectively.

[0198] Here, the local high-voltage line decoder 3709 is shared by VMM arrays 3701 and 3702, and the local high-voltage line decoder 3710 is shared by VMM arrays 3703 and 3704. The global high-voltage decoder 3730 routes the high-voltage and low-voltage pre-decoding signals to local high-voltage line decoders, such as local high-voltage line decoders 3709 and 3710. Therefore, the high-voltage decoding function is divided between the global high-voltage line decoder 3730 and the local high-voltage decoders, such as local high-voltage decoders 3709 and 3710.

[0199] In the VMM system 3700, VMM arrays 3701, 3702, 3703, and 3704 share the HV / LV pre-decoding line 3732, source line 3733, erase gate line 3734, and global high-voltage line decoder 3730. However, each of the VMM arrays has its own low-voltage line decoder, such that low-voltage line decoder 3705 is used with VMM array 3701; low-voltage line decoder 3706 is used with VMM array 3702; low-voltage line decoder 3707 is used with VMM array 3703; and low-voltage line decoder 3708 is used with VMM array 3704. Advantageous to this layout is that word lines 3711, 3712, 3713, and 3714 are arranged vertically, allowing word line 3711 to be routed only to VMM array 3701, word line 3712 only to VMM array 3702, word line 3713 only to VMM array 3703, and word line 3714 only to VMM array 3704. This would be highly inefficient with a conventional layout, where word lines are arranged horizontally for multiple arrays sharing a single high-voltage decoder.

[0200] Figure 38 The VMM system 3800 is shown, which is particularly suitable for use with... Figure 4It is used with a memory cell of the type shown as memory cell 410. VMM system 3800 includes VMM arrays 3801, 3802, 3802, and 3804 (each of which may be based on any of the aforementioned VMM designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, and 3200 or other VMM array designs); low-voltage line decoders 3805, 3806, 3807, and 3808; local high-voltage line decoders 3809 and 3810; global high-voltage line decoder 3830; bit lines 3821, 3822, 3823, and 3824; control gate lines or control gate input lines 3811 and 3812; HV / LV pre-decoding line 3833; source line 3834; and erase gate line 3835. A shared global high-voltage row decoder 3830 provides HV / LV pre-decoding lines 3833, source lines 3834, and erase gate lines 3835. Local high-voltage decoders 3809 and 3810 couple control gate inputs CG 3811 and 3812 to the local control gates of VMM arrays 3801, 3802 and 3803, 3804, respectively. Low-voltage row decoders 3805, 3806, 3807, and 3808 provide local (horizontal) word lines to arrays 3801, 3802, 3803, and 3804, respectively. In this layout, control gate lines 3811 and 3812 and bit lines 3821, 3822, 3823, and 3824 are parallel to each other and arranged in the vertical direction. The source line 3834 and the erase gate line 3835 are parallel to each other and arranged in the horizontal direction, thus perpendicular to the control gate lines 3811 and 3812 and the bit lines 3821, 3822, 3823 and 3824.

[0201] As in Figure 37 In the VMM system 3700, the local high-voltage row decoder 3809 is shared by VMM arrays 3801 and 3802, and the local high-voltage row decoder 3810 is shared by VMM arrays 3803 and 3804. The global high-voltage decoder 3830 routes signals to local high-voltage row decoders, such as local high-voltage row decoders 3809 and 3810. Therefore, high-voltage decoding functionality is divided between the global high-voltage row decoder 3830 and local high-voltage decoders such as local high-voltage decoders 3809 and 3810 (which can provide local source lines and / or local erase gate lines).

[0202] In the VMM system 3800, VMM arrays 3801, 3802, 3803, and 3804 share the HV / LV pre-decoding line 3833, source line 3834, erase gate line 3835, and global high-voltage line decoder 3830. However, each of the VMM arrays has its own low-voltage line decoder, such that low-voltage line decoder 3805 is used with VMM array 3801; low-voltage line decoder 3806 is used with VMM array 3802; low-voltage line decoder 3807 is used with VMM array 3803; and low-voltage line decoder 3808 is used with VMM array 3804. An advantage of this layout is that control gate lines 3811 and 3812 (which can be read lines or input lines) are arranged vertically, such that control gate line 3811 can be routed only to VMM arrays 3801 and 3802, and control gate line 3812 can be routed only to VMM arrays 3803 and 3804. Using a conventional layout with its characters arranged horizontally would be impossible.

[0203] Figure 39 The VMM system 3900 is shown, which is particularly suitable for use with... Figure 3 The image shows memory cell 310. Figure 4 The image shows memory cell 410. Figure 5 The image shows memory cell 510 or... Figure 7 The memory cells shown as type 710 are used together. The VMM system 3900 includes VMM arrays 3901 and 3902 (each of which may be based on any of the aforementioned VMM designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, and 3200 or other VMM array designs); a low-voltage row decoder 3903 (used with arrays 3901 and 3902); a local high-voltage row decoder 3905; a global high-voltage row decoder 3904; control gate lines 3908 and 3909; and bit lines 3906 and 3907. In this layout, control gate line 3908 is used only by VMM array 3901, and control gate line 3909 is used only by VMM array 3902. Low-voltage line decoding line 3910 is used as a decoding input to the global high-voltage line decoder 3904. Global high-voltage line decoding line 3911 is used as a decoding input to the local high-voltage decoder 3905.

[0204] The local high-voltage line decoder 3905 is shared by VMM arrays 3901 and 3902. The global high-voltage decoder 3904 routes signals to local high-voltage line decoders in multiple VMM systems, such as the local high-voltage line decoder 3905 of VMM system 3900. Therefore, the high-voltage decoding function is divided between the global high-voltage line decoder 3904 and local high-voltage decoders such as the local high-voltage decoder 3905, as described above.

[0205] In the VMM system 3900, VMM arrays 3901 and 3902 share word lines (not shown), source gate lines (if present) (not shown), erase gate lines (if present) (not shown), and a global high-voltage row decoder 3904. Here, VMM arrays 3901 and 3902 share a low-voltage row decoder 3903. Advantageously, VMM arrays 3901 and 3902 do not share control gate lines, allowing each array to be accessed independently using control gate lines 3908 and 3909 respectively.

[0206] Figure 51 The VMM system 5100 is shown, which is particularly suitable for use with... Figure 4 The memory cell shown as memory cell 410 is used together. The VMM system 5100 includes VMM arrays 5101, 5102, 5103 and 5104 (each of which may be based on any of the aforementioned VMM array designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1510, 2400, 2510, 2600, 2700, 2800, 2900, 3000, 3100 and 3200 or other VMM array designs); a high-voltage decoder 5130; routing frames 5151 and 5152; input word lines 5111 and 5112, bit lines 5121, 5122, 5123 and 5124; control gate line 5132, source line 5133 and erase gate line 5134. The high-voltage decoder 5130 provides control gate lines 5132, source lines 5133, and erase gate lines 5134. Routing blocks 5151 and 5152 route the vertically received input word lines 5111 and 5112 to the horizontal operating word lines of the VMM array 5101-5104, respectively. Alternatively, routing blocks 5151 and 5152 can route the vertically received control gate input line 5132 to the horizontal operating control gate line 5132 of the VMM array.

[0207] Figure 40A low-voltage line decoder 4000 is shown, comprising a NAND gate 4001, a PMOS transistor 4002, and an NMOS transistor 4003. The NAND gate 4001 receives a line address signal 4004. The PMOS transistor 4002 is coupled to a vertical word line input 4005. The output is located on a horizontal word line 4006, which is one of many word lines coupled to a corresponding VMM array. In this example, there are a total of 16 word lines, and therefore 16 instantiations of the line decoder 4000 will exist, each instantiating one of the 16 word lines. Thus, based on the received line address signal, one word line (such as word line 4006) will output a corresponding signal (such as a voltage), and the other word lines will be set to ground.

[0208] Figure 41 The combined select / deselect word line and control gate decoder 4100 is shown, which includes, for example... Figure 40 The low-voltage row decoder includes a NAND gate 4101, a PMOS transistor 4102, an NMOS transistor 4103, a row address signal 4104, a vertical input word line 4105, and a horizontal word output line 4106 coupled to the word line of the VMM array. The combined word line and control gate decoder 4100 also includes an inverter 4107, switches 4108 and 4112, and an isolation transistor 4109, and receives a control gate input 4110CGIN0 and outputs a control gate line 4111CG0. The word line output 4106WL0 and the control gate output CG0 4111 are simultaneously selected or deselected by a decoding logic component (not shown) controlling the NAND gate 4101.

[0209] Figure 42 A bitline decoder 4200 is shown, operating on VMM arrays 4201 and 4202. The bitline decoder 4200 includes a column multiplexer 4203 (for selecting one or more bit lines for programming and verification, where verification operations are used to confirm that the cell current reaches a certain target during tuning operations (programming or erasing operations)) and a sense amplifier 4204 (for performing read operations on one or more bit lines). As shown, local bitline muxes 4201b and 4202b multiplex local array bit lines to global bit lines 4220x to couple to the column multiplexer 4203. The sense amplifier includes an ADC or other device. Therefore, the bitline decoder 4200 is shared across multiple arrays.

[0210] Figure 43The diagram illustrates a VMM system 4300, which includes VMM arrays 4301, 4302, 4303, and 4304; low-voltage row decoders 4305 and 4307; local high-voltage row decoders 4306 and 4308; a global high-voltage row decoder 4309; digital bus inputs QIN[7:0] 4311 and 4312 (here they are inputs to the VMM arrays); and bit lines 4321, 4322, 4323, and 4324. Each low-voltage row decoder, such as low-voltage row decoder 4305, includes a circuit block row decoder 4335 for each word line, such as exemplary data input block 4331 (which may consist of 8 latches or registers) and block 4332 (which may include data-to-voltage converter circuitry or data-to-pulse converter circuitry), which outputs a signal 4333 on the word line. Thus, the input to this low-voltage row decoder is a digital bus QIN[7:0] with appropriate control logic components. For each circuit block of the line decoder 4335, the digital inputs QIN[7:0]4311 and 4312 are latched appropriately, such as by means of a synchronous clock device and method (such as by means of a serial-to-parallel clock interface).

[0211] Figure 44 A neural network array input-output bus multiplexer 4400 is shown, which receives outputs from a VMM array (such as an ADC) and provides those outputs in groups to the input blocks of other VMM arrays (such as a DAC or DPC) in a multiplexed manner. In the example shown, the inputs to the input-output bus multiplexer 4400 comprise 2048 bits (256 groups, NEU0...NEU255, 8 bits per group), and the input-output bus multiplexer 4400 provides those bits in 64 distinct groups (32 bits per group), where it is multiplexed between different groups, such as by using time-division multiplexing (where it provides one group of 32 bits at any given time). Control logic unit 4401 generates control signals 4402 to control the input-output bus multiplexer 4400.

[0212] Figure 45A and Figure 45B An exemplary layout of a VMM array is shown, in which word lines are arranged horizontally ( Figure 45A ) and in a vertical manner ( Figure 45B Such as in Figure 34 or Figure 35 (Chinese) layout.

[0213] Figure 46 An exemplary layout of a VMM array is shown, in which word lines are arranged vertically (such as in...). Figure 34 or Figure 35 (in the middle). However, in this layout, two word lines (such as word lines 4601 and 4602) can occupy the same column but access different rows in the array (due to the gap between them).

[0214] Figure 47 A VMM high-voltage decoding circuit is shown, which includes components adapted to work with... Figure 2 The memory cells of the type shown are used together with word line decoder circuit 4701, source line decoder circuit 4704, and high voltage level shifter 4708.

[0215] The word line decoder circuit 4701 includes a PMOS select transistor 4702 (controlled by the signal HVO_B) and an NMOS deselect transistor 4703 (controlled by the signal HVO_B) configured as shown.

[0216] The source line decoder circuit 4704 includes an NMOS monitoring transistor 4705 (controlled by signal HVO), a drive transistor 4706 (controlled by signal HVO), and a deselect transistor 4707 (controlled by signal HVO_B) configured as shown.

[0217] The high-voltage level shifter 4708 receives the enable signal EN and outputs a high-voltage signal HV and its complementary signal HVO_B.

[0218] Figure 48 A VMM high-voltage decoding circuit is shown, which includes components adapted to work with... Figure 3 The erase gate decoder circuit 4801, control gate decoder circuit 4804, source line decoder circuit 4807, and high voltage level shifter 4811 are used together with memory cells of the type shown.

[0219] The erase gate decoder circuit 4801 and the control gate decoder circuit 4804 are used with Figure 47 It uses the same design as the word line decoder circuit 4701.

[0220] Source line decoder circuit 4807 is used with Figure 47 It uses the same design as the source-line decoder circuit 4704.

[0221] High voltage level shifter 4811 is used in Figure 47 It has the same design as the high-voltage level shifter 4708 in the series.

[0222] Figure 49A word line driver 4900 is shown. The word line driver 4900 selects word lines (such as the exemplary word lines WL0, WL1, WL2, and WL3 shown here) and provides a bias voltage to those word lines. Each word line is attached to a select isolation transistor, such as select transistor 4901, controlled by control line 4902. The select transistor (such as select transistor 4901) isolates the high voltages (e.g., 8-12V) used during erase operations from the word line decoding transistors, which can be implemented using I / O transistors operating at low voltages (e.g., 1.8V, 3.3V). Here, during any operation, control line 4902 is activated, and all select transistors similar to select transistor 4901 are turned on. An exemplary bias transistor 4903 (part of the word line decoding circuitry) selectively couples word lines to a first bias voltage (such as 3V), and an exemplary bias transistor 4904 (part of the word line decoding circuitry) selectively couples word lines to a second bias voltage (below the first bias voltage, including ground, a bias between ground and the first bias voltage, or a negative bias to reduce leakage from unused memory lines). During an ANN (Analog Neural Network) read operation, all used word lines are selected and bound to the first bias voltage. All unused word lines are bound to the second bias voltage. During other operations, such as programming operations, only one word line is selected and the other word lines are bound to the second bias voltage, which may be negatively biased (e.g., -0.3V to -0.5V or greater) to reduce array leakage.

[0223] Bias transistors 4903 and 4904 are coupled to the output of stage 4906 of shift register 4905. Shift register 4905 allows each row to be controlled independently according to the input data pattern (loaded at the start of the ANN operation).

[0224] Figure 50 Word line driver 5000 is shown. Word line driver 5000 is similar to word line driver 4900, except that each select transistor is further coupled to a capacitor (such as capacitor 5001). Capacitor 5001 can provide pre-charge or bias to the word line at the start of operation, enabled by transistor 5002 to sample the voltage on line 5003. Capacitor 5001 is used for sample-and-hold (S / H) of the input voltage for each word line. Transistors 5004 and 5005 are turned off during ANN operation (array current adder and activation function) of the VMM array, meaning that the voltage on S / H capacitor 5001 will be used as the (floating) voltage source for the corresponding word line. Alternatively, capacitor 5001 can be provided by word line capacitance from the VMM array (or as control gate capacitance if the input is on the control gate).

[0225] It should be noted that, as used herein, the terms “above” and “on” both encompass “directly on” (without intermediate material, elements, or space between) and “indirectly on” (with intermediate material, elements, or space between). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, elements, or space between) and “indirectly adjacent” (with intermediate material, elements, or space between), “mounted to” includes “directly mounted to” (without intermediate material, elements, or space between) and “indirectly mounted to” (with intermediate material, elements, or space between), and “electrically coupled to” includes “directly electrically coupled to” (without intermediate material or elements electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or elements electrically connecting the elements together). For example, forming an element “above a substrate” can include forming an element directly on the substrate without intermediate material / elements between them, and forming an element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. A simulated neural memory system, comprising: Multiple vector-matrix multiplication arrays, each array comprising non-volatile memory cells organized into rows and columns; Multiple low-voltage row decoders, each low-voltage row decoder providing row decoder functionality for one of the multiple vector-matrix multiplication arrays; and Multiple global high-voltage row decoders, each of which is shared by two vector-matrix multiplication arrays among the multiple vector-matrix multiplication arrays, and provides high-voltage signals to two low-voltage row decoders among the multiple low-voltage row decoders.

2. The system according to claim 1, wherein the non-volatile memory cell is a split-gate flash memory cell.

3. The system according to claim 1, wherein the non-volatile memory cell is a stacked gate flash memory cell.

4. A simulated neural memory system, comprising: Vector-matrix multiplication array, comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell includes a control gate terminal and a word line terminal; Multiple word lines, each of which is coupled to the word line terminal of a row of memory cells; Multiple control gate lines, each of which is coupled to the control gate terminal of a row of memory cells; and Multiple decoders, each of which is selectively coupled to one or both of the multiple word lines used to provide line decoder functionality and the multiple control gate lines used to provide control gate decoder functionality.

5. The system of claim 4, wherein the decoder is selectively coupled to the plurality of word lines, and wherein the line decoder function can be selected or deselected.

6. The system of claim 4, wherein the decoder is selectively coupled to the control gate line, and wherein the control gate decoder function can be selected or deselected.

7. The system of claim 5, wherein the decoder is further selectively coupled to the control gate line, and wherein the control gate decoder function can be selected or deselected.

8. The system of claim 4, wherein the non-volatile memory cell is a split-gate flash memory cell.

9. The system of claim 4, wherein the non-volatile memory cell is a stacked gate flash memory cell.

10. A simulated neural memory system, comprising: Vector-matrix multiplication array, comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell includes a bit line terminal, a source line terminal, a control gate terminal, and a word line terminal; Multiple bit lines, each of which is coupled to a bit line terminal of a column of memory cells; Multiple word lines, each of which is coupled to the word line terminal of a row of memory cells; Multiple control gate lines, each of which is coupled to the control gate terminal of a row of memory cells; Multiple source lines, each of which is coupled to the source line terminals of two rows of memory cells; An output block, the output block being coupled to the plurality of bit lines; An input block, the input block being coupled to the plurality of word lines, the plurality of control gate lines, or the plurality of source lines; and A multiplexer for receiving bits from the output block and, in response to a control signal, providing a portion of the bits to the input block or to the input block of another vector-matrix multiplication array.

11. The system of claim 10, wherein the non-volatile memory cell is a split-gate flash memory cell.

12. The system of claim 10, wherein the non-volatile memory cell is a stacked gate flash memory cell.

13. The system of claim 10, wherein the multiplexer is a time-division multiplexer.

14. A simulated neural memory system, comprising: Vector-matrix multiplication array, comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell includes a bit line terminal, a source line terminal, and a word line terminal; Multiple bit lines, each of which is coupled to a bit line terminal of a column of memory cells; Multiple word lines, each of which is coupled to the word line terminal of a row of memory cells via one or more routing blocks; and Multiple source lines, each of which is coupled to the source line terminals of two rows of memory cells; The word lines are parallel to the bit lines and perpendicular to the source lines. and The one or more routing blocks therein couple the plurality of word lines to the word line terminals of a row of memory cells, wherein the row is arranged in a direction perpendicular to the plurality of word lines.

15. The system of claim 14, wherein the non-volatile memory cell is a split-gate flash memory cell.

16. The system of claim 14, wherein the non-volatile memory cell is a stacked gate flash memory cell.

17. A simulated neural memory system, comprising: Multiple global bit lines; A plurality of sense amplifiers, each of which is coupled to one of the plurality of global bit lines; A column multiplexer, coupled to the plurality of global bit lines, is used to select one or more of the plurality of global bit lines for programming and verification operations; and Multiple vector-matrix multiplication arrays, each vector-matrix multiplication array comprising: A non-volatile memory cell array, the non-volatile memory cell array being organized into rows and columns, each memory cell including bit line terminals; Multiple local bit lines, each of which is coupled to the bit line terminal of a corresponding column memory cell in the array; and Multiple multiplexers are used to couple the multiple local bit lines to the multiple global bit lines; The column multiplexer and the plurality of sense amplifiers are shared by the plurality of vector-matrix multiplication arrays.

18. The system of claim 17, wherein the non-volatile memory cell is a split-gate flash memory cell.

19. The system of claim 17, wherein the non-volatile memory cell is a stacked gate flash memory cell.

20. The system of claim 17, wherein the sensing amplifier is an analog-to-digital converter.

21. A simulated neural memory system, comprising: A first vector-matrix multiplication array, comprising an array of non-volatile memory cells organized into rows and columns, each memory cell including a bit line terminal and a control gate terminal; The second vector-matrix multiplication array includes an array of non-volatile memory cells organized into rows and columns, each memory cell including bit line terminals, word line terminals and control gate terminals; A high-voltage row decoder, the high-voltage row decoder being used to apply a high voltage to the word line terminals of cells in selected rows of the first vector-matrix multiplication array and selected rows of the second vector-matrix multiplication array; The first set of control gate lines, each of which is coupled to the control gate terminal of a row cell in the first vector-matrix multiplication array, and is not coupled to the second vector-matrix multiplication array; and The second set of control gate lines, each of which is coupled to the control gate terminal of a row cell in the second vector-matrix multiplication array, and is not coupled to the first vector-matrix multiplication array.

22. The system of claim 21, wherein the non-volatile memory cell is a split-gate flash memory cell.

23. The system of claim 21, wherein the non-volatile memory cell is a stacked gate flash memory cell.

24. A simulated neural memory system, comprising: Multiple vector-matrix multiplication arrays, each vector-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell includes word line terminals; Multiple read row decoders, each coupled to one of the multiple vector-matrix multiplication arrays, are used to apply voltage to one or more selected rows during a read operation; A shared programming row decoder, coupled to all of the plurality of vector-matrix multiplication arrays, is used to apply voltage to one or more selected rows of one or more of the vector-matrix multiplication arrays during programming operations.

25. The system of claim 24, wherein the non-volatile memory cell is a split-gate flash memory cell.

26. The system of claim 24, wherein the non-volatile memory cell is a stacked gate flash memory cell.

27. A simulated neural memory system, comprising: Multiple vector-matrix multiplication arrays, each array comprising non-volatile memory cells organized into rows and columns; Multiple low-voltage row decoders, each low-voltage row decoder providing row decoder functionality for one of the multiple vector-matrix multiplication arrays; and A high-voltage row decoder, which is shared by the plurality of vector-matrix multiplication arrays and provides a high-voltage signal to one or more terminals of one or more non-volatile memory cells in the array.

28. The system of claim 27, wherein the non-volatile memory cell is a split-gate flash memory cell.

29. The system of claim 27, wherein the non-volatile memory cell is a stacked gate flash memory cell.

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