Power supply circuit, memory device and operation method thereof, and memory system

Abstract

The embodiment of the invention discloses a power supply circuit, a memory device and an operation method thereof, the power supply circuit comprises a voltage selection circuit, the first end of the voltage selection circuit is used for accessing at least two different voltages, and the second end of the voltage selection circuit is used for accessing a first control signal; the voltage selection circuit is configured to: select one of at least two different voltages according to a first control signal; the reference voltage is output according to the selected voltage; the first end of the comparator is coupled with the third end of the voltage selection circuit, the second end of the comparator is coupled with the second end of the voltage generation circuit, and the comparator is configured to compare the reference voltage provided by the third end of the voltage selection circuit with the feedback voltage provided by the second end of the voltage generation circuit and output a second control signal according to a comparison result; the first end of the voltage generating circuit is coupled with the third end of the comparator, and the voltage generating circuit is configured to receive the second control signal and output the power supply voltage required by the load.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a power supply circuit, a memory device, an operating method thereof, and a memory system. Background Technology

[0002] Memory devices are storage devices used to preserve information in modern information technology. Some semiconductor memories, including both non-volatile and volatile memories, have gradually become mainstream products in the memory market due to their high storage density, controllable production costs, suitable erasure speeds, and retention characteristics. However, as the demands on storage devices continue to increase, there is still much room for improvement in memory devices and their systems. Summary of the Invention

[0003] According to some aspects of embodiments of this disclosure, a power supply circuit is provided, comprising: a voltage selection circuit, a first terminal of which is used to receive at least two different voltages, and a second terminal of which is used to receive a first control signal; the voltage selection circuit is configured to: select one of the at least two different voltages according to the first control signal; and output a reference voltage according to the selected voltage; a comparator, a first terminal of which is coupled to a third terminal of the voltage selection circuit, and a second terminal of which is coupled to a second terminal of a voltage generating circuit, and is configured to: compare the reference voltage provided by the third terminal of the voltage selection circuit with a feedback voltage provided by the second terminal of the voltage generating circuit, and output a second control signal according to the comparison result; the first terminal of the voltage generating circuit is coupled to the third terminal of the comparator and is configured to: receive the second control signal and output a power supply voltage required by the load.

[0004] In some embodiments, the first control signal includes a first sub-control signal and a second sub-control signal, and the voltage selection circuit includes: a first sub-selection circuit, the first sub-selection circuit including: a first transistor, the first terminal and the second terminal of the first transistor being respectively connected to a first voltage and a first sub-control signal; and a second transistor, the first terminal and the second terminal of the second transistor being respectively connected to a second voltage and a second sub-control signal.

[0005] In some embodiments, the voltage selection circuit further includes a second sub-selection circuit, the second sub-selection circuit including a first resistor and a second resistor connected in series, the third terminal of the first transistor being coupled to the first terminal of the comparator through the first resistor and the second resistor connected in series; the third terminal of the second transistor being coupled to the first terminal of the comparator through the first resistor.

[0006] In some embodiments, the second sub-selection circuit further includes: a first switch and a second switch; a first terminal of the second resistor is coupled to a first terminal of the first resistor, the first switch is coupled between a second terminal of the second resistor and a first terminal of the comparator; the second switch is coupled between a first terminal of the second resistor and a first terminal of the comparator; wherein the first switch and the second switch are configured such that: when a first sub-control signal is applied to the second terminal of the first transistor and the transistor is turned on, the first switch is closed and the second switch is open; when a second sub-control signal is applied to the second terminal of the second transistor and the transistor is turned on, the second switch is closed and the first switch is open.

[0007] In some embodiments, the second sub-selection circuit further includes an adjustable resistor, one end of which is coupled to the second end of the second resistor, and the other end is grounded.

[0008] In some embodiments, the power supply circuit further includes: an enable circuit, including a first inverter and a second inverter; a first terminal of the first inverter is connected to a control level, and a second terminal of the first inverter is coupled to the first terminal of the second inverter; the second terminal of the first inverter outputs the first sub-control signal; and the second terminal of the second inverter outputs the second sub-control signal.

[0009] In some embodiments, the voltage generating circuit includes: a control circuit, a first terminal of which is coupled to a third terminal of the comparator, the control circuit being configured to generate and output a third control signal based on a second control signal output by the comparator; a boost circuit, a first terminal of which is coupled to a second terminal of the control circuit; the boost circuit being configured to increase the voltage based on the third control signal to generate and output the supply voltage; and a voltage divider circuit, one terminal of which is coupled to the second terminal of the boost circuit, and the other terminal of which is coupled to the second terminal of the comparator; wherein the supply voltage, after passing through the voltage divider circuit, generates a feedback voltage that is connected to the second terminal of the comparator.

[0010] In some embodiments, the control circuit includes: a clock generating circuit, a first terminal of which is coupled to a third terminal of the comparator; the clock generating circuit is configured to generate and output a pulse control signal based on the second control signal output by the comparator; and a clock driving circuit, coupled to a second terminal of the clock generating circuit; the clock driving circuit is configured to generate and output the third control signal based on the pulse control signal.

[0011] In some embodiments, the boost circuit includes a charge pump circuit.

[0012] According to some aspects of embodiments of this disclosure, a memory device is provided, including a voltage generator with a power supply circuit, the power supply circuit including: a voltage selection circuit, a first terminal of the voltage selection circuit being used to receive at least two different voltages, and a second terminal of the voltage selection circuit being used to receive a first control signal; the voltage selection circuit being configured to: select one of the at least two different voltages according to the first control signal; and output a reference voltage according to the selected voltage; a comparator, a first terminal of the comparator being coupled to a third terminal of the voltage selection circuit, a second terminal of the comparator being coupled to a second terminal of a voltage generation circuit, and being configured to: compare the reference voltage provided by the third terminal of the voltage selection circuit with a feedback voltage provided by the second terminal of the voltage generation circuit, and output a second control signal according to the comparison result; the first terminal of the voltage generation circuit being coupled to the third terminal of the comparator and being configured to: receive the second control signal and output a power supply voltage required by a load.

[0013] In some embodiments, the first control signal includes a first sub-control signal and a second sub-control signal, and the voltage selection circuit includes: a first sub-selection circuit, the first sub-selection circuit including: a first transistor, the first terminal and the second terminal of the first transistor being respectively connected to a first voltage and a first sub-control signal; and a second transistor, the first terminal and the second terminal of the second transistor being respectively connected to a second voltage and a second sub-control signal.

[0014] In some embodiments, the voltage selection circuit further includes a second sub-selection circuit, the second sub-selection circuit including a first resistor and a second resistor connected in series, the third terminal of the first transistor being coupled to the first terminal of the comparator through the first resistor and the second resistor connected in series; the third terminal of the second transistor being coupled to the first terminal of the comparator through the first resistor.

[0015] In some embodiments, the second sub-selection circuit further includes: a first switch and a second switch; a first end of the second resistor is coupled to one end of the first resistor, the first switch is coupled between a second end of the second resistor and a first end of the comparator; the second switch is coupled between a first end of the second resistor and a first end of the comparator; wherein the first switch and the second switch are configured such that: when a first control signal is applied to the second end of the first transistor and the transistor is turned on, the first switch closes and the second switch opens; when a second control signal is applied to the second end of the second transistor and the transistor is turned on, the second switch closes and the first switch opens.

[0016] In some embodiments, the second sub-selection circuit further includes an adjustable resistor, one end of which is coupled to the second end of the second resistor, and the other end is grounded.

[0017] In some embodiments, the power supply circuit further includes: an enable circuit, including a first inverter and a second inverter; a first terminal of the first inverter is connected to a control level, and a second terminal of the first inverter is coupled to the first terminal of the second inverter; the second terminal of the first inverter outputs the first sub-control signal; and the second terminal of the second inverter outputs the second sub-control signal.

[0018] In some embodiments, the first voltage is an external power supply voltage; the voltage selection circuit is configured to: in response to a first mode requirement of the memory device, the second terminal of the first transistor is connected to a low-level first sub-control signal, and the first switch is closed; the second terminal of the second transistor is connected to a high-level second sub-control signal, and the second switch is open; in response to a second mode requirement of the memory device, the second terminal of the second transistor is connected to a low-level second sub-control signal, and the second switch is closed; the second terminal of the first transistor is connected to a high-level first sub-control signal, and the first switch is open.

[0019] In some embodiments, the voltage generating circuit includes: a control circuit, a first terminal of which is coupled to a third terminal of the comparator, the control circuit being configured to generate and output a third control signal based on a second control signal output by the comparator; a boost circuit, a first terminal of which is coupled to a second terminal of the control circuit; the boost circuit being configured to increase the voltage based on the third control signal to generate and output the supply voltage; and a voltage divider circuit, one terminal of which is coupled to the second terminal of the boost circuit, and the other terminal of which is coupled to the second terminal of the comparator; wherein the supply voltage, after passing through the voltage divider circuit, generates a feedback voltage that is connected to the second terminal of the comparator.

[0020] In some embodiments, the control circuit includes: a clock generating circuit, a first terminal of which is coupled to a third terminal of the comparator; the clock generating circuit is configured to generate and output a pulse control signal based on the second control signal output by the comparator; and a clock driving circuit, coupled to a second terminal of the clock generating circuit; the clock driving circuit is configured to generate and output the third control signal based on the pulse control signal.

[0021] In some embodiments, the boost circuit includes a charge pump circuit.

[0022] According to some aspects of embodiments of this disclosure, a memory system is provided, including: the memory device; and a memory controller coupled to and controlling the memory device.

[0023] According to some aspects of embodiments of the present disclosure, a method of operating a memory device is provided, comprising: in response to a mode requirement of the memory device, inputting a first control signal to a voltage selection circuit in a power supply circuit of the memory device, such that the voltage selection circuit selects one of the input voltages and outputs a reference voltage according to the selected voltage; comparing a feedback voltage provided by a voltage generation circuit with the reference voltage, and outputting a second control signal according to the comparison result; and causing the voltage generation circuit to output a power supply voltage required by the load according to the second control signal.

[0024] This disclosure provides a power supply circuit, including a voltage selection circuit. A first terminal of the voltage selection circuit is used to receive at least two different voltages, and a second terminal is used to receive a first control signal. The circuit selects one of the two different voltages based on the first control signal and outputs a reference voltage based on the selected voltage. A comparator compares the reference voltage provided by the third terminal of the voltage selection circuit with the feedback voltage provided by the second terminal of a voltage generator circuit, and outputs a second control signal based on the comparison result. The voltage generator circuit receives the second control signal and outputs the power supply voltage required by the load. The voltage generator circuit receives the second control signal to output the power supply voltage of the load and the feedback voltage. After the feedback voltage is boosted to a target set value, the level of the second control signal of the comparator changes. Upon receiving the second control signal with the changed level, the voltage generator stops increasing the voltage and maintains the voltage output. This allows the load power supply voltage output by the voltage generator circuit to be boosted by a multiple of the input voltage of the voltage selection circuit. The output voltage of the voltage generator circuit can be characterized or adjusted by the input voltage value of the voltage selection circuit, facilitating real-time adjustment of the output voltage of the voltage generator circuit. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of an exemplary electronic system shown according to exemplary embodiments of the present disclosure;

[0026] Figure 2 This is a schematic diagram of an exemplary memory card according to an embodiment of the present disclosure;

[0027] Figure 3 This is a schematic diagram of an exemplary solid-state drive according to an embodiment of the present disclosure;

[0028] Figure 4 This is a schematic diagram of an exemplary storage cell array according to an embodiment of the present disclosure;

[0029] Figures 5 to 7 This is a schematic diagram of an exemplary electronic system shown according to embodiments of the present disclosure;

[0030] Figure 8 This is a schematic diagram of an exemplary aging test voltage according to an embodiment of the present disclosure;

[0031] Figure 9 and Figure 10 This is a schematic diagram of an exemplary power supply circuit shown according to an embodiment of the present disclosure;

[0032] Figure 11 This is a schematic diagram of an exemplary enable circuit shown according to an embodiment of the present disclosure;

[0033] Figure 12 This is a schematic diagram illustrating an exemplary operating mode of a power supply circuit according to an embodiment of this disclosure;

[0034] Figure 13 This is a schematic diagram of another exemplary aging test voltage according to an embodiment of the present disclosure;

[0035] Figure 14 This is a schematic diagram of an exemplary control circuit according to an embodiment of the present disclosure;

[0036] Figure 15 This is a schematic diagram of an exemplary pulse control signal according to an embodiment of the present disclosure;

[0037] Figure 16 This is a schematic diagram illustrating an operation method of a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0038] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0039] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0040] It should be understood that when an element or layer is referred to as "on," "adjacent to," "coupled to," "linked to," or "connected to" other elements or layers, it may be directly on, adjacent to, coupled to, or linked to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly coupled to," or "directly linked to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part. When a second element, component, region, layer, or portion is discussed, it does not imply that a first element, component, region, layer, or portion necessarily exists in this disclosure.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0043] The memory devices of this disclosure are explained and illustrated using NAND (Not-And) type memory and Dynamic Random Access Memory (DRAM) as examples. Other types of memory may also be included in the memory devices of this disclosure.

[0044] Figure 1 A block diagram of an exemplary electronic system 100 having a memory device according to some aspects of this disclosure is shown. Electronic system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, electronic system 100 may include host 108 and memory system 102, the memory system 102 having one or more memory devices 104 and memory controller 106. Host 108 may be a processor of electronic device (e.g., central processing unit (CPU)) or system-on-a-chip (SoC) (e.g., application processor (AP)). Host 108 may be configured to send data to or receive data from memory device 104. Memory device 104 may be NAND flash memory, and memory system 102 may also include DRAM, which acts as a data cache for caching data such as logical address-physical address mapping tables. Memory controller 106 also includes a cache controller for controlling the reading, writing, and refreshing of DRAM.

[0045] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0046] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0047] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2 In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 3 In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0048] In some embodiments, the memory device may include DRAM memory, and the DRAM memory cell array may be as follows: Figure 4 The example memory device or DRAM memory cell array is applicable to Double Data Rate Synchronous Dynamic Random Access Memory (DRAM) using DDR4 memory specifications, DDR5 memory specifications, and Low Power Double Data Rate DRAM using LPDDR5 memory specifications. In DRAM, the memory array can be arranged in rows and columns, allowing memory cells to be addressed by specifying the rows and columns of the array. The memory array includes multiple word lines and multiple bit lines. Word lines and bit lines intersect; selecting a memory cell at the intersection of a selected word line and a selected bit line selects it for read, write, or refresh operations. For example... Figure 4 As shown, the memory array may include multiple word lines WLn, WLn+1, WLn-1, and WLn-2, ​​and multiple bit lines BLn, BLn+1, BLn-1, and BLn-2, ​​with word lines and bit lines intersecting. Memory cells in the memory array may include capacitors and transistors; each memory cell may include one transistor and one capacitor. Word lines may also be conductive structures such as gate layers, serving as the gate of a transistor. One controlled terminal (source) of the transistor is coupled to one electrode of the capacitor, and the other controlled terminal (drain) of the transistor is coupled to the bit line. The other electrode of the capacitor may be grounded or have another voltage (such as Vdd / 2) applied to it. Figure 4 As shown, the memory cell array is arranged in an x-row, y-column configuration, with rows and columns that are either perpendicular or not. The bit lines can extend parallel to the x-direction or at an angle to it, and the word lines can extend parallel to the y-direction or at an angle to it. The orthographic projection of the word line onto the xoy plane is perpendicular to the orthographic projection of the bit line onto the xoy plane, or not perpendicular but at an angle; this embodiment does not impose limitations on this. During read or write operations, a word line selection signal can be used to select the corresponding word line, and a column selection signal can be used to select the corresponding bit line. Simultaneous selection of the word line and bit line allows location of the selected memory cell. At this time, the transistor of the selected memory cell is turned on due to the operating voltage applied to the word line, thereby enabling read, write, or refresh operations on the selected memory cell. In some embodiments, the capacitor can be replaced with other memory structures, including but not limited to: phase-change memory structures, resistive switching memory structures, or magnetic switching memory structures. For example, the capacitor represents logical 1 and 0 by the amount of charge stored within it, or the high and low voltage difference across the capacitor. The voltage signal on the word line is applied to the gate to control the transistor to turn on or off, thereby selecting or deselecting the capacitor. Then, the data information stored in the capacitor is read through the bit line, or the data is written into the capacitor for storage through the bit line.

[0049] In some embodiments, the memory device 104 includes DRAM, or a package structure formed by stacking multiple DRAMs, such as an HBM or HMC package structure. A memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104 to perform read, write, or refresh operations. The host 108 can be configured to send data to or receive data from the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. The memory system 102 can serve as memory for the host 108 in the electronic system 100 or as a cache for the electronic system 100. In some specific examples, the memory system 102 can be used in conjunction with a solid-state drive (SSD) to improve read and write speeds. Currently, high-end SSD products often embed DRAM to improve product performance and random read / write speeds. For example, during file writing, especially small file writing, small files are processed by DRAM before being stored in flash memory, making the SSD storage more efficient and faster. Flash memory includes non-volatile memory, including but not limited to 2D NAND memory or 3D NAND memory.

[0050] In other embodiments, reference is made to Figure 5 As shown, the electronic system 100 may consist only of a host 108 and a memory device 104 coupled thereto. The controller for controlling the memory device 104 may be located inside the host 108, such as a memory controller integrated within a central processing unit (CPU), or a southbridge or northbridge chip integrated into the motherboard of the electronic system 100. The memory device 104 may include, but is not limited to: DDR4 memory, DDR5 memory (double data rate synchronous dynamic random access memory), and low-power LPDDR5 memory (double data rate synchronous dynamic random access memory).

[0051] In some embodiments, reference Figure 6 The illustrated electronic system 100 example includes a memory controller 701, and a host CPU 707 and flash memory 706 coupled thereto, the flash memory 706 including NAND memory. This disclosure embodiment Figure 5The memory device 104 in the figure may include the DRAM 708 shown in the figure. The controller controlling the memory device 104 may be the memory controller integrated into the host CPU 707 to control the write, read, and refresh operations of the DRAM 708. The host CPU 707 and the DRAM 708 can be coupled and exchange data through a PCIe interface. The memory controller 701 and the flash memory 706 can constitute a separate memory system, such as an SSD or a memory card. The memory controller 701 may be an SSD controller. The memory controller 701 may include a CPU 702 (control unit), which can receive commands from the host CPU 707 and control components such as the host interface controller 704, the flash memory controller 703, and the cache 705. The flash memory controller 703 can control the back-end interface to exchange data with the flash memory 706 and can perform data encoding / decoding and ECC operations. The host interface controller 704 controls the front-end interface to exchange data with the host CPU 707. The host interface controller 704 can adapt to protocols such as SATA, PCIe, and SAS. The register 705 can cache a portion of the logical address-physical address mapping table, while another portion can be stored in the flash memory 706, with the physical address corresponding to the physical address in the flash memory 706. The register 705 may include, but is not limited to, static random access memory (SRAM), phase-change memory (PCM), etc. For example, the memory controller 701 and the host CPU 707 can use DRAM 708 as a data intermediary or data buffer, and exchange data through DRAM 708.

[0052] In some other embodiments, memory device 104 may be DRAM 710, see reference 1. Figure 7 The illustrated electronic system 100 example includes a memory controller 701 that may include a cache controller 709. The cache controller 710 may be a DRAM controller that controls write, read, and refresh operations of the DRAM 710. The DRAM 710 may cache logical addresses and physical addresses. Figure 1 The memory device 104 may include Figure 7 The DRAM 710 and memory controller 102 can be memory controller 701 with integrated cache controller 709. The memory controller 701, flash memory 706, and DRAM 710 can constitute memory system 102 or be part of memory system 102. Memory system 102 can be an SSD or a memory card, etc. In some embodiments, Figure 7The memory system shown may include a memory controller 701 with an integrated cache controller 709, and memory devices 104_A and B coupled to the memory controller 701. Memory device 104_A may be DRAM 710, and memory device 104_B may be NAND flash memory 706. The memory controller 701 controls the memory devices.

[0053] For memory device 104, memory controller 106, or memory system 102, various operational speed tests, calibration tests of various operating parameters, and burn-in tests can be performed during the factory testing phase. Burn-in tests for devices or chips can include electrical burn-in tests, thermal burn-in tests, and radiation burn-in tests. Electrical burn-in tests simulate the aging process of a chip after long-term use by increasing the time, voltage, or current applied to the chip. This test can detect potential performance degradation and failures that may occur after prolonged use, and further optimize the chip's reliability design. Similar to electrical burn-in tests and other electrical tests, a test voltage can be applied to the device. This test voltage differs from the device's operating voltage. The voltage range of the test voltage includes the device's operating voltage range, and the test range can be larger than the operating voltage range to simulate voltage fluctuations under various environmental and operating conditions, fully testing the device's stability.

[0054] When testing a device, an external power supply voltage is connected to the device's power supply circuit or module to power the device. The test voltage is changed or maintained according to relevant test standards, and relevant test data is collected to characterize the device's test results. For some test items, an operating voltage can be provided to the device under test, and the voltage generator or voltage generator inside the device under test can generate the relevant test voltage, without the need for an external power supply to provide an additional test voltage. Examples include test items such as the read rate and write rate of memory device 104. For other test items, an external test voltage can be used to test the device.

[0055] In some embodiments, taking the electrical aging test (burn-in mode) of memory device 104 or memory device as an example, the voltage application curve is as follows: Figure 8The example uses voltages VPP, Vneg, and Vbb inside memory device 104 as examples. The specific voltage range is not limited; different memory devices 104 will have different voltages. Voltages VPP, Vneg, and Vbb can be generated by a voltage generator inside memory device 104 to power different components. Taking voltage VPP as an example, under normal operating conditions of memory device 104, this operating condition can be called user mode. The voltage can be increased within a certain voltage range, with a maximum voltage of the default voltage. After reaching the default voltage, the voltage value stabilizes and no longer increases. To simulate the situation where the internal voltage may increase due to prolonged use of memory device 104 leading to increased internal resistance, interference, or other potential peak power consumption, during aging tests, the VPP voltage can be increased to 1.6 times or other multiples of the default voltage. The aging test voltages for other voltages Vneg and Vbb can also be 1.6 times or other multiples of their respective maximum voltages under normal operating conditions.

[0056] In some embodiments, taking VPP as an example, during aging tests on memory device 104, power is supplied to memory device 104, and the adjustment code or boost factor of the voltage generator of memory device 104 is adjusted to increase the voltage output of the voltage generator for aging tests. It is understood that after fine-tuning the code, the voltage output value is fixed. To output other voltage values, the code needs to be adjusted again. Adjusting the internal adjustment code of the voltage generator is complex and inconvenient, making it difficult to conveniently implement multi-voltage value testing. According to some aspects of embodiments of this disclosure, a power supply circuit 200 is provided that can adjust the output voltage based on a multiple of the input voltage without adjusting the circuit's adjustment code and boost factor. The output voltage is adjusted by adjusting the input voltage. This power supply circuit 200 can be configured to meet the voltage supply needs of aging tests or other devices, adjusting the input voltage to obtain multiple output voltages.

[0057] According to some aspects of embodiments of this disclosure, Figure 9A power supply circuit 200 is provided, comprising: a voltage selection circuit 210, a first terminal of which is used to receive at least two different voltages, and a second terminal of which is used to receive a first control signal; the voltage selection circuit 210 is configured to: select one of the at least two different voltages according to the first control signal; and output a reference voltage according to the selected voltage; a comparator 221, a first terminal (negative input terminal) of which is coupled to a third terminal of the voltage selection circuit 210, and a second terminal (positive input terminal) of which is coupled to a second terminal of a voltage generation circuit 230, and is configured to: compare the reference voltage vref provided by the third terminal of the voltage selection circuit 210 with the feedback voltage vpp_fb provided by the second terminal of the voltage generation circuit 230, and output a second control signal according to the comparison result; and a first terminal of the voltage generation circuit 230 is coupled to the third terminal (output terminal) of the comparator 221, and is configured to: receive the second control signal and output the power supply voltage VPP required by the load.

[0058] The voltage selection circuit 210 may include multiple terminals for connecting input voltages, such as multiple first terminals, each terminal for connecting the input voltage to be transformed; it may also include multiple second terminals for connecting to a first control signal, the number of second terminals being equal to the number of first terminals, and a third output terminal for outputting voltage; one second terminal corresponds to one first terminal, and the input voltage on different second terminals can be selected to be output from the third terminal by controlling different levels of the control signals on different second terminals. The voltage output from the third terminal is connected to the first terminal of comparator 221 (e.g., the negative input terminal of comparator 221) as the reference voltage vref of comparator 221. Figure 9 As illustrated, the voltage selection circuit 210 may include, but is not limited to, two first terminals A1 and A2, two second terminals B1 and B2, and a third terminal C1. The first terminals A1 and A2 are respectively input to the power supply voltages required by the two devices, such as a first voltage and a second voltage. The voltage sources for the first and second voltages can be internal voltages generated by the internal voltage generator of the device, or they can be external power supply voltages. For example, terminal A1 can be connected to the first voltage VDD1 provided by an external power supply, and terminal A2 can be connected to the internal voltage modulated by the internal voltage generator (or power module) from the external power supply voltage, such as the second voltage GLB_REF. VDD1 and GLB_REF are merely examples; there are no restrictions on the specific voltage range and phase, and they can be flexibly adapted and connected according to the specific operating requirements of the devices.

[0059] The first control signal connected to the second terminal B1 controls the selection or non-selection of the first voltage, and the first control signal connected to the second terminal B2 controls the selection or non-selection of the second voltage. For example, if the first control signal connected to the second terminal B1 is high and the first control signal connected to the second terminal B2 is low, the third terminal C1 outputs the first voltage connected to the first terminal B1; or, if the first control signal connected to the second terminal B1 is low and the first control signal connected to the second terminal B2 is high, the third terminal C1 outputs the first voltage; or, if the first control signal connected to the second terminal B1 is high and the first control signal connected to the second terminal B2 is low, the third terminal C1 outputs the second voltage connected to the second terminal B2; or, if the first control signal connected to the second terminal B1 is low and the first control signal connected to the second terminal B2 is high, the third terminal C1 outputs the second voltage. The first voltage or the second voltage is selected by the voltage selection circuit 210 and used as the reference voltage vref of the comparator 221. The first voltage or the second voltage can be divided by the load to output the reference voltage vref. The reference voltage vref can be less than or equal to the first voltage, and the reference voltage vref can be less than or equal to the second voltage. For example, the first voltage and the second voltage can be analog signals, and the control signals such as the first control signal and the second control signal can be logic signals.

[0060] Comparator 221 has two input terminals and one output terminal. The input terminals can be a first terminal (negative input terminal) and a second terminal (positive input terminal), and the output terminal is a third terminal. The negative input terminal of comparator 221 is connected to the voltage output of voltage selection circuit 210 as a reference voltage vref, and the positive input terminal of comparator 221 is connected to feedback voltage vpp_fb. Comparator 221 compares the reference voltage vref and the feedback voltage vpp_fb and outputs a second control signal with different logic levels. The input terminal (first terminal) of voltage generation circuit 230 is connected to the second control signal and outputs the power supply voltage VPP required by the load and the feedback voltage vpp_fb according to the different levels of the second control signal. One output terminal of voltage generation circuit 230 outputs VPP, and the other output terminal (second terminal) outputs vpp_fb. The second control signal can be a clock signal composed of high and low levels or a pulse signal. The output terminal of voltage generation circuit 230 can output the power supply voltage VPP required by the load. VPP can power the word lines of memory device 104, or it can power other components; this embodiment is not limited to this. The voltage VPP can be used as the feedback voltage vpp_fb after being reduced by the voltage divider circuit 233, which may include resistors and / or transistors. Specifically, the voltage generating circuit 230 and the comparator 221 constitute a closed-loop voltage feedback regulation circuit. When the feedback voltage vpp_fb is less than the reference voltage vref, the comparator 221 generates a high-level second control signal. In response to the high-level second control signal, the voltage generating circuit 230 increases the voltage and outputs it, and VPP and vpp_fb will increase accordingly. When vpp_fb is greater than or equal to vref, the comparator 221 outputs a low-level second control signal, the voltage generating circuit 230 stops increasing the voltage, maintains the voltage value of vref greater than or equal to vpp_fb, and maintains the supply voltage VPP required by the load output at the output terminal.

[0061] In some embodiments, the voltage VPP output by the voltage generating circuit 230 and the feedback voltage vpp_fb may have a multiple relationship. For example, VPP = f1 * vpp_fb, f1 is greater than 1; and vpp_fb = f2 * vref, f2 ≥ 1; vref = f3 * VDD1, 0 < f3 < 1; vref = f4 * GLB_REF, 0 < f4 < 1; thus, VPP = f1 * f2 * f3 * VDD1, f1 * f2 * f3 > 1; VPP = f1 * f2 * f4 * GLB _REF; f1*f2*f4>1; f1, f2, f3, and f4 can be calibrated according to the actual circuit test; it can realize that the output voltage VPP of the power supply circuit 200 is boosted by a multiple of the input voltage VDD1, and VPP is boosted by a multiple of the input voltage GLB_REF. For example, VPP is 1.23 times VDD1. Thus, the size of VPP can be changed by changing the size of the input voltage VPP or GLB_REF. The boost factor of VPP is the same as the boost factor of VPP or GLB_REF. For example, VDD1 inputs 0V, 1.8V, 2.34V, boosted by a multiple of 1.3 (2.34 / 1.8=1.3); VPP can also be boosted by a multiple of 1.3, outputting 0V, 2.22V, 2.89V respectively. Therefore, the output voltage of the voltage generating circuit 230 can be adjusted by adjusting the input voltage value of the voltage selection circuit 210, and the output voltage value can be characterized according to the input voltage value, which facilitates the real-time adjustment of the output voltage of the voltage generating circuit 230. Without adjusting the boost adjustment code inside the voltage generating circuit 230, predictable, accurate and convenient output of the output voltage value can be achieved.

[0062] In some embodiments, when performing electrical tests such as aging tests on devices like the memory device 104, the first terminal A1 of the voltage selection circuit 210 can be connected to an external power supply. The first voltage VDD1 is the external power supply voltage. During testing, a low-level first control signal is connected to terminal B1, and a high-level first control signal is connected to terminal B2. The first voltage VDD1 is selected for output and generates vref. By sequentially increasing the voltage of VDD1, VPP is sequentially increased to perform aging tests. VPP can supply power to the word lines of the memory device 104. The boost factor of VPP is the same as that of VDD1. VDD1 is the external power supply voltage, which allows for direct adjustment of the voltage value and the boost factor, such as 1.3 times or 1.6 times. This makes the boost of VPP convenient, intuitive, and easy to control, facilitating real-time adjustment of the VPP voltage value and accelerating the efficiency of aging tests. VDD1 can be 1.8V, 2.34V, or higher. In some other embodiments, the first terminal A2 of the voltage selection circuit 210 can be connected to an internal voltage GLB_REF modulated by the device's internal voltage generator. This voltage is used to generate VPP to power the word lines during normal device operation, with a default value of 1.2V. In normal device operation (non-test mode) mode, a high-level first control signal is connected to terminal B1, and a low-level first control signal is connected to terminal B2. The second voltage GLB_REF is selected to generate vref, and the voltage is increased by the voltage generation circuit 230 to generate VPP to power the word lines.

[0063] In some embodiments, reference Figure 10 As shown, the first control signal includes a first sub-control signal burnin_en_n and a second sub-control signal burnin_en. The voltage selection circuit 210 includes: a first sub-selection circuit 211, which includes: a first transistor 2111, whose first and second terminals are respectively connected to a first voltage and the first sub-control signal burnin_en_n; and a second transistor 2112, whose first and second terminals are respectively connected to a second voltage and the second sub-control signal burnin_en.

[0064] Figure 10As exemplified, the first terminal of the first transistor 2111 is the first terminal A1 of the voltage selection circuit 210, or is coupled to terminal A1. The first terminal of the first transistor 2111 is connected to the first voltage VDD1. The second terminal of the first transistor 2111 is the control gate terminal of the transistor, which is the second terminal B1 of the voltage selection circuit 210, or is coupled to terminal B1. The second terminal of the first transistor 2111 is connected to the first sub-control signal burnin_en_n. The third terminal of the first transistor 2111 is coupled to the negative input terminal of the comparator 221, or is coupled to the negative input terminal of the comparator 221 after passing through a load such as a resistor. When the first transistor 2111 is turned on, it provides a reference voltage vref to the comparator 221. The first terminal of the second transistor 2112 is either the first terminal A2 of the voltage selection circuit 210 or coupled to terminal A2. The first terminal of the second transistor 2112 is connected to the second voltage GLB_REF. The second terminal of the second transistor 2112 is the control gate terminal of the transistor, which is either the second terminal B2 of the voltage selection circuit 210 or coupled to terminal B2. The second terminal of the second transistor 2112 is connected to the second sub-control signal burnin_en. The third terminal of the second transistor 2112 is coupled to the negative input terminal of the comparator 221 or, after passing through a resistor or other load, is coupled to the negative input terminal of the comparator 221. When the second transistor 2112 is turned on, it provides a reference voltage vref to the comparator 221. In some embodiments, the first transistor 2111 and the second transistor 2112 can be P-type transistors. When the first sub-control signal burnin_en_n and the second sub-control signal burnin_en are low, the corresponding transistors are turned on; when the first sub-control signal burnin_en_n and the second sub-control signal burnin_en are high, the corresponding transistors are turned off.

[0065] In some embodiments, reference Figure 10 As shown, the voltage selection circuit 210 further includes a second sub-selection circuit 212, which includes a first resistor R1 and a second resistor R2 connected in series. The third terminal of the first transistor 2111 is coupled to the first terminal of the comparator 221 through the first resistor R1 and the second resistor R2 connected in series. The third terminal of the second transistor 2112 is coupled to the first terminal of the comparator 221 through the first resistor R1.

[0066] In some embodiments, reference Figure 10As shown, the second sub-selection circuit 212 further includes: a first switch S1 and a second switch S2; the first end of the second resistor R2 is coupled to one end of the first resistor R1, the first switch S1 is coupled between the second end of the second resistor R2 and the first end of the comparator 221; the second switch S2 is coupled between the first end of the second resistor R2 and the first end of the comparator 221; wherein, the first switch S1 and the second switch S2 are configured such that: when the second end of the first transistor 2111 is turned on by the first sub-control signal burnin_en_n, the first switch S1 is closed and the second switch S2 is open; when the second end of the second transistor 2112 is turned on by the second sub-control signal burnin_en, the second switch S2 is closed and the first switch S1 is open.

[0067] A first resistor R1 and a second resistor R2 are connected in series. One end of the first resistor R1 is coupled to the third terminal of the first transistor 2111 and the third terminal of the second transistor 2112. A first switch S1 is positioned between the second terminal of the second resistor R2 and the third terminal C1 of the voltage selection circuit 210. When the first switch S1 is closed and the second switch S2 is open, both the first resistor R1 and the second resistor R2 are coupled to the third terminal C1, and both are connected to the negative input terminal of the comparator 221. A second switch S2 is positioned between the first terminal of the second resistor R2 and the third terminal C1. When the second switch S2 is closed and the first switch S1 is open, the first resistor R1 is coupled to the third terminal C1, and the first resistor R1 is connected to the negative input terminal of the comparator 221. The first switch S1 and the second switch S2 can be CMOS switches, controlled by the first sub-control signal burnin_en_n and the second sub-control signal burnin_en, respectively. Specifically, during aging tests, when the first sub-control signal burnin_en_n is low and the second sub-control signal burnin_en is high, the first transistor 2111 is turned on, the first switch S1 is closed, and the second switch S2 is open. The first voltage VDD1, after being divided by the first resistor R1 and the second resistor R2, is connected to the negative input terminal of comparator 221 to provide the reference voltage vref. In normal user mode, when the first sub-control signal burnin_en_n is high and the second sub-control signal burnin_en is low, the second transistor 2112 is turned on, the first switch S1 is open, and the second switch S2 is closed. The second voltage GLB_REF, after being divided by the first resistor R1, is connected to the negative input terminal of comparator 221 to provide the reference voltage vref.

[0068] In some embodiments, the second sub-selection circuit 212 further includes an adjustable resistor Rtrim, one end of which is coupled to the second end of the second resistor R2, and the other end is grounded. The adjustable resistor Rtrim can be used to adjust the voltage drop between the first voltage and the second voltage to adjust the value of vref to match the voltage input range of the comparator 221, and can also adjust the voltage output VPP of the voltage generation circuit 230 by adjusting the value of vref.

[0069] In some embodiments, reference Figure 11 The power supply circuit 200 shown further includes an enable circuit 250, comprising a first inverter 251 and a second inverter 252. The first terminal of the first inverter 251 is connected to a control level reg_burnin, and the second terminal of the first inverter 251 is coupled to the first terminal of the second inverter 252. The second terminal of the first inverter 251 outputs a first sub-control signal burnin_en_n; the second terminal of the second inverter 252 outputs a second sub-control signal burnin_en. The enable circuit 250 is connected to a control level to provide a first control signal to the first terminal of the voltage selection circuit 210, specifically providing the first sub-control signal burnin_en_n to the first transistor 2111 and the second sub-control signal burnin_en to the second transistor 2112.

[0070] The input terminal of the first inverter 251 is connected to the control level reg_burnin. The output level burnin_en_n of the second terminal of the first inverter 251 is connected as the first sub-control signal to the second terminal of the first transistor 2111 or the second terminal B1 of the voltage selection circuit 210. burnin_en_n is input to the input terminal of the second inverter 252, and the output level burnin_en is connected as the second sub-control signal to the second terminal of the second transistor 2112 or the second terminal B2 of the voltage selection circuit 210. The logic levels of burnin_en_n and burnin_en are opposite. The operating mode of the power supply circuit 200 and the corresponding control signal logic levels are as follows: Figure 12 In the example, 0 represents a low level, and 1 represents a high level. Combined with... Figure 10 As shown, when vpp_fb = vref, the output requires a stable VPP, vpp_fb = fb * VPP. vpp_fb is generated by the voltage drop of VPP after passing through the voltage divider circuit 233 and connected to the comparator 221. Therefore, vpp_fb is less than VPP, 0 < fb < 1. When the power supply circuit 200 is in normal user mode, reg_burnin = 0, burnin_en = 0, burnin_en_n = 1, S2 is closed, and S1 is open. We can record vref = fd * GLB_REF; when the power supply circuit 200 is in burn-in mode, reg_burnin = 1, burnin_en = 1, burnin_en_n = 0, S1 is closed, and S2 is open. The value of vref can be recorded as fe * VDD1. By adjusting the value of the adjustable resistor Rtrim, the vref of comparator 221 in the two modes can be made equal or basically equal within a certain range to adapt to the voltage range of the input voltage of comparator 221, such as vref = fe * VDD1 = fd * GLB_REF.

[0071] In aging test mode, vref = vpp_fb = fe * VDD1 = fb * VPP, VPP = fe * VDD1 / fb. The boost factor (or multiple) for aging test can be denoted as x, VPP = fe * x * VDD1 / fb, and the boost factor of VPP is also x. VDD1 can be the external power supply voltage. The external power supply voltage allows for direct adjustment of the voltage value and the boost factor, such as 1.3 times or 1.6 times, making the boost of VPP convenient, intuitive, and easy to control. This facilitates real-time adjustment of the VPP voltage value and accelerates the efficiency of aging test.

[0072] In some embodiments, Figure 13 An example is shown: aging test curves of power supply circuit 200 under different modes. The test temperature for aging test is 110℃. The vertical axis represents voltage, and the horizontal axis can represent time. Vdd2h provides voltage to the control level reg_burnin. In user mode, Vdd2h = V3, while reg_burnin = 0V. At this time, the logic levels reg_burnin = 0, burnin_en = 0, burnin_en_n = 1, S2 is closed, S1 is open, input VDD1 = V2, and output VPP = V1. In aging test mode, Vdd2h is boosted to 1.6V3 with a boost factor of 1.6, and the provided reg_burnin voltage is greater than 0, which is a high level. At this time, reg_burnin = 1, burnin_en = 1, burnin_en_n = 0, S1 is closed, S2 is open, input VDD1 = 1.3V2, and output VPP = 1.3V1. The boost factor of VPP is the same as that of VDD1. VDD1 can be provided by an external power supply. The external power supply voltage allows for direct adjustment of the voltage value and the boost factor, making the boost of VPP convenient, intuitive, and easy to control, facilitating real-time adjustment of the VPP voltage value.

[0073] In some embodiments, reference Figure 10As shown, the voltage generating circuit 230 includes: a control circuit 231, the first terminal of which is coupled to the third terminal of comparator 221, and the control circuit 231 is configured to generate and output a third control signal based on a second control signal output by comparator 221; a boost circuit 232, the first terminal of which is coupled to the second terminal of control circuit 231, and the boost circuit 232 is configured to increase the voltage based on the third control signal to generate and output a supply voltage; and a voltage divider circuit 233, one end of which is coupled to the second terminal of boost circuit 232, and the other end of which is coupled to the second terminal of comparator 221. The supply voltage VPP can be divided by voltage divider circuit 233 to generate a reference voltage vpp_fb, which is connected to the positive input terminal of comparator 221. vpp_fb is less than VPP. Voltage divider circuit 233 may include a load resistor and / or a transistor.

[0074] The input terminal of the control circuit 231 is coupled to the output terminal of the comparator 221. When the feedback voltage vpp_fb connected to the comparator 221 is less than the reference voltage vref, the output terminal of the comparator 221 can output a high-level second control signal. Upon receiving the high-level signal, the control circuit 231 generates a third control signal. The third control signal can be a boost control signal, a pulse control signal, or a clock control signal. The boost circuit 232 may include a boost unit, which may include a charge pump circuit. The third control signal charges the boost circuit 232, causing the boost circuit 232 to pull up the voltage values ​​of vpp_fb and VPP. When vpp_fb is greater than or equal to vref, the output terminal of the comparator 221 outputs a low-level second control signal. Upon receiving the low-level signal, the control circuit 231 does not generate a third control signal, and the voltage generating circuit 230 stops increasing the voltage.

[0075] In some embodiments, reference Figure 14 As shown, the control circuit 231 includes: a clock generating circuit 2311, the first terminal of which is coupled to the third terminal of the comparator 221; the clock generating circuit 2311 is configured to generate and output a pulse control signal based on the second control signal output by the comparator 221; and a clock driving circuit 2312, which is coupled to the second terminal of the clock generating circuit 2311; the clock driving circuit 2312 is configured to generate and output a third control signal based on the pulse control signal.

[0076] The clock generation circuit 2311 may include an oscillator or an oscillation circuit. When vpp_fb is less than the reference voltage vref, the clock generation circuit 2311 receives a high-level second control signal and generates an oscillation signal. Figure 15The example pulse control signal CLK1 is used by the clock drive circuit 2312 to generate a third control signal CLK2. The third control signal CLK2 is another pulse control signal generated from CLK1. The clock drive circuit 2312 can shorten or lengthen the clock period of the pulse control signal CLK1, reduce delay, or remove noise to make the third control signal CLK2 more stable. When vpp_fb is greater than or equal to vref, the comparator 221 outputs a low-level second control signal, and the clock generation circuit 2311 either does not generate the pulse control signal CLK1 or is turned off.

[0077] In some embodiments, the boost circuit 232 includes a charge pump circuit. The boost circuit 232 may include multiple boost units connected in parallel. Each boost unit may include a charge pump circuit that receives a third control signal CLK2 and is charged, thereby increasing the output voltage of the charge pump circuit.

[0078] The charge pump circuit of this disclosure embodiment can be any charge pump structure known in the art. For example, the charge pump circuit may include a capacitor, an inverter, and / or a transistor. The third control signal CLK2 can charge the first capacitor in the charge pump circuit, and the charge is stored in the first capacitor. When the switching circuit (which may include a transistor) between the first capacitor and the second capacitor is turned on, the charge of the first capacitor is transferred to the second capacitor, raising the voltage difference across the second capacitor to achieve a boost voltage. One end of the second capacitor is connected to the output terminal to output voltage VPP. VPP is reduced by voltage divider circuit 233 to generate vpp_fb.

[0079] According to some aspects of embodiments of this disclosure, Figure 1 and Figure 5 A memory device 104 is provided, including a voltage generator having a power supply circuit 200, as shown in the reference. Figure 9As shown, the power supply circuit 200 includes: a voltage selection circuit 210, a first terminal of which is used to receive at least two different voltages, and a second terminal of which is used to receive a first control signal; the voltage selection circuit 210 is configured to: select one of the at least two different voltages according to the first control signal; and output a reference voltage vref according to the selected voltage; a comparator 221, a first terminal of which is coupled to a third terminal of the voltage selection circuit 210, and a second terminal of which is coupled to a second terminal of the voltage generation circuit 230, and is configured to: compare the reference voltage vref provided by the third terminal of the voltage selection circuit 210 with the feedback voltage vpp_fb provided by the second terminal of the voltage generation circuit 230, and output a second control signal according to the comparison result; the first terminal of the voltage generation circuit 230 is coupled to the third terminal of the comparator 221, and is configured to: receive the second control signal and output the power supply voltage VPP required by the load.

[0080] Memory device 104 may include NAND memory; memory device 104 as Figure 4 Examples include DRAM memory. The power supply circuit 200 may be part of a voltage generator or power module inside the memory device 104, which is configured to receive an external voltage, such as VDD1. The voltage generator or power module modulates the external voltage to generate the internal voltage required by different components to meet the different voltage requirements of different components. For example, the power supply circuit 200 outputs VPP to power the word line.

[0081] In some embodiments, reference Figure 10 As shown, the first control signal includes a first sub-control signal burnin_en_n and a second sub-control signal burnin_en. The voltage selection circuit 210 includes: a first sub-selection circuit 211, which includes: a first transistor 2111, whose first and second terminals are respectively connected to a first voltage VDD1 and the first sub-control signal burnin_en_n; and a second transistor 2112, whose first and second terminals are respectively connected to a second voltage GLB_REF and the second sub-control signal burnin_en.

[0082] In some embodiments, reference Figure 10 As shown, the voltage selection circuit 210 further includes a second sub-selection circuit 212, which includes a first resistor R1 and a second resistor R2 connected in series. The third terminal of the first transistor 2111 is coupled to the first terminal of the comparator 221 through the first resistor R1 and the second resistor R2 connected in series. The third terminal of the second transistor 2112 is coupled to the first terminal of the comparator 221 through the first resistor R1.

[0083] In some embodiments, reference Figure 10 As shown, the second sub-selection circuit 212 further includes: a first switch S1 and a second switch S2; the first end of the second resistor R2 is coupled to one end of the first resistor R1, the first switch S1 is coupled between the second end of the second resistor R2 and the first end of the comparator 221; the second switch S2 is coupled between the first end of the second resistor R2 and the first end of the comparator 221; wherein, the first switch S1 and the second switch S2 are configured such that: when the second end of the first transistor 2111 is turned on by a first control signal, the first switch S1 is closed and the second switch S2 is open; when the second end of the second transistor 2112 is turned on by a second control signal, the second switch S2 is closed and the first switch S1 is open.

[0084] In some embodiments, reference Figure 10 As shown, the second sub-selection circuit 212 also includes an adjustable resistor Rtrim, one end of which is coupled to the second end of the second resistor R2, and the other end is grounded.

[0085] In some embodiments, reference Figure 11 As shown, the power supply circuit 200 further includes an enable circuit 250, which includes a first inverter 251 and a second inverter 252; the first terminal of the first inverter 251 is connected to a control level, and the second terminal of the first inverter 251 is coupled to the first terminal of the second inverter 252; the second terminal of the first inverter 251 outputs a first sub-control signal burnin_en_n; the second terminal of the second inverter 252 outputs a second sub-control signal burnin_en.

[0086] In some embodiments, reference Figure 12 As shown, the first voltage VDD1 is the external power supply voltage; the voltage selection circuit 210 is configured such that, in response to the first mode requirement of the memory device 104, the second terminal of the first transistor 2111 is connected to a low-level first sub-control signal burnin_en_n, and the first switch S1 is closed; the second terminal of the second transistor 2112 is connected to a high-level second sub-control signal burnin_en, and the second switch S2 is opened; in response to the second mode requirement of the memory device 104, the second terminal of the second transistor 2112 is connected to a low-level second sub-control signal burnin_en, and the second switch S2 is closed; the second terminal of the first transistor 2111 is connected to a high-level first sub-control signal burnin_en_n, and the first switch S1 is opened.

[0087] Combination Figure 10As shown, the first mode can be an aging test mode or other test modes, and the second mode can be the normal operating user mode. During aging testing, the first sub-control signal burnin_en_n is connected to a low level, the second sub-control signal burnin_en is connected to a high level, the first transistor 2111 is turned on, the first switch S1 is closed, and the second switch S2 is open. The first voltage VDD1, after being divided by the first resistor R1 and the second resistor R2, is connected to the negative input terminal of comparator 221 to provide the reference voltage vref. In user mode, the first sub-control signal burnin_en_n is connected to a high level, the second sub-control signal burnin_en is connected to a low level, the second transistor 2112 is turned on, the first switch S1 is open, and the second switch S2 is closed. The second voltage GLB_REF, after being divided by the first resistor R1, is connected to the negative input terminal of comparator 221 to provide the reference voltage vref.

[0088] In some embodiments, reference Figure 10 As shown, the voltage generating circuit 230 includes: a control circuit 231, the first terminal of which is coupled to the third terminal of comparator 221, and the control circuit 231 is configured to generate and output a third control signal based on a second control signal output by comparator 221; a boost circuit 232, the first terminal of which is coupled to the second terminal of control circuit 231, and the boost circuit 232 is configured to increase the voltage based on the third control signal to generate and output a supply voltage; and a voltage divider circuit 233, one end of which is coupled to the second terminal of boost circuit 232, and the other end of which is coupled to the second terminal of comparator 221; wherein, the supply voltage is fed back to the second terminal of comparator 221 after passing through the voltage divider circuit 233.

[0089] In some embodiments, reference Figure 14 As shown, the control circuit 231 includes: a clock generating circuit 2311, the first terminal of which is coupled to the third terminal of comparator 221; the clock generating circuit 2311 is configured to generate and output a pulse control signal CLK1 based on the second control signal output by comparator 221; and a clock driving circuit 2312, which is coupled to the second terminal of clock generating circuit 2311; the clock driving circuit 2312 is configured to generate and output a third control signal CLK1 based on the pulse control signal.

[0090] In some embodiments, the boost circuit 232 includes a boost unit, which includes a charge pump circuit. According to some aspects of embodiments of this disclosure, Figure 1A memory system 102 is provided, including: a memory device 104; and a memory controller 106 coupled to and controlling the memory device 104. The memory device 104 may include NAND memory (NAND flash memory); the memory device 104 may be as follows: Figure 4 The examples include DRAM memory, and memory device 104 may include... Figure 9 and Figure 10 The power supply circuit 200 shown.

[0091] According to some aspects of embodiments of this disclosure, Figure 6 An electronic system 100 is provided, including: a memory controller 701, a host CPU 707 coupled to the memory controller 701, a flash memory 706, and a memory device (DRAM 708) coupled to the host; the memory controller 701 controls the flash memory 706. The flash memory 706 may include NADN memory, and the memory controller 701 and the flash memory 706 can constitute a memory system. The controller of the DRAM 708 may be integrated into the host CPU 707, such as a memory controller.

[0092] According to some aspects of embodiments of this disclosure, Figure 7 An electronic system 100 is provided, including: a memory controller 701, and a host CPU 707, flash memory 706, and a memory device (DRAM 710) coupled to the memory controller 701; the memory controller 701 may include a cache controller 709 to control the DRAM 710. The memory controller 701, flash memory 706, and DRAM 710 can constitute a memory system.

[0093] The device embodiments described above are merely illustrative. For example, the division of units, devices, and systems is only a logical functional division illustration. In actual implementation, there may be other division methods, such as multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed.

[0094] According to some aspects of embodiments of this disclosure, Figure 16 A method for operating a memory device 104 is provided, comprising: in response to a mode requirement of the memory device, inputting a first control signal to a voltage selection circuit in a power supply circuit of the memory device, such that the voltage selection circuit selects one of the input voltages and outputs a reference voltage according to the selected voltage; comparing a feedback voltage provided by a voltage generation circuit with the reference voltage, and outputting a second control signal according to the comparison result; and causing the voltage generation circuit to output a power supply voltage required by the load according to the second control signal.

[0095] When testing the memory device 104, it can be placed on a corresponding test bench. The test bench provides external power voltage to the power supply circuit 200 through probes or contacts and acquires the output voltage of the power supply circuit 200. The memory device 104 can be in a first mode or a second mode; it can be in a test mode or a normal operating user mode. Figure 10 As shown, the first mode can be an aging test mode or other test modes, and the second mode can be a user mode. During aging testing, the first sub-control signal burnin_en_n is connected to a low level, the second sub-control signal burnin_en is connected to a high level, the first switch S1 is closed, and the second switch S2 is open. The first voltage VDD1, after being divided by the first resistor R1 and the second resistor R2, is connected to the negative input terminal of comparator 221 to provide a reference voltage vref. In user mode, the first sub-control signal burnin_en_n is connected to a high level, the second sub-control signal burnin_en is connected to a low level, the second transistor 2112 is turned on, the first switch S1 is open, and the second switch S2 is closed. The second voltage GLB_REF, after being divided by the first resistor R1, is connected to the negative input terminal of comparator 221 to provide a reference voltage vref.

[0096] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A power supply circuit, characterized in that, include: A voltage selection circuit, wherein a first terminal of the voltage selection circuit is used to connect at least two different voltages, and a second terminal of the voltage selection circuit is used to connect a first control signal; The voltage selection circuit is configured to: select one of the at least two different voltages according to the first control signal; and output a reference voltage according to the selected voltage; A comparator, wherein a first terminal of the comparator is coupled to a third terminal of the voltage selection circuit, and a second terminal of the comparator is coupled to a second terminal of the voltage generation circuit, and is configured to: compare the reference voltage provided by the third terminal of the voltage selection circuit with the feedback voltage provided by the second terminal of the voltage generation circuit, and output a second control signal based on the comparison result; The first terminal of the voltage generating circuit is coupled to the third terminal of the comparator and is configured to receive the second control signal and output the power supply voltage required by the load.

2. The power supply circuit according to claim 1, characterized in that, The first control signal includes a first sub-control signal and a second sub-control signal. The voltage selection circuit includes: a first sub-selection circuit, which includes: A first transistor, wherein a first terminal and a first sub-control signal are respectively connected to a first voltage and a first sub-control signal; The second transistor has a first terminal and a second sub-control signal respectively connected to its second terminal.

3. The power supply circuit according to claim 2, characterized in that, The voltage selection circuit further includes: a second sub-selection circuit, the second sub-selection circuit comprising: A first resistor and a second resistor are connected in series, and the third terminal of the first transistor is coupled to the first terminal of the comparator through the first resistor and the second resistor connected in series. The third terminal of the second transistor is coupled to the first terminal of the comparator through the first resistor.

4. The power supply circuit according to claim 3, characterized in that, The second sub-selection circuit also includes: A first switch and a second switch; a first end of the second resistor is coupled to one end of the first resistor, and the first switch is coupled between the second end of the second resistor and the first end of the comparator; The second switch is coupled between the first terminal of the second resistor and the first terminal of the comparator; wherein the first switch and the second switch are configured as follows: When a first sub-control signal is applied to the second terminal of the first transistor and the transistor is turned on, the first switch closes and the second switch opens. When a second sub-control signal is applied to the second terminal of the second transistor and the second switch is turned on, the second switch closes and the first switch opens.

5. The power supply circuit according to claim 3, characterized in that, The second sub-selection circuit also includes: An adjustable resistor, one end of which is coupled to the second end of the second resistor, and the other end is grounded.

6. The power supply circuit according to claim 2, characterized in that, The power supply circuit also includes: The enable circuit includes a first inverter and a second inverter; a first terminal of the first inverter is connected to a control level, and a second terminal of the first inverter is coupled to the first terminal of the second inverter; the second terminal of the first inverter outputs the first sub-control signal; and the second terminal of the second inverter outputs the second sub-control signal.

7. The power supply circuit according to claim 1, characterized in that, The voltage generating circuit includes: A control circuit, wherein a first terminal of the control circuit is coupled to a third terminal of the comparator, and the control circuit is configured to generate and output a third control signal based on a second control signal output by the comparator. A boost circuit, wherein a first terminal of the boost circuit is coupled to a second terminal of the control circuit; the boost circuit is configured to: increase the voltage according to the third control signal to generate the supply voltage and output it; A voltage divider circuit is provided, with one end of the voltage divider circuit coupled to the second end of the boost circuit and the other end coupled to the second end of the comparator; wherein, the supply voltage is fed back to the second end of the comparator after passing through the voltage divider circuit.

8. The power supply circuit according to claim 7, characterized in that, The control circuit includes: A clock generating circuit, wherein a first terminal of the clock generating circuit is coupled to a third terminal of the comparator; the clock generating circuit is configured to generate and output a pulse control signal based on the second control signal output by the comparator. A clock driving circuit is coupled to the second terminal of the clock generating circuit; the clock driving circuit is configured to generate and output the third control signal according to the pulse control signal.

9. The power supply circuit according to claim 7, characterized in that, The boost circuit includes a charge pump circuit.

10. A memory device comprising a voltage generator having a power supply circuit, characterized in that, The power supply circuit includes: A voltage selection circuit, wherein a first terminal of the voltage selection circuit is used to receive at least two different voltages, and a second terminal of the voltage selection circuit is used to receive a first control signal; the voltage selection circuit is configured to: select one of the at least two different voltages according to the first control signal; and output a reference voltage according to the selected voltage; A comparator, wherein a first terminal of the comparator is coupled to a third terminal of the voltage selection circuit, and a second terminal of the comparator is coupled to a second terminal of the voltage generation circuit, and is configured to: compare the reference voltage provided by the third terminal of the voltage selection circuit with the feedback voltage provided by the second terminal of the voltage generation circuit, and output a second control signal based on the comparison result; The first terminal of the voltage generating circuit is coupled to the third terminal of the comparator and is configured to receive the second control signal and output the power supply voltage required by the load.

11. The memory device according to claim 10, characterized in that, The first control signal includes a first sub-control signal and a second sub-control signal. The voltage selection circuit includes: a first sub-selection circuit, which includes: A first transistor, wherein a first terminal and a first sub-control signal are respectively connected to a first voltage and a first sub-control signal; The second transistor has a first terminal and a second sub-control signal respectively connected to its second terminal.

12. The memory device according to claim 11, characterized in that, The voltage selection circuit further includes: a second sub-selection circuit, the second sub-selection circuit comprising: A first resistor and a second resistor are connected in series, and the third terminal of the first transistor is coupled to the first terminal of the comparator through the first resistor and the second resistor connected in series. The third terminal of the second transistor is coupled to the first terminal of the comparator through the first resistor.

13. The memory device according to claim 12, characterized in that, The second sub-selection circuit also includes: A first switch and a second switch; a first end of the second resistor is coupled to one end of the first resistor, and the first switch is coupled between the second end of the second resistor and the first end of the comparator; The second switch is coupled between the first terminal of the second resistor and the first terminal of the comparator; wherein the first switch and the second switch are configured as follows: When a first control signal is applied to the second terminal of the first transistor and the transistor is turned on, the first switch closes and the second switch opens. When a second control signal is applied to the second terminal of the second transistor and the second switch is turned on, the second switch closes and the first switch opens.

14. The memory device according to claim 12, characterized in that, The second sub-selection circuit also includes: An adjustable resistor, one end of which is coupled to the second end of the second resistor, and the other end is grounded.

15. The memory device according to claim 11, characterized in that, The power supply circuit also includes: The enable circuit includes a first inverter and a second inverter; a first terminal of the first inverter is connected to a control level, and a second terminal of the first inverter is coupled to the first terminal of the second inverter; the second terminal of the first inverter outputs the first sub-control signal; and the second terminal of the second inverter outputs the second sub-control signal.

16. The memory device according to claim 13, characterized in that, The first voltage is an external power supply voltage; the voltage selection circuit is configured as follows: In response to a first mode requirement of the memory device, a low-level first sub-control signal is applied to the second terminal of the first transistor, and the first switch is closed; a high-level second sub-control signal is applied to the second terminal of the second transistor, and the second switch is opened. In response to a second mode requirement of the memory device, a low-level second sub-control signal is applied to the second terminal of the second transistor, and the second switch is closed; a high-level first sub-control signal is applied to the second terminal of the first transistor, and the first switch is opened.

17. The memory device according to claim 10, characterized in that, The voltage generating circuit includes: A control circuit, wherein a first terminal of the control circuit is coupled to a third terminal of the comparator, and the control circuit is configured to generate and output a third control signal based on a second control signal output by the comparator. A boost circuit, wherein a first terminal of the boost circuit is coupled to a second terminal of the control circuit; the boost circuit is configured to: increase the voltage according to the third control signal to generate the supply voltage and output it; A voltage divider circuit is provided, with one end of the voltage divider circuit coupled to the second end of the boost circuit and the other end coupled to the second end of the comparator; wherein, the supply voltage is fed back to the second end of the comparator after passing through the voltage divider circuit.

18. The memory device according to claim 17, characterized in that, The control circuit includes: A clock generating circuit, wherein a first terminal of the clock generating circuit is coupled to a third terminal of the comparator; the clock generating circuit is configured to generate and output a pulse control signal based on the second control signal output by the comparator. A clock driving circuit is coupled to the second terminal of the clock generating circuit; the clock driving circuit is configured to generate and output the third control signal according to the pulse control signal.

19. The memory device according to claim 18, characterized in that, The boost circuit includes a charge pump circuit.

20. A memory system, characterized in that, include: The memory device as claimed in any one of claims 10 to 19; as well as A memory controller is coupled to and controls the memory device.

21. A method of operating a memory device, characterized in that, include: In response to the mode requirements of the memory device, a first control signal is input to the voltage selection circuit in the power supply circuit of the memory device, so that the voltage selection circuit selects one of the input voltages and outputs a reference voltage according to the selected voltage; The feedback voltage provided by the voltage generation circuit is compared with the reference voltage, and a second control signal is output based on the comparison result. The voltage generating circuit outputs the power supply voltage required by the load according to the second control signal.

Images