Memory device, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a memory device and a manufacturing method thereof, and a memory system. The memory device comprises a memory unit array; a plurality of word lines coupled to the memory cell array; and a peripheral circuit coupled to the memory cell array through the plurality of word lines, the peripheral circuit including: a driving circuit; the driving circuit comprises a main driver and a plurality of word line drivers; each word line driver is correspondingly coupled with each word line, the main driver is connected with n word line drivers, and n is an integer greater than 8.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device and its manufacturing method, and a memory system. Background Technology

[0002] Semiconductor devices, such as Dynamic Random Access Memory (DRAM), are among the most important storage components in electronic systems. They typically employ a 1T1C structure, consisting of a transistor and a capacitor, as a single storage cell. This 1T1C structure allows DRAM to achieve high integration density and low cost, giving it an irreplaceable position in computer storage devices. With the rapid development of semiconductor technology, DRAM is rapidly evolving towards higher density and higher quality. Summary of the Invention

[0003] This disclosure provides a memory device, a method for manufacturing the same, and a memory system.

[0004] In a first aspect, embodiments of this disclosure provide a memory device, the memory device comprising: a memory cell array; a plurality of word lines coupled to the memory cell array; and peripheral circuitry coupled to the memory cell array via the plurality of word lines. The peripheral circuitry includes: a driving circuitry; the driving circuitry includes a main driver and a plurality of word line drivers; each word line driver is coupled to each word line, and the main driver is connected to n word line drivers, where n is an integer greater than 8.

[0005] In some embodiments, the main driver includes a pre-charge circuit and an output circuit; the transistor size of the transistor in the output circuit is larger than the transistor size of the transistor in the pre-charge circuit.

[0006] In some embodiments, the ratio of the transistor size of the transistor in the output circuit to the transistor size of the transistor in the precharge circuit ranges from 1.5 to 2.

[0007] In some embodiments, the master driver is connected to 16 word line drivers.

[0008] In some embodiments, the peripheral circuit further includes: a row decoder coupled to the driving circuit; the row decoder is configured to: decode the 9th to 5th bits of the m-bit row address signal to generate a main driving signal, and decode the lowest 4 bits of the m-bit row address signal to generate a word line driving signal, where m is an integer greater than 9; the driving circuit is configured to: drive a target word line based on the main driving signal and the word line driving signal.

[0009] In some embodiments, the memory cell array includes a plurality of memory cells, each memory cell includes a plurality of memory groups, and each memory group includes at least one memory block; the orthographic projection of the drive circuit is located within the orthographic projection of the memory group.

[0010] In some embodiments, the memory blocks in each memory group are arranged in an array along the word line direction and the bit line direction; the orthographic projection of the word line driver is located between the orthographic projections of adjacent memory blocks along the word line direction.

[0011] In some embodiments, the plurality of memory banks are arranged in an array along the word line direction and the bit line direction; the orthographic projection of the row decoder is located between the orthographic projections of adjacent memory banks along the bit line direction.

[0012] In some embodiments, the driving circuit further includes: a first power supply circuit configured to provide a charging voltage to the word line driver; the orthographic projection of the first power supply circuit is located within the orthographic projection of the memory block.

[0013] In some embodiments, the driving circuit further includes: a second power supply circuit configured to provide a discharge voltage to the word line driver; the orthographic projection of the second power supply circuit is located within the orthographic projection of the memory block.

[0014] In some embodiments, the driving circuit further includes: a driving circuit interconnect for coupling between the first power supply circuit and the word line driver, and for coupling between the second power supply circuit and the word line driver; the orthographic projection of the driving circuit interconnect is located within the orthographic projection of the memory group, and the driving circuit interconnect extends along the word line direction.

[0015] In some embodiments, one of the word line drivers located on either side of a first memory block in a plurality of memory blocks is coupled to an even number line and the other is coupled to an odd number line.

[0016] In some embodiments, the memory cell array includes a plurality of memory cells, each memory cell including a vertical transistor and a capacitor.

[0017] In some embodiments, the memory cell array and the peripheral circuitry are formed on different substrates, and the peripheral circuitry is stacked with the memory cell array in the vertical direction.

[0018] In a second aspect, embodiments of this disclosure provide a memory system, including: a memory device as described in any one of the first aspects; and a memory controller; the memory controller being coupled to the memory device and used to control the memory device.

[0019] Thirdly, embodiments of this disclosure provide a method for manufacturing a memory device, the method comprising: forming a memory cell array and a plurality of word lines coupled to the memory cell array; forming peripheral circuitry, including forming a plurality of driving circuits, the driving circuits including a main driver and a plurality of word line drivers; each word line driver being coupled to each word line, the main driver being connected to n word line drivers, where n is an integer greater than 8.

[0020] In some embodiments, a plurality of driving circuits are formed, including: forming a pre-charge circuit and an output circuit; the transistor size of the transistor in the output circuit is larger than the transistor size of the transistor in the pre-charge circuit.

[0021] In some embodiments, the ratio of the transistor size of the transistor in the output circuit to the transistor size of the transistor in the precharge circuit ranges from 1.5 to 2.

[0022] In some embodiments, the master driver is connected to 16 word line drivers.

[0023] In some embodiments, forming a peripheral circuit further includes: forming a row decoder, the row decoder being coupled to the driving circuit; the row decoder being configured to: decode the 9th to 5th bits of the m-bit row address signal to generate a main driving signal, and decode the lowest 4 bits of the m-bit row address signal to generate a word line driving signal, where m is an integer greater than 9; the word line driver being configured to: drive a target word line based on the main driving signal and the word line driving signal.

[0024] In some embodiments, forming a memory cell array includes: forming a memory cell array comprising a plurality of memory cells, each memory cell comprising a plurality of memory groups, each memory group comprising at least one memory block; and the orthographic projection of the drive circuit is located within the orthographic projection of the memory group.

[0025] In some embodiments, the memory blocks in the memory group are arranged in an array along the word line direction and the bit line direction; forming a plurality of driving circuits, including: forming a plurality of word line drivers, wherein the orthographic projection of the word line drivers is located between the orthographic projections of adjacent memory blocks along the word line direction.

[0026] In some embodiments, the plurality of memory banks are arranged in an array along the word line direction and the bit line direction; forming a row decoder includes: forming a row decoder whose orthographic projection is located between the orthographic projections of adjacent memory banks along the bit line direction.

[0027] In some embodiments, forming a peripheral circuit further includes forming a first power supply circuit configured to provide a charging voltage to the word line driver; the orthographic projection of the first power supply circuit lies within the orthographic projection of the memory block.

[0028] In some embodiments, forming a peripheral circuit further includes forming a second power supply circuit, the second power supply circuit being configured to provide a discharge voltage to the word line driver; the orthographic projection of the second power supply circuit is located within the orthographic projection of the memory block.

[0029] In some embodiments, forming a peripheral circuit further includes: forming a driving circuit interconnect, the driving circuit interconnect being used to couple the first power supply circuit and the word line driver, and to couple the second power supply circuit and the word line driver; the orthographic projection of the driving circuit interconnect is located within the orthographic projection of the memory group, and the driving circuit interconnect extends along the word line direction.

[0030] In some embodiments, one of the word line drivers located on either side of a first memory block in a plurality of memory blocks is coupled to an even number line and the other is coupled to an odd number line.

[0031] In some embodiments, forming a memory cell array includes forming a plurality of memory cells, each memory cell including a vertical transistor and a capacitor.

[0032] In some embodiments, forming a memory cell array includes: forming a memory cell array on a first substrate; forming a peripheral circuit includes: forming a peripheral circuit on a second substrate; the method further includes: bonding the memory cell array and the peripheral circuit.

[0033] This disclosure provides a memory device and its manufacturing method, as well as a memory system. The memory device includes: a memory cell array; multiple word lines coupled to the memory cell array; and peripheral circuitry coupled to the memory cell array via the multiple word lines. The peripheral circuitry includes: a driving circuit; the driving circuitry includes a main driver and multiple word line drivers; each word line driver is coupled to each word line, and the main driver connects to n word line drivers, where n is an integer greater than 8. In this disclosure, each main driver connects to more than 8 word line drivers, so that one main word line can drive more than 8 word lines (partial word lines), thereby greatly improving the integration density of the memory device. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0035] Figure 2 This is a schematic diagram of an exemplary computer system having a memory system according to an embodiment of the present disclosure;

[0036] Figure 3This is a schematic diagram of an exemplary memory device according to an embodiment of the present disclosure;

[0037] Figure 4 This is a schematic diagram showing the distribution of the memory cell array and peripheral circuitry in an exemplary memory device according to an embodiment of the present disclosure;

[0038] Figure 5 This is a top view showing the distribution of the memory cell array and peripheral circuitry in an exemplary memory device according to an embodiment of the present disclosure. Figure 1 ;

[0039] Figure 6 This is a top view showing the distribution of the memory cell array and peripheral circuitry in an exemplary memory device according to an embodiment of the present disclosure. Figure 2 ;

[0040] Figure 7 This is a schematic diagram of a driving circuit in an exemplary peripheral circuit according to an embodiment of the present disclosure;

[0041] Figure 8 This is a schematic diagram of a word line driver in an exemplary driving circuit according to an embodiment of the present disclosure;

[0042] Figure 9 This is a schematic diagram of the main driver in an exemplary driving circuit according to an embodiment of the present disclosure;

[0043] Figure 10 This is a schematic diagram illustrating an exemplary row address signal decoding according to an embodiment of this disclosure;

[0044] Figure 11A This is a partial schematic diagram of an exemplary memory device according to an embodiment of the present disclosure;

[0045] Figure 11B This is an enlarged schematic diagram of an exemplary first storage group according to an embodiment of the present disclosure;

[0046] Figure 11C This is an enlarged schematic diagram of an exemplary second storage group according to an embodiment of the present disclosure;

[0047] Figure 11D This is an enlarged schematic diagram of an exemplary third storage group according to an embodiment of the present disclosure;

[0048] Figure 12 This is a schematic flowchart illustrating a method for manufacturing a memory device according to an embodiment of this application. Detailed Implementation

[0049] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0050] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0051] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0052] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0053] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0055] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0056] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). The host 108 may be configured to send data to or receive data from the memory device 104. The memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 may manage the data stored in the memory device 104 and communicate with the host 108.

[0057] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols.

[0058] In some specific embodiments, one or more memory devices 104 and memory controller 106 can be integrated into various types of storage devices. For example, multiple memory devices 104 can be integrated into a memory module; the memory controller 106 can be integrated into the northbridge of the motherboard or directly into the CPU. In other words, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0059] In such Figure 2 In one system example shown, the system includes a system-on-chip (SoC) and one or more memory devices; the memory devices include DRAM 204, and the SoC includes a graphics processing unit (GPU) 208, a DRAM controller 206, and a DRAM physical layer 210; wherein, the DRAM controller 206 is responsible for scheduling read and write instructions and timing control of DRAM 204; the DRAM physical layer 210 is responsible for encoding the scheduled instructions according to the requirements of DRAM 204, sending the corresponding write data to DRAM 204, and receiving data read from DRAM 204.

[0060] Figure 3 This is a schematic diagram of an exemplary memory device DRAM according to an embodiment of the present disclosure; Figure 3The right side shows the circuitry of the memory cells in a DRAM. Each DRAM chip 304 (Die) includes a memory cell array, which contains multiple memory cells 301 arranged in an array. Each memory cell 301 includes a transistor T and a capacitor C. The main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, which can be viewed as a typical mesh structure. The memory array uses rows and columns to specify addresses. By specifying the intersection of the rows and columns (by specifying the row address and column address of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and perform read or write operations on the data stored therein.

[0061] In some embodiments, the memory device includes a memory cell array and peripheral circuitry. The memory cell array includes multiple banks, each bank is divided into multiple groups, each group may include multiple blocks, and each block includes multiple rows and columns of memory cells. Each row of memory cells is coupled to a corresponding word line, and each column of memory cells is coupled to a corresponding bit line. The peripheral circuitry includes a series of complementary metal-oxide-semiconductor (CMOS) control circuitry. For example, this series of CMOS control circuitry includes: control circuitry corresponding to each memory block, such as a sensing amplifier (SA) and a word-line driver (WLD); control circuitry corresponding to each bank, such as a row decoder and a column decoder; and control circuitry corresponding to all banks, such as a command register, a command decoder, an address register, a data register, and a mode register.

[0062] The following combination Figures 4 to 6 A detailed description of the memory device is provided. (In the introduction...) Figures 4 to 6 Before illustrating the memory device, the various directions that may be used in the following description are defined. The stacking direction of the memory cell array and peripheral circuitry is defined as the vertical direction (i.e., the Z direction). The intersecting word line direction (i.e., the X direction) and bit line direction (i.e., the Y direction) are defined in a plane perpendicular to the Z direction. In some embodiments, the X, Y, and Z directions may be mutually perpendicular.

[0063] In practical applications, the layout between the memory cell array and the peripheral circuitry is important. In some embodiments, the memory cell array and the peripheral circuitry are arranged side-by-side on different substrates. An example is... Figure 4 A schematic diagram showing the distribution of the memory cell array and peripheral circuitry in an exemplary memory device; Figure 5 Top view of the distribution of memory cell array and peripheral circuitry in the exemplary memory device shown. Figure 1 .like Figure 4 As shown, the storage cell array 401 and peripheral circuit 402 are stacked vertically. More specifically, each storage block has a control circuit corresponding to its side at least once, and each storage cell has a control circuit corresponding to its side at least once. Every K storage cells out of M storage cells form a storage cell row, and the M storage cells form M / K storage cell rows. Peripheral circuits corresponding to all storage cells are arranged between the two middle storage cell rows. It should be noted that M, N, and K are all positive integers, and M is an integer multiple of K.

[0064] In some embodiments, the memory cell array 401 and the peripheral circuitry 402 are disposed on two substrates. Exemplary memory devices, such as... Figure 4 As shown, it includes: a first substrate 100, which includes at least a memory cell array 401;

[0065] The second substrate 200 includes at least peripheral circuitry 402; the first substrate 100 and the second substrate 200 are stacked and connected by bonding.

[0066] Here, the first substrate 100 may include, but is not limited to, a silicon substrate. The first substrate 100 may at least include a memory cell array 401. Later, the first substrate 100 may also include a dummy memory cell array. The memory cell array 401 may include multiple memory banks arranged in an array. Each memory bank includes multiple memory blocks arranged in an array. Each memory block includes multiple rows and columns of memory cells. Each row and column of memory cells includes multiple memory cells. The memory cell array 401 may also include multiple word lines and multiple bit lines. Each row of memory cells is coupled to a corresponding word line, and each column of memory cells is coupled to a corresponding bit line.

[0067] Here, the second substrate 200 is a different substrate from the first substrate, and the second substrate includes, but is not limited to, a silicon substrate. In the following text, the second substrate 200 includes peripheral circuitry 402; the peripheral circuitry 402 may include control circuitry corresponding to the memory block and / or control circuitry corresponding to the memory bank. Here, the peripheral circuitry 402 also includes control circuitry corresponding to all memory banks, such as a command register, command decoder, address register, data register, mode register, etc.

[0068] In some embodiments, as Figure 4The memory device shown may further include: a bonding interface located between the first substrate and the second substrate;

[0069] A first interconnect layer is located between the first substrate and the bonding interface;

[0070] A second interconnect layer is located between the second substrate and the bonding interface;

[0071] The first substrate and the second substrate are connected through the first interconnect layer, the bonding interface, and the second interconnect layer.

[0072] Here, the memory device may further include a bonding interface, a first interconnect layer, and a second interconnect layer. Both the first and second interconnect layers may include multiple bonding contacts and a dielectric material electrically isolating the bonding contacts. In some embodiments, the bonding contacts may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof; the dielectric material may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics (dielectric constant less than 3.9), or any combination thereof. In some embodiments, a first interconnect layer is formed on a first substrate; a second interconnect layer is formed on a second substrate; then, the memory array contained in the first substrate and the peripheral circuitry contained in the second substrate are bonded at the bonding interface, and the bonding contacts and the surrounding dielectric material may be connected using hybrid bonding. That is, in some embodiments, the bonding interface is formed perpendicularly between the first and second interconnect layers. In some embodiments, the memory cell array in the first substrate and the peripheral circuitry in the second substrate are bonded at the bonding interface through bonding contacts contained in the first interconnect layer and bonding contacts contained in the second interconnect layer to achieve connection between the memory cell array and the peripheral circuitry.

[0073] For example, such as Figure 5 As shown, the storage cell array 401 includes 16 storage banks 401-1, each storage bank including multiple storage blocks. Each storage block has corresponding storage blocks SA and WLD arranged around its perimeter. Each storage bank has a column decoder 504 and a row decoder 506 on its sides. Every four storage banks form a storage bank row, and the 16 storage banks form four storage bank rows. A control circuit 502 is arranged between the two middle storage bank rows. It should be noted that... Figure 5 The number of memory banks is for illustrative purposes only and is not intended to limit the number of memory banks in the memory devices of this disclosure.

[0074] For example, such as Figure 6 The diagram shown is a top view illustrating the distribution of the memory cell array and peripheral circuitry in a memory device. Figure 2It should be noted that, Figure 6 The first substrate 100 is located above the second substrate 200, and Figure 6 The solid lines correspond to the structures located in the first substrate 100, and the dashed lines correspond to the structures located in the second substrate 200. For ease of understanding, the structures in the second substrate 200 are shown in perspective.

[0075] For example, such as Figure 6 As shown, the storage array 401 includes 16 storage banks 401-1. Each storage bank includes multiple storage blocks. Directly below each storage block, there are first SA and second SA arranged opposite each other along a first direction, and first WLD and second WLD arranged opposite each other along a second direction. On both sides of each storage bank, there are column decoders 504 and row decoders 506 corresponding to the storage bank. Every 4 storage banks form a storage bank row, and 16 storage banks form 4 storage bank rows. A control circuit 502 is arranged below the middle two storage bank rows.

[0076] It should be noted that, Figure 6 The number of memory banks is for illustrative purposes only and is not intended to limit the number of memory banks in the memory devices of this disclosure.

[0077] It should be noted that, Figure 6 The size relationship between a memory block and the surrounding SA and word line drivers shown is for illustrative purposes only and is not intended to limit the size relationship between a memory block and the surrounding SA and word line drivers in the memory device of this disclosure.

[0078] It should be noted that the above are only two exemplary layouts of memory cell arrays and peripheral circuits. Other layouts are also possible in practice, but more layouts will not be described here.

[0079] To reduce the area occupied by peripheral circuitry and thus the size of the memory device, this disclosure provides another memory device, which includes:

[0080] Storage cell array;

[0081] Multiple word lines coupled to the memory cell array; and

[0082] The peripheral circuitry is coupled to the memory cell array via the multiple word lines, and the peripheral circuitry includes: a driving circuitry;

[0083] The driving circuit includes a main driver and multiple word line drivers; each word line driver is coupled to each word line, and the main driver is connected to n word line drivers, where n is an integer greater than 8.

[0084] Figure 7 This is a schematic diagram of a driving circuit in an exemplary peripheral circuit according to an embodiment of the present disclosure, with reference to... Figure 7 The driving circuit includes a main driver 710 and a plurality of word line drivers 720; each word line driver 720 is coupled to each word line, and the main driver 710 is connected to n word line drivers 720.

[0085] In some embodiments, the master driver 710 is connected to 16 word line drivers 720.

[0086] Each master word line (or global word line MWL) driven by master driver 710 can be coupled to 16 word line drivers 720, and each word line driver 720 can be coupled to a corresponding word line WL (e.g., a local word line LWL) in the memory cell array. Word line drivers 720 are used in conjunction with master drivers 710 to control the voltage on the corresponding word line WL. Word lines extending from master drivers 710 to word line drivers 720 can be referred to as master word lines. Word lines extending from word line drivers 720 to the memory cell array can be referred to as local word lines.

[0087] In some embodiments, word line driver 720 may include word line drive transistors for transferring voltage from the main word line to the word line WL. Figure 8 This is a schematic diagram of a word line driver in an exemplary driving circuit according to an embodiment of the present disclosure, with reference to... Figure 8 The word line driver 720 includes a first transistor 721, a second transistor 722, and a third transistor 723. The first transistor 721 is a PMOS transistor, and the second transistor 722 and the third transistor 723 are NMOS transistors. In some embodiments, node XPP is connected to a first power supply circuit, node LWL is connected to a second power supply circuit, and node MWL_n is connected to the main driver 710. When the enable signal provided by the first voltage supply circuit is high (VPP), the enable signal provided by the second voltage supply circuit is low (VSS), and the enable signal provided by the main driver 710 is low (VSS), the voltage on the word line WL is pulled up to the operating voltage Vpp.

[0088] In some embodiments, Figure 9 This is a schematic diagram of the main driver in an exemplary driving circuit according to an embodiment of the present disclosure, with reference to... Figure 9 The main driver 710 includes a pre-charge circuit 711 and an output circuit 712; the transistor size of the transistor in the output circuit 712 is larger than the transistor size of the transistor in the pre-charge circuit 711. In some embodiments, the transistor size of the NMOS transistor in the output circuit 712 is larger than the transistor size of the NMOS transistor in the pre-charge circuit 711.

[0089] In some embodiments, the output circuit 712 includes a pull-up transistor 7121 and a pull-down transistor 7122; the transistor size of the pull-down transistor 7122 in the output circuit 712 is larger than the transistor size of the NMOS transistor in the pre-charge circuit 711. In other embodiments, the transistor size of the pull-down transistor 7122 is larger than the transistor size of the pull-up transistor 7121. The pull-up transistor 7121 is a PMOS transistor, and the pull-down transistor 7122 is an NMOS transistor. The drive current output by the main driver 710 is determined by the pull-down current flowing through the pull-down transistor 7122.

[0090] In some implementations, transistor size refers to the ratio of channel width to channel length. In other implementations, adjusting the transistor size can be done by keeping the channel length constant while adjusting the channel width.

[0091] In some embodiments, the ratio of the transistor size of the transistor in the output circuit to the transistor size of the transistor in the precharge circuit ranges from 1.5 to 2.

[0092] In some embodiments, the ratio of the transistor size of the pull-down transistor 7122 to the transistor size of the pull-up transistor 7121 is in the range of 1.5-2.

[0093] Compared to a master driver connecting 8 word lines, a master driver connecting 16 word lines experiences greater drive pressure, thus requiring a larger drive current to increase its drive speed. Since transistor current is proportional to transistor size, in some embodiments, transistor size refers to the ratio of channel width to channel length. By adjusting the pull-up transistor size, the pull-down current of the pull-down transistor can be increased by 1.5 to 2 times. In other embodiments, adjusting the transistor size can keep the channel length constant while adjusting the channel width. Embodiments of this disclosure can largely compensate for the decrease in drive speed caused by connecting more word lines (more than 8 word lines) simply by increasing the transistor width of one transistor in the master driver (the pull-down transistor in the output circuit).

[0094] In some embodiments, the storage cell array includes a plurality of storage banks, each storage bank includes a plurality of storage groups, and each storage group includes at least one storage block.

[0095] In some embodiments, the peripheral circuit further includes: a row decoder coupled to the driving circuit; the row decoder is configured to: decode the 9th to 5th bits of the m-bit row address signal to generate a main driving signal, and decode the lowest 4 bits of the m-bit row address signal to generate a word line driving signal, where m is an integer greater than 9; the driving circuit is configured to: drive a target word line based on the main driving signal and the word line driving signal.

[0096] In some implementations... Figure 10 This is a schematic diagram illustrating an exemplary row address signal decoding according to an embodiment of the present disclosure, with reference to... Figure 10 The row decoder receives a 16-bit row address signal (Row Address<15:0>). It decodes bits 16 to 10 (Row Address<15:9>) to generate a memory group signal, bits 9 to 5 (Row Address<8:4>) to generate a master drive signal, and the lowest four bits (Row Address<3:0>) to generate a word line drive signal. The memory group signal activates the target memory group, the master drive signal activates the target master word line, and the word line drive signal activates the target word line. In some embodiments, each memory bank includes 128 memory groups, and each memory group includes 32 master word lines and 512 word lines (WL). The drive circuitry can activate a target master word line based on the master drive signal via one of the 32 master drivers connected to the target memory group, and activate a target word line (WL) based on the word line drive signal via one of the 16 word line drivers connected to the master driver connected to the target master word line.

[0097] In some embodiments, a plurality of the memory banks are arranged in an array along the word line direction and the bit line direction; the orthographic projection of the row decoder lies between the orthographic projections of adjacent memory banks along the bit line direction. The memory bank described herein includes memory cells that perform actual storage functions, i.e., the memory bank does not include dummy cells that do not perform actual storage functions.

[0098] It should be noted that the orthographic projection is the projection of the device structure along a vertical direction onto a reference plane, where the reference plane is the lower surface of the memory device or the plane containing the lower surface. Here, the reference plane is parallel to the bonding interface between the memory cell array and the peripheral circuitry.

[0099] Continue to refer Figures 5 and 6The plurality of memory banks are arranged in an array along the word line direction (X direction) and the bit line direction (Y direction). In embodiments of this disclosure, the peripheral circuitry and the memory cell array are formed on different substrates. The memory cell array is formed on a first substrate, and in a plan view of the first substrate, the area occupied by each memory bank on the first substrate is referred to as a first region. The peripheral circuitry is formed on a second substrate, and in a plan view of the second substrate, the area occupied by each row decoder on the second substrate is referred to as a second region. After the memory cell array is bonded to the peripheral circuitry, the orthographic projection of the second region lies between the orthographic projections of adjacent first regions along the Y direction. In some embodiments, the main driver may be disposed in the second region. In other words, the orthographic projection of the main driver lies between the orthographic projections of adjacent memory banks along the bit line direction.

[0100] In some embodiments, the orthographic projection of the drive circuit lies within the orthographic projection of the memory group.

[0101] Continue to refer Figures 5 and 6 Multiple memory blocks are arranged in an array along the word line direction (X direction) and the bit line direction (Y direction). In some embodiments, the area occupied by each memory group on the first substrate is called the third region. The area occupied by each driving circuit on the second substrate is called the fourth region. After the memory cell array is bonded to the peripheral circuitry, the third and fourth regions overlap in the vertical direction; in other words, the orthographic projection of the third region overlaps with the orthographic projection of the fourth region, and the orthographic projection of the fourth region lies within the orthographic projection of the third region.

[0102] In some embodiments, the memory blocks in each memory group are arranged in an array along the word line direction and the bit line direction; the orthographic projection of the word line driver is located between the orthographic projections of adjacent memory blocks along the word line direction. The memory cells included in the memory block herein are memory cells that perform actual storage functions; that is, the memory block does not include dummy cells that do not perform actual storage functions.

[0103] In some implementations, the area occupied by each memory block on the first substrate is referred to as the third region. The area occupied by each driver circuit on the second substrate is referred to as the fourth region. The fourth region also includes a first sub-region for hosting word line drivers, wherein, after the memory cell array is bonded to the peripheral circuitry, the orthographic projection of the first sub-region lies between the orthographic projections of adjacent third regions along the X direction.

[0104] In some embodiments, one of the word line drivers located on either side of a first memory block in a plurality of memory blocks in the orthographic projection direction is coupled to an even number line and the other is coupled to an odd number line.

[0105] Continue to refer Figure 6The word line driver may further include an even-number line driver (first WLD) and an odd-number line driver (second WLD). In some embodiments, the even-number line driver can be used to control the even-number lines of the memory block, and the odd-number line driver can be used to control the odd-number lines of the memory block. In some embodiments, the even-number line driver may be shared by the first memory block and an adjacent second memory block located to the left of the first memory block, and the odd-number line driver may be shared by the first memory block and another adjacent third memory block located to the right of the first memory block. In some embodiments, the even-number line driver can be used to control the even-number lines of the first memory block and the even-number lines of the adjacent second memory block, and the odd-number line driver can be used to control the odd-number lines of the first memory block and the odd-number lines of another adjacent third memory block.

[0106] In some implementations, even-numbered lines (e.g., WL0, WL2, WL4, WL6, WL8, WL10, WL12, WL14) can be connected to an even-numbered line driver, and odd-numbered lines (e.g., WL1, WL3, WL5, WL7, WL9, WL11, WL13, WL15) can be connected to an odd-numbered line driver.

[0107] In some embodiments, the driving circuit further includes: a first power supply circuit configured to provide a charging voltage to the plurality of word line drivers; the orthographic projection of the first power supply circuit is located within the orthographic projection of the memory block.

[0108] In some embodiments, the driving circuit further includes: a second power supply circuit configured to provide a discharge voltage to the plurality of word line drivers; the orthographic projection of the second power supply circuit is located within the orthographic projection of the memory block.

[0109] In some embodiments, the first power supply circuit is configured to provide a charging voltage to the word line drivers of the memory blocks in the corresponding memory group. In some embodiments, the second power supply circuit is configured to provide a discharging voltage to the word line drivers of the memory blocks in the corresponding memory group.

[0110] In some embodiments, the fourth region may include a second sub-region where the first power supply circuit is disposed and a third sub-region where the second power supply circuit is disposed. In some embodiments, the second sub-region and the third region at least partially overlap in the vertical direction. In other embodiments, the orthographic projection of the second sub-region lies within the orthographic projection of the third region. In some embodiments, the third sub-region and the third region at least partially overlap in the vertical direction. In other embodiments, the orthographic projection of the third sub-region lies within the orthographic projection of the third region.

[0111] Figure 11AThis is a partial schematic diagram of an exemplary memory device according to an embodiment of the present disclosure. The memory device includes a memory cell array and peripheral circuitry, which are stacked vertically. The memory cell array includes a plurality of memory blocks, and each memory block includes a plurality of memory cells.

[0112] According to this disclosure, the memory device includes a row decoder 1002 and a memory group array 1004. Note that... Figure 11A A row of storage group array 1004 is shown for illustrative purposes. It should be noted that the number of rows in the storage groups illustrated in FIG11 is not intended to limit the number of rows of storage blocks included in each storage group in this disclosure. Storage group array 1004 includes a first storage group 1006, a second storage group 1008, and a third storage group 1010. Each storage group includes at least one storage block. Embodiments according to this disclosure are not limited to having three storage groups, and various embodiments may have more or fewer storage groups. Furthermore, storage groups in any embodiment may have the same or different numbers of storage blocks.

[0113] Still refer to Figure 11A The first memory group 1006 may be coupled to word line drivers 1100-O, 1100-E, 11101-O, and 101-E, wherein word line drivers 1100-O and 1101-O are odd-number word line drivers, and word line drivers 1100-E and 1101-E are even-number word line drivers. In some embodiments, the driving circuit of the first memory group may include a first power supply circuit 1012 and a second power supply circuit 1014 coupled to the word line drivers, and the first power supply circuit 1012 and the second power supply circuit 1014 may be located between WLD Column_0 (including 1100-O and 1100-E) and WLD Column_1 (including 1101-O and 1101-E).

[0114] The second memory bank 1008 may be coupled to WLD Column_2 (including odd-number line driver 1102-0 and even-number line driver 1102-E). In some embodiments, the driving circuitry of the second memory bank may include a first power supply circuit 1016 and a second power supply circuit 1018 coupled to the word line drivers, and the first power supply circuit 1016 and the second power supply circuit 1018 may be located between the odd-number line driver 1102-0 and the even-number line driver 1102-E.

[0115] The third memory group 1010 may be coupled to word line drivers 1103-O, 1103-E, 1104-O, and 1104-E, wherein word line drivers 1103-O and 1104-O are odd-number word line drivers, and word line drivers 1103-E and 1104-E are even-number word line drivers. In some embodiments, the driving circuitry of the third memory group may include a first power supply circuit 1020 and a second power supply circuit 1022 coupled to the word line drivers, and the first power supply circuit 1020 and the second power supply circuit 1022 may be located between WLDColumn_3 (including 1103-O and 1103-E) and WLD Column_4 (including 1104-O and 1104-E).

[0116] like Figure 11A As shown, the first power supply circuits 1012, 1016, and 1020 overlap with the memory group in the vertical direction, and in some embodiments, overlap with at least one memory block in the memory group. Similarly, the second power supply circuits 1014, 1018, and 1022 overlap with the memory group in the vertical direction, and in some embodiments, overlap with at least one memory block in the memory group. In other words, the projections of the first power supply circuit 1012 and the second power supply circuit 1014 in the driving circuit of the first memory group in the vertical direction can overlap with the projection portion of at least one memory block in the first memory group 1006, and the word line drivers 1100-O, 1100-E, 1101-O, and 1101-E in the driving circuit of the first memory group can be located between the memory blocks in the first memory group 1006. The projections of the first power supply circuit 1016 and the second power supply circuit 1018 in the driving circuit of the second memory group can overlap with the projection portion of at least one memory block in the second memory group 1008. The word line drivers 1102-O and 1103-E in the driving circuit of the second memory group can be located between the memory blocks in the second memory group 1008. The projections of the first power supply circuit 1020 and the second power supply circuit 1022 in the driving circuit of the third memory group can overlap with the projection portion of at least one memory block in the third memory group 1010. The word line drivers 1103-O, 103-E, 1104-O, and 1104-E in the driving circuit of the third memory group can be located between the memory blocks in the third memory group 1010.

[0117] In some embodiments, the driving circuit further includes: a driving circuit interconnect for coupling between the first power supply circuit and the word line driver, and for coupling between the second power supply circuit and the word line driver; the orthographic projection of the driving circuit interconnect is located within the orthographic projection of the memory group, and the driving circuit interconnect extends along the word line direction.

[0118] Figure 11BThis is an enlarged schematic diagram of an exemplary first storage group 1006 according to an embodiment of this disclosure. (See also...) Figure 11B The first memory group 1006 includes a first memory block (block 0), a second memory block (block 1), a third memory block (block 2), and a first portion of a fourth memory block (i.e., the first portion of block 3). According to this disclosure, the drive circuit interconnects 1032a, 1032b, 1034a, and 1034b of the drive circuit of the first memory group can be connected to even-number line drivers and odd-number line drivers, respectively. For example, in the drive circuit interconnect XPPb<15:0>, XPPb<0,2,4,6,8,10,12,14> is connected to the even-number line driver, and XPPb<1,3,5,7,9,11,13,15> is connected to the odd-number line driver. The drive circuit interconnects 1032a, 1032b, 1034a, and 1034b extend along the X-direction within the boundary of the first memory group 1006. In other words, the drive circuit interconnects 1032a, 1032b, 1034a, and 1034b do not extend beyond the boundary of the first memory group 1006 to other memory groups. The drive circuit interconnects 1032a and 1034a coupled to the first power supply circuit 1012 occupy one set of horizontal wiring channels; the drive circuit interconnects 1032b and 1034b coupled to the second power supply circuit 1014 occupy another set of horizontal wiring channels. Here, the horizontal direction is the X-direction.

[0119] Figure 11C This is an enlarged schematic diagram of an exemplary second storage group 1008 according to an embodiment of this disclosure. (See reference...) Figure 11CThe second memory group 1008 includes a second portion of a fourth memory block (i.e., the second part of block 3), a fifth memory block (block 4), and a first portion of a sixth memory block (i.e., the first portion of block 5). According to this disclosure, the drive circuit interconnects 1036a, 1036b, 1038a, and 1038b of the drive circuit of the second memory group can be connected to even-number line drivers and odd-number line drivers, respectively. For example, in the drive circuit interconnect XPPc<15:0>, XPPc<0,2,4,6,8,10,12,14> is connected to the even-number line driver, and XPPc<1,3,5,7,9,11,13,15> is connected to the odd-number line driver. The drive circuit interconnects 1036a, 1036b, 1038a, and 1038b extend along the X-direction within the boundary of the second memory group 1008. In other words, the drive circuit interconnects 1036a, 1036b, 1038a, and 1038b do not extend beyond the boundary of the second memory group 1008 to other memory groups. The drive circuit interconnects 1036a and 1038a coupled to the first power supply circuit 1016 occupy one set of horizontal wiring channels; the drive circuit interconnects 1036b and 1038b coupled to the second power supply circuit 1018 occupy another set of horizontal wiring channels. Here, the horizontal direction is the X-direction.

[0120] Figure 11D This is an enlarged schematic diagram of an exemplary third memory group 1010 according to an embodiment of the present disclosure. The third memory group 1010 includes a second portion of a sixth memory block (i.e., the second part of block 5), a seventh memory block (block 6), an eighth memory block (block 7), and a ninth memory block (block 8). According to the present disclosure, the drive circuit interconnects 1042a, 1042b, 1044a, and 1044b of the drive circuit of the third memory group can be connected to even-number line drivers and odd-number line drivers, respectively. For example, in the drive circuit interconnect XPPa<15:0>, XPPa<0,2,4,6,8,10,12,14> is connected to the even-number line driver, and XPPa<1,3,5,7,9,11,13,15> is connected to the odd-number line driver. The drive circuit interconnects 1042a, 1042b, 1044a, and 1044b extend along the X direction within the boundary of the third memory group 1010. In other words, the drive circuit interconnects 1042a, 1042b, 1044a, and 1044b do not extend beyond the boundary of the third memory group 1010 to other memory groups. The drive circuit interconnects 1042a and 1044a coupled to the first power supply circuit 1020 occupy one set of horizontal wiring channels; the drive circuit interconnects 1042b and 1044b coupled to the second power supply circuit 1022 occupy another set of horizontal wiring channels.

[0121] Reference Figures 11B to 11DThe drive circuit interconnects 1032a and 1034a of the first memory group 1006, the drive circuit interconnects 1036a and 1038a of the second memory group 1008, and the drive circuit interconnects 1042a and 1044a of the third memory group 1010 occupy the same horizontal wiring path. Even though the drive circuit interconnects of the first, second, and third memory groups coupled to the first power supply circuit occupy the same horizontal wiring path, they are not connected to each other. Similarly, the drive circuit interconnects 1032b and 1034b of the first memory group 1006, the drive circuit interconnects 1036b and 1038b of the second memory group 1008, and the drive circuit interconnects 1042b and 1044b of the third memory group 1010 occupy the same horizontal wiring path. Even though the drive circuit interconnects of the first, second, and third memory groups coupled to the second power supply circuit occupy the same horizontal wiring path, they are not connected to each other. In other words, the drive circuit interconnects of each memory group are located within the orthographic projection range of their respective memory group (see Figure 11). Therefore, in this embodiment of the present disclosure, the wiring channels occupied by the drive circuit interconnects of each memory group are integrated so that the wiring channels occupied by the drive circuit interconnects of each memory group are shared, thereby reducing the number of horizontal wiring channels required for each memory group.

[0122] In some embodiments, the memory device includes dynamic random access memory.

[0123] In some embodiments, the memory cell array includes a plurality of memory cells, each memory cell including a vertical transistor and a capacitor.

[0124] According to the above embodiments of this disclosure, the first power supply circuit and the second power supply circuit and their coupled drive circuit interconnects are rearranged so that the first power supply circuit and the second power supply circuit and their coupled drive circuit interconnects can be arranged in the available space in the memory group, thereby reducing the area occupied by the drive circuit and thus effectively reducing the size of the memory device.

[0125] This disclosure also provides a memory system, the memory system comprising:

[0126] One or more memory devices as described in any of the above embodiments; and

[0127] A memory controller, coupled to the memory device and used to control the memory device.

[0128] Here, the specific structure and composition of the memory system can be referred to the foregoing. Figure 1 The relevant structure and composition of the memory system 102 are described below. For the sake of brevity, they will not be elaborated here.

[0129] Based on the above-described memory device, this disclosure also provides a method for manufacturing a memory device, such as... Figure 12 As shown, the method includes:

[0130] Step 1001: Form a memory cell array and multiple word lines coupled to the memory cell array;

[0131] Step 1003: Forming peripheral circuits, including forming multiple driving circuits; the driving circuits include a main driver and multiple word line drivers; each word line driver is coupled to each word line, and the main driver is connected to n word line drivers, where n is an integer greater than 8.

[0132] In some embodiments, a plurality of driving circuits are formed, including: forming a pre-charge circuit and an output circuit; the transistor size of the transistor in the output circuit is larger than the transistor size of the transistor in the pre-charge circuit.

[0133] In some embodiments, the ratio of the transistor size of the transistor in the output circuit to the transistor size of the transistor in the precharge circuit ranges from 1.5 to 2.

[0134] In some embodiments, the master driver is connected to 16 word line drivers.

[0135] In some embodiments, forming a peripheral circuit further includes: forming a row decoder, the row decoder being coupled to the driving circuit; the row decoder being configured to: decode the 9th to 5th bits of the m-bit row address signal to generate a main driving signal, and decode the lowest 4 bits of the m-bit row address signal to generate a word line driving signal, where m is an integer greater than 9; the word line driver being configured to: drive a target word line based on the main driving signal and the word line driving signal.

[0136] In some embodiments, forming a memory cell array includes: forming a memory cell array comprising a plurality of memory cells, each memory cell comprising a plurality of memory groups, each memory group comprising at least one memory block; and the orthographic projection of the drive circuit is located within the orthographic projection of the memory group.

[0137] In some embodiments, the memory blocks in the memory group are arranged in an array along the word line direction and the bit line direction; forming a plurality of driving circuits, including: forming a plurality of word line drivers, wherein the orthographic projection of the word line drivers is located between the orthographic projections of adjacent memory blocks along the word line direction.

[0138] In some embodiments, the plurality of memory banks are arranged in an array along the word line direction and the bit line direction; forming a row decoder includes: forming a row decoder whose orthographic projection is located between the orthographic projections of adjacent memory banks along the bit line direction.

[0139] In some embodiments, forming a peripheral circuit further includes forming a first power supply circuit configured to provide a charging voltage to the word line driver; the orthographic projection of the first power supply circuit lies within the orthographic projection of the memory block.

[0140] In some embodiments, forming a peripheral circuit further includes forming a second power supply circuit, the second power supply circuit being configured to provide a discharge voltage to the word line driver; the orthographic projection of the second power supply circuit is located within the orthographic projection of the memory block.

[0141] In some embodiments, forming a peripheral circuit further includes: forming a driving circuit interconnect, the driving circuit interconnect being used to couple the first power supply circuit and the word line driver, and to couple the second power supply circuit and the word line driver; the orthographic projection of the driving circuit interconnect is located within the orthographic projection of the memory group, and the driving circuit interconnect extends along the word line direction.

[0142] In some embodiments, one of the word line drivers located on either side of a first memory block in a plurality of memory blocks is coupled to an even number line and the other is coupled to an odd number line.

[0143] In some embodiments, forming a memory cell array includes forming a plurality of memory cells, each memory cell including a vertical transistor and a capacitor.

[0144] In some embodiments, forming a memory cell array includes: forming a memory cell array on a first substrate; forming a peripheral circuit includes: forming a peripheral circuit on a second substrate; the method further includes: bonding the memory cell array and the peripheral circuit.

[0145] This disclosure provides a memory device and its manufacturing method, as well as a memory system. The memory device includes: a memory cell array; multiple word lines coupled to the memory cell array; and peripheral circuitry coupled to the memory cell array via the multiple word lines. The peripheral circuitry includes: a driving circuit; the driving circuitry includes a main driver and multiple word line drivers; each word line driver is coupled to each word line, and the main driver connects to n word line drivers, where n is an integer greater than 8. In this disclosure, each main driver connects to more than 8 word line drivers, so that one main word line can drive more than 8 word lines (partial word lines), thereby greatly improving the integration density of the memory device.

[0146] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0147] The above description is only a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. All equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory device, characterized in that, The memory device includes: Storage cell array; Multiple word lines coupled to the memory cell array; and The peripheral circuitry is coupled to the memory cell array via the multiple word lines, and the peripheral circuitry includes: a driving circuitry; The driving circuit includes a main driver and multiple word line drivers; each word line driver is coupled to each word line, and the main driver is connected to n word line drivers, where n is an integer greater than 8.

2. The memory device according to claim 1, characterized in that, The main driver includes a pre-charge circuit and an output circuit; the transistor size of the transistor in the output circuit is larger than the transistor size of the transistor in the pre-charge circuit.

3. The memory device according to claim 1, characterized in that, The ratio of the transistor size in the output circuit to the transistor size in the pre-charge circuit is in the range of 1.5-2.

4. The memory device according to claim 1, characterized in that, The master driver is connected to 16 word line drivers.

5. The memory device according to claim 1, characterized in that, The peripheral circuit also includes: A row decoder, coupled to the driving circuit; the row decoder is configured to: decode the 9th to 5th bits of the m-bit row address signal to generate a main driving signal, and decode the lowest 4 bits of the m-bit row address signal to generate a word line driving signal, where m is an integer greater than 9; The driving circuit is configured to drive the target word line based on the main driving signal and the word line driving signal.

6. The memory device according to claim 1, characterized in that, The storage cell array includes multiple storage cells, each storage cell includes multiple storage groups, and each storage group includes at least one storage block; The orthographic projection of the driving circuit lies within the orthographic projection of the memory group.

7. The memory device according to claim 6, characterized in that, The memory blocks in each memory group are arranged in an array along the word line direction and the bit line direction; The orthographic projection of the word line driver lies between the orthographic projections of adjacent memory blocks along the word line direction.

8. The memory device according to claim 5, characterized in that, The plurality of the memory cells are arranged in an array along the word line direction and the bit line direction; The orthographic projection of the row decoder lies between the orthographic projections of adjacent memory cells along the bit line direction.

9. The memory device according to claim 7, characterized in that, The driving circuit also includes: A first power supply circuit is configured to provide a charging voltage to the word line driver; The orthographic projection of the first power supply circuit is located within the orthographic projection of the storage block.

10. The memory device according to claim 9, characterized in that, The driving circuit also includes: A second power supply circuit is configured to provide a discharge voltage to the word line driver; The orthographic projection of the second power supply circuit is located within the orthographic projection of the storage block.

11. The memory device according to claim 10, characterized in that, The driving circuit also includes: The driving circuit interconnect is used to realize the coupling between the first power supply circuit and the word line driver, and to realize the coupling between the second power supply circuit and the word line driver; The orthographic projection of the drive circuit interconnect is located within the orthographic projection of the memory group, and the drive circuit interconnect extends along the word line direction.

12. The memory device according to claim 7, characterized in that, One of the word line drivers located on either side of the first memory block in a plurality of memory blocks is coupled to an even number line, and the other is coupled to an odd number line.

13. The memory device according to claim 1, characterized in that, The memory cell array includes multiple memory cells, each of which includes a vertical transistor and a capacitor.

14. The memory device according to claim 1, characterized in that, The memory cell array and the peripheral circuit are formed on different substrates, and the peripheral circuit is stacked with the memory cell array in the vertical direction.

15. A memory system, characterized in that, include: The memory device as claimed in any one of claims 1 to 14; as well as Memory controller; The memory controller is coupled to the memory device and is used to control the memory device.

16. A method for manufacturing a memory device, characterized in that, The method includes: Forming a memory cell array and multiple word lines coupled to the memory cell array; The peripheral circuitry is formed by forming multiple driving circuits, each driving circuit including a main driver and multiple word line drivers; each word line driver is coupled to each word line, and the main driver is connected to n word line drivers, where n is an integer greater than 8.

17. The method for manufacturing a memory device according to claim 16, characterized in that, Multiple drive circuits are formed, including: A pre-charge circuit and an output circuit are formed; the transistor size of the transistor in the output circuit is larger than the transistor size of the transistor in the pre-charge circuit.

18. The method for manufacturing a memory device according to claim 17, characterized in that, The ratio of the transistor size in the output circuit to the transistor size in the pre-charge circuit is in the range of 1.5-2.

19. The method for manufacturing a memory device according to claim 16, characterized in that, The master driver is connected to 16 word line drivers.

20. The method for manufacturing a memory device according to claim 16, characterized in that, The formation of peripheral circuits also includes: A row decoder is formed, which is coupled to the driving circuit; the row decoder is configured to: decode the 9th to 5th bits of the row address in the m-bit row address signal to generate the main driving signal, and decode the lowest 4 bits of the row address in the m-bit row address signal to generate the word line driving signal, where m is an integer greater than 9; The word line driver is configured to drive the target word line based on the main drive signal and the word line drive signal.

21. The method for manufacturing a memory device according to claim 16, characterized in that, Forming a storage cell array includes: A storage cell array is formed, comprising multiple storage cells, each storage cell comprising multiple storage groups, and each storage group comprising at least one storage block; The orthographic projection of the driving circuit lies within the orthographic projection of the memory group.

22. The method for manufacturing a memory device according to claim 21, characterized in that, The memory blocks in the memory group are arranged in an array along the word line direction and the bit line direction; Multiple drive circuits are formed, including: Multiple word line drivers are formed, and the orthographic projection of the word line drivers is located between the orthographic projections of adjacent memory blocks along the word line direction.

23. The method for manufacturing a memory device according to claim 20, characterized in that, The plurality of the memory cells are arranged in an array along the word line direction and the bit line direction; Forming a line decoder includes: A row decoder is formed by orthographically projecting between the orthographic projections of adjacent memory cells along the bit line direction.

24. The method for manufacturing a memory device according to claim 22, characterized in that, The formation of peripheral circuits also includes: A first power supply circuit is formed, which is configured to provide a charging voltage to the word line driver; The orthographic projection of the first power supply circuit lies within the orthographic projection of the storage block.

25. The method for manufacturing a memory device according to claim 24, characterized in that, The formation of peripheral circuits also includes: A second power supply circuit is formed, which is configured to provide a discharge voltage to the word line driver; The orthographic projection of the second power supply circuit is located within the orthographic projection of the storage block.

26. The method for manufacturing a memory device according to claim 25, characterized in that, The formation of peripheral circuits also includes: A drive circuit interconnect is formed, which is used to realize the coupling between the first power supply circuit and the word line driver, and to realize the coupling between the second power supply circuit and the word line driver; The orthographic projection of the drive circuit interconnect is located within the orthographic projection of the memory group, and the drive circuit interconnect extends along the word line direction.

27. The method for manufacturing a memory device according to claim 22, characterized in that, One of the word line drivers located on either side of the first memory block in a plurality of memory blocks is coupled to an even number line, and the other is coupled to an odd number line.

28. The method for manufacturing a memory device according to claim 16, characterized in that, Forming a storage cell array includes: Multiple memory cells are formed, each memory cell including a vertical transistor and a capacitor.

29. The method for manufacturing a memory device according to claim 16, characterized in that, Forming a storage cell array includes: A memory cell array is formed on the first substrate; Forming the peripheral circuit includes: The peripheral circuit is formed on the second substrate; The method further includes: The memory cell array and the peripheral circuitry are bonded together.

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