Gain-adjustable low-noise amplifier and design method thereof

Abstract

The invention discloses a gain-adjustable low-noise amplifier and a design method thereof, and belongs to the technical field of radio frequency integrated circuits. In order to solve the problems that in the prior art, when a gain-adjustable low-noise amplifier is used for adjusting the gain, a large phase difference is easily introduced, and multiple performance indexes and the integration level are difficult to consider, the invention provides a design scheme that a common-source amplifier with a source inductance negative feedback structure is adopted as an input stage; wherein the source series inductor is designed into a reconfigurable structure comprising at least two inductor units and corresponding bypass switches; the total inductance value of the source electrode connected to the circuit is changed by controlling the state of the bypass switch so as to adjust the gain, and the parameters of the input matching network and the output matching network are cooperatively adjusted so as to maintain impedance matching. The invention has the beneficial effects that very small phase difference can be realized among different gain gears, signal distortion is reduced, flexible gain adjustment is realized, linearity and stability are improved, the chip area is effectively reduced, and the integration level is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a gain-adjustable low-noise amplifier and its design method. Background Technology

[0002] With the rapid development of wireless communication technology and the continuous evolution of market demands, such as from GSM and UMTS to LTE and newer communication standards, radio frequency (RF) front-end receivers are constantly evolving towards higher integration, higher performance, and lower power consumption. As the first active amplification stage in the RF receiver link, the low-noise amplifier (LNA) plays a crucial role in the sensitivity and dynamic range of the entire receiver.

[0003] To adapt to application scenarios with different communication standards and meet the operational requirements of different frequency bands and input signal power intensities, modern wireless communication systems place higher demands on LNAs. Specifically, LNAs not only need to achieve high gain and low noise figure (NF) within the target operating frequency band, but also need to have adjustable gain to adapt to input signals of varying strengths, avoid saturation distortion in subsequent circuits, and optimize the dynamic range of the entire receiver link.

[0004] Currently, the common source, common gate architecture is one of the commonly used topologies in LNA design (e.g., Figure 2 As shown in the figure, LNAs are widely used due to their good input-output isolation and high output impedance. To achieve multi-standard, multi-band applications, a common approach is to use a reconfigurable LNA architecture (such as...). Figure 1 (As shown). This architecture is more advantageous in reducing power consumption, saving chip area, and improving integration compared to designing separate LNA links for each frequency band or standard.

[0005] However, existing variable gain LNA design methods often face challenges in achieving gain adjustment. For example, some methods that adjust gain by changing bias current or load impedance may adversely affect noise figure, linearity, or operating bandwidth. Other methods that switch between different amplification paths or matching network components, while achieving gain level switching, may introduce significant phase differences between different gain levels. Large phase differences increase signal processing complexity and can even lead to signal distortion, especially in applications requiring rapid gain level switching. Furthermore, achieving wide-range, finely adjustable gain while maintaining high integration and low power consumption, while simultaneously optimizing noise, linearity, stability, and phase consistency between different gain levels, remains a crucial challenge in LNA design.

[0006] Therefore, there is an urgent need to propose a new LNA design method that can effectively control the phase difference between different gain levels while realizing the variable gain function required for multi-band and multi-standard applications, and take into account key performance indicators such as noise, linearity, stability and chip area. Summary of the Invention

[0007] The technical problem to be solved by this invention is that, when adjusting the gain of an existing gain-adjustable low-noise amplifier, it is often difficult to take into account multiple aspects such as phase difference, noise performance, linearity, stability and chip integration between different gain levels. In particular, how to maintain a low phase difference while achieving flexible gain adjustment in order to reduce signal distortion is an urgent problem to be solved in the design of radio frequency receivers.

[0008] To address the aforementioned technical problems, this invention provides a design method for a gain-adjustable low-noise amplifier, comprising the following steps:

[0009] Step 1: Provide an input stage circuit. The input stage circuit adopts a common-source amplifier topology with a source inductor negative feedback structure. The source inductor negative feedback structure includes at least two source inductor units connected in series and at least one bypass switch corresponding to the source inductor unit.

[0010] Step 2: According to the preset gain level, control the on / off state of at least one bypass switch to change the total inductance value of the source inductor unit connected to the input stage circuit, thereby adjusting the gain of the low noise amplifier.

[0011] Step 3: Based on the change in the total inductance value, adjust the capacitance value of the variable capacitor element in the input matching network connected to the input stage circuit in a coordinated manner to achieve input impedance matching;

[0012] Step 4: Based on the change in the total inductance value, adjust the parameters of the variable inductor or variable capacitor in the output matching network connected to the output terminal of the low-noise amplifier in a coordinated manner to achieve output impedance matching.

[0013] Preferably, the input stage circuit adopts a common-source, common-gate amplifier topology.

[0014] Preferably, the common-source amplifier topology or common-source cascode amplifier topology uses metal-oxide-semiconductor field-effect transistors, bipolar junction transistors, or heterojunction bipolar transistors as amplification elements.

[0015] Preferably, step three further includes: adjusting the inductance value of the series inductor element in the input matching network in a coordinated manner according to the change in the total inductance value.

[0016] Preferably, the source inductor unit is an on-chip spiral inductor, and the bypass switch is implemented by leading out taps at different positions of the on-chip spiral inductor and connecting them to a switching transistor; the variable capacitor element is implemented by connecting multiple capacitor units in parallel and controlling their connection state through a switching transistor.

[0017] Preferably, there are at least two preset gain levels.

[0018] Preferably, the preset gain level is selected by a control circuit based on externally input communication standards, operating frequency bands, and signal power strength information.

[0019] Preferably, the low-noise amplifier is fabricated on a bulk silicon, high-resistivity silicon, or silicon-on-insulator substrate.

[0020] Furthermore, the present invention also provides a gain-adjustable low-noise amplifier, comprising:

[0021] The input stage circuit adopts a common-source amplifier topology with a source inductor negative feedback structure. The source inductor negative feedback structure includes at least two source inductor units connected in series and at least one bypass switch corresponding to the source inductor unit. The bypass switch is used to change the total inductance value of the source inductor units connected to the input stage circuit.

[0022] An input matching network, connected to the input stage circuit, includes a variable capacitor element whose capacitance value is adjusted in tandem with the change in the total inductance value to achieve input impedance matching.

[0023] An output matching network, connected to the output of the low-noise amplifier, includes a variable inductor or variable capacitor element whose parameters are coordinated to adjust according to the change in the total inductance value to achieve output impedance matching.

[0024] The control circuit is used to control the on / off state of the bypass switch and to coordinately adjust the parameters of the input matching network and the output matching network according to the preset gain level.

[0025] Preferably, the input stage circuit adopts a common-source, common-gate amplifier topology.

[0026] Preferably, the common-source amplifier topology or common-source cascode amplifier topology uses metal-oxide-semiconductor field-effect transistors, bipolar junction transistors, or heterojunction bipolar transistors as amplification elements.

[0027] Preferably, the input matching network further includes a series inductor element, the inductance value of which is adjusted collaboratively according to the change in the total inductance value.

[0028] Preferably, the source inductor unit is an on-chip spiral inductor, and the bypass switch is implemented by leading out taps at different positions of the on-chip spiral inductor and connecting them to a switching transistor; the variable capacitor element is implemented by connecting multiple capacitor units in parallel and controlling their connection state through a switching transistor.

[0029] Preferably, there are at least two preset gain levels.

[0030] Preferably, the control circuit receives externally input communication standard, operating frequency band, and signal power strength information to determine the preset gain level.

[0031] Preferably, the low-noise amplifier is fabricated on a bulk silicon, high-resistivity silicon, or silicon-on-insulator substrate.

[0032] As described above, the gain-adjustable low-noise amplifier and its design method of the present invention have the following beneficial effects:

[0033] The gain adjustment in this invention is primarily achieved by changing the value of the source series inductor, which is not located on the main path of the input high-frequency signal. Simultaneously, only the input and output matching networks are adjusted collaboratively. Compared to switching the entire amplification path or introducing switching elements into the signal path, this method can achieve a very small phase difference between different gain levels, which helps reduce signal distortion and is particularly suitable for communication systems with high phase consistency requirements. Furthermore, the presence of the source series inductor can also improve the stability and linearity of the circuit under different signal strengths. Generally, the larger the series inductance value, the higher the linearity and stability of the amplifier (but this requires a trade-off between gain requirements and out-of-band stability). Using a reconfigurable architecture based on the source inductor avoids the need for multiple parallel amplifiers to achieve gain adjustment, thereby significantly reducing chip area, increasing integration density, and lowering cost and power consumption. Attached Figure Description

[0034] Figure 1 The diagram shows a reconfigurable LNA architecture as described in the prior art.

[0035] Figure 2 The diagram shows a common-source, common-gate architecture of the prior art.

[0036] Figure 3 The diagram shown is a schematic diagram of the gain-adjustable low-noise amplifier circuit structure of the present invention.

[0037] Figure 4 The diagram shown illustrates that the source inductor unit of this invention is an on-chip spiral inductor.

[0038] Figure 5 The diagram shown illustrates the design method of the gain-adjustable low-noise amplifier of the present invention. Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Please see Figure 5 This invention provides a design method for a gain-adjustable low-noise amplifier, characterized by the following steps:

[0041] Step 1: Provide the input stage circuit. The input stage circuit adopts a common-source amplifier topology with a source-inductor negative feedback structure. The source-inductor negative feedback structure includes at least two source inductor units connected in series (e.g., Figure 3 Ls1 to Lsn) and at least one bypass switch (e.g., Ls1 to Lsn) corresponding to the source inductor unit Figure 3 In the amplifier, SW1 to SWn are controlled by control voltages Vctrl1 to Vctrln. This source inductor negative feedback structure helps improve the linearity and stability of the amplifier.

[0042] In some embodiments, the input stage circuit employs a cascode amplifier topology. The cascode topology offers good input-output isolation and high output impedance, which is beneficial for improving the amplifier's high-frequency performance and stability.

[0043] In some embodiments, the common-source amplifier topology or the common-source cascode amplifier topology uses a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), or a heterojunction bipolar transistor (HBT) as the amplification element. This specification uses a MOSFET as an example, but those skilled in the art will understand that similar functionality can be achieved using a BJT or HBT.

[0044] In some embodiments, the low-noise amplifier is fabricated on a bulk silicon (Bulk Si), high-resistivity silicon (HR Si), or silicon-on-insulator (SOI) substrate. High-resistivity silicon or SOI substrates are preferred to improve the quality factor (Q value) of on-chip passive devices (such as inductors and capacitors) and thus reduce losses.

[0045] Step 2: Based on the preset gain level, control the on / off state of at least one bypass switch to change the total inductance value L (L = Ls1 + Lsi + ... + Lsn, where Lsi represents the i-th source inductor unit) of the source inductor unit connected to the input stage circuit, thereby adjusting the gain of the low-noise amplifier. When a bypass switch is turned on, its corresponding source inductor unit Lsi is short-circuited, thus reducing the total source series inductance value. By controlling different combinations of switches, multiple different total inductance values ​​can be achieved, corresponding to different gain levels. This reconfigurable method of controlling the source inductor through switches allows for flexible gain adjustment.

[0046] In some embodiments, there are at least two preset gain levels. The more levels there are, the finer the gain adjustment and the stronger the ability to adapt to different signal strengths.

[0047] In some embodiments, the preset gain level is determined by a control circuit based on externally input communication standards, operating frequency bands, and signal power strength information. For example, a filter and signal strength detector control circuit can be combined to automatically select an appropriate inductance value (i.e., an appropriate gain level) based on the frequency band and strength of the input signal, achieving coordinated adjustment and optimizing the receiver's performance under different operating conditions.

[0048] Step 3: Based on the change in total inductance, adjust the variable capacitor elements (e.g., ...) in the input matching network connected to the input stage circuit accordingly. Figure 3The input matching network (including the parallel capacitor C, C1 through Cn, and the switch control) is used to adjust the capacitance value to achieve input impedance matching. Changes in the source inductance value affect the input impedance (e.g., Z_in = V_in / I_in = jωL_g+1 / jω(C_gs+C_ex+C_1+…+C_n)+jω(Ls_1+Ls_i+…+Ls_n)+g_m / C_gs+C_ex+C_1+…+C_n(Ls_1+Ls_i+…+Ls_n)). Therefore, the input matching network needs to be adjusted to re-achieve impedance matching (e.g., satisfying the goal of input impedance Zin≈Rs), thereby ensuring effective signal transmission and a low noise figure. The input matching network typically includes parallel capacitors and series inductors.

[0049] In some embodiments, see Figure 4 The source inductor is an on-chip spiral inductor. The bypass switch is implemented by leading taps from different positions of the on-chip spiral inductor and connecting them to a switching transistor (usually a MOSFET). The variable capacitor element is implemented by connecting multiple capacitor units (such as C1 to Cn) in parallel and controlling their connection state through a switching transistor. This integrated implementation method helps to reduce chip size and parasitic parameters.

[0050] In some embodiments, step three further includes: coordinating the inductance value of the series inductor element (Lg) in the input matching network according to the change in the total inductance value. Adjusting Lg can further optimize input matching and noise matching (e.g., Re{Z_in}=jωL_g+1 / jω(C_gs+C_ex+C_1+…+C_n)+jω(Ls_1+Ls_i+…+Ls_n)=0, Im{Z_in}=g_m / C_gs+C_ex+C_1+…+C_n(Ls_1+Ls_i+…+Ls_n)=50Ω), achieving better noise performance at different gain levels.

[0051] Step 4: Based on the change in total inductance, adjust the variable inductance element (e.g., ...) in the output matching network connected to the low-noise amplifier output terminal accordingly. Figure 3 Ld in the figure consists of Ld1 to Ldn) or variable capacitor elements (e.g. Figure 3 The parameters of Cout (composed of Cd and C1 to Cn) are adjusted to achieve output impedance matching. A change in the total inductance L of the source series inductor leads to a change in the equivalent transconductance Gm, which in turn affects the amplifier's output impedance Zout (e.g., A_v = -G_mR_D = -g_mR_D / 1 + g_mR_s). To efficiently transmit the signal to the next stage circuit (such as a mixer), the parameters of the output matching network (usually an LC network) need to be adjusted to conjugate match with the input impedance or standard impedance (e.g., 50 ohms) of the next stage circuit.

[0052] A significant advantage of this design approach is that gain adjustment is primarily achieved by changing the source series inductance value, which is not located on the main path of the input high-frequency signal. Furthermore, only the input and output matching networks are adjusted collaboratively. Compared to switching the entire amplification path or introducing switching elements into the signal path, this method can achieve a very small phase difference between different gain levels, which helps reduce signal distortion and is particularly suitable for communication systems with high phase consistency requirements. In addition, the presence of the source series inductance can also improve the stability and linearity of the circuit under different signal strengths. Generally, a larger series inductance value results in higher amplifier linearity and stability (but this requires a trade-off between gain requirements and out-of-band stability). Using a reconfigurable architecture based on source inductors avoids the need for multiple parallel amplifiers to achieve gain adjustment, thereby significantly reducing chip area, increasing integration density, and lowering cost and power consumption.

[0053] Please see Figure 3 The present invention also provides a gain-adjustable low-noise amplifier, characterized in that it comprises:

[0054] The input stage circuit adopts a common-source amplifier topology with a source-inductor negative feedback structure. The source-inductor negative feedback structure includes at least two source inductor units connected in series (such as Ls1 to Lsn) and at least one bypass switch (such as SW1 to SWn) corresponding to the source inductor units. The bypass switch is used to change the total inductance value of the source inductor units connected to the input stage circuit. By controlling the opening and closing of the bypass switch, some source inductor units can be selectively short-circuited, thereby changing the equivalent total source inductance.

[0055] In some embodiments, the input stage circuitry employs a cascode amplifier topology. The cascode structure provides higher gain and better reverse isolation.

[0056] In some embodiments, the common-source amplifier topology or the common-source cascode amplifier topology uses a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), or a heterojunction bipolar transistor (HBT) as the amplification element.

[0057] In some embodiments, the amplifier is fabricated on a bulk silicon (Bulk Si), high-resistivity silicon (HR Si), or silicon-on-insulator (SOI) substrate. High-resistivity silicon or SOI substrates are preferred to improve the performance of passive devices.

[0058] The input matching network, connected to the input stage circuit, includes variable capacitor elements (such as a parallel capacitor network C). The capacitance value of the variable capacitor elements is adjusted in tandem with the change in the total inductance value to achieve input impedance matching; ensuring that the amplifier's input port presents the required impedance (e.g., 50 ohms) at different gains (i.e., different source inductance values) to maximize power transfer and minimize reflections.

[0059] In some embodiments, the input matching network further includes a series inductor (such as Lg) whose inductance value is coordinated with changes in the total inductance. Adjusting the series inductance helps to simultaneously optimize noise matching and input impedance matching.

[0060] The output matching network, connected to the output of the low-noise amplifier, includes a variable inductor (such as Ld) or a variable capacitor (such as Cout). The parameters of the variable inductor or capacitor are adjusted in tandem according to the change in the total inductance value to achieve output impedance matching, ensuring that the amplifier's output signal can be efficiently transmitted to subsequent circuits.

[0061] The control circuit (not explicitly shown in the figure, but implicitly present, used to generate signals from Vctrl1 to Vctrln and to control the input and output matching network switches) is used to control the on / off state of the bypass switch and to coordinately adjust the parameters of the input and output matching networks according to the preset gain level.

[0062] In some embodiments, see Figure 4 The source inductor is an on-chip spiral inductor. The bypass switch is implemented by leading taps from different positions of the on-chip spiral inductor and connecting them to a switching transistor (usually a MOSFET). The variable capacitor element is implemented by connecting multiple capacitor units (such as C1 to Cn) in parallel and controlling their connection state through a switching transistor. This integrated implementation method helps to reduce chip size and parasitic parameters.

[0063] In some embodiments, there are at least two preset gain levels.

[0064] In some embodiments, the control circuit receives external input information such as communication standard, operating frequency band, and signal power intensity to determine a preset gain level. This enables the amplifier to intelligently adapt to different operating environments and signal conditions.

[0065] The gain-adjustable low-noise amplifier and its design method proposed in this invention achieve flexible gain adjustment through reconfigurable source inductor negative feedback combined with a collaboratively adjusted input-output matching network. At the same time, it effectively controls the phase difference between different gain levels and takes into account performance such as noise, linearity, stability, chip area and power consumption. It is suitable for high-performance, highly integrated multi-band, multi-standard RF receiver applications.

[0066] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A design method for a gain-adjustable low-noise amplifier, characterized in that, At least including: Step 1: Provide an input stage circuit. The input stage circuit adopts a common-source amplifier topology with a source inductor negative feedback structure. The source inductor negative feedback structure includes at least two source inductor units connected in series and at least one bypass switch corresponding to the source inductor unit. Step 2: According to the preset gain level, control the on / off state of at least one bypass switch to change the total inductance value of the source inductor unit connected to the input stage circuit, thereby adjusting the gain of the low noise amplifier. Step 3: Based on the change in the total inductance value, adjust the capacitance value of the variable capacitor element in the input matching network connected to the input stage circuit in a coordinated manner to achieve input impedance matching; Step 4: Based on the change in the total inductance value, adjust the parameters of the variable inductor or variable capacitor in the output matching network connected to the output terminal of the low-noise amplifier in a coordinated manner to achieve output impedance matching.

2. The design method of the gain-adjustable low-noise amplifier according to claim 1, characterized in that: The input stage circuit adopts a common-source, common-gate amplifier topology.

3. The design method of the gain-adjustable low-noise amplifier according to claim 1 or 2, characterized in that: The common-source amplifier topology or common-source cascode amplifier topology uses metal-oxide-semiconductor field-effect transistors, bipolar junction transistors, or heterojunction bipolar transistors as amplification elements.

4. The design method of the gain-adjustable low-noise amplifier according to claim 1, characterized in that: Step three further includes: adjusting the inductance value of the series inductor element in the input matching network in a coordinated manner according to the change in the total inductance value.

5. The design method of the gain-adjustable low-noise amplifier according to claim 1, characterized in that: The source inductor unit is an on-chip spiral inductor, and the bypass switch is implemented by leading out taps at different positions of the on-chip spiral inductor and connecting them to a switching transistor; the variable capacitor element is implemented by connecting multiple capacitor units in parallel and controlling their connection state through a switching transistor.

6. The design method of the gain-adjustable low-noise amplifier according to claim 1, characterized in that: The preset gain levels are at least two.

7. The design method of the gain-adjustable low-noise amplifier according to claim 1, characterized in that: The preset gain level is selected based on the externally input communication standard, operating frequency band, and signal power strength information, and is determined by the control circuit.

8. The design method of the gain-adjustable low-noise amplifier according to claim 1, characterized in that: The low-noise amplifier is fabricated on a bulk silicon, high-resistivity silicon, or silicon-on-insulator substrate.

9. A gain-adjustable low-noise amplifier, characterized in that, include: The input stage circuit adopts a common-source amplifier topology with a source inductor negative feedback structure. The source inductor negative feedback structure includes at least two source inductor units connected in series and at least one bypass switch corresponding to the source inductor units. The bypass switch is used to change the total inductance value of the source inductor units connected to the input stage circuit. An input matching network, connected to the input stage circuit, includes a variable capacitor element whose capacitance value is adjusted in coordination with the change of the total inductance value to achieve input impedance matching. An output matching network, connected to the output of the low-noise amplifier, includes a variable inductor or a variable capacitor. The parameters of the variable inductor or variable capacitor are adjusted in tandem according to the change in the total inductance value to achieve output impedance matching. The control circuit is used to control the on / off state of the bypass switch and to coordinately adjust the parameters of the input matching network and the output matching network according to a preset gain level.

10. The gain-adjustable low-noise amplifier according to claim 9, characterized in that: The input stage circuit adopts a common-source, common-gate amplifier topology.

11. The gain-adjustable low-noise amplifier according to claim 9 or 10, characterized in that: The common-source amplifier topology or common-source cascode amplifier topology uses metal-oxide-semiconductor field-effect transistors, bipolar junction transistors, or heterojunction bipolar transistors as amplification elements.

12. The gain-adjustable low-noise amplifier according to claim 9, characterized in that: The input matching network further includes a series inductor element whose inductance value is adjusted collaboratively according to the change in the total inductance value.

13. The gain-adjustable low-noise amplifier according to claim 9, characterized in that: The source inductor unit is an on-chip spiral inductor, and the bypass switch is implemented by leading out taps at different positions of the on-chip spiral inductor and connecting them to a switching transistor. The variable capacitor element is implemented by connecting multiple capacitor units in parallel and controlling their connection state through a switching transistor.

14. The gain-adjustable low-noise amplifier according to claim 9, characterized in that: The preset gain levels are at least two.

15. The gain-adjustable low-noise amplifier according to claim 9, characterized in that: The control circuit receives externally input communication standards, operating frequency bands, and signal power strength information to determine the preset gain level.

16. The gain-adjustable low-noise amplifier according to claim 9, characterized in that: The low-noise amplifier is fabricated on a bulk silicon, high-resistivity silicon, or silicon-on-insulator substrate.

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