A charging pile signal and communication message synchronous recording device

Abstract

The application relates to the field of charging pile signal recording and wave device, and particularly discloses a charging pile signal and communication message synchronous recording and wave device, which comprises a collection module, a control module and an interface simulation module; the interface simulation module is used for recording message signals and generating message trigger signals; the interface simulation module is also used for recording message data types, data times and data intervals which need to be monitored and uploading the data to the control module; when the interface simulation module detects the message, the message trigger signal is triggered, the collection module simultaneously records the message trigger signal and other channel signals, and uploads the data to the control module; the control module takes the trigger signal as a reference, and draws the message data types, times and intervals on the recording waveforms, so that a timing diagram combining the waveforms and the messages is finally presented. The application solves the problems of high cost, limitation on the recorder manufacturers, inflexibility and uncontrollability of the conventional method.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of charging pile signal recording device, in particular to a charging pile signal and communication message synchronous recording device. BACKGROUND

[0002] At present, with the large popularity of electric vehicles, the demand for charging infrastructure is increasing, and the detection of charging piles becomes particularly important. In the detection of charging piles, it can be roughly divided into protocol consistency detection and interoperability detection. In interoperability detection, some detection items need to combine messages and corresponding charging pile signals to judge whether the detection items are qualified, such as charging connection control timing test and other items. The conventional implementation method is to use a recording instrument combined with a corresponding CAN communication monitoring module (as shown in the specific principle of Figure 1 The use of an oscilloscope or a recording instrument is expensive, and the channel configuration is not flexible. The number of channels of the oscilloscope is limited, and at most 4 channels. The CAN message and the terminal signal time cannot be accurately synchronized, resulting in differences in test results, and being limited by the recording instrument manufacturer, not flexible and not self-controllable. SUMMARY

[0003] The present application proposes a charging pile signal and communication message synchronous recording device to solve the defects of the prior art, such as high cost, inflexible channel configuration, limited number of channels of the oscilloscope, resulting in differences in test results, and not being self-controllable.

[0004] The technical scheme adopted by the present application is as follows:

[0005] A charging pile signal and communication message synchronous recording device, comprising:

[0006] a collection module;

[0007] a control module; and

[0008] an interface simulation module; the interface simulation module is used to record message signals and generate message trigger signals; the interface simulation module is also used to record the message data type, data times, and data interval that need to be monitored, and upload them to the control module; when the interface simulation module detects the message, the message trigger signal is triggered, the collection module records the message trigger signal and other channel signals at the same time, and uploads the data to the control module; the control module takes the trigger signal as the reference to depict the message data type, times, and interval on the recording waveform, and finally presents a timing diagram combining the waveform and the message.

[0009] Optionally, the collection module uses a 32-bit ARM processor and an 8-channel ADC.

[0010] Optionally, the ADC adopts a 16-bit ADC and is built-in 8-channel measurement, and the 8 channels respectively measure DC+DC-, DCI, CC1, sending message signal, receiving message signal and two reserved signals.

[0011] Optionally, the acquisition module adopts a CPLD mode to control the sampling frequency, and the time error between each data is less than 0.1 us.

[0012] Optionally, the control module adopts a PC.

[0013] Optionally, the acquisition module and the control module adopt a USB mode for communication.

[0014] The application further discloses a use method of the charging pile signal and communication message synchronous recording device, which is applied to the charging pile signal and communication message synchronous recording device and comprises the following steps.

[0015] 1) Start BMS and charging pile communication to charge, and in the charging process, the interface simulation module monitors CAN communication messages, and monitors the messages; or triggers the high-speed acquisition card to receive the message channel at a predetermined message; or a sending channel;

[0016] 2) When the charging is completed, record data of the channel is obtained from the acquisition module and saved to a local file;

[0017] 3) Record message data is obtained from the interface simulation module;

[0018] 4) Each message channel data is fitted according to the channel record data and all message data, and is saved to a local file;

[0019] 5) The charging pile signal channel local file and the generated each message local file are loaded, the control module takes the trigger signal as a reference, and message data types, times and intervals are depicted on a recording waveform, and finally a time sequence diagram combining the waveform and the message is presented.

[0020] Optionally, the message data comprises sending times, average time, maximum interval time, minimum interval time and first frame time.

[0021] Optionally, the specific fitting process in step 5) comprises:

[0022] a. The number of points of the receiving message channel or the sending message channel of the acquisition card is obtained, and initialization is performed;

[0023] b. The trigger position is found from the receiving message channel or the sending message of the acquisition card, and the receiving message channel or the sending message channel is traversed, and when the record data is less than or equal to 0.1*channel variable ratio*0.95, the trigger position is found.

[0024] c. Find the relative collection card time point of each message, and update it in a loop;

[0025] d. The updated data is saved to a local file.

[0026] Optionally, it further includes a clearing step, which specifically includes: sending a reset command to the interface simulation module to clear the message record.

[0027] The beneficial effects of the present application at least include:

[0028] In the present application, the collection module is matched with the interface simulation module to realize charging pile signal recording and communication message recording, and the time reference is based on the high-speed collection card, avoiding the influence of PC message analysis, communication and other delays. The present application solves the problems of high cost, limitation by wave recorder manufacturers, inflexibility and inability to achieve self-control in the conventional method.

[0029] The present application significantly reduces the probability of false triggering caused by noise interference by dynamically adapting to input signals of different ranges through double coefficients.

[0030] The cycle update time point mechanism in the present application, combined with DMA channel transmission technology, realizes millisecond-level data stream synchronous update, avoiding the fitting distortion caused by data delay in the traditional interpolation method.

[0031] In the initialization stage (step a) of the present application, the collection card channel granularity is accurately controlled, and the localized storage strategy of step d is used to reduce memory occupation by more than 40%, which is especially suitable for long-term continuous monitoring scenarios.

[0032] The present application effectively overcomes the problem of hardware clock drift by traversing the message channel to locate the trigger position (step b) and combining the relative timestamp calibration (step c), and still maintains a fitting accuracy of more than 95% in a strong electromagnetic interference environment. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is the working principle diagram of the wave recorder matched with the corresponding CAN communication monitoring module in the prior art;

[0034] Figure 2 is the principle diagram of a charging pile signal and communication message synchronous recording device of embodiment 1 of the present application;

[0035] Figure 3 is the principle diagram of a collection module of a charging pile signal and communication message synchronous recording device of embodiment 1 of the present application;

[0036] Figure 4 is the flowchart of the use method of a charging pile signal and communication message synchronous recording device of embodiment 2 of the present application. DETAILED DESCRIPTION

[0037] The specific embodiments of the present application are described in further detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present application but are not intended to limit the scope of the present application.

[0038] In the description of the present application, CAN message is the basic unit of Controller Area Network (CAN) bus communication, including frame start, arbitration field, control field, data field, CRC field, ACK field and frame end, etc., used for data transmission between nodes. CPLD is the abbreviation of Complex Programmable Logic Device. "CPLD mode" generally refers to the design and implementation method using complex programmable logic device.

[0039] ADC (Analog-to-Digital Converter) refers to an analog-to-digital converter in a software environment, and its core function is to convert continuous analog signals (such as voltage, current) into discrete digital signals for digital system (such as microcontroller, processor) processing and analysis.

[0040] In power system test instruments, "channel variable ratio" refers to the voltage or current transformation ratio setting of each channel of the device, which is used to ensure the measurement accuracy.

[0041] In the present application, DCI (Downlink Control Information) is the key control information transmitted through physical layer signaling in a wireless communication system.

[0042] In the present application, DC signal refers to Direct Current signal, i.e. voltage or current signal whose direction and time remain unchanged.

[0043] CC signal (Control Channel) is an important mechanism for transmitting signaling or synchronization data in a communication system, mainly realizing connection control and synchronization operation between devices. In digital cellular communication, CC signal is divided into three types of broadcast, public and private, responsible for paging, access and large amount of data transmission. For example, between base station and mobile station, downlink channel is used for paging, and uplink channel is used for calling.

[0044] Example 1

[0045] The technical solutions adopted by the present application are as follows:

[0046] As Figure 2As shown, the application discloses a charging pile signal and communication message synchronous recording device, which comprises a collection module, an interface simulation module and a control module; the interface simulation module is used for recording message signals and generating message trigger signals; the interface simulation module is also used for recording the message data types, data times and data intervals that need to be monitored and uploading them to the control module; when the interface simulation module detects the message, the message trigger signal is triggered, the collection module simultaneously records the message trigger signal and other channel signals, and uploads the data to the control module; the control module takes the trigger signal as the reference to depict the message data types, times and intervals on the recording waveform, and finally presents a timing diagram combining the waveform and the message. The message is a CAN message.

[0047] The collection module adopts a high-speed collection card, which comprises a 32-bit ARM high-speed processor and an 8-channel high-speed ADC. The control module adopts a PC. The ADC adopts a 16-bit high-precision ADC and is internally provided with 8-channel measurement. The 8 channels are used to measure DC+DC- signals, DCI signals, CC1 signals, sending message signals, receiving message signals and two reserved signals respectively.

[0048] Specifically, in the embodiment, the high-speed collection card principle is as shown in the figure. Figure 3 The 32-bit ARM high-speed processor and the 8-channel high-speed ADC are adopted, the sampling frequency is controlled in the CPLD mode, the highest sampling frequency can reach 500KHz, the time error between each data is less than 0.1us, and the time accuracy of the collected data is ensured. The PC is communicated in the USB mode, and the data transmission speed is fast. The 16-bit high-precision ADC is adopted, and 8-channel measurement is internally provided. The eight channels are used to measure DC+DC- signals, DCI signals, CC1 signals, sending message signals, receiving message signals and two reserved signals respectively.

[0049] The interface simulation module is mainly responsible for recording CAN message signals and generating message trigger signals. When the PC informs the interface simulation module of when to start recording the message and the trigger signal during the test project, the interface simulation module detects the message, the message trigger signal is triggered, the high-speed collection card simultaneously records the message trigger signal and other channel signals, and uploads the data to the PC. The PC takes the message trigger signal as the time origin and the collection card data interval as the time reference to draw the recording waveform. The interface simulation module records the message data types, data times and data intervals that need to be monitored and uploads them to the PC. The PC takes the trigger signal as the reference to depict the message data types, times and intervals on the recording waveform, and finally presents a timing diagram combining the waveform and the message.

[0050] In this embodiment, the host computer is a PC. The message is a CAN message. The host computer software will read the message record in the interface simulation module, synchronize to the signal waveform of the acquisition card, and fit the waveform. The host computer software uses the ScottPlot open source module for 2 times of development, and displays the waveform.

[0051] Embodiment 2

[0052] As Figure 4 shown, the application also discloses a use method of the charging pile signal and communication message synchronous recording device, which comprises the following steps:

[0053] 1) Set the interface simulation module message record parameters; set the message record type, record all messages or record a certain message, marked as a predetermined message.

[0054] 2) Set the high-speed acquisition card channel and parameters; wherein, the fixed channel 5 is the message receiving channel, the channel 6 is the message sending channel, and the other channel types can be dynamically set according to the test project.

[0055] 3) Start the interface simulation module message record.

[0056] 4) Start the high-speed acquisition card data acquisition.

[0057] 5) Start BMS and charging pile communication for charging. During the charging process, the interface simulation module monitors the CAN communication message, and triggers the high-speed acquisition card receiving message channel or sending channel when the CHM message or the predetermined message is monitored, so as to ensure the synchronization of signal quantity and message time.

[0058] 6) End of charging.

[0059] 7) Get the channel record data from the high-speed acquisition card and save it to the local file.

[0060] 8) Get the recorded message data from the interface simulation module. The message data format is: [SendNum, AVGt, MaxT, MinT, FirstT], through SendNum and AVGt, the message duration FrameT = (SendNum-1)*AVGt is calculated; FirstT is the time when the first message CHM message or predetermined message is received.

[0061] 9) Fit each message channel data according to the channel record data and all message data, and save it to the local file. The specific fitting process is as follows:

[0062] a. Get the point number of the receiving message channel or the sending message channel of the acquisition card as PointTotalNum, and initialize lDataFile[FrameNum][PointNum] = 0. FrameNum is the message channel number, not more than the total number of message types, PointNum is the data number, 0≤PointNum≤PointTotalNum, and PointTotalNum is the point number.

[0063] b. Find the trigger position from the receiving message channel or the sending message of the acquisition card, that is, find the time point of the CHM message or the predetermined message; traverse the receiving message channel or the sending message channel, and when the recorded data≤0.1*channel variable ratio*0.95, it is the trigger position, which is marked as Index.

[0064] c. Find the time point of each message relative to the acquisition card through FirstT+Index+1, FrameT is the sending time length of the message; update lDataFile[i][j] = Value in a loop; 0≤i≤FrameNum, FirstT+Index+1≤j≤FrameT+Index+1, and Value is a self-defined fixed value.

[0065] d. Save the data of lDataFile[FrameNum][PointNum] to a local file, and the file format of the application is.dat.

[0066] 10) The host computer software loads the local file of the charging pile signal channel and the generated local file of each message, and draws a waveform graph. The PC takes the trigger signal as the reference, and depicts the message data type, number, and interval on the recording waveform, and finally presents a time sequence graph combining the waveform and the message.

[0067] 11) Send a reset command to the interface simulation module to clear the message record.

[0068] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0069] The present application is referred to the flow of the method, equipment (system), and computer program product according to the embodiments of the present application

[0070] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The flowchart and / or block diagram in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments. In this regard, each block in the flowchart and / or block diagrams can represent a module, segment, or portion of code, which comprises one or more executable Figure 1 instructions for implementing the specified logical functions. It should also be noted that each block of the flowchart and / or block diagrams and combinations of blocks in the flowchart and / or block diagrams can be implemented by computer program instructions. Such

[0071] instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 The flowchart and / or block diagram in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments. In this regard, each block in the flowchart and / or block diagrams can represent a module, segment, or portion of code, which comprises one or more executable Figure 1 instructions for implementing the specified logical functions. It should also be noted that each block of the flowchart and / or block diagrams and combinations of blocks in the flowchart and / or block diagrams can be implemented by computer program instructions. Such

[0072] instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks.

[0073] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 The flowchart and / or block diagram in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments. In this regard, each block in the flowchart and / or block diagrams can represent a module, segment, or portion of code, which comprises one or more executable Figure 1 instructions for implementing the specified logical functions. It should also be noted that each block of the flowchart and / or block diagrams and combinations of blocks in the flowchart and / or block diagrams can be implemented by computer program instructions. Such

[0074] The above-described embodiments are merely representative of the present application and do not limit the patent protection scope of the present application. Any equivalent structural transformation, direct or indirect, applied to the content of the present application specification and drawings, or applied to other related technical fields, is also included in the protection scope of the present application.

Claims

1. A charging pile signal and communication message synchronous recording device, characterized in that, It comprises: a collection module; a control module; and an interface simulation module; The interface simulation module is responsible for recording CAN message signals and generating message trigger signals; the interface simulation module is also used to record the message data types, data times, and data intervals that need to be monitored, and upload them to the control module; when the interface simulation module detects a message, it triggers a message signal, and the collection module will record the message trigger signal and other channel signals at the same time, and upload the data to the control module; the control module uses the trigger signal as a reference to depict the message data type, number, and interval on the recorded waveform, and finally presents a timing diagram that combines the waveform and the message.

2. The charging pile signal and communication message synchronous recording device according to claim 1, wherein The collection module uses a 32-bit ARM processor and an 8-channel ADC.

3. The charging pile signal and communication message synchronous recording device according to claim 2, characterized in that, The ADC uses a 16-bit ADC with 8 built-in channels.

4. The charging pile signal and communication message synchronous recording device according to claim 1 or 2 or 3, characterized in that, The collection module uses a CPLD to control the sampling frequency, and the time error between each data is less than 0.1us.

5. The charging pile signal and communication message synchronous recording device according to claim 1 or 2 or 3, characterized in that, The control module uses a PC.

6. The charging pile signal and communication message synchronous recording device according to claim 1 or 2 or 3, characterized in that, The collection module and the control module communicate via USB.

7. A method for using a charging pile signal and communication message synchronous recording device, characterized in that, It is applied to the charging pile signal and communication message synchronous recording device of any one of claims 1-6, comprising the following steps: 1) Start BMS and charging pile communication to charge, during the charging process, the interface simulation module monitors the CAN communication message, and monitors the message; or when the predetermined message is triggered, the high-speed collection card receives the message channel; or the sending channel; 2) After the charging is completed, the channel record data is obtained from the collection module and saved to the local file; 3) Record the message data from the interface simulation module; 4) According to the channel record data and all message data, fit each message channel data, and save to the local file; 5) Load the charging pile signal channel local file and the generated each message local file, the control module uses the trigger signal as a reference to depict the message data type, number, and interval on the recorded waveform, and finally presents a timing diagram that combines the waveform and the message.

8. The use of a charging pile signal and communication message synchronous recording device according to claim 7, characterized in that, The message data includes the number of sending times, average time, maximum interval time, minimum interval time, and first frame time.

9. The use of a charging pile signal and communication message synchronous recording device according to claim 8, characterized in that, The specific fitting process in step 5) includes: a. Get the number of collection card receiving message channels or sending message channels, and initialize; b. Find the trigger position from the collection card receiving message channel or sending message, and traverse the receiving message channel or sending message channel when the record data ≤0.1*channel variable ratio*0.95, which is the trigger position; c. Find the relative collection card time point of each message, and update it in a loop; d. Save the updated data to the local file.

10. The use of a charging pile signal and communication message synchronous recording device according to claim 9, characterized in that, It also includes a clearing step, which specifically includes sending a reset command to the interface simulation module to clear the message record.

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