Semiconductor memory device

Abstract

A semiconductor memory device includes: a bit line array including a plurality of bit lines extending in a first direction; a plurality of source layers extending in a second direction crossing the plurality of bit lines; a plurality of gate stack structures disposed between the bit line array and the plurality of source layers; and a conductive via structure coupled to a corresponding bit line among the plurality of bit lines.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to semiconductor memory devices and electronic systems including such semiconductor memory devices, and more specifically, to a three-dimensional semiconductor memory device and an electronic system including such a three-dimensional semiconductor memory device. Background Art

[0002] Semiconductor memory devices are used in a variety of electronic devices, such as those in the automotive, healthcare, and data center sectors, as well as in small electronic devices. Therefore, the demand for semiconductor memory devices continues to increase.

[0003] Semiconductor memory devices include memory cell arrays, which comprise multiple memory cells for storing data. Non-volatile memory devices can be categorized into two-dimensional semiconductor memory devices, which include two-dimensional memory cell arrays, and three-dimensional semiconductor memory devices, which include three-dimensional memory cell arrays.

[0004] A three-dimensional memory cell array can arrange multiple memory cells in three dimensions. Therefore, a three-dimensional cell array is more advantageous for high-capacity semiconductor memory devices compared to a two-dimensional cell array which includes multiple memory cells arranged in a plane. Summary of the Invention

[0005] According to an embodiment, a semiconductor memory device may include: a bit line array including a plurality of bit lines extending in a first direction; a plurality of source layers extending in a second direction intersecting the plurality of bit lines, the plurality of source layers overlapping the plurality of bit lines; a plurality of gate stack structures disposed in the first direction, each of the plurality of gate stack structures including a plurality of conductive layers stacked and spaced apart from each other in a third direction toward the plurality of source layers and away from the bit line array; a plurality of channel pillars extending in a third direction to pass through the plurality of gate stack structures respectively; memory layers extending on the sidewalls of each of the plurality of channel pillars respectively; an isolation structure disposed between adjacent gate stack structures in the plurality of gate stack structures, the isolation structure extending in the second direction; and a first conductive via structure disposed in the isolation structure, the first conductive via structure being connected to a corresponding bit line among the plurality of bit lines.

[0006] According to an embodiment, a semiconductor memory device may include: a first bit line array including a plurality of first bit lines extending in a first direction; a second bit line array disposed above the first bit line array and including a plurality of second bit lines extending in the first direction; a plurality of first source layers disposed between the first bit line array and the second bit line array, extending in a second direction intersecting the plurality of first bit lines, and arranged in the first direction; a plurality of second source layers disposed between the plurality of first source layers and the second bit line array, extending in the second direction, and arranged in the first direction; a first memory cell array disposed between the first bit line array and the plurality of first source layers, the first memory cell array being connected to a plurality of first gate stacks arranged in the first direction; a second memory cell array disposed between the second bit line array and the plurality of second source layers, the second memory cell array being connected to a plurality of second gate stacks arranged in the first direction; and a first conductive via structure including a first portion disposed between the plurality of first gate stacks and a second portion disposed between the plurality of second gate stacks, and connecting a pair of first bit lines and a second bit lines. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure;

[0008] Figure 2A This is a perspective view showing a semiconductor memory device according to an embodiment of the present disclosure;

[0009] Figure 2B It is shown Figure 2A The circuit diagrams of the second sub-peripheral circuit, the first sub-memory cell array, and the second sub-memory cell array are shown below.

[0010] Figure 3 This is a plan view showing a semiconductor memory device according to an embodiment of the present disclosure;

[0011] Figure 4A and Figure 4B It is shown Figure 3 A cross-sectional view of the semiconductor memory device shown;

[0012] Figure 5A , Figure 5B and Figure 5C It is shown Figure 3 A cross-sectional view of the semiconductor memory device shown;

[0013] Figure 6 This is a perspective view showing the bit line array and the first conductive via group of a semiconductor memory device according to an embodiment of the present disclosure;

[0014] Figure 7 This is a plan view showing a semiconductor memory device according to an embodiment of the present disclosure;

[0015] Figure 8 This is a perspective view showing a semiconductor memory device according to an embodiment of the present disclosure;

[0016] Figure 9A and Figure 9B It is shown Figure 8 A cross-sectional view of the semiconductor memory device shown;

[0017] Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 19 This is a plan view illustrating a manufacturing process for providing a semiconductor memory device according to an embodiment of the present disclosure;

[0018] Figure 11A , Figure 11B , Figure 13A , Figure 13B , Figure 15A , Figure 15B , Figure 17 , Figure 18A , Figure 18B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 21E and Figure 21F This is a cross-sectional view illustrating a manufacturing process for providing a semiconductor memory device according to an embodiment of the present disclosure; and

[0019] Figure 22 This is a block diagram illustrating an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0020] Specific structural or functional descriptions of examples of embodiments of the concepts disclosed in this specification are shown only to describe examples of embodiments of the concepts, and examples of embodiments of the concepts may be implemented in various forms, but these descriptions are not limited to the examples of embodiments described in this specification.

[0021] Terms such as “first” and “second” are used to distinguish between various elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be referred to as the second element, and in another example, the second element may be referred to as the first element. Terms such as “top,” “above,” “over,” “side,” “upper,” “lower,” “row,” “column,” “inner,” and “outer,” as well as other terms that imply relative spatial relationships or orientations, are used only for ease of description or reference to the accompanying drawings and are not intended to be limiting. Crosshairs running through the drawings indicate corresponding or similar areas between the drawings and do not indicate material associated with the areas. It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “attached to” another element or layer, it may be directly on, directly connected to, or attached to the other element or layer, or there may be intermediate elements or layers. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly attached to” another element or layer, there are no intermediate elements or layers.

[0022] According to various embodiments of the present disclosure, a semiconductor memory device capable of improving operational reliability can be provided.

[0023] Figure 1 This is a block diagram illustrating a semiconductor memory device 50 according to an embodiment of the present disclosure.

[0024] Reference Figure 1 The semiconductor memory device 50 may include peripheral circuitry 40 and a memory cell array 10.

[0025] The peripheral circuitry 40 can be configured to perform programming operations that store data in the memory cell array 10, reading operations that output data stored in the memory cell array 10, and erasing operations that erase data stored in the memory cell array 10. According to an embodiment, the peripheral circuitry 40 may include an input / output circuitry 21, a control circuitry 23, a voltage generation circuitry 31, a row decoder 33, a column decoder 35, a page buffer 37, and a source driver 39.

[0026] The peripheral circuit 40 can be connected to the memory cell array 10 through multiple common source structures CS, multiple bit lines BL, multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL.

[0027] Input / output circuit 21 can transmit commands (CMD) and addresses (ADD) received from an external device (e.g., a memory controller) of semiconductor memory device 50 to control circuit 23. Input / output circuit 21 can exchange data (DATA) with external devices and column decoder 35.

[0028] Control circuit 23 can output operation signal OP_S, row address RADD, common source control signal CS_S, page buffer control signal PB_S and column address CADD in response to command CMD and address ADD.

[0029] The voltage generation circuit 31 can generate various operating voltages Vop for performing programming, reading and erasing operations in response to the operation signal OP_S.

[0030] The line decoder 33 can transmit the operating voltage Vop to multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL in response to the line address RADD.

[0031] In response to the column address CADD, the column decoder 35 can transfer data DATA input from the input / output circuit 21 to the page buffer 37, or can transfer data DATA stored in the page buffer 37 to the input / output circuit 21. The column decoder 35 can exchange data DATA with the input / output circuit 21 via the column line CL. The column decoder 35 can exchange data DATA with the page buffer 37 via the data line DL.

[0032] Page buffer 37 can control bit lines BL in response to page buffer control signal PB_S. During programming operations, page buffer 37 can store data DATA received from column decoder 35 in response to page buffer control signal PB_S, and can apply voltages to multiple bit lines BL based on the stored data DATA. During read operations, page buffer 37 can sense the voltage or current of bit lines BL in response to page buffer control signal PB_S and store the sensing results.

[0033] The source driver 39 can control the voltage or bias applied to the common source structure CS, or can connect to the common source structure CS in response to the common source control signal CS_S received from the control circuit 23.

[0034] The memory cell array 10 may include multiple memory blocks BLK1 to BLKn, where n is a natural number of 2 or greater. The multiple memory blocks BLK1 to BLKn may be connected to the page buffer 37 via multiple bit lines BL. Each memory block may include multiple strings of memory cells. Each memory block may be divided into multiple sub-blocks. Each sub-block may include multiple memory cells. The multiple memory cells of each sub-block may be arranged in different directions (first to third) to form a three-dimensional cell array. Each sub-block may include at least one source select line SSL, at least one drain select line DSL, and word lines WL stacked between the at least one source select line SSL and the at least one drain select line DSL. Some word lines WL of each sub-block may be used as dummy word lines. Erasure operations may be controlled on a unit of a common source structure CS. The common source structure CS may be connected to a sub-block. At least one source layer may be connected to the common source structure CS.

[0035] The memory cell array 10 of the semiconductor memory device 50 may overlap with the peripheral circuit 40. The memory cell array 10 may be connected to the peripheral circuit 40 through conductive via structures.

[0036] Figure 2A This is a perspective view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0037] Reference Figure 2A The peripheral circuit 40 may include a first sub-peripheral circuit 40A and a second sub-peripheral circuit 40B. The memory cell array 10 may be disposed between the first sub-peripheral circuit 40A and the second sub-peripheral circuit 40B, and includes multiple sub-memory cell arrays MCA_S1 to MCA_Si, where i is a natural number of 2 or greater. The bit line array BA may include multiple bit lines BL and is disposed between the memory cell array 10 and the first sub-peripheral circuit 40A. Multiple source layers SR may be arranged between the memory cell array 10 and the second sub-peripheral circuit 40B.

[0038] Multiple bit lines BL can extend along the first direction DR1. Multiple bit lines BL can be separated from each other along the second direction DR2.

[0039] Multiple sub-memory cell arrays MCA_S1 to MCA_Si may be arranged on a first direction DR1. Sub-memory cell arrays adjacent to each other on the first direction DR1 (e.g., sub-memory cell arrays MCA_S1 and MCA_S2) may be separated from each other by an isolation structure SS. Each of the sub-memory cell arrays MCA_S1 to MCA_Si may include multiple sub-memory blocks. Each memory block may include two or more sub-memory cell arrays. For example, a first memory block may include a first sub-memory cell array MCA_S1 and a second sub-memory cell array MCA_S2.

[0040] Multiple source layers SR may overlap with the bit line array BA and the memory cell array 10. Multiple source layers SR may extend along the second direction DR2 to intersect with multiple bit lines BL. Multiple source layers SR may be arranged along the first direction DR1. Multiple source layers SR may respectively correspond to multiple sub-memory cell arrays MCA_S1 to MCA_Si. According to an embodiment, the multiple source layers SR may include a first source layer SR1 corresponding to the first sub-memory cell array MCA_S1, a second source layer SR2 corresponding to the second sub-memory cell array MCA_S2, and an i-th source layer SRi corresponding to the i-th sub-memory cell array MCA_Si. Each source layer SR may be arranged between its corresponding position in the multiple sub-memory cell array and the second sub-peripheral circuit 40B.

[0041] Each source layer SR may include a semiconductor layer, which includes at least one of n-type impurities and p-type impurities. According to one embodiment, the source layer SR may include a first conductivity type doped region, which includes n-type impurities as majority carriers. The first conductivity type doped region may be connected to a common source structure. According to another embodiment, the source layer SR may further include a second conductivity type doped region, which includes p-type impurities as majority carriers.

[0042] The bit line array BA can be electrically connected to the first sub-peripheral circuit 40A via a first conductive via group. The first conductive via group can include multiple first conductive via structures corresponding to multiple bit lines BL respectively. The multiple first conductive via structures can extend from the bit line array BA in a third direction DR3. The third direction DR3 can refer to the direction from the bit line array BA toward multiple source layers SR.

[0043] Multiple source layers (SRs) can be electrically connected to the reference above via a second set of conductive vias. Figure 1 The description includes multiple common source structures CS. The second conductive via group may include multiple second conductive via structures connected to the respective source layers SR.

[0044] Figure 2B It is shown Figure 2A The circuit diagram shown is for the second sub-peripheral circuit 40B, the first sub-memory cell array MCA_S1, and the second sub-memory cell array MCA_S2.

[0045] Reference Figure 2B The first sub-memory cell array MCA_S1 and the second sub-memory cell array MCA_S2 may be contained in the same memory block.

[0046] The second sub-peripheral circuit 40B may include a page buffer 37 and a source driver 39. The page buffer 37 may include multiple first transistors TR1. The source driver 39 may include a second transistor TR2. The multiple first transistors TR1 may be connected to multiple bit lines BL of the corresponding memory block. The second transistor TR2 may be connected to its corresponding common source structure CS.

[0047] Each of the first sub-memory cell array MCA_S1 and the second sub-memory cell array MCA_S2 may include multiple memory cell strings MCS. Each memory cell string MCS may include at least one drain select transistor (DST), multiple memory cells (MC), and at least one source select transistor (SST). The multiple memory cells (MC) in each memory cell string MCS may be stacked between the drain select transistor (DST) and the source select transistor (SST).

[0048] The memory cell strings of the first sub-memory cell array MCA_S1 and the second sub-memory cell array MCA_S2 of each bit line BL can be electrically connected to each other. The bit line BL can be electrically connected to the corresponding first transistor TR1 via the first conductive via structure V1.

[0049] Multiple memory cell strings (MCS) of the first sub-memory cell array MCA_S1 can be electrically connected to the first source layer SR1. Multiple memory cell strings (MCS) of the second sub-memory cell array MCA_S2 can be electrically connected to the second source layer SR2. Each of the first source layer SR1 and the second source layer SR2 can be electrically connected to the common source structure CS via its corresponding second conductive via structure V2.

[0050] A first sub-memory cell array MCA_S1 can be connected to a first gate group GG1. A second sub-memory cell array MCA_S2 can be connected to a second gate group GG2. Each of the first gate group GG1 and the second gate group GG2 may include at least one drain select line DSL, multiple word lines WL, and at least one source select line SSL. In each gate group (GG1 or GG2), the multiple word lines WL may be stacked between the drain select line DSL and the source select line SSL. In each gate group (GG1 or GG2), the drain select line DSL may be connected to the gate electrode of the drain select transistor DST, the multiple word lines WL may be connected to multiple gate electrodes of multiple memory cells MC, and the multiple source select lines SSL may be connected to the gate electrode of the source select transistor SST. Each of the first gate group GG1 and the second gate group GG2 may include a conductive layer of a corresponding gate stack structure.

[0051] Figure 3 This is a plan view illustrating a semiconductor memory device according to an embodiment of the present disclosure. Figure 4A and Figure 4B It is shown Figure 3 The diagram shows a cross-sectional view of a semiconductor memory device. Figure 4A Show along Figure 3 The cross-section of the semiconductor memory device is taken by line I-I'. Figure 4B Show along Figure 3 The cross-section of the semiconductor memory device is taken by line II-II'.

[0052] Reference Figure 3 , Figure 4A and Figure 4B As shown above Figure 2A As described, multiple bit lines BL may extend in a first direction DR1 and be spaced apart from each other in a second direction DR2. (Refer to the above...) Figure 2A As described, multiple source layers SR can be arranged on the first direction DR1.

[0053] Multiple gate stack structures (GSTs) can be disposed between multiple bit lines (BLs) and multiple source layers (SRs), and can be arranged on the first direction (DR1). Each GST can correspond to a different source layer (SR). Each GST can be arranged between its corresponding source layer (SR) and multiple bit lines (BLs).

[0054] An isolation structure SS may be arranged between adjacent gate stack structures on the first direction DR1 (e.g., between GST1 and GST2 or between GST2 and GST3). The isolation structure SS may be arranged alternately with the gate stack structures GST on the first direction DR1. Adjacent gate stack structures on the first direction DR1 may be spaced apart from each other by the isolation structure SS. The isolation structure SS may extend on the second direction DR2 and overlap with multiple bit lines BL.

[0055] The source isolation insulating layer SIL can be disposed between adjacent source layers SR on the first direction DR1. The source isolation insulating layer SIL can be arranged alternately with the source layers SR on the first direction DR1. The source isolation insulating layer SIL can separate adjacent source layers SR on the first direction DR1 from each other. The source isolation insulating layer SIL can overlap with the isolation structure SS. The source isolation insulating layer SIL can extend on the second direction DR2.

[0056] Each gate stack structure (GST) may include a first insulating layer IL1, a plurality of second insulating layers IL2, a plurality of conductive layers CDL, and a third insulating layer IL3. The first insulating layer IL1 may be disposed adjacent to the source layer SR. The third insulating layer IL3 may be disposed adjacent to the bit line BL. The plurality of second insulating layers IL2 and the plurality of conductive layers CDL may be disposed between the first insulating layer IL1 and the third insulating layer IL3. The second insulating layers IL2 may be alternately disposed with the conductive layers CDL on a third-direction DR3. The plurality of conductive layers CDL may be spaced apart from each other on the third-direction DR3 by the plurality of second insulating layers IL2. However, embodiments of this disclosure are not limited thereto. According to embodiments, the plurality of conductive layers CDL may be separated from each other by air gaps between them. Air gaps include hollow spaces that typically encapsulate vacuum, gas, or air.

[0057] In the conductive layers CDL, at least one conductive layer CDL can be used as a source select line SSL (i.e., CDL(SSL)), at least one conductive layer CDL can be used as a drain select line DSL (i.e., CDL(DSL)), and the other conductive layers CDL can be used as word lines WL (i.e., CDL(WL)). Each conductive layer CDL may include various conductive materials such as doped semiconductor layers, metal layers, etc. The doped semiconductor layer may include a doped silicon layer. The metal layer may include tungsten, copper, molybdenum, etc. Each conductive layer CDL may also include a conductive metal nitride layer provided as a barrier layer. The conductive metal nitride layer may include tantalum nitride, titanium nitride, etc. The first insulating layer IL1, the plurality of second insulating layers IL2, and the third insulating layer IL3 may include insulating materials such as silicon oxide (SiOx) layers and silicon oxynitride (SiON) layers.

[0058] Each gate stack (GST) can be penetrated by multiple channel pillars (CH). (See above reference.) Figure 2B The described memory cell string (MCS) can be formed along individual channel pillars (CH). Each channel pillar (CH) can extend on a third-direction DR3 to pass through a first insulating layer IL1, multiple second insulating layers IL2, multiple conductive layers CDL, and a third insulating layer IL3 of its corresponding gate stack structure GST. The channel pillars (CH) can include a semiconductor material serving as the channel region of the memory cell string. The semiconductor material can include silicon (Si), germanium (Ge), or mixtures thereof. The channel pillars (CH) can have various structures. According to an embodiment, the central region of the channel pillar (CH) can be filled with a core insulating layer CO. Each end of the channel pillar (CH) adjacent to the bit line BL and the source layer SR can include at least one of n-type impurities and p-type impurities. According to an embodiment, each end of the channel pillar (CH) adjacent to the bit line BL and the source layer SR can be configured to include an n-type impurity region where n-type impurities serve as majority carriers.

[0059] The semiconductor memory device may further include a memory layer ML extending on the sidewall of the channel pillar CH. The memory layer ML may be interposed between the channel pillar CH and the gate stack structure GST.

[0060] One end of the channel pillar CH may extend into the source layer SR to contact the corresponding source layer SR. The channel pillar CH may include a contact surface that contacts the source layer SR. The contact surface may be defined between one end of the channel pillar CH and the source layer SR. According to an embodiment, the channel pillar CH may protrude beyond the memory layer ML toward its corresponding source layer SR, and the source layer SR may include a recess therein into which one end of the channel pillar CH is inserted. The contact surface between the source layer SR and the channel pillar CH may be defined along the recess of the source layer SR.

[0061] Multiple channel pillars (CH) can be connected to multiple bit line contacts (BCTs). Each bit line contact (BCT) connects a channel pillar (CH) to a bit line (BL). The bit line contacts (BCTs) can pass through a fourth insulating layer (IL4) inserted between the gate stack (GST) and the bit line (BL).

[0062] Each bit line BL can be connected to its corresponding first conductive via structure V1. The first conductive via structure V1 may include a first contact pattern C1, a second contact pattern C2, and a third contact pattern C3. The first contact pattern C1 may include conductive material disposed in the isolation structure SS. The second contact pattern C2 may include conductive material passing through the fourth insulating layer IL4. The third contact pattern C3 may include conductive material passing through the source isolation insulating layer SIL. The first contact pattern C1 may be aligned with and connected to the second contact pattern C2 on the third-direction DR3. The third contact pattern C3 may be aligned with and connected to the first contact pattern C1 on the third-direction DR3.

[0063] The isolation structure SS may include a plurality of first insulating structures SS1 and a plurality of second insulating structures SS2 disposed on the second direction DR2. The plurality of first insulating structures SS1 may be spaced apart from each other on the second direction DR2. Each second insulating structure SS2 may be disposed between adjacent first insulating structures SS1 on the second direction DR2. The second insulating structures SS2 may surround the sidewall of the first contact pattern C1 of the first conductive via structure V1. The first contact pattern C1 may be separated from the gate stack structure GST through the second insulating structures SS2.

[0064] Bit line BL may include one side facing the gate stack structure GST and another side opposite to said side. The other side of bit line BL may be covered by a fifth insulating layer IL5. The fifth insulating layer IL5 may include at least two insulating layers. A first cell side bonding pattern CBP1 may be arranged in the fifth insulating layer IL5.

[0065] Multiple source layers SR can be covered by a sixth insulating layer IL6. A common source structure CS can be disposed above the sixth insulating layer IL6. The common source structure CS can have various structures such as linear, mesh, and planar. The common source structure CS may include a conductive material, including a metal. The common source structure CS can be connected to the multiple source layers SR via multiple second conductive via structures V2. The multiple second conductive via structures V2 can pass through the sixth insulating layer IL6.

[0066] The common source structure CS may be covered by a seventh insulating layer IL7. The seventh insulating layer IL7 may include at least two insulating layers. The second cell side bonding pattern CBP2 may be disposed in the seventh insulating layer IL7. The second cell side bonding pattern CBP2 may include a bonding pattern connected to the third contact pattern C3 of the first conductive via structure V1 and a bonding pattern connected to the common source structure CS.

[0067] The first unit-side bonding pattern CBP1 can be bonded to the first peripheral circuit-side bonding pattern PBP1 of the first sub-peripheral circuit 40A. The second unit-side bonding pattern CBP2 can be bonded to the second peripheral circuit-side bonding pattern PBP2 of the second sub-peripheral circuit 40B. Each of the first unit-side bonding pattern CBP1, the second unit-side bonding pattern CBP2, the first peripheral circuit-side bonding pattern PBP1, and the second peripheral circuit-side bonding pattern PBP2 may include a bonding metal such as copper, aluminum, and tungsten.

[0068] As shown above (refer to the reference) Figure 2B As described, the second sub-peripheral circuit 40B may include a first transistor TR1 and a second transistor TR2. The first sub-peripheral circuit 40A may include a third transistor TR3. According to an embodiment, the third transistor TR3 may be a component constituting... Figure 1 The line decoder 33 shown is one of the transistors.

[0069] The third transistor TR3 of the first sub-peripheral circuit 40A can be covered by the first peripheral circuit insulation structure PIL1 between the first semiconductor substrate SUB1 and the fifth insulating layer IL5. The third transistor TR3 can be disposed in the active region of the first semiconductor substrate SUB1 separated by the first isolation layer ISO1.

[0070] The first transistor TR1 and the second transistor TR2 of the second sub-peripheral circuit 40B can be covered by the second peripheral circuit insulation structure PIL2 between the second semiconductor substrate SUB2 and the seventh insulating layer IL7. The first transistor TR1 and the second transistor TR2 can be disposed in the active region of the second semiconductor substrate SUB2, which is separated by the second isolation layer ISO2.

[0071] Each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may include a gate insulating layer (GI1, GI2, or GI3), a gate electrode (GE1, GE2, or GE3), a first junction (JN11, JN21, or JN31), and a second junction (JN12, JN22, or JN32). The gate insulating layer GI1, GI2, or GI3 and the gate electrode GE1, GE2, or GE3 may be stacked on the active region of the corresponding semiconductor substrate SUB1 or SUB2. The first junction JN11, JN21, or JN31 and the second junction JN12, JN22, or JN32 may be arranged in the corresponding semiconductor substrate SUB1 or SUB2 and may serve as the source region and drain region, respectively.

[0072] The third transistor TR3 can be connected to the first interconnect IC1 disposed in the first peripheral circuit insulation structure PIL1. The first transistor TR1 and the second transistor TR2 can be connected to the second interconnect IC2 disposed in the second peripheral circuit insulation structure PIL2. Some of the second interconnect IC2 can be used to connect the second junction JN12 of the first transistor TR1 to one of the second cell side bonding patterns CBP2. Other second interconnect IC2 can be used to connect the second junction JN22 to another second cell side bonding pattern CBP2.

[0073] Figure 5A , Figure 5B and Figure 5C It is shown Figure 3 The diagram shows a plan view of a semiconductor memory device.

[0074] Figure 5A Semiconductor memory devices are in Figure 3 The diagram shows the height of the conductive layer CDL. Figure 5B yes Figure 5A An enlarged plan view of the area “AR1” shown.

[0075] Reference Figure 5A and Figure 5B The conductive layer CDL can extend in the first direction DR1 and the second direction DR2 to surround the sidewalls of the channel post CH. The core insulating layer CO can be disposed in the central region of the channel post CH. The memory layer ML can be interposed between the channel post CH and the conductive layer CDL.

[0076] The memory layer ML may include a tunnel isolation layer TI, a data storage layer DS, and a barrier insulating layer BI. The tunnel isolation layer TI may extend along a third-direction DR3 on the outer wall of the channel pillar CH. The tunnel isolation layer TI may include an insulating material such as a silicon oxide layer. The data storage layer DS may be interposed between the conductive layer CDL and the tunnel isolation layer TI. According to one embodiment, the data storage layer DS may extend continuously along a third-direction DR3 on the outer wall of the tunnel isolation layer TI. According to another embodiment, the data storage layer DS may be separated into a plurality of data storage patterns spaced apart from each other on the third-direction DR3, and each data storage pattern may be disposed between the conductive layer CDL and its corresponding channel pillar CH. The data storage layer DS may include a material layer capable of storing varying data using Fowler-Nordheim tunneling. According to one embodiment, the data storage layer DS may include a charge trap insulating layer, a floating gate layer, or an insulating layer comprising conductive nanodots. The charge trap insulating layer may include a silicon nitride layer. The barrier insulating layer BI may be interposed between the conductive layer CDL and the data storage layer DS. The barrier insulating layer BI may include either a silicon dioxide (SiO2) layer or a high-dielectric layer with a dielectric constant greater than that of the silicon dioxide layer. The high-dielectric layer may include an aluminum oxide layer, a hafnium oxide layer, etc.

[0077] The first insulating structure SS1 and the second insulating structure SS2 may be arranged alternately in the second direction DR2 to form a row. The second insulating structure SS2 may surround the sidewall of the first contact pattern C1 of the first conductive via structure V1.

[0078] Figure 5C This illustrates a semiconductor memory device in Figure 3 A plan view showing the height of the source layer SR.

[0079] Reference Figure 5C The source layer SR can be alternately arranged with the source isolation insulation layer SIL in the first direction DR1. The source layer SR can overlap with multiple channel pillars CH.

[0080] The source isolation insulating layer SIL can be penetrated by the third contact pattern C3 of the first conductive via structure. The third contact pattern C3 can overlap with the first contact pattern C1 of the first conductive via structure V1.

[0081] As shown above (refer to the reference) Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B and Figure 5CAs described, the first conductive via structure V1 connecting the bit line BL can be disposed between adjacent gate stack structures GST. Therefore, in this embodiment, since it is not necessary to provide a separate area for the first conductive via structure V1 for connecting the bit line BL to the first transistor TR1, the integration density of the semiconductor memory device can be increased. Furthermore, in this embodiment, because the connection structure between the bit line BL and the first transistor TR1 is simplified, structural defects occurring during the manufacturing process of the semiconductor memory device can be reduced.

[0082] Figure 6 This is a perspective view showing the bit line array and the first conductive via group of a semiconductor memory device according to an embodiment of the present disclosure.

[0083] According to embodiments of this disclosure, a first conductive via group may include a plurality of first conductive via structures corresponding to a plurality of bit lines, and each first conductive via group may include a first contact pattern and a corresponding second contact pattern. The plurality of first contact patterns of the plurality of first conductive via structures may overlap with the corresponding bit lines and be spaced apart from each other in a first direction DR1 and a second direction DR2. Each of the plurality of second contact patterns of the plurality of first conductive via structures may be disposed between a bit line and its corresponding first contact pattern.

[0084] Reference Figure 6 According to an embodiment, multiple bit lines may include first bit lines BL1 to fifth bit lines BL5 spaced apart from each other in the second direction DR2. The first bit lines BL1 to fifth bit lines BL5 may be connected to different first conductive via structures. In an embodiment, each of the first contact patterns C11, C12, C13, C14, and C15 may overlap with its corresponding bit line among the first bit lines BL1 to fifth bit lines BL5, and has a width greater than that of each bit line in the second direction DR2. As a result, in an embodiment, the misalignment error between each of the first contact patterns C11, C12, C13, C14, and C15 and its corresponding bit line can be reduced. In an embodiment, each of the second contact patterns C21, C22, C23, C24, and C25 of the first conductive via structure may connect a corresponding bit line and a corresponding first contact pattern in the area where the bit lines and first contact patterns overlap.

[0085] Figure 7 This is a plan view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0086] Reference Figure 7The conductive layer CDL (i.e., CDL(WL)) used as the word line WL can be penetrated by multiple channel pillars CH, and the multiple channel pillars CH can form at least one row. Each row can consist of channel pillars CH arranged in a row. According to an embodiment, the multiple channel pillars CH can be arranged into a first row R1 to an eighth row R8. When the channel pillars CH passing through each word line WL are arranged in four or more rows, at least one of the drain-select gate layer and source-select gate layer overlapping each word line WL can be separated into two or more select lines on the same layer by the select line isolation structure SEL_SS. Although Figure 7 As not shown, dummy posts can be arranged along the select line isolation structure SEL_SS. Each dummy post may include a dummy channel post with a structure similar to the channel post CH, a dummy core insulation layer with a structure similar to the core insulation layer CO, and a dummy memory layer with a structure similar to the memory layer ML.

[0087] Reference Figure 5A and Figure 7 The second insulating structure SS2 of the isolation structure SS and the first contact pattern C1 of the first conductive via structure may extend beyond the first insulating structure SS1 of the isolation structure SS in the second direction DR2. In various embodiments, the second insulating structure SS2 of the isolation structure SS and the first contact pattern C1 of the first conductive via structure SS may be designed to have various lengths. In various embodiments, the second insulating structure SS2 of the isolation structure SS and the first contact pattern C1 of the first conductive via structure SS may have uneven sidewalls.

[0088] Figure 8 This is a perspective view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0089] Reference Figure 8 The memory cell array 10 may include a first memory cell array 10A and a second memory cell array 10B. Multiple bit lines may include multiple first bit lines BL_A of the first bit line array BA_A and multiple second bit lines BL_B of the second bit line array BA_B. Multiple source layers SR may include multiple first source layers SR_A and multiple second source layers SR_B. (Refer to the above...) Figure 2A As described, each source layer SR may include a semiconductor layer, which includes at least one of n-type impurities and p-type impurities.

[0090] The first memory cell array 10A, the first bit line array BA_A, and multiple first source layers SR_A can constitute the first structure ST1. The second memory cell array 10B, the second bit line array BA_B, and multiple second source layers SR_B can constitute the second structure ST2.

[0091] The first bit array BA_A of the first structure ST1 can be positioned above the peripheral circuit 40. Multiple first bit lines BL_A can extend along the first direction DR1 and be spaced apart from each other along the second direction DR2. The second bit array BA_B of the second structure ST2 can be positioned above the first structure ST1. Multiple first bit lines BL_A can extend along the first direction DR1 and be spaced apart from each other along the second direction DR2.

[0092] The multiple first source layers SR_A of the first structure ST1 can be disposed between the first bit linear array BA_A and the second bit linear array BA_B. The multiple first source layers SR_A can extend in the second direction DR2 to intersect with multiple first bit lines BL_A, and can be spaced apart from each other in the first direction DR1.

[0093] The multiple second source layers SR_B of the second structure ST2 can be disposed between the multiple first source layers SR_A and the second bit line array BA_B. The multiple second source layers SR_B can extend in the second direction DR2 to intersect with the multiple second bit lines BL_B, and can be spaced apart from each other in the first direction DR1.

[0094] The first memory cell array 10A of the first structure ST1 may be disposed between the first linear array BA_A and a plurality of first source layers SR_A. The first memory cell array 10A may include a plurality of first sub-memory cell arrays MCA_S1A and MCA_S2A arranged on the first direction DR1. The first sub-memory cell arrays MCA_S1A and MCA_S2A adjacent to each other may be separated by a first isolation structure SS_A. The first structure ST1 may also include a first dummy memory cell array DM_A and a first common source structure CS_A disposed between the first dummy memory cell array DM_A and the peripheral circuit 40. The first common source structure CS_A may be spaced apart from the first linear array BA_A on the second direction DR2. The first common source structure CS_A may include a plurality of first sub-source structures CSS_A. The plurality of first sub-source structures CSS_A may extend on the first direction DR1 and be spaced apart from each other on the second direction DR2. Although not shown, the first common source structure CS_A may also include a first connection structure connecting the plurality of first sub-source structures CSS_A to each other.

[0095] The second memory cell array 10B of the second structure ST2 may be disposed between the second bit line array BA_B and a plurality of second source layers SR_B. The second memory cell array 10B may include a plurality of second sub-memory cell arrays MCA_S1B and MCA_S2B arranged on the first direction DR1. Adjacent second sub-memory cell arrays MCA_S1B and MCA_S2B may be separated by a second isolation structure SS_B. The second structure ST2 may also include a second dummy memory cell array DM_B and a second common source structure CS_B disposed above the second dummy memory cell array DM_B. The second common source structure CS_B may be spaced apart from the second bit line array BA_B on the second direction DR2. The second common source structure CS_B may include a plurality of second sub-source structures CSS_B. The plurality of second sub-source structures CSS_B may extend on the first direction DR1 and be spaced apart from each other on the second direction DR2. Although not shown, the second common source structure CS_B may also include a second connection structure that connects the plurality of second sub-source structures CSS_B to each other.

[0096] The first bit array BA_A can be electrically connected to the second bit array BA_B via a first group of conductive vias. The first common source structure CS_A, multiple first source layers SR_A, multiple second source layers SR_B, and the second common source structure CS_B can be electrically connected to each other via a second group of conductive vias. The first group of conductive vias may include a first conductive via structure extending from the interior of the first isolation structure SS_A into the second isolation structure SS_B. The second group of conductive vias may include a second conductive via structure extending from the interior of the first isolation structure SS_A into the second isolation structure SS_B.

[0097] Figure 9A and Figure 9B It is shown Figure 8 The diagram shows a cross-sectional view of a semiconductor memory device. Figure 9A The diagram shows a cross-section of a semiconductor memory device taken along either the first bit line BL_A or the second bit line BL_B. Figure 9B A cross-section of a semiconductor memory device is shown, taken along the first sub-source structure CSS_A of the first common source structure CS_A or the second sub-source structure CSS_B of the second common source structure CS_B.

[0098] Reference Figure 8 , Figure 9A and Figure 9BThe first structure ST1 may include multiple first gate stack structures GST_A, a first bit line BL_A, and multiple first source layers SR_A connected to multiple first memory cell arrays 10A. The second structure ST2 may include multiple second gate stack structures GST_B, a second bit line BL_B, and multiple second source layers SR_B connected to multiple second memory cell arrays 10B.

[0099] Reference Figure 9A and Figure 9B Multiple first gate stack structures GST_A can be arranged on the first direction DR1 between the first bit line BL_A and multiple first source layers SR_A. Each first gate stack structure GST_A can be arranged between the first source layer SR_A and its corresponding first bit line BL_A. The first gate stack structure GST_A and the first source layer SR_A can extend to overlap with the first common source structure CS_A. Hereinafter, the portion of the first gate stack structure GST_A disposed between the first source layer SR_A and the first bit line BL_A is referred to as the first cell array region CR1 (i.e., GST_A / CR1), and the other portion disposed between the first source layer SR_A and the first common source structure CS_A is referred to as the first dummy cell array region DCR1 (i.e., GST_A / DCR1).

[0100] Multiple second gate stack structures GST_B can be arranged on the first direction DR1 between the second bit line BL_B and multiple second source layers SR_B. Each second gate stack structure GST_B can be arranged between the second source layer SR_B and its corresponding second bit line BL_B. The second gate stack structure GST_B and the second source layer SR_B can extend to overlap with the second common source structure CS_B. Hereinafter, the portion of the second gate stack structure GST_B disposed between the second source layer SR_B and the second bit line BL_B is referred to as the second cell array region CR2 (i.e., GST_B / CR2), and the other portion disposed between the second source layer SR_B and the second common source structure CS_B is referred to as the second dummy cell array region DCR2 (i.e., GST_B / DCR2).

[0101] As shown above (refer to the reference) Figure 4A and Figure 4B In the described gate stack structure GST, each of the first gate stack structure GST_A and the plurality of second gate stack structures GST_B may include a first insulating layer, a plurality of conductive layers, a plurality of insulating layers and a third insulating layer.

[0102] Reference Figure 8 , Figure 9A and Figure 9BThe first sub-memory cell array MCA_S1A or MCA_S2A of the first memory cell array 10A can be connected to multiple conductive layers of the corresponding first gate stack structure GST_A. The second sub-memory cell array MCA_S1B or MCA_S2B of the second memory cell array 10B can be connected to multiple conductive layers of the corresponding second gate stack structure GST_B.

[0103] Reference Figure 9A and Figure 9B Each first sub-memory cell array may include a first channel post CH_A connected to its corresponding first source layer SR_A and first bit line BL_A, and a first memory layer ML_A extending on the sidewall of the first channel post CH_A. Each second memory cell array may include a second channel post CH_B connected to its corresponding second source layer SR_B and second bit line BL_B, and a second memory layer ML_B extending on the sidewall of the second channel post CH_B.

[0104] Reference Figure 8 , Figure 9A and Figure 9B The first dummy memory cell array DM_A may include a first dummy channel pillar DCH_A passing through the first dummy cell array region DCR1 of the first gate stack structure GST_A, and a first dummy memory layer DML_A extending on the sidewall of the first dummy channel pillar DCH_A. The second dummy memory cell array DM_B may include a second dummy channel pillar DCH_B passing through the second dummy cell array region DCR2 of the second gate stack structure GST_B, and a second dummy memory layer DML_B extending on the sidewall of the second dummy channel pillar DCH_B.

[0105] Reference Figure 9A and Figure 9B Each of the first channel post CH_A, the second channel post CH_B, the first dummy channel post DCH_A, and the second dummy channel post DCH_B may have the same characteristics as... Figure 4A and Figure 4B The channel pillar CH shown has the same configuration. Each of the first memory layer ML_A, the second memory layer ML_B, the first dummy memory layer DML_A, and the second dummy memory layer DML_B may have the same configuration as... Figure 5B The memory layer ML shown has the same configuration.

[0106] The first channel pillar CH_A can pass through the first cell array region CR1 of the first gate stack structure GST_A to directly contact the first source layer SR_A, and can be connected to the first bit line BL_A via the first bit line contact BCT_A. The second channel pillar CH_B can pass through the second cell array region CR2 of the second gate stack structure GST_B to directly contact the second source layer SR_B, and can be connected to the second bit line BL_B via the second bit line contact BCT_B.

[0107] Each of the first bit line contact BCT_A and the second bit line contact BCT_B can pass through a fourth insulating layer (IL4_A or IL4_B) disposed between the bit line BL_A or BL_B and the gate stack structure GST_A or GST_B. The fourth insulating layer may include the lower fourth insulating layer IL4_A of the first structure ST1 and the upper fourth insulating layer IL4_B of the second structure ST2. The lower fourth insulating layer IL4_A may extend between the first gate stack structure GST_A and the first common source structure CS_A. The upper fourth insulating layer IL4_B may extend between the second gate stack structure GST_B and the second common source structure CS_B. The first dummy channel pillar DCH_A may pass through the first gate stack structure GST_A to directly contact the first source layer SR_A, and is insulated from the first common source structure CS_A through the lower fourth insulating layer IL4_A. The second dummy channel pillar DCH_B can pass through the second gate stack structure GST_B to directly contact the second source layer SR_B, and is insulated from the second common source structure CS_B through the upper fourth insulating layer IL4_B.

[0108] The first line BL_A may include a side facing the first gate stack structure GST_A and an opposite side. The opposite side of the first line BL_A may be covered by a fifth insulating layer IL5. The fifth insulating layer IL5 may include at least two insulating layers. A cell-side bonding pattern CBP may be disposed within the fifth insulating layer IL5.

[0109] The cell-side bonding pattern CBP can be bonded to the peripheral circuit-side bonding pattern PBP of the peripheral circuit 40. Each of the cell-side bonding pattern CBP and the peripheral circuit-side bonding pattern PBP may include a bonding metal such as copper, aluminum, and tungsten.

[0110] The peripheral circuit 40 may include a first transistor TR1 and a second transistor TR2. The first transistor TR1 may include, for example, Figure 1 Page buffer 37 is shown. The second transistor TR2 can be included in, for example... Figure 1 In the source driver 39 shown.

[0111] The first transistor TR1 and the second transistor TR2 can be covered by the peripheral circuit insulation structure PIL between the semiconductor substrate SUB and the fifth insulating layer IL5. The first transistor TR1 and the second transistor TR2 can be arranged in the active region of the semiconductor substrate SUB separated by the isolation layer ISO.

[0112] As shown above (refer to the reference) Figure 4A and Figure 4B As described, each of the first transistor TR1 and the second transistor TR2 may include a gate insulating layer GI1 or GI2, a gate electrode GE1 or GE2, a first junction JN11 or JN21, and a second junction JN12 or JN22. The first transistor TR1 and the second transistor TR2 may be connected to interconnect ICs disposed in a peripheral circuit insulation structure (PIL). Some interconnect ICs may be used to connect the junction JN12 of the first transistor TR1 to one of the cell-side bonding patterns (CBP), and other interconnect ICs may be used to connect the junction JN22 of the second transistor TR2 to another cell-side bonding pattern (CBP).

[0113] Multiple first source layers SR_A can be separated from multiple second source layers SR_B through a sixth insulating layer (IL6A and IL6B). The sixth insulating layer may include a lower sixth insulating layer IL6A of the first structure ST1 and an upper sixth insulating layer IL6B of the second structure ST2. The lower sixth insulating layer IL6A and the upper sixth insulating layer IL6B may be bonded to each other.

[0114] Reference Figure 8 , Figure 9A and Figure 9B The first isolation structure SS_A of the first structure ST1 can be disposed between adjacent first gate stack structures GST_A. The second isolation structure SS_B of the second structure ST2 can be disposed between adjacent second gate stack structures GST_B. Each of the first isolation structure SS_A and the second isolation structure SS_B can extend in the second direction DR2.

[0115] Each of the first isolation structure SS_A and the second isolation structure SS_B may include multiple first insulation structures and multiple second insulation structures SS2A or SS2B. Although Figure 9A and Figure 9B Multiple first insulating structures are not shown, but the multiple first insulating structures of each of the first isolation structure SS_A and the second isolation structure SS_B may be spaced apart from each other in the second direction DR2, as follows: Figure 5A The multiple first insulating structures SS1 or shown Figure 7The plurality of first insulating structures SS1 shown are arranged in rows. Each of the second insulating structures SSA2A and SS2B can be disposed between adjacent first insulating structures in the second direction DR2. Some of the plurality of second insulating structures SS2A of the first isolation structure SS_A can be disposed between the first cell array regions CR1 of the first gate stack structure GST_A, and the other second insulating structures SS2A can be disposed between the first dummy cell array regions DCR1 of the first gate stack structure GST_A. Some of the plurality of second insulating structures SS2B of the second isolation structure SS_B can be disposed between the second cell array regions CR2 of the second gate stack structure GST_B, and the other second insulating structures SS2B can be disposed between the second dummy cell array regions DCR2 of the second gate stack structure GST_B. Hereinafter, for ease of explanation, the second insulating structure SS2A of the first isolation structure SS_A is referred to as the lower insulating structure, and the second insulating structure SS2B of the second isolation structure SS_B is referred to as the upper insulating structure.

[0116] In the first direction DR1, a first source isolation insulating layer SIL_A may be disposed between adjacent first source layers SR_A, and a second source isolation insulating layer SIL_B may be disposed between adjacent second source layers SR_B. The first source isolation insulating layer SIL_A may overlap with the first isolation structure SS_A, and the second source isolation insulating layer SIL_B may overlap with the second isolation structure SS_B.

[0117] Reference Figure 9A A pair of first bit lines BL_A and second bit lines BL_B can be interconnected through a first conductive via structure V1. The first conductive via structure V1 may include a first portion V1A and a second portion V1B. The first portion V1A may be associated with a first structure ST1, and the second portion V1B may be associated with a second structure ST2. Each of the first portion V1A and the second portion V1B may include a first contact pattern C1A or C1B, a second contact pattern C2A or C2B, and a third contact pattern C3A or C3B.

[0118] At the first portion V1A of the first conductive via structure V1, the first contact pattern C1A may include conductive material disposed between the first gate stack structure GST_A, the second contact pattern C2A may include conductive material passing through the lower fourth insulating layer IL4_A, and the third contact pattern C3A may include conductive material passing through the first source isolation insulating layer SIL_A and the lower sixth insulating layer IL6A. The first contact pattern C1A may be aligned with and connected to the second contact pattern C2A on the third-direction DR3. The third contact pattern C3A may be aligned with and connected to the first contact pattern C1A on the third-direction DR3. The lower insulating structure SS2A disposed between the first cell array regions CR1 of the first gate stack structure GST_A may surround the sidewall of the first contact pattern C1A.

[0119] At the second portion V1B of the first conductive via structure V1, the first contact pattern C1B may include conductive material disposed between the second gate stack structure GST_B, the second contact pattern C2B may include conductive material passing through the upper fourth insulating layer IL4_B, and the third contact pattern C3A may include conductive material passing through the second source isolation insulating layer SIL_B and the upper sixth insulating layer IL6B. The first contact pattern C1B may be aligned with and connected to the third contact pattern C3B on the third-direction DR3. The second contact pattern C2B may be aligned with and connected to the first contact pattern C1B on the third-direction DR3. The upper insulating structure SS2B disposed between the second cell array regions CR2 of the second gate stack structure GST_B may surround the sidewall of the first contact pattern C1B.

[0120] In the first conductive via structure V1, the third contact pattern C3A of the first portion V1A and the third contact pattern C3B of the second portion V1B can be joined to each other. The third contact pattern C3A of the first portion V1A and the third contact pattern C3B of the second portion V1B can include a bonding metal such as copper, aluminum and tungsten.

[0121] A pair of first bit lines BL_A and second bit lines BL_B, which are connected to each other through the first conductive via structure V1, can be electrically connected to the second junction JN12 of the first transistor TR1 through the interconnect IC, the peripheral circuit side bonding pattern PBP and the cell side bonding pattern CBP.

[0122] Reference Figure 9BThe first common source structure CS_A and the second common source structure CS_B can be interconnected through a second conductive via structure V2. The second conductive via structure V2 may include a first source contact portion V2A and a second source contact portion V2B. The first source contact portion V2A may be associated with the first structure ST1, and the second source contact portion V2B may be associated with the second structure ST2. Each of the first source contact portion V2A and the second source contact portion V2B may include a first source contact pattern C1A' or C1B', a second source contact pattern C2A' or C2B', and a third source contact pattern C3A' or C3B'.

[0123] At the first source contact portion V2A of the second conductive via structure V2, the first source contact pattern C1A' may include conductive material disposed between the first gate stack structure GST_A, the second source contact pattern C2A' may include conductive material passing through the lower fourth insulating layer IL4_A, and the third source contact pattern C3A' may include conductive material disposed between adjacent first source layers SR_A on the first direction DR1. The first source contact pattern C1A' may be aligned with and connected to the second source contact pattern C2A' on the third direction DR3. The third source contact pattern C3A' may be aligned with and connected to the third source contact pattern C3A' on the third direction DR3. The lower insulating structure disposed between the first dummy cell array regions DCR1 of the first gate stack structure GST_A (see the second insulating structure SS2A of the first isolation structure SS_A) may surround the sidewall of the first source contact pattern C1A'. The first source layer SR_A can contact the sidewall of the third source contact pattern C3A'. The third source contact pattern C3A' can pass through the lower sixth insulating layer IL6A.

[0124] At the second source contact portion V2B of the second conductive via structure V2, the first source contact pattern C1B' may include conductive material disposed between the second gate stack structure GST_B, the second source contact pattern C2B' may include conductive material passing through the fourth insulating layer IL4_B of the second gate stack structure GST_B, and the third source contact pattern C3B' may include conductive material disposed between adjacent second source layers SR_B on the first direction DR1. The first source contact pattern C1B' may be aligned with and connected to the third source contact pattern C3B' on the third direction DR3. The second source contact pattern C2B' may be aligned with and connected to the first source contact pattern C1B' on the third direction DR3. The upper insulating structure disposed between the second dummy cell array regions DCR2 of the second gate stack structure GST_B (see the second insulating structure SS2B of the second isolation structure SS_B) may surround the sidewall of the first source contact pattern C1B'. The second source layer SR_B can contact the sidewall of the third source contact pattern C3B'. The third source contact pattern C3B' can pass through the upper sixth insulating layer IL6B.

[0125] In the second conductive via structure V2, the third source contact pattern C3A' of the first source contact portion V2A and the third source contact pattern C3B' of the second source contact portion V2B can be joined to each other. The third source contact pattern C3A' of the first source contact portion V2A and the third source contact pattern C3B' of the second source contact portion V2B may include a bonding metal such as copper, aluminum, and tungsten.

[0126] The first common source structure CS_A and the second common source structure CS_B, which are interconnected through the second conductive via structure V2, can be electrically connected to the second junction JN22 of the second transistor TR2 via the interconnect IC, the peripheral circuit side bonding pattern PBP, and the cell side bonding pattern CBP.

[0127] As shown above (refer to the reference) Figure 8 , Figure 9A and Figure 9BDescribed, a first bit line BL_A connected to a first memory cell array 10A and a second bit line BL_B connected to a second memory cell array 10B can be connected to each other via a first conductive via structure V1. The first conductive via structure V1 can extend from adjacent first gate stack structures GST_A to adjacent second gate stack structures GST_B. As a result, in this embodiment, since a separate area may not be provided for the first conductive via structure V1 for connecting the first bit line BL_A and the second bit line BL_B to each other, the integration density of the semiconductor memory device can be increased. Furthermore, in this embodiment, by connecting one of the first bit line BL_A and the second bit line BL_B to a first transistor TR1, a pair of first bit lines BL_A and second bit lines BL_B can be controlled by the first transistor TR1, thereby simplifying the connection structure between each of the first bit line BL_A and the second bit line BL_B and the page buffer. As a result, in this embodiment, structural defects occurring during the manufacturing process of the semiconductor memory device can be reduced.

[0128] Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 19 This is a plan view illustrating a manufacturing process for providing a semiconductor memory device according to an embodiment of the present disclosure. Figure 11A , Figure 11B , Figure 13A , Figure 13B , Figure 15A , Figure 15B , Figure 17 , Figure 18A , Figure 18B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 21E and Figure 21F This is a cross-sectional view illustrating a manufacturing process for providing a semiconductor memory device according to an embodiment of the present disclosure.

[0129] Figure 10 This is a plan view showing the process for forming a plurality of openings 113A and 113B and a plurality of sacrificial pillars 115 in the laminate 100. Figure 11A It is along Figure 10 A cross-sectional view of the laminate 100 taken by line I-I'. Figure 11B It is along Figure 10 The cross-sectional view of the laminate 100 taken by line II-II' is shown.

[0130] Reference Figure 10 , Figure 11A and Figure 11B A stack 100 may be formed over a substrate 101. The substrate 101 may include a silicon wafer. The substrate 101 may include an upper surface extending in a first direction DR1 and a second direction DR2 that intersect each other. The stack 100 may include a first insulating layer 103, a plurality of sacrificial layers 105, a plurality of second insulating layers 107 and a third insulating layer 109 disposed over the substrate 101.

[0131] Each of the first insulating layer 103, the plurality of second insulating layers 107, and the third insulating layer 109 may include an insulating material such as a silicon oxide layer and a silicon oxynitride layer. The plurality of sacrificial layers 105 may include materials with etch rates different from those of each of the first insulating layer 103, the plurality of second insulating layers 107, and the third insulating layer 109. According to an embodiment, the plurality of sacrificial layers 105 may include a sacrificial insulating material such as silicon nitride. The sacrificial layers 105 and the second insulating layers 107 may be arranged alternately on a third direction DR3 between the first insulating layer 103 and the third insulating layer 109. The third direction DR3 may be perpendicular to the top surface of the substrate 101.

[0132] Subsequently, a plurality of openings (113A and 113B) can be formed through the laminate 100. Each of the plurality of openings 113A can extend into the substrate 101. The plurality of openings may include a plurality of first openings 113A and a plurality of second openings 113B. The plurality of first openings 113A can be arranged in multiple rows, with the first openings 113A in each row arranged adjacent to each other in the second direction DR2. The plurality of second openings 113B can be disposed between the first openings 113A spaced apart from each other in the first direction DR1. According to an embodiment, the plurality of first openings 113A may include a first opening in a first row Ra and a first opening in a second row Rb separated from the first row Ra. The plurality of second openings 113B can be disposed between the first row Ra and the second row Rb and form at least one row.

[0133] Subsequently, a sacrificial layer can be used to fill each of the plurality of first openings 113A and the plurality of second openings 113B. The sacrificial layer may include titanium nitride (TiN) and carbon. The plurality of second openings 113B can then be exposed by removing the sacrificial layer from the plurality of second openings 113B using a masking process and an etching process. The remaining sacrificial layer can be used to form a plurality of sacrificial pillars 115 in the plurality of first openings 113A.

[0134] Figure 12 This is a plan view showing the process of filling multiple second openings 113B. Figure 13A It is along Figure 12 A cross-sectional view of the laminate 100 taken by line I-I'. Figure 13B It is along Figure 12 A cross-sectional view of the laminate 100 taken from line II-II'.

[0135] Reference Figure 12 , Figure 13A and Figure 13B A memory layer 121 can be formed on the inner wall of each of the second openings 113B. The memory layer 121 may include, for example, Figure 5B The barrier insulation layer BI, data storage layer DS, and tunnel isolation layer TI are shown. A channel post 123 and a core insulation layer 125 may be formed in the central region of the second opening 113B that is open through the memory layer 121.

[0136] According to an embodiment, the process of forming the channel pillar 123 and the core insulating layer 125 may include a process of forming a channel layer on the inner wall of the memory layer 121 and a process of filling the central region of the tubular structure defined by the channel layer with the core insulating layer 125 and a capping pattern. The channel layer may include a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof used as the channel region. The capping pattern may include a doped semiconductor layer. The channel layer and the capping pattern may form the channel pillar 123.

[0137] Although not shown, the process described above for forming the memory layer 121, channel pillars 123, and core insulating layer 125 can be used. Figure 9A and Figure 9B The described dummy memory layer, dummy channel pillar, and dummy core insulation layer.

[0138] Figure 14 This is a plan view showing the process of forming a plurality of first insulating structures 131. Figure 15A It is along Figure 14 The cross-sectional view of the laminate 100 taken by line I-I' is shown. Figure 15B It is along Figure 14 The cross-sectional view of the laminate 100 taken by line II-II' is shown.

[0139] Reference Figure 14 , Figure 15A and Figure 15B Some of the sacrificial posts 115 can be replaced by the first insulating structure 131. To do this, some of the multiple sacrificial posts 115 can be removed, and the areas where the sacrificial posts 115 have been removed can be filled with insulating material.

[0140] In each row, the first insulating structure 131 may be spaced apart from each other in the second direction DR2 with at least two sacrificial posts 115 arranged in the second direction DR2. According to an embodiment, referring to the first row Ra, the two sacrificial posts 115 arranged in the second direction DR2 may be disposed between the first insulating structures 131 that are separated from each other in the second direction DR2.

[0141] Figure 16This is a plan view illustrating the process of separating multiple preliminary gate stack structures 100PG from each other. Figure 17 It is along Figure 16 The diagram shows a cross-sectional view of the initial gate stack structure 100PG taken by line I-I'.

[0142] Reference Figure 16 and Figure 17 It can be removed Figure 14 , Figure 15A and Figure 15B Multiple sacrificial pillars 115 are shown to define multiple third openings 113OP. Multiple third openings 113OP and multiple first insulating structures 131 can form multiple rows.

[0143] Subsequently, each of the first insulating layer 103, the plurality of sacrificial layers 105, the plurality of second insulating layers 107, and the third insulating layer 109 may be partially etched such that adjacent third openings 113OP on the second direction DR2 in each row can be interconnected. As a result, a plurality of fourth openings 141 may be formed. Each fourth opening 141 may be defined by the interconnected third openings 113OP.

[0144] Each of the plurality of first insulating structures 131 may have its sidewall partially exposed through a plurality of fourth openings 141.

[0145] Multiple fourth openings 141 and multiple first insulating structures 131 can form multiple rows. In each row, the fourth openings 141 can be disposed between adjacent first insulating structures 131 in the second direction DR2. For example, referring to the first row Ra, the first insulating structures 131 and the fourth openings 141 can be alternately disposed on the second direction DR2 and can be connected to each other, with the fourth openings 141 disposed between adjacent first insulating structures 131 in the second direction DR2.

[0146] The stack 100 can be separated into multiple preliminary gate stack structures 100PG by multiple first insulating structures 131 and multiple fourth openings 141.

[0147] Figure 18A and Figure 18B This is a cross-sectional view showing the process performed after the process of separating multiple initial gate stack structures. Figure 18A and Figure 18B Show along Figure 16 The cross-section of the gate stack structure 150 is taken by line I-I'.

[0148] Reference Figure 18A Multiple fourth openings 141 can be used to selectively remove, such as Figure 17The preliminary gate stack structure 100PG shown has multiple sacrificial layers 105. Subsequently, multiple conductive layers 151 can be formed in the regions where the multiple sacrificial layers are removed. As a result, a gate stack structure 150 including a first insulating layer 103, multiple conductive layers 151, multiple second insulating layers 107, and a third insulating layer 109 can be formed.

[0149] In the implementation method, such as Figure 16 The plurality of first insulating structures 131 and channel posts 123 shown can be used as support structures to prevent or mitigate spatial distortion between the first insulating layer 103, the plurality of second insulating layers 107 and the third insulating layer 109 before the plurality of conductive layers 151 are formed after the plurality of sacrificial layers are removed.

[0150] Reference Figure 18B An insulating layer can be deposited on the surface of each of the plurality of fourth openings 141. As a result, a plurality of second insulating structures 161 can be formed in the plurality of fourth openings 141.

[0151] Subsequently, the central region of each of the plurality of fourth openings 141 can be filled with a conductive material. As a result, a plurality of first contact patterns 163 can be formed in the plurality of fourth openings 141. According to an embodiment, each of the first contact patterns 163 can be self-aligned in the central region corresponding to a fourth opening 141. Therefore, in an embodiment, misalignment errors in the plurality of first contact patterns 163 can be prevented or reduced. The plurality of first contact patterns 163 can be... Figure 16 The plurality of second insulating structures 161 and the plurality of first insulating structures 131 shown are insulated from the plurality of conductive layers 151.

[0152] The process of forming multiple first contact patterns 163 can be used to form such as Figure 9B The first source contact pattern shown is C1A' or C1B'.

[0153] Figure 19 This is a plan view showing the subsequent processes after the formation of multiple first contact patterns 163. Figure 20A It is along Figure 19 A cross-sectional view of the gate stack structure 150 taken by line I-I'. Figure 20B It is along Figure 19 The cross-sectional view of the gate stack structure 150 taken by line II-II' is shown.

[0154] Reference Figure 19 , Figure 20A and Figure 20B A fourth insulating layer 169 may be formed over multiple gate stack structures 150. The fourth insulating layer 169 may extend in a first direction DR1 and a second direction DR2 to cover multiple first contact patterns 163, multiple first insulating structures 131 and channel pillars 123.

[0155] Subsequently, a plurality of second contact patterns 171A and bit line contacts 171B can be formed through the fourth insulating layer 169. The plurality of second contact patterns 171A can be respectively connected to a plurality of first contact patterns 163. The bit line contacts 171B can be connected to the channel post 123.

[0156] The process of forming multiple second contact patterns 171A can be used to form Figure 9B The second source contact pattern shown is C2A' or C2B'.

[0157] Figures 21A to 21F This is a cross-sectional view showing the process performed after the formation of multiple second contact patterns 171A and bit line contacts 171B. Figures 21A to 21F Show along Figure 19 The cross-section of the gate stack structure 150 is taken by line I-I'.

[0158] Reference Figure 21A Multiple bit lines 181 may be formed above the fourth insulating layer 169. The multiple bit lines 181 may extend in the first direction DR1 and be spaced apart from each other in the second direction DR2.

[0159] The process of forming multiple bit lines 181 can be used to form it. Figure 8 , Figure 9A and Figure 9B The first common source structure CS_A or the second common source structure CS_B are shown.

[0160] Reference Figure 21B It can remove Figure 21A The substrate 101 is shown. As a result, the second insulating structure 161 and the memory layer 121 are exposed.

[0161] Although not shown, in removal Figure 21A Various processes can be performed on the substrate 101 shown.

[0162] According to the implementation method, in removing Figure 21A Before the substrate 101 shown, a substrate can be formed Figure 4A and Figure 4B The fifth insulating layer IL5 and the first unit side bonding pattern CBP1 shown are provided, and can provide Figure 4A and Figure 4B The first sub-peripheral circuit shown is 40A. For example... Figure 4A and Figure 4B As shown, the first unit-side bonding pattern CBP1 can be bonded to the first peripheral circuit-side bonding pattern PBP1 of the first sub-peripheral circuit 40A. After bonding, it can be removed. Figure 21A The substrate 101 shown.

[0163] In another embodiment, in removing Figure 21A Before the substrate 101 shown, a substrate can be formed Figure 9A and Figure 9B The fifth insulating layer IL5 and the unit-side bonding pattern CBP shown are provided, and can be provided with Figure 9A and Figure 9B The peripheral circuit 40 is shown. (e.g.) Figure 9A and Figure 9B As shown, the unit-side bonding pattern CBP can be bonded to the peripheral circuit-side bonding pattern PBP of the peripheral circuit 40. After bonding, it can be removed. Figure 21A The substrate 101 shown.

[0164] Reference Figure 21C The exposed portions of each of the second insulating structures 161 and the memory layer 121 can be selectively removed. The memory layer 121 can be etched to expose the ends of the channel pillars 123. Because the second insulating structure 161 is thicker than the memory layer 121, although the second insulating structure 161 is partially etched while the memory layer 121 is being removed, another portion of the second insulating structure 161 can be retained to cover the ends of each of the plurality of first contact patterns 163.

[0165] Reference Figure 21D The exposed portion of the channel pillar 123 can be covered by the doped semiconductor layer 201. The doped semiconductor layer 201 can extend to cover a plurality of second insulating structures 161. Each first contact pattern 163 can be separated from the doped semiconductor layer 201 through the second insulating structures 161.

[0166] Reference Figure 21E A portion of the etchable doped semiconductor layer 201 is made so that Figure 21D The doped semiconductor layer 201 shown can be separated into multiple source layers 201S. The multiple source layers 201S can overlap with multiple gate stack structures 150 respectively. The multiple source layers 201S can be patterned such that a corresponding first contact pattern 163 can be disposed between adjacent source layers 201S.

[0167] Subsequently, the etched areas of the doped semiconductor layer can be filled with an insulating material. As a result, a plurality of source isolation insulating layers 211 can be formed. Each source isolation insulating layer 211 can be disposed between adjacent source layers 201S and extend in the second direction DR2. The plurality of source isolation insulating layers 211 can overlap with a plurality of second insulating structures 161 and a plurality of first contact patterns 163.

[0168] Reference Figure 21FA sixth insulating layer 221 can be formed to cover multiple source layers 201S. Subsequently, multiple third contact patterns 231 can be formed through the sixth insulating layer 221, multiple source isolation insulating layers 211, and multiple second insulating structures 161. Each third contact pattern 231 can overlap with and be connected to a corresponding first contact pattern 163.

[0169] The process of forming multiple third contact patterns 231 can be used to form Figure 9B The third source contact pattern shown is C3A' or C3B'.

[0170] Although not shown, subsequent processes can be performed in various ways.

[0171] According to the implementation method, after forming the third contact pattern 231, a forming process can be performed. Figure 4A and Figure 4B The process and formation of the second conductive via structure V2 shown. Figure 4A and Figure 4B The process and formation of the common source structure CS shown Figure 4A and Figure 4B The process shown is for the seventh insulating layer IL7 and the second unit side bonding pattern CBP2. It can be supplied separately. Figure 4A and Figure 4B The second sub-peripheral circuit 40B is shown. In the formation... Figure 4A and Figure 4B After the second unit side bonding pattern shown, the second peripheral circuit side bonding pattern PBP2 of the second sub-peripheral circuit 40B can be bonded to the second unit side bonding pattern CBP2.

[0172] In another embodiment, the above references Figure 9A and Figure 9B The described second structure can be provided by a separate process. After the third contact pattern 231 is formed, the second structure can be bonded to the third contact pattern 231 and the sixth insulating layer 221.

[0173] Figure 22 This is a block diagram illustrating an electronic system 1000 according to an embodiment of the present disclosure.

[0174] Reference Figure 22 The electronic system 1000 may include a computing system, a medical device, a communication device, a wearable device, or a memory system. The electronic system 1000 may include a host 1100 and a storage device 1200.

[0175] Host 1100 can store data in storage device 1200 or read stored data from storage device 1200 based on an interface. The interface may include at least one of the following: Double Data Rate (DDR) interface, Universal Serial Bus (USB) interface, Multimedia Card (MMC) interface, Embedded MMC (eMMC) interface, Peripheral Component Interconnect (PCI) interface, High-Speed ​​PCI (PCI-E) interface, Advanced Technology Attachment (ATA) interface, Serial ATA interface, Parallel ATA interface, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Interface (IDE), FireWire interface, Universal Flash Memory (UFS) interface, and High-Speed ​​Non-Volatile Memory (NVMe) interface.

[0176] Storage device 1200 may include storage controller 1210 and semiconductor memory device 1220. According to an embodiment, storage device 1200 may be a solid-state drive (SSD), a universal serial bus (USB) memory, or the like.

[0177] The storage controller 1210 may store data in the semiconductor memory device 1220 or read data stored in the semiconductor memory device 1220 in response to control by the host 1100.

[0178] Semiconductor memory device 1220 may include a single memory chip or multiple memory chips. Semiconductor memory device 1220 may store data or output stored data in response to control by memory controller 1210.

[0179] Semiconductor memory device 1220 may be a non-volatile memory device. Semiconductor memory device 1220 may include a plurality of gate stack structures penetrated by a plurality of channel pillars, conductive via structures disposed between adjacent gate stack structures, and bit lines connected to the conductive via structures.

[0180] According to embodiments of this disclosure, the structure of a semiconductor memory device can be simplified by arranging conductive via structures connecting to bit lines between adjacent gate stack structures. Therefore, in these embodiments, structural defects occurring during the manufacturing process of the semiconductor memory device can be reduced, thereby improving the operational reliability of the semiconductor memory device.

[0181] It will be apparent to those skilled in the art that various modifications can be made to the above embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is intended to cover all such modifications, provided they fall within the scope of the appended claims and their equivalents.

[0182] Cross-reference to related applications

[0183] This application claims priority to Korean Patent Application No. 10-2024-0055435, filed with the Korean Intellectual Property Office on April 25, 2024, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Bit line array, the bit line array comprising a plurality of bit lines extending in a first direction; Multiple source layers extend in a second direction intersecting the multiple bit lines, and the multiple source layers overlap with the multiple bit lines; A plurality of gate stack structures are arranged in the first direction, each of the plurality of gate stack structures including a plurality of conductive layers stacked and spaced apart from each other in a third direction, the third direction being toward the plurality of source layers and away from the bit line array; Multiple channel pillars, the multiple channel pillars extending upward in the third direction to pass through the multiple gate stack structures respectively; A memory layer extends on the sidewall of each of the plurality of channel pillars; An isolation structure is disposed between adjacent gate stacks in the plurality of gate stacks, the isolation structure extending in the second direction; as well as A first conductive via structure is disposed in the isolation structure and is connected to a corresponding bit line among the plurality of bit lines.

2. The semiconductor memory device according to claim 1, wherein, Each of the plurality of gate stack structures corresponds to each of the plurality of source layers, and Each of the plurality of gate stack structures is disposed between the bit line array and the corresponding source layer in the plurality of source layers.

3. The semiconductor memory device according to claim 1, further comprising a source isolation insulating layer disposed between adjacent source layers among the plurality of source layers, overlapping the isolation structure, and penetrated by the first conductive via structure.

4. The semiconductor memory device according to claim 1, wherein, The isolation structure includes: A plurality of first insulating structures, the plurality of first insulating structures being spaced apart from each other in the second direction; and A second insulating structure is disposed between adjacent first insulating structures and surrounding the sidewall of the first conductive via structure.

5. The semiconductor memory device according to claim 1, further comprising: An insulating layer covering the plurality of source layers; A plurality of second conductive via structures, wherein the plurality of second conductive via structures pass through the insulating layer and are respectively connected to the plurality of source layers; as well as A common source structure is connected to the plurality of second conductive via structures and is disposed above the insulating layer.

6. The semiconductor memory device according to claim 1, wherein, Each of the plurality of channel pillars extends into the corresponding source layer among the plurality of source layers to contact the corresponding source layer.

7. The semiconductor memory device of claim 1, further comprising a plurality of bit line contacts connecting the plurality of channel pillars to the bit line array.

8. A semiconductor memory device, the semiconductor memory device comprising: A first linear array comprising a plurality of first lines extending in a first direction; A second bit line array is disposed above the first bit line array and includes a plurality of second bit lines extending in the first direction; A plurality of first source layers are disposed between the first bit line array and the second bit line array, extend in a second direction intersecting the plurality of first bit lines, and are arranged in the first direction; A plurality of second source layers are disposed between the plurality of first source layers and the second bit line array, extending in the second direction and arranged in the first direction; A first memory cell array is disposed between the first bit line array and the plurality of first source layers, and the first memory cell array is connected to a plurality of first gate stack structures arranged in the first direction. A second memory cell array is disposed between the second bit line array and the plurality of second source layers, and the second memory cell array is connected to a plurality of second gate stack structures arranged in the first direction. as well as A first conductive via structure includes a first portion disposed between the plurality of first gate stack structures and a second portion disposed between the plurality of second gate stack structures, and connects a first bit line among the plurality of first bit lines and a second bit line among the plurality of second bit lines as a pair of bit lines.

9. The semiconductor memory device according to claim 8, wherein, The first memory cell array includes: A plurality of first channel pillars, the plurality of first channel pillars being connected to the first bit line array, passing through the plurality of first gate stack structures, and connected to the plurality of first source layers; and A first memory layer extends on the sidewall of each of the plurality of first channel pillars, and The second memory cell array includes: A plurality of second channel pillars, the plurality of second channel pillars being connected to the second bit line array, passing through the plurality of second gate stack structures, and connected to the plurality of second source layers; and A second memory layer extends on the sidewall of each of the plurality of second channel pillars.

10. The semiconductor memory device of claim 8, further comprising: A first isolation structure is disposed between adjacent first gate stacks in the plurality of first gate stacks, extends in the second direction, and surrounds the first portion of the first conductive via structure; as well as A second isolation structure is disposed between adjacent gate stacks in the plurality of second gate stacks, extends in the second direction, and surrounds the second portion of the first conductive via structure.

11. The semiconductor memory device of claim 10, wherein, Each of the first isolation structure and the second isolation structure includes: A plurality of first insulating structures, the plurality of first insulating structures being spaced apart from each other in the second direction; and A second insulating structure is disposed between adjacent first insulating structures and surrounding the sidewall of the first conductive via structure.

12. The semiconductor memory device of claim 8, further comprising: A first source isolation insulating layer is disposed between adjacent first source layers among the plurality of first source layers and is penetrated by the first portion of the first conductive via structure. as well as A second source isolation insulating layer is disposed between adjacent second source layers among the plurality of second source layers and is penetrated by the second portion of the first conductive via structure.

13. The semiconductor memory device of claim 8, further comprising: A first common source structure is spaced apart from the first bit line array in the second direction; as well as A second common source structure, which is spaced apart from the second bit line array in the second direction. The plurality of first source layers and the plurality of second source layers extend to overlap with the first common source structure and the second common source structure.

14. The semiconductor memory device of claim 13, further comprising a second conductive via structure including a first source contact portion and a second source contact portion, the first source contact portion being connected to the first common source structure extending between the plurality of first source layers, and the second source contact portion being connected to the second common source structure extending between the plurality of second source layers. in, Among the plurality of first source layers, the adjacent first source layer with the first source contact portion inserted therein contacts the first source contact portion, and The adjacent second source layer in which the second source contact portion is inserted among the plurality of second source layers contacts the second source contact portion.

15. The semiconductor memory device according to claim 14, wherein, The plurality of first gate stack structures and the plurality of second gate stack structures extend to overlap with the first common source structure and the second common source structure.

16. The semiconductor memory device of claim 15, further comprising a lower insulating structure and an upper insulating structure, the lower insulating structure being disposed between adjacent first gate stacks in the plurality of first gate stacks, and the upper insulating structure being disposed between adjacent second gate stacks in the plurality of second gate stacks. in, The first source contact portion of the second conductive via structure includes a portion disposed in the lower insulating structure, and The second source contact portion of the second conductive via structure includes a portion disposed within the upper insulating structure.

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