High-speed high-density low-disturbance ferroelectric memory structure and preparation method thereof
By adopting the three-dimensional integration of multi-layer vertical storage cell columns and metal word line planar overlapping structure and selection device dielectric layer in ferroelectric cross-point matrix memory, and utilizing the dynamic voltage division characteristics of the selection device, the disturbance problem of ferroelectric memory during writing is solved, and storage operations with higher density and lower bit error rate are achieved.
Patent Information
- Application Number
- CN202410521331.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-28
- Publication Date
- 2025-10-28
AI Technical Summary
When writing information into existing ferroelectric cross-point memory, unselected cells are easily disturbed by voltage pulses, resulting in bit flipping problems, making it difficult to achieve high-speed and low-disturbance storage operations.
A multi-layer vertical memory cell column and metal word line plane overlapping structure is adopted, combined with the three-dimensional integration of the selection device dielectric layer and the ferroelectric dielectric layer. The dynamic voltage division characteristics of the selection device are utilized to control the voltage distribution by applying a half-selection voltage, thereby reducing the disturbance degree of the unselected cells.
It achieves higher storage density and lower bit error rate, improves the anti-disturbance performance of the storage unit, and reduces the impact of write disturbance.
Smart Images
Figure CN120857508A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor memory, and in particular to a high-speed, high-density, low-disturbance ferroelectric memory structure and its fabrication method. Background Art
[0002] With the widespread adoption of big data and AIoT applications, massive amounts of data require high-speed and low-power storage and access, posing a significant challenge to existing memory technologies. In recent years, novel two-terminal non-volatile memories have been extensively researched, capable of forming the smallest in-plane 4F... 2 Cell-area cross-matrix memory arrays, with the ability to be stacked in three dimensions, can significantly improve storage density. Common double-ended non-volatile devices include resistive devices (RRAM, MRAM, PCRAM, etc.) and capacitive devices (FeRAM). Among them, cross-matrix memory based on ferroelectric capacitance has the characteristics of ultra-low power access and fast readout due to its field-induced switching and polarization readout features. Moreover, due to its good reliability and fluctuation characteristics, it is one of the popular technologies for next-generation memory.
[0003] Among different types of ferroelectric capacitor memories, hafnium oxide (HfO2)-based ferroelectric materials exhibit excellent CMOS process compatibility and size miniaturization potential, making them more suitable for high-density memory fabrication and integration compared to traditional ferroelectric materials. Cross-array memories based on ferroelectric capacitors offer high storage density; however, due to the polycrystalline and multi-domain characteristics of HfO2-based ferroelectric materials and the wide coercive field distribution of its ferroelectric domains, unselected cells are subject to voltage pulse perturbations when writing information to cells in a cross-array array without gated transistors, easily causing severe bit-flipping problems. Therefore, realizing high-speed, low-perturbation ferroelectric cross-array memories has become an urgent problem to be solved. Summary of the Invention
[0004] The purpose of this invention is to propose a high-speed, high-density, low-disturbance cross-matrix ferroelectric memory structure and a three-dimensional integration method. This invention has higher storage density per unit area and lower bit error rate.
[0005] The specific technical solution of this invention is as follows:
[0006] A low-disturbance cross-matrix ferroelectric memory structure is characterized by being formed by the overlapping of multiple vertical memory cell pillars and multiple horizontal metal word line planes; each memory cell pillar is composed of bit line metal, an intermediate conductive layer, a select device dielectric layer, and a ferroelectric dielectric layer from the inside out; the intersection of each metal word line and a single memory cell pillar forms a memory cell, which is formed by a select device and a ferroelectric capacitor connected in series; by simultaneously applying corresponding half-select voltages to the metal word line and the metal bit line, the memory cell connected to the metal word line and the metal bit line completes the access operation.
[0007] The selection device dielectric layer in the memory cell of this invention has selective variable capacitance or variable resistance characteristics, which is electrically equivalent to a device whose capacitance / resistance value changes with the applied voltage. When the voltage applied to the memory cell is lower than a certain limit, the selection device is in a high resistance or small capacitance state. When the voltage applied to the memory cell exceeds a certain limit, the selection device switches to a low resistance or large capacitance state. The memory cell of this invention is electrically equivalent to a ferroelectric capacitor connected in series with a select device. When a half-select voltage is applied simultaneously to the metal word line and metal bit line of the selected memory cell, the memory cell is affected by twice the half-select voltage, and the select device switches to a low-resistance or high-capacitance state. At this time, due to the small RC delay caused by the low resistance of the select device, or the small voltage division caused by the large capacitance of the select device, most of the voltage will drop to the ferroelectric capacitor with a relatively smaller capacitance value, causing the ferroelectric capacitor to undergo polarization reversal, thus completing the access operation of the selected cell. Other memory cells connected to the selected metal word line and metal bit line are disturbed cells, which are affected by one half-select voltage. The select device maintains a high-resistance or high-capacitance state. At this time, due to the large RC delay or the large voltage division caused by the small capacitance of the select device, most of the voltage drops to the select device with a relatively smaller capacitance value, thereby reducing the voltage on the ferroelectric capacitor in the disturbed cell and reducing the degree of disturbance of the disturbed cell.
[0008] To provide sufficient stress during annealing to allow ferroelectric crystal formation in the ferroelectric dielectric layer, the metal bit lines, intermediate conductive layer, and metal word lines in the aforementioned memory cell can be selected from the following: TiN, TaN, Pt, Mo, Ru, W, etc. The selected device dielectric layer is based on HfO2, ZrO2, or TaO. x and NbO x The dielectric material can produce variable capacitance or variable resistance effects; the ferroelectric dielectric layer adopts traditional ferroelectric materials such as perovskite ferroelectric (PZT, BFO, SBT) and ferroelectric polymer (P(VDF-TrFE)) or novel ferroelectric materials based on HfO2 that produce ferroelectricity under specific treatments (doping, stress, annealing, etc.). In the above-mentioned ferroelectric capacitor memory based on cross-matrix, the thickness of the metal bit lines, intermediate conductive layer, and metal word lines is preferably 5–50 nm; the thickness of the select device dielectric layer and the ferroelectric dielectric layer is preferably 5–30 nm.
[0009] Furthermore, the present invention provides a method for fabricating a low-disturbance cross-array ferroelectric memory, the fabrication steps of which include:
[0010] 1) Si3N4 word wire sacrificial material is grown on the surface of a substrate or insulating material SiO2 by chemical vapor deposition (CVD).
[0011] 2) SiO2 insulating dielectric material is grown on the surface of Si3N4 sacrificial material by CVD;
[0012] 3) Repeat steps 1) and 2) several times to prepare a multi-layered structure with alternating Si3N4-SiO2 growth on a SiO2 substrate;
[0013] 4) Define the top and bottom surface patterns of the memory cell pillars using photolithography, and form through-holes that penetrate the stacked structure using dry etching.
[0014] 5) Selectively remove a portion of Si3N4 from the sidewall of the via using wet etching or dry etching methods to form trenches on the sidewall of the via.
[0015] 6) Ferroelectric materials are grown on the inner wall of through-holes using atomic layer deposition (ALD).
[0016] 7) Etch away excess ferroelectric material outside the trenches on the sidewalls of the through holes, and remove a portion of the ferroelectric material inside the trenches near the edges;
[0017] 8) Grow intermediate metal material on the inner wall of the through hole using ALD or CVD methods;
[0018] 9) Etch away excess intermediate metal material outside the trench on the sidewall of the through hole, and remove a portion of the intermediate metal material inside the trench near the edge;
[0019] 10) Selective device dielectric materials are grown on the inner wall of vias using atomic layer deposition (ALD).
[0020] 11) Etch away excess selectable device dielectric material outside the trenches on the sidewalls of the vias;
[0021] 12) Metal wire material is grown on the inner wall of the through hole by ALD or CVD method;
[0022] 13) Remove excess metal material deposited on the surface of the stacked structure by etching;
[0023] 14) Define the bottom layer bit line pattern using photoresist and pattern the first layer bit line using dry etching.
[0024] 15) Define the pattern of each metal bit line electrode by multiple photoresist trimming processes, and pattern each bit line metal layer sequentially by dry etching, stacking layers to form a stepped structure, exposing each bit line electrode for contact.
[0025] 16) Based on the division of the memory array structure, the bit line pattern is defined by photolithography, and the bit lines are cut by wet etching or dry etching to form a discrete memory cell array.
[0026] 17) Selectively remove the sacrificial material of the Si3N4 word lines in the stack by wet etching or dry etching.
[0027] 18) Fill the word line positions with metallic material using ALD or CVD methods;
[0028] 19) Remove excess letter line metal material deposited in other locations by dry etching;
[0029] 20) The ferroelectric dielectric layer exhibits ferroelectric properties through rapid thermal annealing (RTA) crystallization.
[0030] The advantages and basic principles of the selected device-ferroelectric capacitor cross-matrix memory of this invention:
[0031] This invention utilizes the three-dimensional stacking capability of the ferroelectric dielectric layer and the selector dielectric layer to integrate the ferroelectric capacitor and the selector in the overlapping area of the memory cell pillar and the metal word line plane. This significantly increases the number of memory cells within the cell area, breaking through the cell density limitation of traditional planar cross-matrix capacitor memories and achieving higher cell area storage density. Furthermore, by utilizing the dynamic voltage division characteristics of the selector, the disturbance rejection performance of the ferroelectric capacitor in the memory cell is greatly improved. When accessing a memory cell in the cross-matrix memory, the metal word line and metal bit line corresponding to the selected memory cell are simultaneously applied. When the positive / negative half-select voltage is applied, the memory cell is affected by twice the half-select voltage. The selector switches to a low-resistance or high-capacitance state, causing most of the voltage to drop across the ferroelectric capacitor, which has a relatively smaller capacitance value. This causes the ferroelectric capacitor to reverse its polarization, thus completing the access operation to the selected cell. Other memory cells connected to the selected word line and bit line are disturbed cells. They are affected by one half-select voltage, and the selector maintains a high-resistance or high-capacitance state. Therefore, most of the voltage drops across the selector, thereby reducing the voltage on the ferroelectric capacitor in the disturbed cell and reducing the degree of disturbance to the disturbed cell. Attached Figure Description
[0032] Figure 1 This is a schematic diagram of the three-dimensional stacked high-speed, high-density, low-disturbance ferroelectric memory array structure of the present invention.
[0033] In the picture:
[0034] 1 — Single memory cell column
[0035] 2 - Metallic lettering
[0036] 3——Selection of Devices-Ferroelectric Capacitor Cross-dot Array
[0037] Figure 2 This is a schematic diagram of a single vertical storage cell column structure according to the present invention.
[0038] In the picture:
[0039] 4 - Metallic lettering
[0040] 5—Ferroelectric layer
[0041] 6—Selecting the Device Dielectric Layer
[0042] 7—Intermediate conductive layer
[0043] 8 - Metal Part Line
[0044] 9 – Single storage unit
[0045] Figure 3 This is an electrical schematic diagram of the low-disturbance cross-dot ferroelectric memory structure of the present invention.
[0046] In the picture:
[0047] 10 - Bit Line
[0048] 11 - Word Line
[0049] 12 — Single storage unit
[0050] 13—Selecting Devices
[0051] 14—Ferroelectric Capacitors Detailed Implementation
[0052] The invention will be further described below with reference to the accompanying drawings and through implementation.
[0053] like Figure 1 As shown, this embodiment provides a low-disturbance cross-point ferroelectric memory structure, such as... Figure 1 As shown, the low-disturbance cross-matrix ferroelectric memory structure consists of several metal word line planes and several memory cell pillars, as shown in the figure. Figure 2 As shown, from the inside out, it consists of bit line metal, an intermediate conductive layer, a select device dielectric layer, and a ferroelectric dielectric layer. The intersection of each metal word line and a single memory cell pillar forms a memory cell, which is composed of a select device and a ferroelectric capacitor connected in series. The word line plane / bit line metal and the intermediate conductive layer can provide sufficient stress during annealing to allow the ferroelectric dielectric layer to form ferroelectric crystals. The selected dielectric layer can be selected from the following metal materials as required: TiN, TaN, Pt, Mo, Ru, W, etc. The select device dielectric layer uses an oxide dielectric material that can produce resistive or capacitive switching effects under different voltages and has three-dimensional stacking capability. It can be selected from the following as required: HfO2, ZrO2, TaO2, etc. x NbO xThe ferroelectric dielectric layer is constructed using a ferroelectric material that can generate ferroelectricity and has three-dimensional stacking capability, such as HfO2, which exhibits ferroelectricity under specific treatments (doping, stress, annealing, etc.); the thickness of the word line plane / bit line metal and the intermediate conductive layer is preferably 5 to 50 nm; the thickness of the ferroelectric dielectric layer and the select device dielectric layer is preferably 5 to 30 nm.
[0054] This invention also provides a method for fabricating the above-mentioned low-disturbance cross-point ferroelectric memory, the fabrication process of which is as follows:
[0055] (1) Si3N4 word line sacrificial material is grown on the surface of a substrate or insulating material SiO2 by chemical vapor deposition (CVD);
[0056] (2) SiO2 isolation dielectric material was grown on the surface of Si3N4 sacrificial material by CVD;
[0057] (3) Repeat steps (1) and (2) several times to grow a multi-layered structure with alternating Si3N4-SiO2 on a SiO2 substrate.
[0058] (4) Define the top and bottom surface pattern of the memory cell pillar by photolithography, and form through holes of the memory cell pillar through the stacked structure by dry etching.
[0059] (5) Selectively remove a portion of Si3N4 from the sidewall of the through hole by wet etching or dry etching to form a trench on the sidewall of the through hole.
[0060] (6) Ferroelectric materials are grown on the inner wall of through-holes by atomic layer deposition (ALD);
[0061] (7) Etch away excess ferroelectric material outside the trench on the sidewall of the through hole, and remove a portion of the ferroelectric material inside the trench near the edge;
[0062] (8) An intermediate metal material is grown on the inner wall of the through hole by ALD or CVD.
[0063] (9) Etch away excess intermediate metal material outside the trench on the sidewall of the through hole, and remove a portion of the intermediate metal material inside the trench near the edge;
[0064] (10) Selective device dielectric material is grown on the inner wall of the via using atomic layer deposition (ALD);
[0065] (11) Etching removes excess selectable device dielectric material other than the trenches on the sidewall of the via;
[0066] (12) Growing metal wire material in the through-hole by ALD or CVD method;
[0067] (13) Remove excess metal material deposited on the surface of the stacked structure by etching;
[0068] (14) Define the bottom layer bit line pattern using photoresist and pattern the first layer bit line using dry etching;
[0069] (15) Define the pattern of each bit line electrode by multiple photoresist trimming processes, and pattern each bit line metal layer sequentially by dry etching, stacking layers to form a stepped structure, exposing each bit line electrode layer for contact.
[0070] (16) Based on the division of the storage array structure, the bit line pattern is defined by photolithography, and the bit lines are cut by wet etching or dry etching to form a discrete storage cell array.
[0071] (17) Selectively remove the sacrificial material of the Si3N4 word line in the stack by wet etching or dry etching;
[0072] (18) Fill the word line positions with metal material by ALD or CVD method;
[0073] (19) Remove excess metal material deposited in other locations by dry etching;
[0074] (20) Ferroelectric dielectric materials are made ferroelectric by rapid thermal annealing (RTA) crystallization.
[0075] The beneficial effects of the present invention are illustrated in this embodiment:
[0076] This invention utilizes the three-dimensional stacking capability of the ferroelectric dielectric layer and the selector dielectric layer to integrate the ferroelectric capacitor and the selector in the overlapping area of the memory cell pillar and the metal word line plane. By utilizing the dynamic voltage division characteristics of the selector, the disturbance rejection performance of the memory cell ferroelectric capacitor is greatly improved, reducing memory write disturbances while significantly increasing its memory window, thus achieving more reliable data storage capability.
[0077] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.
Claims
1. A low-disturbance ferroelectric memory structure, characterized in that, It is formed by the overlapping of multiple vertical memory cell pillars and multiple horizontal metal word line planes; the memory cell pillar is composed of metal bit lines, intermediate conductive layers, select device dielectric layers and ferroelectric dielectric layers from the inside out; the intersection of each metal word line and a single memory cell pillar forms a memory cell, which is composed of a select device and a ferroelectric capacitor connected in series; by simultaneously applying corresponding half-select voltages to the metal word line and the metal bit line, the memory cell connected to the metal word line and the metal bit line completes the access operation.
2. The low-disturbance ferroelectric memory structure as described in claim 1, characterized in that, The metal bit line, intermediate conductive layer and metal word line are selected from one of the following materials: TiN, TaN, Pt, Mo, Ru or W.
3. The low-disturbance ferroelectric memory structure as described in claim 1, characterized in that, The dielectric layer of the selected device uses HfO2, ZrO2, and TaO. x or NbO x .
4. The low-disturbance ferroelectric memory structure as described in claim 1, characterized in that, The ferroelectric dielectric layer is made of perovskite-type ferroelectric material, ferroelectric polymer, or novel ferroelectric material based on HfO2 that exhibits ferroelectricity under specific treatment.
5. The low-disturbance ferroelectric memory structure as described in claim 1, characterized in that, The thickness of the metal bit line, intermediate conductive layer and metal word line ranges from 5 to 50 nm.
6. The low-disturbance ferroelectric memory structure as described in claim 1, characterized in that, The thickness range of the selected device dielectric layer and ferroelectric dielectric layer is 5–30 nm.
7. The fabrication method of the low-disturbance cross-array ferroelectric memory as described in claim 1, wherein the fabrication steps include: 1) Si3N4 word wire sacrificial material is grown on the surface of a substrate or insulating material SiO2 by chemical vapor deposition (CVD). 2) SiO2 insulating dielectric material is grown on the surface of Si3N4 sacrificial material by CVD; 3) Repeat steps 1) and 2) several times to prepare a multi-layered structure with alternating Si3N4-SiO2 growth on a SiO2 substrate; 4) Define the top and bottom surface patterns of the memory cell pillars using photolithography, and form through-holes that penetrate the stacked structure using dry etching. 5) Selectively remove a portion of Si3N4 from the sidewall of the via using wet etching or dry etching methods to form trenches on the sidewall of the via. 6) Ferroelectric materials are grown on the inner wall of through-holes using atomic layer deposition (ALD). 7) Etch away excess ferroelectric material outside the trenches on the sidewalls of the through holes, and remove a portion of the ferroelectric material inside the trenches near the edges; 8) Grow intermediate metal material on the inner wall of the through hole using ALD or CVD methods; 9) Etch away excess intermediate metal material outside the trench on the sidewall of the through hole, and remove a portion of the intermediate metal material inside the trench near the edge; 10) Selective device dielectric materials are grown on the inner wall of vias using atomic layer deposition (ALD). 11) Etch away excess selectable device dielectric material outside the trenches on the sidewalls of the vias; 12) Growing metallic bit line material within through-holes using ALD or CVD methods; 13) Remove excess metal material deposited on the surface of the stacked structure by etching; 14) Define the bottom layer bit line pattern using photoresist and pattern the first layer bit line using dry etching. 15) Define the pattern of each metal bit line by multiple photoresist trimming processes, and pattern each metal bit line sequentially by dry etching. Stack the layers to form a stepped structure, exposing each metal bit line for contact. 16) Based on the division of the memory array structure, the bit line pattern is defined by photolithography, and the bit lines are cut by wet etching or dry etching to form a discrete memory cell array. 17) Selectively remove the sacrificial material of the Si3N4 word lines in the stack by wet etching or dry etching. 18) Fill the word line positions with metallic material using ALD or CVD methods; 19) Remove excess metallic lettering material deposited in other locations by dry etching; 20) Ferroelectric dielectric layers exhibit ferroelectric properties through rapid thermal annealing (RTA) crystallization.