Transistor, gallium nitride device and preparation method thereof
By employing multiple spaced p-GaN structures and field plate structures in the transistor, the problem of film stress mismatch was solved, the device yield was improved, the electric field distribution was enhanced, and high-frequency crosstalk was reduced.
Patent Information
- Application Number
- CN202510780004.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-12
- Publication Date
- 2025-10-28
AI Technical Summary
The problem of mismatched film stress in existing transistors leads to cracks in the p-GaN layer, affecting device yield.
Multiple p-GaN structures spaced apart along the first direction are used in combination with a field plate structure to release stress, avoid stress mismatch, and improve electric field distribution.
It effectively avoids cracks in the p-GaN layer, improves transistor yield, and enhances the electric field distribution under high voltage, reducing high-frequency crosstalk.
Smart Images
Figure CN120857552A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the semiconductor field, and in particular to a transistor, a gallium nitride device, and a method for fabricating the same. Background Art
[0002] A transistor is a semiconductor device that is widely used in wireless communication, radio frequency amplification, satellite communication, radar systems, and high-efficiency power management.
[0003] The related technology provides a transistor comprising a channel layer, a barrier layer and a p-GaN layer stacked sequentially.
[0004] The aforementioned transistors suffer from a problem of mismatch in film stress. Summary of the Invention
[0005] This disclosure provides a transistor, a gallium nitride device, and a method for fabricating the same, effectively solving the problem of stress mismatch in transistor films. The technical solution is as follows:
[0006] On one hand, a transistor is provided, the transistor comprising:
[0007] Channel layer, barrier layer, p-GaN layer, gate, source and drain;
[0008] The barrier layer is located in the channel layer, the source and the drain are located in the barrier layer, and the source and the drain are located on opposite sides of the barrier layer, respectively.
[0009] The p-GaN layer is located in the barrier layer and between the source and the drain. The p-GaN layer includes a plurality of p-GaN structures spaced apart along a first direction. The first direction is perpendicular to a second direction, and the second direction is the direction from the source to the drain.
[0010] The gate is located on a plurality of the p-GaN structures.
[0011] Optionally, the transistor further includes a field plate structure located between the p-GaN layer and the barrier layer;
[0012] The field plate structure includes multiple spaced field plate substructures, each corresponding to a multiple p-GaN structure, with one end of each field plate structure extending out of the p-GaN structure toward the drain.
[0013] Optionally, the transistor further includes: a field plate structure located between the p-GaN layer and the drain, and connected to the p-GaN layer;
[0014] The field plate structure includes multiple spaced field plate substructures, each corresponding to a multiple p-GaN structure.
[0015] Optionally, the p-GaN structure is a first cuboid, and the field plate substructure is a second cuboid with a stepped structure.
[0016] The length of the first cuboid is 35–1500 nm, the width is 200–500 nm, and the height is 30–120 nm;
[0017] The second cuboid has a length of 35–1500 nm, a width of 300–1000 nm, and a height of 30–120 nm; the total width of the stepped structure is 100–500 nm, and the total height of the stepped structure is 100–500 nm.
[0018] Optionally, the p-GaN structure is a first cuboid, and the field plate structure is a third cuboid with a concave arc surface;
[0019] The length of the third cuboid is 35–1500 nm, the width is 100–1000 nm, and the height is 30–120 nm; the arc length of the concave arc surface is 2000–5000 nm, and the curvature of the concave arc surface is 15–25°.
[0020] Optionally, the p-GaN structure is a first cuboid, and the field plate structure is a fourth cuboid with a raised arc surface;
[0021] The fourth cuboid has a length of 35–1500 nm, a width of 100–1000 nm, and a height of 30–120 nm; the arc length of the convex arc surface is 2000–5000 nm, and the arc angle of the convex arc surface is 15–25°.
[0022] Optionally, the material of the field plate structure is u-GaN or metal.
[0023] On the other hand, a gallium nitride device includes: a substrate, a first transistor, and a second transistor;
[0024] The substrate comprises a nucleation layer, a buffer layer, and a high-resistivity layer stacked sequentially.
[0025] The first transistor and the second transistor are disposed on the substrate at intervals, and the nucleation layer, the buffer layer and the high-resistivity layer between the first transistor and the second transistor have isolation trenches;
[0026] The first transistor and the second transistor are transistors as described above.
[0027] Optionally, the width of the isolation groove is 20 to 1000 μm.
[0028] On the other hand, a transistor fabrication method,
[0029] Create the channel layer;
[0030] A barrier layer is fabricated, the barrier layer being located within the channel layer;
[0031] A p-GaN layer is fabricated, the p-GaN layer being located in the barrier layer, the p-GaN layer comprising a plurality of p-GaN structures spaced apart along a first direction, the first direction being perpendicular to a second direction;
[0032] A source and a drain are fabricated, with the source and the drain located on opposite sides of the barrier layer, and the p-GaN layer located on the barrier layer and between the source and the drain. The second direction is the direction from the source to the drain.
[0033] A gate is fabricated on a plurality of the p-GaN structures.
[0034] The beneficial effects of the technical solutions provided in this disclosure are:
[0035] In this embodiment, the p-GaN layer includes multiple p-GaN structures spaced apart along a first direction, rather than a monolithic structure. This can disperse stress, avoid stress mismatch between p-GaN and the barrier layer, release stress in the p-GaN layer, prevent cracks in the p-GaN layer, and improve transistor yield. Attached Figure Description
[0036] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0037] Figure 1 This is a schematic diagram of the structure of a transistor provided in an embodiment of this disclosure;
[0038] Figure 2 yes Figure 1 A top view of the provided transistor;
[0039] Figure 3 This is a schematic diagram of another transistor structure provided in an embodiment of this disclosure;
[0040] Figure 4 yes Figure 3 A top view of the provided transistor;
[0041] Figure 5 This is a top view of another transistor provided in an embodiment of this disclosure;
[0042] Figure 6 yes Figure 5 The provided schematic diagram of the transistor structure;
[0043] Figure 7 This is a schematic diagram of another transistor structure provided in an embodiment of this disclosure;
[0044] Figure 8 This is a schematic diagram of the structure of a transistor provided in an embodiment of this disclosure;
[0045] Figure 9 This is a schematic diagram of the structure of a gallium nitride device provided in an embodiment of this disclosure;
[0046] Figure 10 This is a flowchart of a transistor fabrication method provided in an embodiment of this disclosure;
[0047] Figure 11 This is a flowchart of a gallium nitride device fabrication method provided in an embodiment of this disclosure;
[0048] Figure 12 This is a comparison diagram of the electric field strength of the gallium nitride device provided in the embodiments of this disclosure and the gallium nitride device provided in related technologies;
[0049] Figure 13 This is a comparison diagram of the voltage and electric field strength of the gallium nitride device provided in the embodiments of this disclosure and the gallium nitride device provided in related technologies;
[0050] Figure 14 This is a comparison chart of the voltage and unit leakage current of epitaxial structures with different thicknesses provided in the embodiments of this disclosure.
[0051] The attached figures are labeled as follows:
[0052] 10: Substrate; 20: First transistor; 30: Second transistor; 40: Capacitor; 50: Resistor; 60: Diode; 70: Low-voltage enhancement-mode transistor;
[0053] 100: Substrate; 101: Nucleation layer; 102: Buffer layer; 103: High-resistivity layer; 104: Channel layer; 105: Barrier layer; 106: Field plate structure; 107: p-GaN layer; 108: Gate; 109: Source; 110: Drain; 111: Planarization layer; 112: Conductive metal; 113: Passivation layer;
[0054] 161: Field plate structure; 171: p-GaN structure;
[0055] 1001: Isolation tank. Detailed Implementation
[0056] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0057] Figure 1 This is a schematic diagram of a transistor structure provided in an embodiment of this disclosure. See also... Figure 1 The transistor includes: a channel layer 104, a barrier layer 105, a p-GaN layer 107, a gate 108, a source 109, and a drain 110.
[0058] The barrier layer 105 is located in the channel layer 104, the source 109 and the drain 110 are located in the barrier layer 105, and the source 109 and the drain 110 are located on opposite sides of the barrier layer 105.
[0059] Figure 2 yes Figure 1 A top view of the provided transistor. See also... Figure 2 The p-GaN layer 107 is located in the barrier layer 105 and between the source 109 and the drain 110. The p-GaN layer 107 includes a plurality of p-GaN structures 171 spaced apart along a first direction. The first direction is perpendicular to a second direction, which is the direction from the source 109 to the drain 110.
[0060] The gate 108 is located on multiple p-GaN structures 171.
[0061] In this embodiment, the p-GaN layer includes multiple p-GaN structures spaced apart along a first direction, rather than a monolithic structure. This can disperse stress, avoid stress mismatch between p-GaN and the barrier layer, release stress in the p-GaN layer, prevent cracks in the p-GaN layer, and improve transistor yield.
[0062] Figure 3 This is a schematic diagram of another transistor structure provided in an embodiment of this disclosure. Figure 4 yes Figure 3 A top view of the provided transistor. See also... Figure 3 and Figure 4 The transistor also includes a field plate structure 106, which is located between the p-GaN layer 107 and the barrier layer 105.
[0063] The field plate structure 106 includes multiple field plate substructures 161 arranged at intervals, and the multiple field plate substructures 161 correspond to multiple p-GaN structures 171. The p-GaN structure 171 extends from one end of the field plate structure 161 toward the drain 110.
[0064] In this implementation, the field plate structure is located between the p-GaN layer and the barrier layer, with the p-GaN structure extending towards the drain. By laterally positioned between the gate and drain, the electric field distribution under high voltage is improved, and the electric field strength is typically 1×10⁻⁶. 4 It will not break down the p-GaN layer; multiple field plate substructures correspond to multiple p-GaN structures, which can release the stress between the field plate structure and the barrier layer, disperse the stress, and prevent cracks from appearing in the field plate structure.
[0065] In this embodiment of the disclosure, the field plate substructure 161 can be a cuboid, with a length of 900-1000 μm, a width of 450-550 nm, and a height of 30-120 nm.
[0066] For example, the field plate substructure 161 can be a cuboid with a length of 960 μm, a width of 500 nm, and a height of 60 nm.
[0067] In this embodiment, the p-GaN structure 171 can be a cuboid, with a length of 35–1500 nm, a width of 40–60 nm, and a height of 30–120 nm.
[0068] For example, the p-GaN structure 171 can be a cuboid with a length of 1000 nm, a width of 50 nm, and a height of 60 nm.
[0069] Figure 5 This is a top view of another transistor provided in an embodiment of this disclosure. Figure 6 yes Figure 5 A schematic diagram of the transistor structure is provided. Figure 5 and Figure 4 The difference lies in the position of the field plate structure 106. See also Figure 5 and Figure 6 The transistor also includes a field plate structure 106, which is located between the p-GaN layer 107 and the drain 110 and is connected to the p-GaN layer 107.
[0070] The field plate structure 106 includes multiple field plate substructures 161 arranged at intervals, and the field plate substructures 161 correspond to multiple p-GaN structures 171.
[0071] In this implementation, the field plate structure is located between the p-GaN layer and the drain. By being positioned laterally between the gate and drain, it improves the electric field distribution under high voltage, with an electric field strength typically of 1×10⁻⁶. 3 It will not break down the p-GaN layer; multiple field plate substructures correspond to multiple p-GaN structures, which can release the stress between the field plate structure and the barrier layer, disperse the stress, and prevent cracks from appearing in the field plate structure.
[0072] In this embodiment of the disclosure, the p-GaN structure 171 is a first cuboid, and the field plate structure 161 is a second cuboid with a stepped structure.
[0073] The length of the first cuboid can be 35–1500 nm, the width can be 200–500 nm, and the height can be 30–120 nm.
[0074] The length of the second cuboid can be 35–1500 nm, the width can be 300–1000 nm, and the height can be 30–120 nm; the total width of the stepped structure can be 100–500 nm, and the total height of the stepped structure can be 100–500 nm.
[0075] In this embodiment of the disclosure, the height of each step in the step structure remains constant along the direction toward the barrier layer, and the width of each step in the step structure remains constant.
[0076] In this implementation, the p-GaN structure and field plate substructure with the above dimensions are not too large, which makes it easy to set them at intervals to release the stress of the p-GaN structure and field plate structure, and they are not too small either, which can improve the electric field distribution under high voltage.
[0077] For example, the first cuboid has a length of 1000nm, a width of 300nm, and a height of 100nm.
[0078] The second cuboid has a length of 1000nm, a width of 400nm, and a height of 100nm; the total width of the stepped structure is 400nm, and the total height of the stepped structure is 100nm.
[0079] For example, the step structure includes four steps, each step having a height of 25 nm and a width of 100 nm.
[0080] In this embodiment of the disclosure, the distance between two adjacent first cuboids can be 100 to 1000 nm.
[0081] For example, the distance between two adjacent first cuboids is 500 nm.
[0082] In this embodiment of the disclosure, the distance between two adjacent second cuboids can be 100 to 1000 nm.
[0083] For example, the distance between two adjacent second cuboids is 500 nm.
[0084] In other embodiments, the p-GaN structure 171 and the field plate substructure 161 may also be other shapes, such as pillars.
[0085] In other embodiments, the field plate substructure 161 may not be connected to the p-GaN structure 171.
[0086] Figure 7 This is a schematic diagram of another transistor structure provided in an embodiment of this disclosure. Figure 7 and Figure 6 The main difference lies in the shape of the field plate structure 161, see [link / reference]. Figure 7 The p-GaN structure 171 is a first cuboid, and the field plate structure 161 is a third cuboid with a concave arc surface.
[0087] The length of the third cuboid is 35–1500 nm, the width is 100–1000 nm, the height is 30–120 nm, the arc length of the concave surface is 2000–5000 nm, and the curvature of the concave surface is 15–25°.
[0088] In this implementation, the p-GaN structure and field plate substructure with the above dimensions are not too large, which makes it easy to set them at intervals to release the stress of the p-GaN structure and field plate structure, and they are not too small either, which can improve the electric field distribution under high voltage.
[0089] For example, the third cuboid has a length of 1000nm, a width of 400nm, a height of 100nm, an arc length of 3000nm, and an arc angle of 20°.
[0090] In this embodiment of the disclosure, the distance between two adjacent third cuboids can be 100 to 1000 nm.
[0091] For example, the distance between two adjacent third cuboids is 500 nm.
[0092] In other embodiments, the p-GaN structure 171 and the field plate substructure 161 may also be other shapes, such as pillars.
[0093] Figure 8 This is a schematic diagram of the structure of a transistor provided in an embodiment of this disclosure. Figure 8 and Figure 7 The main difference lies in the shape of the field plate structure 161. Figure 6 , Figure 7 and Figure 8 The electric field distributions are different, among which Figure 8 The structural electric field simulation results are optimal. Figure 6 Secondly, structure Figure 7 The worst structure. See also Figure 8 The p-GaN structure 171 is a first cuboid, and the field plate structure 161 is a fourth cuboid with a raised arc surface.
[0094] The fourth cuboid has a length of 35–1500 nm, a width of 100–1000 nm, a height of 30–120 nm, an arc length of 2000–5000 nm, and an arc angle of 15–25°.
[0095] For example, the fourth cuboid has a length of 1000nm, a width of 400nm, a height of 100nm, an arc length of 3000nm, and an arc angle of 20°.
[0096] In this implementation, the p-GaN structure and field plate substructure with the above dimensions are not too large, which makes it easy to set them at intervals to release the stress of the p-GaN structure and field plate structure, and they are not too small either, which can improve the electric field distribution under high voltage.
[0097] In this embodiment of the disclosure, the distance between two adjacent fourth cuboids can be 100 to 1000 nm.
[0098] For example, the distance between two adjacent fourth cuboids is 500 nm.
[0099] In other embodiments, the p-GaN structure 171 and the field plate substructure 161 may also be other shapes, such as pillars or cones.
[0100] In other embodiments, the field plate substructure 161 may not be connected to the p-GaN structure 171.
[0101] In this embodiment of the disclosure, the material of the field plate structure 106 is u-GaN or metal.
[0102] For example, the material of the field plate structure 106 is u-GaN.
[0103] In this implementation, the field plate structure is made of u-GaN or a non-conductive metal, and a potential barrier exists, which can improve the electric field distribution under high voltage.
[0104] In this embodiment of the disclosure, the channel layer 104 can be a GaN layer.
[0105] In this embodiment of the disclosure, the thickness of the channel layer 104 can be 100-200 nm.
[0106] For example, the thickness of the channel layer 104 is 150 nm.
[0107] In this embodiment of the disclosure, the barrier layer 105 can be an AlGaN layer.
[0108] In this embodiment of the disclosure, the molar ratio of Al in the AlGaN layer can be 25-35%.
[0109] For example, the molar ratio of Al in the AlGaN layer is 27%.
[0110] In this embodiment of the disclosure, the thickness of the barrier layer 105 can be 10 to 50 nm.
[0111] For example, the thickness of the barrier layer 105 is 40 nm.
[0112] In this embodiment of the disclosure, the gate 108, source 109 and drain 110 can be a TiN, Al and TiN stack.
[0113] In this embodiment of the disclosure, the transistor may further include a planarization layer 111.
[0114] Planarization layer 111 covers barrier layer 105.
[0115] In this embodiment of the disclosure, the planarization layer 111 can be a high-resistivity GaN layer.
[0116] In this embodiment of the disclosure, the height of the planarization layer 111 can be equal to the height of the p-GaN layer 107.
[0117] In other embodiments, the height of the planarization layer 111 may be greater than or less than the height of the p-GaN layer 107.
[0118] Figure 9 This is a schematic diagram of the structure of a gallium nitride device provided in an embodiment of this disclosure. See also... Figure 9 The gallium nitride device includes: a substrate 10, a first transistor 20, and a second transistor 30;
[0119] The substrate 10 includes a nucleation layer 101, a buffer layer 102 and a high-resistivity layer 103 stacked sequentially.
[0120] The first transistor 20 and the second transistor 30 are arranged at intervals on the substrate 10, and the nucleation layer 101, the buffer layer 102 and the high-resistivity layer 103 between the first transistor 20 and the second transistor 30 have an isolation trench 1001.
[0121] The first transistor 20 and the second transistor 30 are the transistors described above.
[0122] In this implementation, the aforementioned transistors can uniformly guide carrier transport, thereby improving the current distribution of the barrier layer and making the current electric field distribution of the barrier layer more uniform; at the same time, setting an isolation trench between the two transistors can reduce high-frequency crosstalk between the first transistor and the second transistor.
[0123] In this embodiment of the disclosure, the width of the isolation groove 1001 can be 20 to 1000 μm.
[0124] In this implementation, the isolation slot uses the aforementioned width to avoid the first transistor and the second transistor being too close together, thereby reducing high-frequency crosstalk.
[0125] For example, the width of the isolation groove 1001 is 60 μm.
[0126] In this embodiment of the disclosure, the nucleation layer 101 can be an AlN layer.
[0127] In this embodiment of the disclosure, the thickness of the nucleation layer 101 can be 10 to 500 nm.
[0128] For example, the thickness of the nucleation layer 101 is 250 nm.
[0129] In this embodiment of the disclosure, the buffer layer 102 may be a superlattice structure layer.
[0130] In this embodiment of the disclosure, the superlattice structure layer can be formed by alternating stacking of GaN and AlN.
[0131] In this embodiment of the disclosure, the thickness of the buffer layer 102 can be 50 to 500 nm.
[0132] For example, the thickness of the buffer layer 102 can be 250 nm.
[0133] In this embodiment of the disclosure, the high-resistivity layer 103 can be a C-doped GaN layer.
[0134] In this embodiment of the disclosure, the C doping concentration in the high-resistivity layer 103 can be 1×10⁻⁶. 12 ~1×10 15 cm -3
[0135] In this embodiment of the disclosure, the thickness of the high-resistivity layer 103 can be 50–300 nm.
[0136] For example, the thickness of the high-resistivity layer 103 is 150 nm.
[0137] In this embodiment of the disclosure, the substrate may further include: substrate 100.
[0138] The substrate 10, the first transistor 20, and the second transistor 30 are located on the substrate 100. The bottom of the isolation trench 1001 is located below the surface of the substrate 10, but does not completely penetrate the substrate 10.
[0139] In other embodiments, the bottom of the isolation groove 1001 may also be located on the surface of the substrate 10.
[0140] In this embodiment of the disclosure, the substrate 100 can be any one of a sapphire patterned substrate, a Si substrate, or a SiC substrate, and the material of the substrate 100 is not limited in this embodiment of the disclosure.
[0141] For example, the substrate 100 is a Si substrate. Si has good electrical and thermal conductivity, which can ensure that the chip has good heat dissipation. In addition, Si is easy to process and has a low manufacturing cost.
[0142] In this embodiment of the disclosure, the gallium nitride device further includes a conductive metal 112 and a passivation layer 113.
[0143] The conductive metal 112 is located on the first transistor 20 and the second transistor 30, and the passivation layer 113 covers the first transistor 20, the second transistor 30, the isolation trench 1001 and the conductive metal 112.
[0144] In this embodiment of the disclosure, the conductive metal 112 can be a TiN, Al and TiN stack.
[0145] In this embodiment, the passivation layer 113 can be AlN or Si. x N y and Si x O y N z A passivation layer composed of one or more materials.
[0146] For example, the passivation layer 113 is Si x N y Layer, x is 3, y is 4.
[0147] In embodiments of this disclosure, the gallium nitride device may further include: a capacitor 40, a resistor 50, a diode 60, and a low-voltage enhancement-mode (LV E-mode) transistor 70.
[0148] A capacitor 40, a resistor 50, a diode 60, a low-voltage enhancement-mode transistor 70, a first transistor 20, and a second transistor 30 are spaced apart on the substrate 10.
[0149] The aforementioned electronic devices can be connected to form a circuit, and this disclosure does not limit how such devices are connected.
[0150] Figure 10 This is a flowchart of a transistor fabrication method provided in an embodiment of this disclosure. See also... Figure 10 The method includes the following steps:
[0151] S11, Create the channel layer.
[0152] S12. Fabricate a barrier layer, wherein the barrier layer is located in the channel layer.
[0153] S13. Fabricate a p-GaN layer, wherein the p-GaN layer is located in the barrier layer, and the p-GaN layer includes a plurality of p-GaN structures spaced apart along a first direction, wherein the first direction is perpendicular to the second direction.
[0154] S14. Fabricate a source and a drain, wherein the source and the drain are located on opposite sides of the barrier layer, and the p-GaN layer is located in the barrier layer and between the source and the drain, and the second direction is the direction from the source to the drain.
[0155] S15. Fabricate a gate, which is located on a plurality of the p-GaN structures.
[0156] In this embodiment, the p-GaN layer includes multiple p-GaN structures spaced apart along a first direction, rather than a monolithic structure. This can disperse stress, avoid stress mismatch between p-GaN and the barrier layer, release stress in the p-GaN layer, prevent cracks in the p-GaN layer, and improve transistor yield.
[0157] Figure 11 This is a flowchart illustrating a gallium nitride device fabrication method provided in this disclosure. See also... Figure 11 The method includes the following steps:
[0158] S21. A buffer layer and a high-resistivity layer are sequentially fabricated on the substrate to form a substrate.
[0159] The substrate can be any one of the following: a patterned sapphire substrate, a Si substrate, or a SiC substrate.
[0160] For example, the substrate is a Si substrate.
[0161] In one example, step S21 includes:
[0162] The first step is to create a buffer layer.
[0163] In this embodiment of the disclosure, the buffer layer may be a superlattice structure layer.
[0164] In this embodiment of the disclosure, the superlattice structure layer can be formed by alternating stacking of GaN and AlN.
[0165] In this embodiment of the disclosure, the thickness of the buffer layer can be 50 to 500 nm.
[0166] For example, the thickness of the buffer layer can be 250 nm.
[0167] The second step is to create a high-resistivity layer.
[0168] In this embodiment of the disclosure, the high-resistivity layer can be a C-doped GaN layer.
[0169] In this embodiment of the disclosure, the C doping concentration in the high-resistivity layer can be 1×10⁻⁶. 12 ~1×10 15 cm -3
[0170] In this embodiment, the thickness of the high-resistivity layer can be 50–300 nm.
[0171] For example, the thickness of the high-resistivity layer is 150 nm.
[0172] S22. Sequentially fabricate a channel layer, a barrier layer, a field structure, and a p-GaN layer on the substrate.
[0173] In one example, step S22 includes:
[0174] The first step is to create the channel layer.
[0175] In this embodiment of the disclosure, the channel layer can be a GaN layer.
[0176] In this embodiment of the disclosure, the thickness of the channel layer can be 100–200 nm.
[0177] For example, the thickness of the channel layer is 150 nm.
[0178] The second step is to create a barrier layer.
[0179] In this embodiment of the disclosure, the barrier layer can be an AlGaN layer.
[0180] In this embodiment of the disclosure, the molar ratio of Al in the AlGaN layer can be 25-35%.
[0181] For example, the molar ratio of Al in the AlGaN layer is 27%.
[0182] In this embodiment of the disclosure, the thickness of the barrier layer can be 10–50 nm.
[0183] For example, the thickness of the barrier layer is 40 nm.
[0184] The third step is to construct the panel structure.
[0185] In this embodiment of the disclosure, the material of the field plate structure is u-GaN or metal.
[0186] For example, the material of the field plate structure is u-GaN.
[0187] In this implementation, the field plate structure is made of u-GaN or a non-conductive metal, and a potential barrier exists, which can improve the electric field distribution under high voltage.
[0188] In this embodiment of the disclosure, the height of the field plate structure can be 30–120 nm;
[0189] For example, the height of the field plate structure is 100 nm.
[0190] The fourth step is to create the p-GaN layer.
[0191] In this embodiment, the height of the p-GaN layer can be 30–120 nm.
[0192] For example, the height of the p-GaN layer is 100 nm.
[0193] S23. Create a partitioned mask layer on the p-GaN layer.
[0194] In one example, step S23 includes:
[0195] The first step is to fabricate a partition mask on the P-gallium nitride layer.
[0196] In this embodiment of the disclosure, partitioned masks are grown using plasma-enhanced chemical vapor deposition (PECVD) or low-energy chemical vapor deposition (LECVD).
[0197] In this embodiment of the disclosure, the partition mask can be a TiN mask.
[0198] The second step is to etch the partitioned mask to form a partitioned mask layer.
[0199] In this embodiment of the disclosure, an ICP etching machine is used to etch the etching partition mask.
[0200] In this embodiment of the disclosure, the etching gas can be Cl2:BCl3:O2.
[0201] In this embodiment of the disclosure, the flow rate ratio of Cl2:BCl3:O2 can be 30:15:20.
[0202] In this embodiment of the disclosure, the O2 flow rate can be 10 to 30 sccm.
[0203] For example, the O2 flow rate is 20 sccm.
[0204] S24. The first transistor and the second transistor are patterned to form an isolation trench that runs through the channel layer and the barrier layer.
[0205] In one example, step S24 includes:
[0206] The first step is to perform graphical processing on the first and second transistors.
[0207] In this embodiment of the disclosure, a partitioned mask layer is used as a mask, and an ICP etching machine is used to etch the channel layer, barrier layer, field plate structure and p-GaN layer to form an isolation trench that penetrates the channel layer and barrier layer.
[0208] In this embodiment of the disclosure, the width of the isolation groove can be 20 to 1000 μm.
[0209] In this implementation, the isolation slot uses the aforementioned width to avoid the first transistor and the second transistor being too close together, thereby reducing high-frequency crosstalk.
[0210] For example, the width of the isolation groove is 60 μm.
[0211] The second step is to remove the partition mask layer.
[0212] In this embodiment, the epitaxial wafer is soaked in BOE solution for 1-2 hours until the partition mask layer and the light-emitting diode epitaxial structure on the partition mask layer are completely removed.
[0213] For example, the epitaxial wafer is soaked in BOE solution for 1 hour.
[0214] S25. Perform patterning on the field plate structure and p-GaN layer.
[0215] In one example, the field plate structure is located between the p-GaN layer and the barrier layer.
[0216] The field plate structure includes multiple spaced field plate substructures, which correspond to multiple p-GaN structures. The p-GaN structure extends from one end of the field plate substructure toward the drain.
[0217] In this implementation, the field plate structure is located between the p-GaN layer and the barrier layer, and the p-GaN structure extends towards the drain. By being located in the lateral direction between the gate and the drain, the electric field distribution under high voltage is improved. Multiple field plate substructures correspond to multiple p-GaN structures, which can release the stress between the field plate structure and the barrier layer, disperse the stress, and prevent cracks from appearing in the field plate structure.
[0218] In this embodiment of the disclosure, the field plate structure can be a cuboid, with a length of 900-1000 μm, a width of 450-550 nm, and a height of 30-120 nm.
[0219] For example, the field plate structure can be a cuboid with a length of 960 μm, a width of 400 nm, and a height of 100 nm.
[0220] In this embodiment of the disclosure, the p-GaN structure can be a cuboid, with a length of 35-1500 nm, a width of 40-60 nm, and a height of 30-120 nm.
[0221] For example, the p-GaN structure can be a cuboid, with a length of 1000 nm, a width of 50 nm, and a height of 100 nm.
[0222] In another example, the field plate structure is located between the p-GaN layer and the drain, and is connected to the p-GaN layer;
[0223] The field plate structure includes multiple spaced field plate substructures, which correspond to multiple p-GaN structures.
[0224] In this implementation, the field plate structure is located between the p-GaN layer and the drain. By being located laterally between the gate and the drain, it improves the electric field distribution under high voltage. Multiple field plate substructures correspond to multiple p-GaN structures, which can release the stress between the field plate structure and the barrier layer, disperse the stress, and prevent cracks from appearing in the field plate structure.
[0225] See Figure 5 The p-GaN structure is a first cuboid, and the field plate structure is a second cuboid with a stepped structure.
[0226] The length of the first cuboid can be 35–1500 nm, the width can be 200–500 nm, and the height can be 30–120 nm.
[0227] The length of the second cuboid can be 35–1500 nm, the width can be 300–1000 nm, and the height can be 30–120 nm; the total width of the stepped structure can be 100–500 nm, and the total height of the stepped structure can be 100–500 nm.
[0228] In this embodiment of the disclosure, the height of each step in the step structure remains constant along the direction toward the barrier layer, and the width of each step in the step structure remains constant.
[0229] In this implementation, the p-GaN structure and field plate substructure with the above dimensions are not too large, which makes it easy to set them at intervals to release the stress of the p-GaN structure and field plate structure, and they are not too small either, which can improve the electric field distribution under high voltage.
[0230] For example, the first cuboid has a length of 1000nm, a width of 400nm, and a height of 100nm;
[0231] The second cuboid has a length of 1000nm, a width of 400nm, and a height of 100nm; the total width of the stepped structure is 400nm, and the total height of the stepped structure is 100nm.
[0232] For example, the step structure includes four steps, each step having a height of 25 nm and a width of 100 nm.
[0233] In this embodiment of the disclosure, the distance between two adjacent first cuboids can be 100 to 1000 nm.
[0234] For example, the distance between two adjacent first cuboids is 500 nm.
[0235] In this embodiment of the disclosure, the distance between two adjacent second cuboids can be 100 to 1000 nm.
[0236] For example, the distance between two adjacent second cuboids is 500 nm.
[0237] In other embodiments, the p-GaN structure and field plate structure can also be other shapes, such as pillars or cones.
[0238] In other embodiments, the field plate substructure may not be connected to the p-GaN structure.
[0239] See Figure 6 The first cuboid of the p-GaN structure is a cuboid with a concave arc surface;
[0240] The length of the third cuboid is 35–1500 nm, the width is 100–1000 nm, the height is 30–120 nm, the arc length of the concave surface is 2000–5000 nm, and the curvature of the concave surface is 15–25°.
[0241] In this implementation, the p-GaN structure and field plate substructure with the above dimensions are not too large, which makes it easy to set them at intervals to release the stress of the p-GaN structure and field plate structure, and they are not too small either, which can improve the electric field distribution under high voltage.
[0242] For example, the third cuboid has a length of 1000nm, a width of 400nm, a height of 100nm, an arc length of 3000nm, and an arc angle of 20°.
[0243] In this embodiment of the disclosure, the distance between two adjacent third cuboids can be 100 to 1000 nm.
[0244] For example, the distance between two adjacent third cuboids is 100 to 1000 nm.
[0245] In other embodiments, the p-GaN structure and field plate structure can also be other shapes, such as pillars or cones.
[0246] In other embodiments, the field plate substructure may not be connected to the p-GaN structure 171.
[0247] See Figure 7 The p-GaN structure is a first cuboid, and the field plate structure is a fourth cuboid with a raised arc surface.
[0248] The fourth cuboid has a length of 35–1500 nm, a width of 100–1000 nm, a height of 30–120 nm, an arc length of 2000–5000 nm, and an arc angle of 15–25°.
[0249] For example, the fourth cuboid has a length of 1000nm, a width of 400nm, a height of 100nm, an arc length of 3000nm, and an arc angle of 20°.
[0250] In this implementation, the p-GaN structure and field plate substructure with the above dimensions are not too large, which makes it easy to set them at intervals to release the stress of the p-GaN structure and field plate structure, and they are not too small either, which can improve the electric field distribution under high voltage.
[0251] In this embodiment of the disclosure, the distance between two adjacent fourth cuboids can be 100 to 1000 nm.
[0252] For example, the distance between two adjacent fourth cuboids is 500 nm.
[0253] In other embodiments, the p-GaN structure and field plate substructure can also be other shapes, such as pillars.
[0254] In other embodiments, the field plate substructure may not be connected to the p-GaN structure.
[0255] S26. Fabricate the source, drain, and gate, with the source and drain located on the barrier layer and the gate located on the plurality of p-GaN layers.
[0256] In the embodiments disclosed herein, the source, drain, and gate may be a stack of TiN, Al, and TiN.
[0257] S27. Create a planarization layer.
[0258] In this embodiment of the disclosure, the planarization layer covers the epitaxial layer and the isolation trench.
[0259] In this embodiment of the disclosure, the planarization layer can be a high-resistivity GaN layer.
[0260] In this embodiment of the disclosure, the thickness of the planarization layer can be equal to the thickness of the p-GaN layer.
[0261] In other embodiments, the thickness of the planarization layer may be greater than or less than the thickness of the p-GaN layer.
[0262] S28. Fabricate a conductive metal, and connect the conductive metal to the first transistor and the second transistor.
[0263] In the embodiments disclosed herein, the conductive metal may be a TiN, Al, and TiN stack.
[0264] S29. Fabricate a passivation layer, which covers the first transistor, the second transistor, the isolation trench, and the conductive metal.
[0265] In this embodiment of the disclosure, the passivation layer may be AlN or Si. x N y and Si x O y N z A passivation layer composed of one or more materials.
[0266] For example, the passivation layer is Si x N y Layer, x is 3, y is 4.
[0267] S30 is used to manufacture capacitors, resistors, diodes, and low-voltage enhancement-mode transistors.
[0268] Capacitors, resistors, diodes, low-voltage enhancement-mode transistors, a first transistor, and a second transistor are arranged horizontally on the substrate in sequence.
[0269] Figure 12 This is a comparison diagram of the electric field strength of the gallium nitride device provided in the embodiments of this disclosure and the gallium nitride device provided in related technologies. Figure 12 The solid line represents the gallium nitride device provided in the embodiments of this disclosure, and the dashed line represents the gallium nitride device provided in the related technology. As can be seen from the figure, the electric field of the gallium nitride device provided in the embodiments of this disclosure is smooth, while the electric field of the gallium nitride device provided in the related technology is fluctuating. The gallium nitride device provided in the embodiments of this disclosure has the effect of smoothing the electric field.
[0270] Figure 13 This is a comparison diagram of the voltage and electric field strength of the gallium nitride device provided in the embodiments of this disclosure and the gallium nitride device provided in related technologies. (Reference) Figure 13The left figure shows a gallium nitride (GaN) device provided in an embodiment of this disclosure, and the right figure shows a GaN device provided in related technologies. The horizontal axis represents voltage, and the vertical axis represents electric field strength. As can be seen from the figures, the GaN device provided in the embodiment of this disclosure has a relatively flat electric field strength under different voltages, and the GaN device provided in the embodiment of this disclosure has the effect of smoothing the electric field.
[0271] Figure 14 This is a comparison chart of voltage and unit leakage current for epitaxial structures of different thicknesses provided in the embodiments of this disclosure. (Reference) Figure 14 The horizontal axis represents the voltage per unit thickness of the epitaxial structure, in V / μm; the vertical axis represents the leakage current per unit area, in A / mm². 2 The black lines (darker in color) represent an epitaxial structure with a thickness of 4.81 μm (in this embodiment of the disclosure), and the gray lines (lighter in color) represent an epitaxial structure with a thickness of 5.33 μm (related art). As can be seen from the figure, the epitaxial structure provided in this embodiment, with reduced thickness and a voltage per unit thickness below 160 V / μm, exhibits a leakage current of less than 100 nA per unit area. Therefore, the solution provided in this embodiment, by improving stress, allows for a thinner epitaxial structure while reducing leakage current, thus saving transistor manufacturing costs.
[0272] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A transistor, characterized in that, The transistor includes: a channel layer (104), a barrier layer (105), a p-GaN layer (107), a gate (108), a source (109), and a drain (110); The barrier layer (105) is located in the channel layer (104), the source (109) and the drain (110) are located in the barrier layer (105), and the source (109) and the drain (110) are located on opposite sides of the barrier layer (105); The p-GaN layer (107) is located in the barrier layer (105) and between the source (109) and the drain (110). The p-GaN layer (107) includes a plurality of p-GaN structures (171) spaced apart along a first direction. The first direction is perpendicular to a second direction, which is the direction from the source (109) to the drain (110). The gate (108) is located on a plurality of the p-GaN structures (171).
2. The transistor according to claim 1, characterized in that, The transistor further includes a field plate structure (106) located between the p-GaN layer (107) and the barrier layer (105); The field plate structure (106) includes a plurality of spaced field plate substructures (161), which correspond to a plurality of p-GaN structures (171). The p-GaN structure (171) extends from one end of the field plate substructure (161) toward the drain (110).
3. The transistor according to claim 1, characterized in that, The transistor further includes a field plate structure (106), which is located between the p-GaN layer (107) and the drain (110) and is connected to the p-GaN layer (107); The field plate structure (106) includes a plurality of spaced field plate substructures (161), and the field plate substructures (161) correspond to a plurality of the p-GaN structures (171).
4. The transistor according to claim 3, characterized in that, The p-GaN structure (171) is a first cuboid, and the field plate substructure (161) is a second cuboid with a stepped structure. The length of the first cuboid is 35–1500 nm, the width is 200–500 nm, and the height is 30–120 nm; The second cuboid has a length of 35–1500 nm, a width of 300–1000 nm, and a height of 30–120 nm; the total width of the stepped structure is 100–500 nm, and the total height of the stepped structure is 100–500 nm.
5. The transistor according to claim 3, characterized in that, The p-GaN structure (171) is a first cuboid, and the field plate substructure (161) is a third cuboid with a concave arc surface; The length of the third cuboid is 35–1500 nm, the width is 100–1000 nm, and the height is 30–120 nm; the arc length of the concave arc surface is 2000–5000 nm, and the curvature of the concave arc surface is 15–25°.
6. The transistor according to claim 3, characterized in that, The p-GaN structure (171) is a first cuboid, and the field plate substructure (161) is a fourth cuboid with a raised arc surface; The fourth cuboid has a length of 35–1500 nm, a width of 100–1000 nm, and a height of 30–120 nm; the arc length of the convex arc surface is 2000–5000 nm, and the arc angle of the convex arc surface is 15–25°.
7. The transistor according to any one of claims 2 to 6, characterized in that, The material of the field plate structure (106) is u-GaN or metal.
8. A gallium nitride device, characterized in that, The gallium nitride device includes: a substrate (10), a first transistor (20), and a second transistor (30); The substrate (10) includes a nucleation layer (101), a buffer layer (102) and a high-resistivity layer (103) stacked sequentially. The first transistor (20) and the second transistor (30) are arranged at intervals on the substrate (10), and the nucleation layer (101), the buffer layer (102) and the high-resistivity layer (103) between the first transistor (20) and the second transistor (30) have isolation trenches (1001); The first transistor (20) and the second transistor (30) are transistors as described in any one of claims 1 to 6.
9. The gallium nitride device according to claim 8, characterized in that, The width of the isolation groove (1001) is 20 to 1000 μm.
10. A method for fabricating a transistor, characterized in that, The transistor fabrication method includes: Create the channel layer; A barrier layer is fabricated, the barrier layer being located within the channel layer; A p-GaN layer is fabricated, the p-GaN layer being located in the barrier layer, the p-GaN layer comprising a plurality of p-GaN structures spaced apart along a first direction, the first direction being perpendicular to a second direction; A source and a drain are fabricated, with the source and the drain located on opposite sides of the barrier layer, and the p-GaN layer located on the barrier layer and between the source and the drain. The second direction is the direction from the source to the drain. A gate is fabricated on a plurality of the p-GaN structures.