Anti-radiation LDMOS device structure and manufacturing method thereof

Abstract

The invention discloses an anti-radiation LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure and a manufacturing method thereof, and belongs to the technical field of semiconductor power devices. The anti-radiation LDMOS device comprises a P-type substrate, an N-type buried layer, a P-type epitaxy, an N-type deep trap, a P-type deep trap, a shallow trench isolation oxide layer, a gate oxide layer, an HTO oxide layer, polycrystalline silicon, an N-type well region, a P-type well region, a P-type buried layer, an N-type drift region, a P-type body region, source region N + injection, drain region N + injection, body region P + injection, isolation N + injection and isolation P + injection. The junction depth of the source body junction is reduced by changing the LDMOS process, so that the emitter junction injection efficiency of the parasitic triode is reduced, and the starting of the parasitic triode in the device is inhibited. And an additional mask plate is not needed, so that the manufacturing cost of the device can be saved while the anti-radiation capability is reinforced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a radiation-resistant LDMOS device structure and its fabrication method. Background Art

[0002] With the increasing application of power semiconductor devices in aerospace electronic systems and other fields, radiation hardening technology has become a key research focus for power management systems and gate drive circuits. LDMOS devices, as core components of analog circuits, are susceptible to single-event burn-out in the radiation environment of space, leading to device failure and malfunction of the entire circuit. Therefore, research is needed on LDMOS devices resistant to single-event burn-out.

[0003] Traditional methods for fabricating single-event hardening LDMOS devices typically require additional photomasks. This invention, by shifting the pattern, reduces the injection dose in certain areas, thus eliminating the need for additional photomasks and achieving single-event hardening. It offers both single-event hardening capability and economic benefits. Summary of the Invention

[0004] To address the single-event burn-out problem in LDMOS devices and suppress the activation of parasitic transistors, this invention proposes an LDMOS device structure resistant to single-event burn-out. In the space environment, high-energy particles will enter the LDMOS device, generating a large number of electron-hole pairs along the incident path through energy deposition. Under the influence of an electric field, electrons and holes move towards the drain and source, respectively, forming a transient current. Some holes flow into the P-well (the base region of the parasitic transistor) and then flow out from the body electrode P+. The hole current generates a voltage drop in the base region, causing the P-well / N+ junction (base / emitter junction) to be forward biased, and the parasitic transistor to turn on. Electrons from the source N+ enter the drift region through the P-well, causing the device to undergo the Kirk effect, ionizing more electron-hole pairs. Holes move towards the source under the influence of the electric field, providing a stable positive feedback current to the base region, ultimately leading to device burn-out. This approach reduces the efficiency of electron injection from the source to the body region (the injection efficiency of the emitter junction in the base region of the parasitic transistor), thereby preventing the parasitic transistor from turning on and effectively improving the single-event burn-out resistance of LDMOS devices.

[0005] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0006] A radiation-resistant LDMOS device structure includes a first conductivity type substrate 1, a second conductivity type buried layer 2, a first conductivity type epitaxial layer 3, a second conductivity type deep well 4, a first conductivity type deep well 5, a second conductivity type well region 6, a first conductivity type well region 7, a first conductivity type buried layer 8, a second conductivity type drift region 9, a first conductivity type body region 10, a shallow trench isolation oxide layer 11, a second conductivity type isolation injection region 12, a first conductivity type isolation injection region 13, a second conductivity type drain region 14, a second conductivity type source region 15, a first conductivity type body injection region 16, an HTO field oxide layer region 17, a gate oxide layer region 18, and a polysilicon gate electrode 19.

[0007] The first conductivity type substrate 1 and the second conductivity type buried layer 2 are stacked sequentially from bottom to top; the first conductivity type epitaxial layer 3 is adjacent to the upper left of the second conductivity type buried layer 2; the first conductivity type deep well 5 is adjacent to the right side of the first conductivity type epitaxial layer 3; the second conductivity type deep well 4 is adjacent to the right side of the first conductivity type deep well 5; the depth of the deep well is greater than the depth of the well region, the second conductivity type well region 6 is located above the second conductivity type deep well 4, and the first conductivity type well region 7 is located above the first conductivity type deep well 5; the first conductivity type buried layer 8 is located inside and above the first conductivity type epitaxial layer 3, and is adjacent to the first conductivity type deep well 5 on its right side; The second conductivity type drift region 9 is located above the first conductivity type buried layer 8; the first conductivity type body region 10 is located to the upper left of the first conductivity type epitaxial layer 3, and is not adjacent to the second conductivity type drift region 9 on the right; the first first shallow trench isolation oxide layer 11 is connected across the first conductivity type well region 7 and the second conductivity type drift region 9, covering part of the first conductivity type well region 7 and the second conductivity type drift region 9; the second second shallow trench isolation oxide layer 11 is connected across the second conductivity type well region 6 and the first conductivity type well region 7, covering part of the second conductivity type well region 6 and the first conductivity type well region 7; the second conductivity type isolation injection region 12 is adjacent to Above the second conductivity type well region 6, adjacent to the right side of the second second shallow trench isolation oxide layer 11; the first conductivity type isolation injection region 13 is adjacent to the first conductivity type well region 7, with its left and right sides respectively adjacent to the right side of the first first shallow trench isolation oxide layer 11 and the left side of the second second shallow trench isolation oxide layer 11; the second conductivity type drain region 14 is located above and to the right of the second conductivity type drift region 9, adjacent to the left side of the first first shallow trench isolation oxide layer 11; the first conductivity type body injection region 16 is located above and to the left of the first conductivity type body region 10, with its left boundary being the same as that of the first conductivity type body region 10; the first conductivity type body injection region 16 is located above and to the left of the first conductivity type body region 10; the second conductivity type drain region 14 is located above and to the right of the second conductivity type drift region 9, adjacent to the left side of the first conductivity type body region 10; the first conductivity type body injection region 16 is located above and to the left of the first conductivity type body region 10, with its left boundary being the same as that ... right of the first conductivity type body region 10, adjacent to the right side of the first conductivity type body region 10; the first conductivity type body injection region 16 is located above and to the right of the first conductivity type body region 10, adjacent to the right side of the first conductivity type body region 10, adjacent to the right side of the first conductivity type body region 10; the first conductivity type body injection region 16 The source region 15 of the second conductivity type is adjacent to the right side of the body injection region 16 of the first conductivity type; the HTO field oxide layer region 17 is located above the drift region 9 of the second conductivity type, and its lower boundary is the same as the upper boundary of the drift region 9 of the second conductivity type; the gate oxide layer region 18 is located above the drift region 9 of the second conductivity type, and its right boundary is the same as the left boundary of the HTO field oxide layer region 17, and its height is lower than that of the HTO field oxide layer region 17; the polysilicon gate electrode 19 is located on the upper surface of the HTO field oxide layer region 17 and the gate oxide layer region 18, and its left boundary is the same as the left boundary of the gate oxide layer region 18, and its right boundary does not exceed the right boundary of the HTO field oxide layer region 17.

[0008] As a preferred embodiment, the lower boundary of the second conductivity type source region 15 does not exceed the lower boundary of the first conductivity type body injection region 16.

[0009] As a preferred embodiment, the left boundary of the second conductivity type source region 15 is adjacent to the right boundary of the first conductivity type volume injection region 16.

[0010] As a preferred embodiment, the right boundary of the source region 15 of the second conductivity type is the same as the left boundary of the gate oxide layer region 18 and the polysilicon gate electrode 19.

[0011] As a preferred embodiment, when the first conductivity type doped impurity is acceptor type and the second conductivity type doped impurity is donor type, the drain electrode is biased to a positive potential relative to the source electrode; when the first conductivity type doped impurity is donor type and the second conductivity type doped impurity is acceptor type, the drain electrode is biased to a negative potential relative to the source electrode.

[0012] A second objective of this invention is to provide a method for fabricating a radiation-resistant LDMOS device structure, which includes the following steps:

[0013] Step 1: Provide a substrate of a first conductivity type, and form a buried layer of a second conductivity type on the substrate of the first conductivity type;

[0014] Step 2: Grow a first conductivity type epitaxial layer on the second conductivity type buried layer, and implant a second conductivity type deep well on the right side of the first conductivity type epitaxial layer, and then implant a first conductivity type deep well immediately on the left side of the second conductivity type deep well.

[0015] Step 3: Etching and growing shallow trench isolation oxide (STI) above the second conductivity type deep well and the first conductivity type deep well;

[0016] Step 4: Perform a second conductivity type well injection above the second conductivity type deep well; perform a first conductivity type well injection above the first conductivity type deep well.

[0017] Step 5: Perform gate oxide growth and field oxide deposition;

[0018] Step 6: Inject the second type of conductivity drift region;

[0019] Step 7: Deposit and etch the polysilicon gate electrode;

[0020] Step 8: Implantation of the first conductivity type body region, wherein the body region implantation is multi-channel, and the last channel is the second conductivity type impurity, forming the second conductivity type source region;

[0021] Step 9: Perform second conductivity type drain and isolation region injection and first conductivity type isolation and body region injection.

[0022] The beneficial effects of the present invention are:

[0023] This invention provides a highly reliable radiation-resistant LDMOS device structure and its fabrication method. Utilizing multiple different injection stages in the body region, the source region is formed during body region injection. Subsequent source and drain injections only inject the drain region, reducing the junction depth and doping of the source region. This, in turn, lowers the electron injection efficiency from the source to the body region (the emitter junction injection efficiency of parasitic transistors), preventing the parasitic transistors from turning on and effectively improving the LDMOS device's resistance to single-event burn-out. Furthermore, since no additional mask is required, the fabrication of this structure can be completed simply by layout biasing during source and drain injection. Therefore, it offers both single-event resistance and economic benefits. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a conventional LDMOS device structure.

[0025] Figure 2 This diagram illustrates the first three implantation processes in the body region implantation of an LDMOS device. The first three implantation processes are: boron implantation (first step), boron implantation (second step), and boron fluoride implantation (third step).

[0026] Figure 3 The diagram shows the structure after the first three implantation processes in the body region of an LDMOS device are completed, and the diagram shows the fourth implantation process.

[0027] Figure 4 This is a schematic diagram of the structure of an LDMOS device after the body region implantation process is completed.

[0028] Figure 5 This diagram illustrates the injection of the source, drain, and isolation regions for the second conductivity type of a conventional LDMOS device.

[0029] Figure 6 This is a schematic diagram of the injection of the source region, drain region, and isolation region of the second conductivity type of LDMOS described in this invention.

[0030] Figure 7 This is a schematic diagram of the LDMOS device structure described in this invention.

[0031] The reference numerals used in the accompanying drawings are as follows:

[0032] 1-First conductivity type substrate, 2-Second conductivity type buried layer, 3-First conductivity type epitaxial layer, 4-Second conductivity type deep well, 5-First conductivity type deep well, 6-Second conductivity type well region, 7-First conductivity type well region, 8-First conductivity type buried layer, 9-Second conductivity type drift region, 10-First conductivity type body region, 11-Shallow trench isolation oxide layer, 12-Second conductivity type isolation implantation region, 13-First conductivity type isolation implantation region, 14-Second conductivity type drain region, 15-Second conductivity type source region, 16-First conductivity type body implantation region, 17-HTO field oxide layer region, 18-Gate oxide layer region, 19-Polysilicon gate electrode. Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] This embodiment provides a radiation-resistant LDMOS device structure, such as Figure 7 As shown, it includes a first conductivity type substrate 1, a second conductivity type buried layer 2, a first conductivity type epitaxial layer 3, a second conductivity type deep well 4, a first conductivity type deep well 5, a second conductivity type well region 6, a first conductivity type well region 7, a first conductivity type buried layer 8, a second conductivity type drift region 9, a first conductivity type body region 10, a shallow trench isolation oxide layer 11, a second conductivity type isolation implantation region 12, a first conductivity type isolation implantation region 13, a second conductivity type drain region 14, a second conductivity type source region 15, a first conductivity type body implantation region 16, an HTO field oxide layer region 17, a gate oxide layer region 18, and a polysilicon gate electrode 19.

[0035] The first conductivity type substrate 1 and the second conductivity type buried layer 2 are stacked sequentially from bottom to top; the first conductivity type epitaxial layer 3 is adjacent to the upper left of the second conductivity type buried layer 2; the first conductivity type deep well 5 is adjacent to the right side of the first conductivity type epitaxial layer 3; the second conductivity type deep well 4 is adjacent to the right side of the first conductivity type deep well 5; the depth of the deep well is greater than the depth of the well region, the second conductivity type well region 6 is located above the second conductivity type deep well 4, and the first conductivity type well region 7 is located above the first conductivity type deep well 5; the first conductivity type buried layer 8 is located inside and above the first conductivity type epitaxial layer 3, and is adjacent to the first conductivity type deep well 5 on its right side; The second conductivity type drift region 9 is located above the first conductivity type buried layer 8; the first conductivity type body region 10 is located to the upper left of the first conductivity type epitaxial layer 3, and is not adjacent to the second conductivity type drift region 9 on the right; the first first shallow trench isolation oxide layer 11 is connected across the first conductivity type well region 7 and the second conductivity type drift region 9, covering part of the first conductivity type well region 7 and the second conductivity type drift region 9; the second second shallow trench isolation oxide layer 11 is connected across the second conductivity type well region 6 and the first conductivity type well region 7, covering part of the second conductivity type well region 6 and the first conductivity type well region 7; the second conductivity type isolation injection region 12 is adjacent to Above the second conductivity type well region 6, adjacent to the right side of the second second shallow trench isolation oxide layer 11; the first conductivity type isolation injection region 13 is adjacent to the first conductivity type well region 7, with its left and right sides respectively adjacent to the right side of the first first shallow trench isolation oxide layer 11 and the left side of the second second shallow trench isolation oxide layer 11; the second conductivity type drain region 14 is located above and to the right of the second conductivity type drift region 9, adjacent to the left side of the first first shallow trench isolation oxide layer 11; the first conductivity type body injection region 16 is located above and to the left of the first conductivity type body region 10, with its left boundary being the same as that of the first conductivity type body region 10; the first conductivity type body injection region 16 is located above and to the left of the first conductivity type body region 10; the second conductivity type drain region 14 is located above and to the right of the second conductivity type drift region 9, adjacent to the left side of the first conductivity type body region 10; the first conductivity type body injection region 16 is located above and to the left of the first conductivity type body region 10, with its left boundary being the same as that ... right of the first conductivity type body region 10, adjacent to the right side of the first conductivity type body region 10; the first conductivity type body injection region 16 is located above and to the right of the first conductivity type body region 10, adjacent to the right side of the first conductivity type body region 10, adjacent to the right side of the first conductivity type body region 10; the first conductivity type body injection region 16 The source region 15 of the second conductivity type is adjacent to the right side of the body injection region 16 of the first conductivity type; the HTO field oxide layer region 17 is located above the drift region 9 of the second conductivity type, and its lower boundary is the same as the upper boundary of the drift region 9 of the second conductivity type; the gate oxide layer region 18 is located above the drift region 9 of the second conductivity type, and its right boundary is the same as the left boundary of the HTO field oxide layer region 17, and its height is lower than that of the HTO field oxide layer region 17; the polysilicon gate electrode 19 is located on the upper surface of the HTO field oxide layer region 17 and the gate oxide layer region 18, and its left boundary is the same as the left boundary of the gate oxide layer region 18, and its right boundary does not exceed the right boundary of the HTO field oxide layer region 17.

[0036] As a preferred embodiment, the lower boundary of the second conductivity type source region 15 does not exceed the lower boundary of the first conductivity type body injection region 16.

[0037] As a preferred embodiment, the left boundary of the second conductivity type source region 15 is adjacent to the right boundary of the first conductivity type volume injection region 16.

[0038] As a preferred embodiment, the right boundary of the source region 15 of the second conductivity type is the same as the left boundary of the gate oxide layer region 18 and the polysilicon gate electrode 19.

[0039] As a preferred embodiment, when the first conductivity type doped impurity is acceptor type and the second conductivity type doped impurity is donor type, the drain electrode is biased to a positive potential relative to the source electrode; when the first conductivity type doped impurity is donor type and the second conductivity type doped impurity is acceptor type, the drain electrode is biased to a negative potential relative to the source electrode.

[0040] A second objective of this invention is to provide a method for fabricating a radiation-resistant LDMOS device structure, which includes the following steps:

[0041] Step 1: Provide a substrate of a first conductivity type, and form a buried layer of a second conductivity type on the substrate of the first conductivity type;

[0042] Step 2: Grow a first conductivity type epitaxial layer on the second conductivity type buried layer, and implant a second conductivity type deep well on the right side of the first conductivity type epitaxial layer, and then implant a first conductivity type deep well immediately on the left side of the second conductivity type deep well.

[0043] Step 3: Etching and growing shallow trench isolation oxide (STI) above the second conductivity type deep well and the first conductivity type deep well;

[0044] Step 4: Perform a second conductivity type well injection above the second conductivity type deep well; perform a first conductivity type well injection above the first conductivity type deep well.

[0045] Step 5: Perform gate oxide growth and field oxide deposition;

[0046] Step 6: Inject the second type of conductivity drift region;

[0047] Step 7: Deposit and etch the polysilicon gate electrode;

[0048] Step 8: Implantation of the first conductivity type body region, wherein the body region implantation is multi-channel, and the last channel is the second conductivity type impurity, forming the second conductivity type source region;

[0049] Step 9: Perform second conductivity type drain and isolation region injection and first conductivity type isolation and body region injection.

[0050] In the space environment, LDMOS devices are affected by single-event effects, generating a large number of ionized electrons and holes inside the device. Under the influence of an electric field, electrons and holes move towards the drain and source, respectively, forming a transient current. Some holes flow into the P-well (the base region of the parasitic transistor) and then flow out from the body electrode P+. The hole current generates a voltage drop in the base region, causing the P-well / N+ junction (base / emitter junction) to be forward biased, and the parasitic transistor to turn on. This invention provides a highly reliable radiation-resistant LDMOS device structure and its fabrication method. By utilizing multiple different injections in the body region, the source region is formed during body region injection. Subsequent source and drain injections only inject the drain region, thereby reducing the junction depth and doping concentration of the source region. This reduces the electron injection efficiency from the source to the body region (the emitter junction injection efficiency of the parasitic transistor), preventing the parasitic transistor from turning on and effectively improving the LDMOS device's resistance to single-event burn-out. Meanwhile, since no additional mask template is required, the fabrication of the structure of this invention can be completed simply by adjusting the layout during injection in the source and drain regions. Therefore, it has both single-particle rejection performance and certain economic benefits.

[0051] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A radiation-resistant LDMOS device structure, characterized in that, It includes a first conductivity type substrate (1), a second conductivity type buried layer (2), a first conductivity type epitaxial layer (3), a second conductivity type deep well (4), a first conductivity type deep well (5), a second conductivity type well region (6), a first conductivity type well region (7), a first conductivity type buried layer (8), a second conductivity type drift region (9), a first conductivity type body region (10), a shallow trench isolation oxide layer (11), a second conductivity type isolation implantation region (12), a first conductivity type isolation implantation region (13), a second conductivity type drain region (14), a second conductivity type source region (15), a first conductivity type body implantation region (16), an HTO field oxide layer region (17), a gate oxide layer region (18), and a polysilicon gate electrode (19). The first conductivity type substrate (1) and the second conductivity type buried layer (2) are stacked from bottom to top; the first conductivity type epitaxial layer (3) is adjacent to the upper left of the second conductivity type buried layer (2); The first conductivity type deep well (5) is adjacent to the right side of the first conductivity type epitaxial layer (3); the second conductivity type deep well (4) is adjacent to the right side of the first conductivity type deep well (5); the second conductivity type well region (6) is located above the second conductivity type deep well (4), and the first conductivity type well region (7) is located above the first conductivity type deep well (5); the first conductivity type buried layer (8) is located inside and above the first conductivity type epitaxial layer (3), and is adjacent to the first conductivity type deep well (5) on its right side; the second conductivity type drift region (9) is located above the first conductivity type buried layer (8); the first conductivity type body region (10) is located at the upper left of the first conductivity type epitaxial layer (3). The right side and the second conductivity type drift region (9) are not adjacent; the first first shallow trench isolation oxide layer (11) is connected across the first conductivity type well region (7) and the second conductivity type drift region (9), covering part of the first conductivity type well region (7) and the second conductivity type drift region (9); the second second shallow trench isolation oxide layer (11) is connected across the second conductivity type well region (6) and the first conductivity type well region (7), covering part of the second conductivity type well region (6) and the first conductivity type well region (7); the second conductivity type isolation injection region (12) is adjacent to the second conductivity type well region (6) above, and is adjacent to the second second shallow trench isolation oxide layer (11). The first conductivity type isolation injection region (13) is adjacent to the top of the first conductivity type well region (7), and its left and right sides are adjacent to the right side of the first first shallow trench isolation oxide layer (11) and the left side of the second second shallow trench isolation oxide layer (11), respectively; the second conductivity type drain region (14) is located above the right of the second conductivity type drift region (9), and is adjacent to the left side of the first first shallow trench isolation oxide layer (11); the first conductivity type body injection region (16) is located above the left of the first conductivity type body region (10), and its left boundary is the same as that of the first conductivity type body region (10); the second conductivity type source region (15) is adjacent to the first conductivity type well region (7). The right side of the type body injection region (16); the HTO field oxide layer region (17) is located above the second conductivity type drift region (9), and its lower boundary is the same as the upper boundary of the second conductivity type drift region (9); the gate oxide layer region (18) is located above the second conductivity type drift region (9), and its right boundary is the same as the left boundary of the HTO field oxide layer region (17), and its height is lower than that of the HTO field oxide layer region (17); the polysilicon gate electrode (19) is located on the upper surface of the HTO field oxide layer region (17) and the gate oxide layer region (18), and its left boundary is the same as the left boundary of the gate oxide layer region (18), and its right boundary does not exceed the right boundary of the HTO field oxide layer region (17).

2. The radiation-resistant LDMOS device structure according to claim 1, characterized in that, The lower boundary of the second conductivity type source region (15) does not exceed the lower boundary of the first conductivity type volume injection region (16).

3. The radiation-resistant LDMOS device structure according to claim 1, characterized in that, The left boundary of the second conductivity type source region (15) is adjacent to the right boundary of the first conductivity type volume injection region (16).

4. The radiation-resistant LDMOS device structure according to claim 1, characterized in that, The right boundary of the source region (15) of the second conductivity type is the same as the left boundary of the gate oxide region (18) and the polysilicon gate electrode (19).

5. The radiation-resistant LDMOS device structure according to claim 1, characterized in that: When the first conductivity type doped impurity is acceptor type and the second conductivity type doped impurity is donor type, the drain electrode is biased to a positive potential relative to the source electrode; when the first conductivity type doped impurity is donor type and the second conductivity type doped impurity is acceptor type, the drain electrode is biased to a negative potential relative to the source electrode.

6. A method for fabricating a radiation-hardened LDMOS device structure, used to prepare the radiation-hardened LDMOS device according to any one of claims 1 to 5, characterized in that... Includes the following steps: Step 1: Provide a substrate of a first conductivity type, and form a buried layer of a second conductivity type on the substrate of the first conductivity type; Step 2: Grow a first conductivity type epitaxial layer on the second conductivity type buried layer, and implant a second conductivity type deep well on the right side of the first conductivity type epitaxial layer, and then implant a first conductivity type deep well immediately on the left side of the second conductivity type deep well. Step 3: Etching and growing shallow trench isolation oxide (STI) above the second conductivity type deep well and the first conductivity type deep well; Step 4: Perform a second conductivity type well injection above the second conductivity type deep well; perform a first conductivity type well injection above the first conductivity type deep well. Step 5: Perform gate oxide growth and field oxide deposition; Step 6: Inject the second type of conductivity drift region; Step 7: Deposit and etch the polysilicon gate electrode; Step 8: Implantation of the first conductivity type body region, wherein the body region implantation is multi-channel, and the last channel is the second conductivity type impurity, forming the second conductivity type source region; Step 9: Perform second conductivity type drain and isolation region injection and first conductivity type isolation and body region injection.

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