Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises a substrate, a photodiode and a floating diffusion region which are arranged at an interval are formed in the substrate, and the floating diffusion region is used for receiving photo-generated charges generated by the photodiode in response to incident light; the PIP capacitor is located on the substrate and at least partially located above the photodiode, the PIP capacitor comprises a first polycrystalline silicon layer, an insulating layer and a second polycrystalline silicon layer which are sequentially stacked from bottom to top, the first polycrystalline silicon layer is electrically connected with a control signal, and the second polycrystalline silicon layer is electrically connected with the floating diffusion region. According to the scheme, the PIP capacitor is formed, at least part of the PIP capacitor is located above the photodiode, the first polycrystalline silicon layer of the PIP capacitor is electrically connected with the control signal, the second polycrystalline silicon layer of the PIP capacitor is electrically connected with the floating diffusion region, and therefore the LOFIC technology and optimization of the photoelectric field of the photodiode can be achieved through the PIP capacitor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Complementary metal oxide semiconductor (CMOS) image sensor (CIS) technology has been widely used in applications such as machine vision, automobiles, analytical instruments, absorption imaging, and medical devices.

[0003] In order to increase the full well capacity (FWC) and thus improve the dynamic range (DR) of the CIS, the lateral overflow integrated capacitor (LOFIC) process, which involves an additional capacitor connected to the floating diffusion region (FD), is often adopted.

[0004] However, the capacitors used in the existing LOFIC process significantly increase the process complexity and the metal trace pressure of the back-end-of-line (BEOL) process. At the same time, the capacitors have a single function, serving only as storage devices for lateral overflow of photogenerated charge.

[0005] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0006] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] To address the existing problems, this application provides a semiconductor device, comprising:

[0008] A substrate in which photodiodes and floating diffusion regions are formed at intervals, the floating diffusion regions being used to receive photogenerated charges generated by the photodiodes in response to incident light;

[0009] A PIP capacitor, located on the substrate and at least partially above the photodiode, comprises a first polysilicon layer, an insulating layer, and a second polysilicon layer stacked sequentially from bottom to top, wherein the first polysilicon layer is electrically connected to a control signal, and the second polysilicon layer is electrically connected to the floating diffusion region.

[0010] For example, the floating diffusion region includes a first floating diffusion region and a second floating diffusion region that are spaced apart, wherein the second polysilicon layer is electrically connected to the second floating diffusion region;

[0011] The semiconductor device further includes a first transmission transistor, a second transmission transistor, a reset transistor, a source follower, and a row select transistor. The gate, drain, and source of the first transmission transistor are electrically connected to a first transmission signal, the photodiode, and the first floating diffusion region, respectively. The gate, drain, and source of the second transmission transistor are electrically connected to a second transmission signal, the first floating diffusion region, and the second floating diffusion region, respectively. The gate, drain, and source of the reset transistor are electrically connected to a reset signal, a first power supply voltage, and the second floating diffusion region, respectively. The gate, drain, and source of the source follower are electrically connected to the first floating diffusion region, the second power supply voltage, and the drain of the row select transistor, respectively. The gate and source of the row select transistor are electrically connected to a row select signal and an output line, respectively.

[0012] For example, the substrate is of P-type conductivity, the first floating diffusion region and the second floating diffusion region are of N-type conductivity, and a first doped region of P-type conductivity and a second doped region of N-type conductivity are also formed in the substrate. The substrate, the first doped region and the second doped region constitute the photodiode, wherein the doping concentration of the first doped region is greater than the doping concentration of the substrate, the first polysilicon layer covers at least part of the first doped region and is electrically connected to the first doped region, and the source of the first transmission transistor is electrically connected to the second doped region.

[0013] Exemplarily, it also includes an interlayer dielectric layer covering the PIP capacitor and the substrate, wherein a first contact plug, a second contact plug, a third contact plug, a fourth contact plug, a first metal layer, a second metal layer, and a third metal layer are formed in the interlayer dielectric layer, wherein,

[0014] The first contact plug is electrically connected to the first metal layer and the first polysilicon layer, the second contact plug is electrically connected to the second metal layer and the second polysilicon layer, the third contact plug is electrically connected to the second metal layer and the second floating diffusion region, and the fourth contact plug is electrically connected to the third metal layer and the drain of the reset tube.

[0015] The first metal layer is electrically connected to the control signal, and the third metal layer is electrically connected to the first power supply voltage.

[0016] For example, the planar area of ​​the PIP capacitor is equal to the planar area of ​​the photodiode.

[0017] Another aspect of this application provides a method for manufacturing a semiconductor device, comprising:

[0018] A substrate is provided in which photodiodes and floating diffusion regions are formed at intervals, the floating diffusion regions being used to receive photogenerated charges generated by the photodiodes in response to incident light;

[0019] A PIP capacitor is formed on the substrate, the PIP capacitor being at least partially located above the photodiode, the PIP capacitor comprising a first polysilicon layer, an insulating layer, and a second polysilicon layer stacked sequentially from bottom to top, wherein the first polysilicon layer is electrically connected to a control signal, and the second polysilicon layer is electrically connected to the floating diffusion region.

[0020] For example, the floating diffusion region includes a first floating diffusion region and a second floating diffusion region that are spaced apart, wherein the second polysilicon layer is electrically connected to the second floating diffusion region;

[0021] The method also includes the steps of forming a first transmission transistor, a second transmission transistor, a reset transistor, a source follower, and a row select transistor. The gate, drain, and source of the first transmission transistor are electrically connected to a first transmission signal, the photodiode, and the first floating diffusion region, respectively. The gate, drain, and source of the second transmission transistor are electrically connected to a second transmission signal, the first floating diffusion region, and the second floating diffusion region, respectively. The gate, drain, and source of the reset transistor are electrically connected to a reset signal, a first power supply voltage, and the second floating diffusion region, respectively. The gate, drain, and source of the source follower are electrically connected to the first floating diffusion region, the second power supply voltage, and the drain of the row select transistor, respectively. The gate and source of the row select transistor are electrically connected to a row select signal and an output line, respectively.

[0022] For example, the PIP capacitor covers at least a portion of the photodiode; and / or

[0023] The substrate is of P-type conductivity, the first floating diffusion region and the second floating diffusion region are of N-type conductivity, and a first doped region of P-type conductivity and a second doped region of N-type conductivity are also formed in the substrate. The substrate, the first doped region and the second doped region constitute the photodiode, wherein the doping concentration of the first doped region is greater than the doping concentration of the substrate, the first polysilicon layer covers at least part of the first doped region, and the source of the first transmission transistor is electrically connected to the second doped region.

[0024] For example, after forming the PIP capacitor, the method further includes the steps of forming an interlayer dielectric layer and forming a first contact plug, a second contact plug, a third contact plug, a fourth contact plug, a first metal layer, a second metal layer, and a third metal layer in the interlayer dielectric layer, wherein,

[0025] The first contact plug is electrically connected to the first metal layer and the first polysilicon layer, the second contact plug is electrically connected to the second metal layer and the second polysilicon layer, the third contact plug is electrically connected to the second metal layer and the second floating diffusion region, and the fourth contact plug is electrically connected to the third metal layer and the drain of the reset tube.

[0026] The first metal layer is electrically connected to the control signal, and the third metal layer is electrically connected to the first power supply voltage.

[0027] For example, the first polysilicon layer and the gates of the first transmission transistor, the second transmission transistor, the reset transistor, the source follower, and the row select transistor are formed synchronously.

[0028] The semiconductor device and manufacturing method of the present application embodiment are provided with a PIP capacitor, which is located at least partially above the photodiode. The first polysilicon layer of the PIP capacitor is electrically connected to a control signal, and the second polysilicon layer is electrically connected to a floating diffusion region, so that LOFIC technology and optimization of the photoelectric field of the photodiode can be realized through the PIP capacitor. Attached Figure Description

[0029] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0030] In the attached image:

[0031] Figures 1A-1E This illustration shows a cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application.

[0032] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown.

[0033] Explanation of reference numerals in the attached figures:

[0034] 100 - Substrate, 101 - First doped region, 102 - Second doped region, 103 - First floating diffusion region, 104 - Second floating diffusion region, 105 - Drain of reset transistor, 106 - Third doped region, 107 - Shallow trench isolation structure, 108 - Gate of first transmission transistor, 109 - Gate of second transmission transistor, 110 - Gate of reset transistor, 111 - First polysilicon layer, 112 - Insulating layer, 113 - Second polysilicon layer, 114 - Interlayer dielectric layer, 115 - First contact plug, 116 - Second contact plug, 117 - Third contact plug, 118 - Fourth contact plug, 119 - First metal layer, 120 - Second metal layer, 121 - Third metal layer, 122 - Source follower, 123 - Row select transistor. Detailed Implementation

[0035] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the application.

[0040] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.

[0041] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0042] The existing LOFIC process uses metal-insulator-metal (MIM) capacitors, which introduces additional process steps in the back-end manufacturing process. For example, additional process steps are required to form the two metal plates of the MIM capacitor, which significantly increases the process complexity and the metal trace pressure in the back-end manufacturing process. At the same time, the MIM capacitor has a single function, only used as a storage device for lateral overflow photogenerated charge.

[0043] In view of the aforementioned technical problems, embodiments of this application provide a semiconductor device, including:

[0044] A substrate in which photodiodes and floating diffusion regions are formed at intervals, the floating diffusion regions being used to receive photogenerated charges generated by the photodiodes in response to incident light;

[0045] A PIP capacitor, located on a substrate and at least partially above a photodiode, comprises a first polysilicon layer, an insulating layer, and a second polysilicon layer stacked sequentially from bottom to top, wherein the first polysilicon layer is electrically connected to a control signal, and the second polysilicon layer is electrically connected to a floating diffusion region.

[0046] The semiconductor device of this application embodiment has a PIP capacitor, which is at least partially located above the photodiode. The first polysilicon layer of the PIP capacitor is electrically connected to a control signal, and the second polysilicon layer is electrically connected to a floating diffusion region, enabling LOFIC technology and optimization of the photoelectric field of the photodiode to be realized through the PIP capacitor.

[0047] Example 1

[0048] Below, for reference Figure 1E The semiconductor device described in this application is described in detail. The semiconductor device can be any suitable device well known to those skilled in the art; this embodiment primarily uses a CIS (Computer Integrated Circuit) as an example to explain and illustrate the technical solution of the present invention. This semiconductor device can be manufactured using the manufacturing method described in Embodiment 2 below.

[0049] like Figure 1EAs shown, the semiconductor device of this application includes a substrate 100 and a polysilicon-insulator-polysilicon (PIP) capacitor, wherein: a photodiode (PD) and a floating diffusion region (FD) are formed in the substrate 100 at intervals, the floating diffusion region is used to receive the photogenerated charge generated by the photodiode in response to incident light; the PIP capacitor is located on the substrate 100 and at least partially above the photodiode, and includes a first polysilicon layer 111, an insulating layer 112 and a second polysilicon layer 113 stacked sequentially from bottom to top, wherein the first polysilicon layer 111 is electrically connected to a control signal and the second polysilicon layer 113 is electrically connected to the floating diffusion region.

[0050] In one example, the floating diffusion region has a parasitic capacitance (i.e., C). FD To store photogenerated charge, however C FD The capacity of PIP capacitors is generally small, and the amount of photogenerated charge they can hold is limited. However, the second polysilicon layer 113 of the PIP capacitor in this application is electrically connected to the floating diffusion region, so that excess photogenerated charge can flow into the PIP capacitor. The PIP capacitor can help store photogenerated charge and realize LOFIC technology.

[0051] In one example, the PIP capacitor is at least partially located above the photodiode. The first polysilicon layer 111 of the PIP capacitor is electrically connected to a control signal. The control signal can bring out the first polysilicon layer 111 as a control terminal, which can be biased by applying a bias voltage. In this case, the first polysilicon layer 111 affects the operation of the photodiode's control gate. Under the influence of the bias voltage, the photoelectric field distribution within the photodiode can be optimized, improving quantum efficiency. When the PIP capacitor is used to help store photogenerated charge, the control terminal is grounded. Exemplarily, a dielectric layer (not shown) is formed between the PIP capacitor and the photodiode; that is, a dielectric layer is formed between the first polysilicon layer 111 and the photodiode. The dielectric layer may include, but is not limited to, an oxide layer (e.g., a silicon oxide layer), which electrically isolates the PIP capacitor and the photodiode.

[0052] In other words, the PIP capacitor can be switched between implementing LOFIC technology and optimizing the photoelectric field distribution within the photodiode by adjusting the control signal (adjusting the potential of the control terminal). In this way, LOFIC technology and optimization of the photoelectric field of the photodiode can be achieved through the PIP capacitor.

[0053] In one example, the first polysilicon layer 111 and the second polysilicon layer 113 serve as the two plates of the PIP capacitor, respectively. The first polysilicon layer 111 or the second polysilicon layer 113 can be formed synchronously with the gates of other transistors (such as the various transistors described below) without significantly increasing the process complexity.

[0054] In one example, PIP capacitors also exhibit better thermal stability compared to MIM capacitors.

[0055] In one example, substrate 100 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors; or substrate 100 may also include silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked germanium (S-SiGeOI), silicon-on-insulator germanium (SiGeOI), or germanium-on-insulator (GeOI), etc. Although several examples of materials that can form substrate 100 have been described herein, any material that can serve as substrate 100 falls within the spirit and scope of this application.

[0056] In one example, substrate 100 may include a substrate and an epitaxial layer formed on the substrate. Exemplarily, the substrate and the epitaxial layer may have different doping concentrations; for example, the doping concentration of the epitaxial layer may be lower than that of the substrate.

[0057] In one example, the PIP capacitor is located at least partially above the photodiode. In this way, the PIP capacitor covering the photodiode can reflect some of the photons that are not absorbed by the photodiode, allowing these photons to re-enter the photodiode and excite photogenerated charge carriers, which helps to improve the quantum efficiency of the photodiode.

[0058] In one example, the planar area of ​​the PIP capacitor is equal to the planar area of ​​the photodiode. That is, the ratio of the planar area of ​​the PIP capacitor to the planar area of ​​the pixel structure is equal to the fill factor of the pixel structure. This allows for optimization of the photoelectric field distribution within the photodiode without increasing the device's planar size. The planar area of ​​the PIP capacitor refers to the area of ​​the first polysilicon layer 111 and the second polysilicon layer 113 facing each other, such as... Figure 1E As shown, one end of the first polysilicon layer 111 extends beyond the second polysilicon layer 113 in the horizontal direction. The area of ​​the first polysilicon layer 111 and the second polysilicon layer 113 facing each other is the planar area of ​​the second polysilicon layer 113. In other embodiments, the planar area of ​​the PIP capacitor can be reasonably set according to actual needs, and this application does not impose any limitations on this.

[0059] In one example, such as Figure 1E As shown, the floating diffusion region includes a first floating diffusion region 103 and a second floating diffusion region 104 that are spaced apart, wherein the second polysilicon layer 113 is electrically connected to the second floating diffusion region 104.

[0060] In one example, such as Figure 1E As shown, the semiconductor device also includes a first transfer gate (TG), a second transfer gate, a reset transistor (RST), a source follower (SF) 122, and a row select transistor (SEL) 123. The gate 108, drain, and source of the first transfer gate are electrically connected to a first transmission signal, a photodiode, and a first floating diffusion region 103, respectively. The gate 109, drain, and source of the second transfer gate are electrically connected to a second transmission signal, the first floating diffusion region 103, and the second floating diffusion region 104, respectively. The gate 110, drain 105, and source of the reset transistor are electrically connected to a reset signal and a first power supply voltage (i.e., V). DD The gate, drain, and source of the source follower 122 are electrically connected to the first floating diffusion region 103 and the second power supply voltage (i.e., V) respectively. DD The drain of the horizontal selection transistor 123 and the gate and source of the horizontal selection transistor 123 are electrically connected to the horizontal selection signal and the output line, respectively.

[0061] In one example, such as Figure 1E As shown, substrate 100 is P-type conductive, and the first floating diffusion region 103 and the second floating diffusion region 104 are N-type conductive. A first doped region 101 of P-type conductivity and a second doped region 102 of N-type conductivity are also formed in substrate 100. Substrate 100, the first doped region 101, and the second doped region 102 constitute a photodiode. The doping concentration of the first doped region 101 is greater than the doping concentration of the substrate 100. A first polysilicon layer 111 covers at least a portion of the first doped region 101, and the source of the first transmission transistor is electrically connected to the second doped region 102. Exemplarily, the second doped region 102 can serve as the drain of the first transmission transistor. Exemplarily, the first doped region 101 is located within the second doped region 102, and both the first doped region 101 and the second doped region 102 constitute a portion of the surface of substrate 100. Exemplarily, the first polysilicon layer 111 may also cover at least a portion of the second doped region 102.

[0062] In one example, substrate 100, first doped region 101, and second doped region 102 constitute a pinned photodiode (PPD). When incident light shines on the photodiode, the energy of the photons is absorbed by electrons in the semiconductor material, causing electrons to jump from the valence band to the conduction band, thereby generating electron-hole pairs (i.e., photogenerated charge carriers). These electron-hole pairs are separated under the built-in electric field of the photodiode, and the electrons (i.e., photogenerated charges) are pushed towards and accumulate in the second doped region 102, which has N-type conductivity. The first doped region 101 can suppress dark current and, together with substrate 100, can completely deplete the second doped region 102.

[0063] In one example, the first doped region 101 may not be formed. The substrate and the second doped region 102 can still form a photodiode. In this case, the first polysilicon layer 111 covers at least part of the second doped region 102. When a control signal is applied to the first polysilicon layer 111, the photoelectric field distribution in the photodiode can also be optimized, thereby improving the quantum efficiency.

[0064] In one example, the first transmission signal, the second transmission signal, the reset signal, and the row selection signal control the formation and disappearance of channels in the first transmission transistor, the second transmission transistor, the reset transistor, and the row selection transistor, respectively.

[0065] In one example, the first floating diffusion region 103 serves as both the source of the first transmission transistor and the drain of the second transmission transistor, while the second floating diffusion region 104 serves as both the source of the second transmission transistor and the source of the reset transistor.

[0066] In one example, such as Figure 1E As shown, a third doped region 106 is also formed in the substrate 100, and the first floating diffusion region 103, the second floating diffusion region 104, and the drain 105 of the reset transistor are located in the third doped region 106. Exemplarily, the third doped region 106 and the substrate 100 have the same conductivity type, for example, both are P-type conductivity type; the third doped region 106 has a different doping concentration than the substrate 100.

[0067] In one example, such as Figure 1E As shown, a shallow trench isolation (STI) structure 107 is also formed in the substrate 100 on the side of the photodiode away from the first transmission tube. The shallow trench isolation structure 107 serves as an isolation structure.

[0068] In one example, the substrate 100, the first doped region 101, and the third doped region 106 are P-type conductive, while the second doped region 102, the first floating diffusion region 103, the second floating diffusion region 104, and the drain 105 of the reset transistor are N-type conductive.

[0069] In one example, the drain 105 of the reset transistor is located in the substrate 100, and the first doped region 101, the second doped region 102, the first floating diffusion region 103, the second floating diffusion region 104, the drain 105 of the reset transistor, and the third doped region 106 can be formed by an ion implantation process.

[0070] In one example, the gate 108 of the first transmission transistor, the gate 109 of the second transmission transistor, and the gate 110 of the reset transistor are all located on the substrate 100.

[0071] In one example Figure 1E The circuit diagram of source follower 122 and row select transistor 123 is shown only. The specific structure of source follower 122 and row select transistor 123 can be referred to the first transmission transistor, second transmission transistor and reset transistor, and will not be described again here. For example, source follower 122 and row select transistor 123 are formed synchronously with the first transmission transistor, second transmission transistor and reset transistor.

[0072] In one example, during the reset phase, the first transmission signal, the second transmission signal, and the reset signal control the formation of channels in the first transmission transistor, the second transmission transistor, and the reset transistor, respectively. At this time, the reset transistor is turned on, the potential of the second floating diffusion region 104 is pulled high, the second transmission transistor is turned on, which in turn pulls the potential of the first floating diffusion region 103 high, the first transmission transistor is turned on, thus completing the reset of the first floating diffusion region 103, the second floating diffusion region 104, the photodiode, and the PIP capacitor. After the reset is completed, the photosensitive phase begins, and the reset signal controls the disappearance of the channel in the reset transistor, turning the reset transistor off.

[0073] In one example, during the first photosensitive stage, the first transmission transistor is turned off, and photogenerated charges accumulate in the second doped region 102 to form a high potential. During this process, a control signal is applied to the first polysilicon layer 111, which can optimize the photoelectric field distribution within the photodiode and improve quantum efficiency. At this time, the first polysilicon layer 111 of the PIP capacitor acts as a control gate affecting the operation of the photodiode. The first photosensitive stage is also called the accumulation stage.

[0074] In the second stage of photosensitive processing, the first transmission signal controls the formation of a channel within the first transmission transistor. The potential difference between the second doped region 102 and the first floating diffusion region 103 drives photogenerated charges to migrate from the second doped region 102 through the channel to the first floating diffusion region 103. At this time, the formation and disappearance of the channel within the second transmission transistor can be selectively controlled according to actual needs. When the second transmission signal controls the formation of a channel within the second transmission transistor, the photogenerated charges in the first floating diffusion region 103 can further migrate to the second floating diffusion region 104 and the PIP capacitor. The PIP capacitor is used as a storage device for photogenerated charges to realize LOFIC technology, thereby increasing the full-well capacity and improving the dynamic range. At this time, the control terminal is grounded, that is, the first polysilicon layer 111 is grounded. When the first floating diffusion region 103 is sufficient to accommodate the photogenerated charges, the second transmission transistor can be controlled to turn off. For example, when the second transmission tube is turned on, it is in low conversion gain mode (the larger the well capacity, the lower the conversion gain); when the second transmission tube is turned on, it is in high conversion gain mode (the smaller the well capacity, the higher the conversion gain). The second stage of photosensitive activity is also called the charge transfer stage.

[0075] In one example, in the third stage of photosensitive sensing, the source follower 122 and the row selector 123 function as signal readout transistors. The source follower 122 is used for voltage buffering and impedance transformation, while the row selector 123 is turned on and off under the control of the row select signal to control whether the current row pixel is connected to the column bus. When the row selector is on, the output signal of the source follower is output to the output line (i.e., the column bus) through the row selector. When the row selector is off, the current row pixel is isolated from the column bus. This third stage of photosensitive sensing is also called the signal readout stage.

[0076] Below, we will describe how to adjust the control signal (i.e., adjust the potential of the control terminal) in both low and high conversion gain modes:

[0077] When in low conversion gain mode, during the accumulation phase, since both the first and second transmission transistors are off, a bias voltage can be applied to the control terminal (i.e., a bias voltage is applied to the first polysilicon layer 111) to optimize the photoelectric field distribution within the photodiode. During the charge transfer phase, both the first and second transmission transistors are on, and the PIP capacitor is used as a storage device for photogenerated charge to realize LOFIC technology. At this time, the control terminal is grounded (i.e., the first polysilicon layer is grounded) to ensure the stability of charge storage. During the signal readout phase, the control terminal also needs to be grounded to ensure the stability of charge storage.

[0078] When in high conversion gain mode, since the second transmission tube is disconnected throughout the entire photosensitive stage, the PIP capacitor is not used to store photogenerated charge throughout the entire photosensitive stage. Therefore, a bias voltage can be applied to the control terminal throughout the entire photosensitive stage (accumulation stage, charge transfer stage, and signal readout stage), or the control terminal can be freely adjusted at different stages of photosensitive.

[0079] In one example, the first transmission transistor, the second transmission transistor, the reset transistor, the source follower, and the row select transistor together constitute a 5T pixel structure. Alternatively, the second transmission transistor can be omitted, i.e., the second floating diffusion region 104 and the gate 109 of the second transmission transistor are not formed. In this case, the source of the reset transistor is electrically connected to the first floating diffusion region 103 (i.e., the first floating diffusion region 103 can serve as the source of the reset transistor), and the second polysilicon layer 113 of the PIP capacitor is electrically connected to the first floating diffusion region 103. In this case, the first transmission transistor, the reset transistor, the source follower, and the row select transistor together constitute a 4T pixel structure. In the 4T pixel structure, a bias voltage can be applied to the control terminal during the accumulation phase, and the control terminal needs to be grounded during the charge transfer phase and the signal readout phase. In the embodiments of this application, the first transmission transistor, the second transmission transistor, the reset transistor, the source follower, and the row select transistor are all N-type MOS transistors. Exemplarily, multiple pixels can share the source follower 122 and the row select transistor 123.

[0080] In one example, such as Figure 1E As shown, it also includes an interlayer dielectric (ILD) 114 covering the PIP capacitor and the substrate 100. The ILD contains a first contact plug 115, a second contact plug 116, a third contact plug 117, a fourth contact plug 118, a first metal layer 119, a second metal layer 120, and a third metal layer 121. Specifically, the first contact plug 115 is electrically connected to the first metal layer 119 and the first polysilicon layer 111; the second contact plug 116 is electrically connected to the second metal layer 120 and the second polysilicon layer 113; the third contact plug 117 is electrically connected to the second metal layer 120 and the second floating diffusion region 104; the fourth contact plug 118 is electrically connected to the third metal layer 121 and the drain 105 of the reset transistor; the first metal layer 119 is electrically connected to a control signal; and the third metal layer 121 is electrically connected to a first power supply voltage. For example, the first contact plug 115, the second contact plug 116, the third contact plug 117, the fourth contact plug 118, the first metal layer 119, the second metal layer 120, and the third metal layer 121 serve as interconnects. This application only shows one specific embodiment, and other structures can also be used to serve as interconnects. This application does not limit the scope of the interconnects.

[0081] In one example, etching and deposition processes commonly used in the art can be used to form the interlayer dielectric layer 114, the first contact plug 115, the second contact plug 116, the third contact plug 117, the fourth contact plug 118, the first metal layer 119, the second metal layer 120, and the third metal layer 121. Exemplarily, the first contact plug 115, the third contact plug 117, and the fourth contact plug 118 also penetrate the insulating layer 112.

[0082] In one example, the material of the interlayer dielectric layer 114 can be an insulating material such as silicon oxide, silicon nitride, fluorocarbon, carbon-doped silicon oxide, or silicon carbonitride. This application does not limit this. Taking the interlayer dielectric layer 114 as a silicon oxide layer as an example, the interlayer dielectric layer 114 can include a layer of silicon oxide material with or without doping, such as undoped silicon glass (USG), silicon phosphosilicate glass (PSG), or borosilicate phosphosilicate glass (BPSG). The materials of the first contact plug 115, the second contact plug 116, the third contact plug 117, the fourth contact plug 118, the first metal layer 119, the second metal layer 120, and the third metal layer 121 include, but are not limited to, copper, tungsten, gold, silver, aluminum, etc.

[0083] In one example, the insulating layer 112 in the PIP capacitor includes an oxide layer and / or a nitride layer. Specifically, in the self-aligned block (SAB) process, a silicon-rich oxide (SRO) layer is typically deposited as the SRO layer, and this SRO layer can serve as the insulating layer 112. Simultaneously, when the interlayer dielectric layer includes a composite film layer, a portion of the film layer in the interlayer dielectric layer 114 can also serve as the insulating layer 112. For example, when the interlayer dielectric layer 114 includes a high-tensile silicon nitride layer... When using SiN (HTN), the high-stress silicon nitride layer can also serve as the insulating layer 112. Furthermore, when combining CIS and flash memory processes, the PIP capacitor will have better process compatibility because the floating gate process in flash memory itself forms a polysilicon-oxide-nitride-oxide-polysilicon (poly-ONO-poly) layered structure. For example, the PIP capacitor can be formed simultaneously with the floating gate process, and the ONO structure in the floating gate process can serve as the insulating layer 112. Simultaneously, the first polysilicon layer 111 and / or the second polysilicon layer 113 in the PIP capacitor can be formed simultaneously with the poly structure in the floating gate process. Exemplarily, the insulating layer 112 may include a silicon-rich oxide layer and a high-stress silicon nitride layer. In other embodiments, the insulating layer 112 can also be any other suitable material. Exemplarily, the capacitance value of the PIP capacitor can be adjusted by adjusting the material and thickness of the insulating layer 112.

[0084] This concludes the description of the structure of the semiconductor device according to the embodiments of this application. A complete semiconductor device may also include other constituent structures, which will not be described in detail here.

[0085] In summary, the semiconductor device of this application embodiment has a PIP capacitor, which is at least partially located above the photodiode. The first polysilicon layer of the PIP capacitor is electrically connected to the control signal, and the second polysilicon layer is electrically connected to the floating diffusion region, enabling LOFIC technology and optimization of the photoelectric field of the photodiode to be realized through the PIP capacitor.

[0086] Example 2

[0087] This application also provides a method for manufacturing a semiconductor device, which is used to manufacture the semiconductor device in the aforementioned Embodiment 1. Below, refer to... Figures 1A-1E as well as Figure 2 The method for manufacturing the semiconductor device of this application is described in detail. Among other things, Figures 1A-1E This diagram illustrates a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application. Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown.

[0088] The semiconductor device can be any suitable device known to those skilled in the art. In this embodiment, the technical solution of the present invention is explained and illustrated mainly by taking the semiconductor device as a CIS.

[0089] For example, the method for manufacturing a semiconductor device according to an embodiment of this application includes the following steps:

[0090] First, execute step S1, as follows: Figure 1A As shown, a substrate 100 is provided, in which photodiodes and floating diffusion regions are formed at intervals. The floating diffusion regions are used to receive photogenerated charges generated by the photodiodes in response to incident light.

[0091] Next, proceed to step S2, as follows: Figures 1A-1C As shown, a PIP capacitor is formed on the substrate 100, at least partially located above the photodiode. The PIP capacitor includes a first polysilicon layer 111, an insulating layer 112, and a second polysilicon layer 113 stacked sequentially from bottom to top. The first polysilicon layer 111 is electrically connected to a control signal, and the second polysilicon layer 113 is electrically connected to a floating diffusion region. Exemplarily, the second polysilicon layer 113 is electrically connected to a second floating diffusion region 104.

[0092] In one example, the floating diffusion region has a parasitic capacitance (i.e., C). FD To store photogenerated charge, however CFD The capacity of PIP capacitors is generally small, and the amount of photogenerated charge they can hold is limited. However, the second polysilicon layer 113 of the PIP capacitor in this application is electrically connected to the floating diffusion region, so that excess photogenerated charge can flow into the PIP capacitor. The PIP capacitor can help store photogenerated charge and realize LOFIC technology.

[0093] In one example, the PIP capacitor is at least partially located above the photodiode. The first polysilicon layer 111 of the PIP capacitor is electrically connected to a control signal. The control signal can bring out the first polysilicon layer 111 as a control terminal, which can apply a bias voltage. In this case, the first polysilicon layer 111 affects the operation of the control gate of the photodiode. Under the influence of the bias voltage, the photoelectric field distribution within the photodiode can be optimized, improving quantum efficiency. When the PIP capacitor is used to help store photogenerated charge, the control terminal is grounded. Exemplarily, the method also includes forming a dielectric layer (not shown) between the PIP capacitor and the photodiode, i.e., forming a dielectric layer between the first polysilicon layer 111 and the photodiode. The dielectric layer may include, but is not limited to, an oxide layer (e.g., a silicon oxide layer), which electrically isolates the PIP capacitor and the photodiode.

[0094] In other words, the PIP capacitor can be switched between implementing LOFIC technology and optimizing the photoelectric field distribution within the photodiode by adjusting the control signal (adjusting the potential of the control terminal). In this way, LOFIC technology and optimization of the photoelectric field of the photodiode can be achieved through the PIP capacitor.

[0095] In one example, the first polysilicon layer 111 and the second polysilicon layer 113 serve as the two plates of the PIP capacitor, respectively. The first polysilicon layer 111 or the second polysilicon layer 113 can be formed synchronously with the gates of other transistors (such as the various transistors described below) without significantly increasing the process complexity.

[0096] In one example, PIP capacitors also exhibit better thermal stability compared to MIM capacitors.

[0097] In one example, the PIP capacitor is located at least partially above the photodiode. In this way, the PIP capacitor covering the photodiode can reflect some of the photons that are not absorbed by the photodiode, allowing these photons to re-enter the photodiode and excite photogenerated charge carriers, which helps to improve the quantum efficiency of the photodiode.

[0098] In one example, such as Figures 1A-1CAs shown, the floating diffusion region includes a first floating diffusion region 103 and a second floating diffusion region 104 that are spaced apart, wherein the second polysilicon layer 113 is electrically connected to the second floating diffusion region 104.

[0099] In one example, such as Figures 1A-1E As shown, the method also includes the steps of forming a first transmission transistor, a second transmission transistor, a reset transistor, a source follower 122, and a row select transistor 123. Specifically, the gate 108, drain, and source of the first transmission transistor are electrically connected to a first transmission signal, a photodiode, and a first floating diffusion region 103, respectively; the gate 109, drain, and source of the second transmission transistor are electrically connected to a second transmission signal, the first floating diffusion region 103, and the second floating diffusion region 104, respectively; and the gate 110, drain 105, and source of the reset transistor are electrically connected to a reset signal and a first power supply voltage (i.e., V). DD The gate, drain, and source of the source follower 122 are electrically connected to the first floating diffusion region 103 and the second power supply voltage (i.e., V) respectively. DD The drain of the horizontal selection transistor 123 and the gate and source of the horizontal selection transistor 123 are electrically connected to the horizontal selection signal and the output line, respectively.

[0100] In one example, substrate 100 is of P-type conductivity, and the first floating diffusion region 103 and the second floating diffusion region 104 are of N-type conductivity. Figures 1A-1C As shown, a first doped region 101 of P-type conductivity and a second doped region 102 of N-type conductivity are also formed in the substrate 100. The substrate 100, the first doped region 101, and the second doped region 102 constitute a photodiode. The doping concentration of the first doped region 101 is greater than the doping concentration of the substrate 100. A first polysilicon layer 111 covers at least a portion of the first doped region 101, and the source of the first transmission transistor is electrically connected to the second doped region 102. Exemplarily, the second doped region 102 can serve as the drain of the first transmission transistor. Exemplarily, the first doped region 101 is located within the second doped region 102, and both the first doped region 101 and the second doped region 102 constitute a portion of the surface of the substrate 100. Exemplarily, the first polysilicon layer 111 may also cover at least a portion of the second doped region 102.

[0101] In one example, substrate 100, first doped region 101, and second doped region 102 constitute a pinned photodiode (PPD). When incident light shines on the photodiode, the energy of the photons is absorbed by electrons in the semiconductor material, causing electrons to jump from the valence band to the conduction band, thereby generating electron-hole pairs (i.e., photogenerated charge carriers). These electron-hole pairs are separated under the built-in electric field of the photodiode, and the electrons (i.e., photogenerated charges) are pushed towards and accumulate in the second doped region 102, which has N-type conductivity. The first doped region 101 can suppress dark current and, together with substrate 100, can completely deplete the second doped region 102.

[0102] In one example, the first doped region 101 may not be formed. The substrate and the second doped region 102 can still form a photodiode. In this case, the first polysilicon layer 111 covers at least part of the second doped region 102. When a control signal is applied to the first polysilicon layer 111, the photoelectric field distribution in the photodiode can also be optimized, thereby improving the quantum efficiency.

[0103] In one example, the first transmission signal, the second transmission signal, the reset signal, and the row selection signal control the formation and disappearance of channels in the first transmission transistor, the second transmission transistor, the reset transistor, and the row selection transistor, respectively.

[0104] In one example, the first floating diffusion region 103 serves as both the source of the first transmission transistor and the drain of the second transmission transistor, while the second floating diffusion region 104 serves as both the source of the second transmission transistor and the source of the reset transistor.

[0105] In one example, such as Figure 1A As shown, a third doped region 106 is also formed in the substrate 100, and the first floating diffusion region 103, the second floating diffusion region 104, and the drain 105 of the reset transistor are located in the third doped region 106. Exemplarily, the third doped region 106 and the substrate 100 have the same conductivity type, for example, both are P-type conductivity type; the third doped region 106 has a different doping concentration than the substrate 100.

[0106] In one example, such as Figure 1A As shown, a shallow trench isolation (STI) structure 107 is also formed in the substrate 100 on the side of the photodiode away from the first transmission tube. The shallow trench isolation structure 107 serves as an isolation structure.

[0107] In one example, the substrate 100, the first doped region 101, and the third doped region 106 are P-type conductive, while the second doped region 102, the first floating diffusion region 103, the second floating diffusion region 104, and the drain 105 of the reset transistor are N-type conductive.

[0108] In one example, the drain 105 of the reset transistor is located in the substrate 100, and the first doped region 101, the second doped region 102, the first floating diffusion region 103, the second floating diffusion region 104, the drain 105 of the reset transistor, and the third doped region 106 can be formed by an ion implantation process.

[0109] In one example, the gate 108 of the first transmission transistor, the gate 109 of the second transmission transistor, and the gate 110 of the reset transistor are all located on the substrate 100.

[0110] In one example Figure 1E The circuit diagram of source follower 122 and row select transistor 123 is shown only. The specific structure of source follower 122 and row select transistor 123 can be referred to the first transmission transistor, second transmission transistor and reset transistor, and will not be described again here. For example, source follower 122 and row select transistor 123 are formed synchronously with the first transmission transistor, second transmission transistor and reset transistor.

[0111] In one example, the first polysilicon layer 111 and the gates 108 of the first transmission transistor, 109 of the second transmission transistor, 110 of the reset transistor, 122 of the source follower, and 123 of the row select transistor are formed simultaneously. This eliminates the need for additional processes to form the first polysilicon layer 111, reducing process complexity.

[0112] In one example, during the reset phase, the first transmission signal, the second transmission signal, and the reset signal control the formation of channels in the first transmission transistor, the second transmission transistor, and the reset transistor, respectively. At this time, the reset transistor is turned on, the potential of the second floating diffusion region 104 is pulled high, the second transmission transistor is turned on, which in turn pulls the potential of the first floating diffusion region 103 high, the first transmission transistor is turned on, thus completing the reset of the first floating diffusion region 103, the second floating diffusion region 104, the photodiode, and the PIP capacitor. After the reset is completed, the photosensitive phase begins, and the reset signal controls the disappearance of the channel in the reset transistor, turning the reset transistor off.

[0113] In one example, during the first stage of photosensitive processing, the first transmission transistor is turned off, and photogenerated charges accumulate in the second doped region 102 to form a high potential. During this process, a control signal is applied to the first polysilicon layer 111, which can optimize the photoelectric field distribution within the photodiode and improve quantum efficiency. At this time, the first polysilicon layer 111 of the PIP capacitor acts as a control gate affecting the operation of the photodiode. The first stage of photosensitive processing is also called the accumulation stage.

[0114] In the second stage of photosensitive processing, the first transmission signal controls the formation of a channel within the first transmission transistor. The potential difference between the second doped region 102 and the first floating diffusion region 103 drives photogenerated charges to migrate from the second doped region 102 through the channel to the first floating diffusion region 103. At this time, the control signal is grounded, i.e., the first polysilicon layer 111 is grounded. The formation and disappearance of the channel within the second transmission transistor can be selectively controlled according to actual needs. When the second transmission signal controls the formation of a channel within the second transmission transistor, the photogenerated charges in the first floating diffusion region 103 can further migrate to the second floating diffusion region 104 and the PIP capacitor. The PIP capacitor serves as a storage device for the photogenerated charges to achieve LOFIC technology, thereby increasing the full-well capacity and improving the dynamic range. At this time, the control terminal is grounded, i.e., the first polysilicon layer 111 is grounded. When the first floating diffusion region 103 is sufficient to accommodate the photogenerated charges, the second transmission transistor can be turned off. For example, when the second transmission tube is turned on, it is in low conversion gain mode (the larger the well capacity, the lower the conversion gain); when the second transmission tube is turned on, it is in high conversion gain mode (the smaller the well capacity, the higher the conversion gain). The second stage of photosensitive activity is also called the charge transfer stage.

[0115] In one example, in the third stage of photosensitive sensing, the source follower 122 and the row selector 123 function as signal readout transistors. The source follower 122 is used for voltage buffering and impedance transformation, while the row selector 123 is turned on and off under the control of the row select signal to control whether the current row pixel is connected to the column bus. When the row selector is on, the output signal of the source follower is output to the output line (i.e., the column bus) through the row selector. When the row selector is off, the current row pixel is isolated from the column bus. This third stage of photosensitive sensing is also called the signal readout stage.

[0116] In one example, the adjustment of the control signal in low conversion gain mode and high conversion gain mode has been described in detail above and will not be repeated here.

[0117] In one example, the first transmission transistor, the second transmission transistor, the reset transistor, the source follower, and the row select transistor together constitute a 5T pixel structure. Alternatively, the second transmission transistor can be omitted, i.e., the second floating diffusion region 104 and the gate 109 of the second transmission transistor are not formed. In this case, the source of the reset transistor is electrically connected to the first floating diffusion region 103 (i.e., the first floating diffusion region 103 can serve as the source of the reset transistor), and the second polysilicon layer 113 of the PIP capacitor is electrically connected to the first floating diffusion region 103. In this case, the first transmission transistor, the reset transistor, the source follower, and the row select transistor together constitute a 4T pixel structure. In the 4T pixel structure, a bias voltage can be applied to the control terminal during the accumulation phase, and the control terminal needs to be grounded during the charge transfer phase and the signal readout phase. In the embodiments of this application, the first transmission transistor, the second transmission transistor, the reset transistor, the source follower, and the row select transistor are all N-type MOS transistors. Exemplarily, multiple pixels can share the source follower 122 and the row select transistor 123.

[0118] In one example, such as Figure 1D and Figure 1E As shown, the method also includes the steps of forming an interlayer dielectric layer 114 and forming a first contact plug 115, a second contact plug 116, a third contact plug 117, a fourth contact plug 118, a first metal layer 119, a second metal layer 120, and a third metal layer 121 in the interlayer dielectric layer 114. Specifically, the first contact plug 115 is electrically connected to the first metal layer 119 and the first polysilicon layer 111; the second contact plug 116 is electrically connected to the second metal layer 120 and the second polysilicon layer 113; the third contact plug 117 is electrically connected to the second metal layer 120 and the second floating diffusion region 104; the fourth contact plug 118 is electrically connected to the third metal layer 121 and the drain 105 of the reset transistor; the first metal layer 119 is electrically connected to a control signal; and the third metal layer 121 is electrically connected to a first power supply voltage. For example, the first contact plug 115, the second contact plug 116, the third contact plug 117, the fourth contact plug 118, the first metal layer 119, the second metal layer 120, and the third metal layer 121 serve as interconnects. This application only shows one specific embodiment, and other structures can also be used to serve as interconnects. This application does not limit the scope of the interconnects.

[0119] In one example, etching and deposition processes commonly used in the art can be used to form the interlayer dielectric layer 114, the first contact plug 115, the second contact plug 116, the third contact plug 117, the fourth contact plug 118, the first metal layer 119, the second metal layer 120, and the third metal layer 121. Exemplarily, the first contact plug 115, the third contact plug 117, and the fourth contact plug 118 also penetrate the insulating layer 112.

[0120] In one example, the material of the interlayer dielectric layer 114 can be an insulating material such as silicon oxide, silicon nitride, fluorocarbon, carbon-doped silicon oxide, or silicon carbonitride. This application does not limit this. Taking the interlayer dielectric layer 114 as a silicon oxide layer as an example, the interlayer dielectric layer 114 can include a layer of silicon oxide material with or without doping, such as undoped silicon glass (USG), silicon phosphosilicate glass (PSG), or borosilicate phosphosilicate glass (BPSG). The materials of the first contact plug 115, the second contact plug 116, the third contact plug 117, the fourth contact plug 118, the first metal layer 119, the second metal layer 120, and the third metal layer 121 include, but are not limited to, copper, tungsten, gold, silver, aluminum, etc.

[0121] In one example, the insulating layer 112 in the PIP capacitor includes an oxide layer and / or a nitride layer. Specifically, in the self-aligned silicide barrier layer process, a silicon-rich oxide layer is generally deposited as the self-aligned silicide barrier layer, and this silicon-rich oxide layer can serve as the insulating layer 112. Simultaneously, when the interlayer dielectric layer includes a composite film layer, a portion of the film layer in the interlayer dielectric layer 114 can also serve as the insulating layer 112. For example, when the interlayer dielectric layer 114 includes a high-tensile-stress silicon nitride layer, this high-tensile-stress silicon nitride layer can also serve as the insulating layer 112. Furthermore, when CIS and flash memory processes are combined, since the floating gate process in flash memory itself forms a polysilicon-oxide-nitride-oxide-polysilicon (poly-ONO-poly) layered structure, the PIP capacitor will have better process compatibility. For example, the PIP capacitor can be formed simultaneously with the floating gate process, and the ONO structure in the floating gate process can serve as the insulating layer 112. Simultaneously, the first polysilicon layer 111 and / or the second polysilicon layer 113 in the PIP capacitor can be formed simultaneously with the poly structure in the floating gate process. Exemplarily, the insulating layer 112 may include a silicon-rich oxide layer and a high-tensile-stress silicon nitride layer. In other embodiments, the insulating layer 112 may also be any other suitable material. Exemplarily, the capacitance value of the PIP capacitor can be adjusted by adjusting the material and thickness of the insulating layer 112.

[0122] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. The manufacturing of a complete semiconductor device may include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0123] In summary, the semiconductor device manufacturing method of this application embodiment forms a PIP capacitor, which is at least partially located above the photodiode. The first polysilicon layer of the PIP capacitor is electrically connected to a control signal, and the second polysilicon layer is electrically connected to a floating diffusion region, enabling LOFIC technology and optimization of the photoelectric field of the photodiode to be realized through the PIP capacitor.

[0124] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A semiconductor device, characterized in that, include: A substrate in which photodiodes and floating diffusion regions are formed at intervals, the floating diffusion regions being used to receive photogenerated charges generated by the photodiodes in response to incident light; A PIP capacitor, located on the substrate and at least partially above the photodiode, comprises a first polysilicon layer, an insulating layer, and a second polysilicon layer stacked sequentially from bottom to top, wherein the first polysilicon layer is electrically connected to a control signal, and the second polysilicon layer is electrically connected to the floating diffusion region.

2. The semiconductor device according to claim 1, characterized in that, The floating diffusion region includes a first floating diffusion region and a second floating diffusion region that are spaced apart, wherein the second polysilicon layer is electrically connected to the second floating diffusion region; The semiconductor device further includes a first transmission transistor, a second transmission transistor, a reset transistor, a source follower, and a row select transistor. The gate, drain, and source of the first transmission transistor are electrically connected to a first transmission signal, the photodiode, and the first floating diffusion region, respectively. The gate, drain, and source of the second transmission transistor are electrically connected to a second transmission signal, the first floating diffusion region, and the second floating diffusion region, respectively. The gate, drain, and source of the reset transistor are electrically connected to a reset signal, a first power supply voltage, and the second floating diffusion region, respectively. The gate, drain, and source of the source follower are electrically connected to the first floating diffusion region, the second power supply voltage, and the drain of the row select transistor, respectively. The gate and source of the row select transistor are electrically connected to a row select signal and an output line, respectively.

3. The semiconductor device according to claim 2, characterized in that, The substrate is of P-type conductivity, the first floating diffusion region and the second floating diffusion region are of N-type conductivity, and a first doped region of P-type conductivity and a second doped region of N-type conductivity are also formed in the substrate. The substrate, the first doped region and the second doped region constitute the photodiode, wherein the doping concentration of the first doped region is greater than the doping concentration of the substrate, the first polysilicon layer covers at least part of the first doped region and is electrically connected to the first doped region, and the source of the first transmission transistor is electrically connected to the second doped region.

4. The semiconductor device according to claim 2, characterized in that, It also includes an interlayer dielectric layer covering the PIP capacitor and the substrate, wherein a first contact plug, a second contact plug, a third contact plug, a fourth contact plug, a first metal layer, a second metal layer, and a third metal layer are formed in the interlayer dielectric layer, wherein, The first contact plug is electrically connected to the first metal layer and the first polysilicon layer, the second contact plug is electrically connected to the second metal layer and the second polysilicon layer, the third contact plug is electrically connected to the second metal layer and the second floating diffusion region, and the fourth contact plug is electrically connected to the third metal layer and the drain of the reset tube. The first metal layer is electrically connected to the control signal, and the third metal layer is electrically connected to the first power supply voltage.

5. The semiconductor device according to claim 1, characterized in that, The planar area of ​​the PIP capacitor is equal to the planar area of ​​the photodiode.

6. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided in which photodiodes and floating diffusion regions are formed at intervals, the floating diffusion regions being used to receive photogenerated charges generated by the photodiodes in response to incident light; A PIP capacitor is formed on the substrate, the PIP capacitor being at least partially located above the photodiode, the PIP capacitor comprising a first polysilicon layer, an insulating layer, and a second polysilicon layer stacked sequentially from bottom to top, wherein the first polysilicon layer is electrically connected to a control signal, and the second polysilicon layer is electrically connected to the floating diffusion region.

7. The manufacturing method according to claim 6, characterized in that, The floating diffusion region includes a first floating diffusion region and a second floating diffusion region that are spaced apart, wherein the second polysilicon layer is electrically connected to the second floating diffusion region; The method also includes the steps of forming a first transmission transistor, a second transmission transistor, a reset transistor, a source follower, and a row select transistor. The gate, drain, and source of the first transmission transistor are electrically connected to a first transmission signal, the photodiode, and the first floating diffusion region, respectively. The gate, drain, and source of the second transmission transistor are electrically connected to a second transmission signal, the first floating diffusion region, and the second floating diffusion region, respectively. The gate, drain, and source of the reset transistor are electrically connected to a reset signal, a first power supply voltage, and the second floating diffusion region, respectively. The gate, drain, and source of the source follower are electrically connected to the first floating diffusion region, the second power supply voltage, and the drain of the row select transistor, respectively. The gate and source of the row select transistor are electrically connected to a row select signal and an output line, respectively.

8. The manufacturing method according to claim 7, characterized in that, The PIP capacitor covers at least a portion of the photodiode; and / or The substrate is of P-type conductivity, the first floating diffusion region and the second floating diffusion region are of N-type conductivity, and a first doped region of P-type conductivity and a second doped region of N-type conductivity are also formed in the substrate. The substrate, the first doped region and the second doped region constitute the photodiode, wherein the doping concentration of the first doped region is greater than the doping concentration of the substrate, the first polysilicon layer covers at least part of the first doped region, and the source of the first transmission transistor is electrically connected to the second doped region.

9. The manufacturing method according to claim 7, characterized in that, After forming the PIP capacitor, the method further includes the steps of forming an interlayer dielectric layer and forming a first contact plug, a second contact plug, a third contact plug, a fourth contact plug, a first metal layer, a second metal layer, and a third metal layer in the interlayer dielectric layer, wherein... The first contact plug is electrically connected to the first metal layer and the first polysilicon layer, the second contact plug is electrically connected to the second metal layer and the second polysilicon layer, the third contact plug is electrically connected to the second metal layer and the second floating diffusion region, and the fourth contact plug is electrically connected to the third metal layer and the drain of the reset tube. The first metal layer is electrically connected to the control signal, and the third metal layer is electrically connected to the first power supply voltage.

10. The manufacturing method according to claim 7, characterized in that, The first polysilicon layer and the gates of the first transmission transistor, the second transmission transistor, the reset transistor, the source follower, and the row select transistor are formed synchronously.

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