Temperature compensation circuit and radio frequency chip

Abstract

The invention discloses a temperature compensation circuit and a radio frequency chip, and relates to the technical field of integrated circuits, and the temperature compensation circuit comprises a band-gap reference circuit used for generating a first group of reference voltage signals, a second group of reference voltage signals and normal temperature current, the high-temperature slope control circuit is used for generating high-temperature current based on the first group of reference voltage signals, the low-temperature slope control circuit is used for generating low-temperature current based on the second group of reference voltage signals, and the current adder is used for generating temperature compensation current according to the high-temperature current, the low-temperature current and the normal-temperature current. According to the circuit, different temperature compensations can be made for low temperature, normal temperature and high temperature, exponential temperature compensation can be provided, more bias current can be compensated at the high temperature and the low temperature, and the temperature compensation circuit is wider in applicability and richer in application scene.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a temperature compensation circuit and a radio frequency chip. Background Technology

[0002] In the field of radio frequency (RF) chips, which heavily rely on performance stability, temperature compensation circuits play an indispensable role in critical components such as power amplifiers (PAs) and low-noise amplifiers (LNAs). Their core value and design goal is to effectively overcome the inherent defects of semiconductor device characteristics drifting with temperature, ensuring that the chip's key RF performance parameters (such as gain, output power, linearity, noise figure, and input-output matching) maintain high stability and consistency over a wide operating temperature range (e.g., from the industrial standard of -40°C to +85°C, and even the more demanding range of automotive applications). This is crucial for improving the overall reliability, link budget, and signal quality of communication systems (such as mobile phones, base stations, satellite communications, and radar).

[0003] The typical effects of temperature changes on amplifier chips are as follows: at high temperatures, factors such as decreased carrier mobility and changes in threshold voltage usually lead to deterioration in amplifier performance. For example, the gain and output power of a power amplifier (PA) decrease, efficiency drops, and the noise figure of an amplifier (LNA) may deteriorate. Conversely, at low temperatures, carrier mobility increases, and device performance often improves (gain may increase). However, this non-uniform variation in performance with temperature is not ideal. It can cause the system's operating characteristics to shift under different environments (such as extreme outdoor temperatures or internal temperature rises), affecting signal consistency and reliability.

[0004] Therefore, this application proposes a temperature compensation circuit that can realize segmented compensation for different temperature ranges, and an RF chip containing the temperature compensation circuit. Summary of the Invention

[0005] To overcome the above-mentioned defects, the temperature compensation circuit provided in this application can combine voltage and current with different slopes of curves that change with temperature to achieve independent control of low temperature, normal temperature and high temperature compensation. At the same time, it uses a differential amplifier to generate an exponential compensation current to provide exponential temperature compensation.

[0006] In a first aspect, this application provides a temperature compensation circuit, comprising: a bandgap reference circuit, a high-temperature slope control circuit, a low-temperature slope control circuit, and a current adder;

[0007] The bandgap reference circuit is used to generate a first set of reference voltage signals, a second set of reference voltage signals, and a room temperature current, and inputs the first set of reference voltage signals to the high temperature slope control circuit, inputs the second set of reference voltage signals to the low temperature slope control circuit, and outputs the room temperature current to the current adder.

[0008] The high-temperature slope control circuit is used to generate a high-temperature current based on the first set of reference voltage signals and output the high-temperature current to the current adder.

[0009] The low-temperature slope control circuit is used to generate a low-temperature current based on the second set of reference voltage signals and output the low-temperature current to the current adder.

[0010] The current adder is used to generate a temperature compensation current based on the input high-temperature current, low-temperature current, and normal-temperature current.

[0011] The temperature compensation current includes an exponentially decreasing or increasing current corresponding to the low temperature range, and an exponentially increasing or decreasing current corresponding to the high temperature range.

[0012] Preferably, the bandgap reference circuit includes a voltage generation circuit and a current generation circuit; the voltage generation circuit is used to generate a first zero temperature coefficient voltage, a second zero temperature coefficient voltage, a positive temperature coefficient voltage, and a negative temperature coefficient voltage, and the current generation circuit is used to generate a room temperature current;

[0013] The first set of reference voltage signals includes the positive temperature coefficient voltage and the first zero temperature coefficient voltage; the second set of reference voltage signals includes the negative temperature coefficient voltage and the second zero temperature coefficient voltage.

[0014] Preferably, the voltage generation circuit includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a first transistor, a second transistor, a third transistor, a first operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor;

[0015] The bases and collectors of the first, second, and third transistors are all connected to ground. The emitter of the first transistor is connected to the drain of the first MOSFET and the first input terminal of the first transport amplifier. The emitter of the second transistor is connected to the drain of the second MOSFET and the second input terminal of the first transport amplifier via the first resistor. The output terminal of the first transport amplifier is connected to the gates of the first and second MOSFETs. The emitter of the third transistor is connected to the drain of the third MOSFET via the second and third resistors. The drain of the fourth MOSFET is grounded via the fourth resistor. The gates of the third and fourth MOSFETs are both connected to the gates of the first and second MOSFETs. The sources of the first, second, third, and fourth MOSFETs are all connected to a power supply terminal.

[0016] Wherein, the connection node between the emitter of the first transistor and the drain of the first MOS transistor serves as the output terminal for generating the negative temperature coefficient voltage, the connection node between the fourth resistor and the drain of the fourth MOS transistor serves as the output terminal for generating the positive temperature coefficient voltage, the connection node between the third resistor and the drain of the third MOS transistor serves as the output terminal for generating the first zero temperature coefficient voltage, and the connection node between the second resistor and the third resistor serves as the output terminal for generating the second zero temperature coefficient voltage.

[0017] Preferably, the current generation circuit includes a second operational amplifier, a fifth MOSFET, a sixth MOSFET, a fifth resistor, and a sixth resistor;

[0018] The first input terminal of the second operational amplifier is connected to the output terminal that generates the first zero temperature coefficient voltage. The second input terminal of the second operational amplifier is connected to the connection node of the fifth resistor and the sixth resistor. The output terminal of the second operational amplifier is connected to the gate of the fifth MOS transistor and the sixth MOS transistor. The sources of the fifth MOS transistor and the sixth MOS transistor are both connected to the power supply terminal. The drain of the fifth MOS transistor is grounded through the sixth resistor and the fifth resistor connected in series.

[0019] The drain of the sixth MOS transistor serves as the output terminal for generating the room temperature current.

[0020] Preferably, the high-temperature slope control circuit and / or the low-temperature slope control circuit includes a reference current generation module, an exponential current generation module, and a current mirror module. The output of the reference current generation module is connected to the input of the exponential current generation module, and the output of the exponential current generation module is connected to the current mirror module.

[0021] The current mirror module includes a bias unit, a first current mirror unit, and a second current mirror unit. The first current mirror unit is used to output a forward current, and the second current mirror unit is used to output a reverse current. The forward current is superimposed on the reverse current to form the high-temperature current or the low-temperature current.

[0022] Preferably, the reference current generating module includes a first transistor and a second transistor;

[0023] The gate of the first transistor is connected to a first constant bias voltage, the source of the first transistor is connected to a power supply terminal, the drain of the first transistor is connected to the source of the second transistor, the gate of the second transistor is connected to a second constant bias voltage, and the drain of the second transistor is connected to the input of the exponential current generation module.

[0024] Preferably, the exponential current generating module includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0025] The sources of the third and fourth transistors are both connected to the drain of the second transistor. The drains of the third and fourth transistors are respectively connected to the drains of the fifth and sixth transistors. The drains of the third and fourth transistors are also respectively connected to the gates of the seventh and eighth transistors. The sources of the fifth and sixth transistors are respectively connected to the drains of the seventh and eighth transistors. The sources of the seventh and eighth transistors are both grounded.

[0026] The gates of the third transistor and the fourth transistor are connected to either the first set of reference voltage signals or the second set of reference voltage signals.

[0027] Preferably, the bias unit includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; both the first current mirror unit and the second current mirror unit include multiple current mirrors;

[0028] The gates of the ninth transistor and the tenth transistor are respectively connected to the gates of the first transistor and the second transistor. The gates of the ninth transistor and the tenth transistor are also connected to the input terminals of multiple current mirrors in the first current mirror unit. The output terminals of the multiple current mirrors in the first current mirror unit are used to output the positive current.

[0029] The gates of the eleventh transistor and the twelfth transistor are respectively connected to the gates of the fifth transistor and the sixth transistor. The gates of the eleventh transistor and the twelfth transistor are also connected to the input terminals of multiple current mirrors in the second current mirror unit. The output terminals of the multiple current mirrors in the second current mirror unit are used to output the reverse current.

[0030] In a second aspect, this application provides an radio frequency chip, including the temperature compensation circuit described in any of the above technical solutions.

[0031] The above-mentioned technical solutions of this application have at least one or more of the following beneficial effects: The temperature compensation circuit structure proposed in this application can make different temperature compensations for low temperature, normal temperature and high temperature, and can provide exponential temperature compensation, so that the bias current at high temperature and low temperature can be compensated more, making the temperature compensation circuit more applicable and richer in application scenarios. Attached Figure Description

[0032] The disclosure of this application will become more readily understood with reference to the accompanying drawings. It will be readily understood by those skilled in the art that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this application. Furthermore, similar numbers in the drawings are used to denote similar components, wherein:

[0033] Figure 1 This is a schematic diagram of a temperature compensation circuit commonly used in existing technology.

[0034] Figure 2 Based on Figure 1 The diagram shows the effect of the temperature compensation current output by the temperature compensation circuit changing with temperature.

[0035] Figure 3 This is a schematic diagram of the composition structure of a temperature compensation circuit provided in an embodiment of this application;

[0036] Figure 4 Based on Figure 3 The diagram shows the output temperature compensation current of the temperature compensation circuit as a function of temperature.

[0037] Figure 5 This is a schematic diagram of the circuit structure of a bandgap reference circuit provided in an embodiment of this application;

[0038] Figure 6 This is a schematic diagram of a high / low temperature slope control circuit structure provided in an embodiment of this application.

[0039] Figure 7 Based on Figure 6 The diagram shows the principle of the high-temperature slope control circuit generating high-temperature current.

[0040] Figure 8 Based on Figure 6 The diagram shows the principle of the low-temperature slope control circuit generating low-temperature current. Detailed Implementation

[0041] Some embodiments of this application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of this application and are not intended to limit the scope of protection of this application.

[0042] In the description of this application, "module" and "unit" can include hardware, software, or a combination of both. A module or unit can include hardware circuitry, various suitable sensors, and communication ports. The term "A and / or B" represents all possible combinations of A and B, such as only A, only B, or A and B. The terms "at least one A or B" or "at least one of A and B" have a similar meaning to "A and / or B" and can include only A, only B, or A and B. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0043] It should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" in this embodiment should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0044] Current mainstream temperature compensation strategies focus on the intelligent design of bias circuits. The most common compensation method is to generate a current source proportional to absolute temperature (PTAT) and inject it into the amplifier's bias network. As the temperature rises, this PTAT current increases accordingly, actively raising the device's quiescent operating point (e.g., the PA's quiescent bias current), thereby offsetting performance degradation caused by high temperatures (e.g., gain reduction), and bringing the amplifier's performance at high temperatures closer to its room-temperature level. Conversely, at low temperatures, the PTAT current decreases, preventing the device from entering the nonlinear region or consuming excessive power due to overly strong performance, thus maintaining stability at low temperatures. This PTAT compensation is the fundamental and widely used method for achieving performance flattening over a wide temperature range.

[0045] However, RF circuit design is complex and diverse, and not all situations can be perfectly solved by a single PTAT compensation. For specific circuit topologies, process characteristics, or special performance requirements, engineers need to design more refined compensation schemes, such as CTAT (Complementary To Absolute Temperature) compensation: generating a current or voltage that decreases with increasing temperature. This compensation method is often used to: 1) compensate for certain temperature-sensitive base reference voltages (such as the negative temperature coefficient of the base-emitter voltage Vbe in a bipolar transistor in a bandgap reference source); 2) when stabilizing specific parameters (such as the transconductance gm of an LNA) or combining it with PTAT to form a zero temperature coefficient (ZTC) bias point; 3) compensate for certain parasitic resistance effects with positive temperature coefficients. In addition, there is ZTAT (Zero Temperature Coefficient) compensation: the goal is to generate a current or voltage that remains almost constant over a target temperature range. This is usually achieved through careful design, combining components or circuit structures with positive temperature coefficients (PTAT) and negative temperature coefficients (CTAT) so that their temperature effects cancel each other out. The ZTAT bias point is particularly important for critical circuit nodes that require extremely high temperature stability (such as high-precision oscillators, ADC / DAC reference sources) or certain RF modules that are extremely sensitive to bias.

[0046] In summary, temperature compensation circuits are an indispensable key module in the design of modern high-performance RF chips (especially PAs and LNAs). Through carefully designed PTAT, CTAT, ZTAT, or combinations thereof, engineers can effectively tame performance drift caused by temperature variations, ensuring that RF chips provide stable, consistent, and predictable performance output under various harsh environmental conditions, laying a solid foundation for the robustness and reliability of the entire communication system.

[0047] Bandgap reference circuits are widely used in integrated circuits, providing a stable current to the bias circuits of various modules on the chip for normal operation. Bandgap reference circuits typically provide a temperature-invariant reference voltage (typically 1.206V) over a relatively wide temperature range (generally -40°C to 150°C). Theoretically, the output voltage of the bandgap reference current is a temperature-invariant value. However, ordinary bandgap reference circuits only cancel out the effects of positive and negative temperatures at a specific temperature. Furthermore, in actual circuits, factors such as resistor mismatches and temperature coefficients, transistor secondary effects, transistor mismatches, and process variations affect the current, resulting in temperature-dependent curvature. Therefore, bandgap reference circuits still require specific temperature compensation circuits to address the curvature caused by temperature variations.

[0048] Conventional temperature compensation circuits in the prior art, such as Figure 1 As shown, it mainly consists of a BandGap circuit (bandgap reference circuit) and a slope adjustment circuit. The BandGap circuit generates the basic IRFE_PTAT (PTAT current), IRFE_CTAT (CTAT current), and IRFE_ZTAT (ZTAT current), and uses a current mirror in the slope adjustment circuit to control the current. Finally, different combinations of PTAT and CTAT currents are used to output IOUT, for example, IOUT = (IREF_PTAT - IREF_ZTAT) × M + (IREF_CTAT - IREF_ZTAT) × N + IREF_ZTAT, thus obtaining currents with different temperature coefficients, such as... Figure 2 As shown.

[0049] In the above schemes and other similar schemes, the slope of the current change with temperature remains constant across the entire temperature range, for example, as... Figure 2 The PTAT current shown increases sequentially from low temperature to high temperature, while its slope remains constant. Figure 2 The CTAT current shown decreases with increasing temperature, while its slope remains constant. This presents limitations in certain applications or circuits. For example, some circuits require higher current at high temperatures and no compensation at room and low temperatures; or higher current at high temperatures, lower current at low temperatures, and no compensation at room temperature. Therefore, conventional temperature compensation circuits cannot achieve segmented temperature control, thus limiting their application. Furthermore, the linear relationship between current and temperature also presents limitations. Some circuits may require greater compensation at higher temperatures, meaning a steeper slope (e.g., exponential compensation), a function that traditional circuit structures cannot achieve.

[0050] like Figure 3 The diagram shows the circuit structure of a novel temperature compensation circuit proposed in this application. It can provide different temperature compensations for low temperature, normal temperature, and high temperature, and can also provide exponential temperature compensation, allowing for greater compensation of bias current at high and low temperatures. This makes the temperature compensation circuit more applicable and suitable for a wider range of applications.

[0051] like Figure 3 As shown, the temperature compensation circuit proposed in this application includes a bandgap circuit, a high-temperature slope control circuit, a low-temperature slope control circuit, and a current adder. The functional configurations of each component in the temperature compensation circuit are as follows:

[0052] The BandGap circuit is used to generate a first set of reference voltage signals (VREF_CTAT and VREF_ZTAT1), a second set of reference voltage signals (VREF_PTAT and VREF_ZTAT2), and a room temperature current. The first set of reference voltage signals is input to the high temperature slope control circuit, the second set of reference voltage signals is input to the low temperature slope control circuit, and the room temperature current is output to the current adder.

[0053] A high-temperature slope control circuit is used to generate a high-temperature current based on the first set of reference voltage signals and output the high-temperature current to the current adder.

[0054] A low-temperature slope control circuit is used to generate a low-temperature current based on the second set of reference voltage signals and output the low-temperature current to the current adder;

[0055] The current adder is used to generate a temperature compensation current based on the input high-temperature current, low-temperature current, and normal-temperature current.

[0056] In this embodiment, the temperature compensation current includes an exponentially decreasing or increasing current corresponding to the low temperature range, and an exponentially increasing or decreasing current corresponding to the high temperature range. The high-temperature slope control circuit and the low-temperature slope control circuit in this embodiment can employ the same circuit structure.

[0057] Figure 3 The temperature compensation circuit shown works as follows: A BandGap circuit generates two sets of reference voltage signals. One set includes VREF_CTAT and VREF_ZTAT1, used for high-temperature slope control; the other set includes VREF_PTAT and VREF_ZTAT2, used for low-temperature slope control. Then, independently controllable high-temperature current IREF_HT and low-temperature current IREF_LT are generated through high-temperature and low-temperature slope control, respectively. Finally, a current adder generates the temperature compensation current IOUT. It should be understood that VREF_CTAT is a reference voltage that decreases with increasing temperature, VREF_PTAT is a reference voltage that increases with increasing temperature, and VREF_ZTAT1 and VREF_ZTAT2 are reference voltages that remain constant with temperature changes.

[0058] like Figure 4 The following is based on Figure 3The diagram shows the curve of the temperature compensation current output by the circuit as a function of temperature. It can be seen from the figure that the slope of the IOUT curve as a function of temperature can be controlled independently in both high-temperature and low-temperature ranges, and the curves of IOUT as a function of temperature are all exponential curves. For example, in practical applications, independent control at high temperatures can be achieved based on SPI CTR1 and SPICTR2, and independent control at low temperatures can be achieved based on SPICTR3 and SPICTR4. In this embodiment, SPICTR1, SPI CTR2, SPI CTR3, and SPI CTR4 can be understood as serial control ports that control the IOUT output by the temperature compensation circuit. By configuring each serial control port of SPI CTR1, SPI CTR2, SPI CTR3, and SPI CTR4 with different bit values, the selection of IOUT with different slopes for different temperature ranges can be achieved.

[0059] In one specific implementation, Figure 3 The BandGap circuit shown can mainly include a voltage generation circuit and a current generation circuit; the voltage generation circuit is used to generate a first zero temperature coefficient voltage, a second zero temperature coefficient voltage, a positive temperature coefficient voltage, and a negative temperature coefficient voltage, and the current generation circuit is used to generate a room temperature current, or it can also be called a isothermal current. Figure 3 Correspondingly, the first set of reference voltage signals includes the positive temperature coefficient voltage and the first zero temperature coefficient voltage generated by the BandGap circuit; the second set of reference voltage signals includes the negative temperature coefficient voltage and the second zero temperature coefficient voltage generated by the BandGap circuit.

[0060] Furthermore, such as Figure 5 The diagram shown is a schematic diagram of a specific circuit structure of a bandgap reference circuit provided in an embodiment of this application, wherein:

[0061] The voltage generation circuit 101 includes a first MOSFET PM0, a second MOSFET PM1, a third MOSFET PM2, a fourth MOSFET PM3, a first transistor Q1, a second transistor Q2, a third transistor Q3, a first operational amplifier AMP1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The bases and collectors of the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all connected to ground (GND). The emitter of the first transistor Q1 is connected to the drain of the first MOSFET PM0 and the first input terminal of the first operational amplifier AMP1. The emitter of the second transistor Q2 is connected to the drain of the second MOSFET PM1 and the first input terminal of the first operational amplifier AMP1 via the first resistor R1. The second input terminal of the transport amplifier AMP1 is connected to the gates of the first MOSFET PM2 and the second MOSFET PM1. The emitter of the third transistor Q3 is connected to the drain of the third MOSFET PM2 via the second resistor R2 and the third resistor R3. The drain of the fourth MOSFET PM3 is connected to ground GND via the fourth resistor R4. The gates of the third MOSFET PM2 and the fourth MOSFET PM3 are both connected to the gates of the first MOSFET PM0 and the second MOSFET PM1. The sources of the first MOSFET PM0, the second MOSFET PM1, the third MOSFET PM2, and the fourth MOSFET PM3 are all connected to the power supply terminal VDD.

[0062] In this embodiment, the connection node between the emitter of the first transistor Q1 and the drain of the first MOSFET PM0 serves as the output terminal for generating the negative temperature coefficient voltage VREF_CTAT; the connection node between the fourth resistor R4 and the drain of the fourth MOSFET PM3 serves as the output terminal for generating the positive temperature coefficient voltage VREF_PTAT; the connection node between the third resistor R3 and the drain of the third MOSFET PM2 serves as the output terminal for generating the first zero temperature coefficient voltage VREF_ZTAT1; and the connection node between the second resistor R2 and the third resistor R3 serves as the output terminal for generating the second zero temperature coefficient voltage VREF_ZTAT2.

[0063] The current generation circuit 102 includes a second operational amplifier AMP2, a fifth MOSFET PM4, a sixth MOSFET PM5, a fifth resistor R5, and a sixth resistor R6. The first input terminal of the second operational amplifier AMP2 is connected to the output terminal that generates the first zero temperature coefficient voltage VREF_ZTAT1. The second input terminal of the second operational amplifier AMP2 is connected to the connection node of the fifth resistor R5 and the sixth resistor R6. The output terminal of the second operational amplifier AMP2 is connected to the gate of the fifth MOSFET PM4 and the sixth MOSFET PM5. The sources of the fifth MOSFET PM4 and the sixth MOSFET PM5 are both connected to the power supply terminal VDD. The drain of the fifth MOSFET PM4 is grounded to GND through the series connection of the sixth resistor R6 and the fifth resistor R5.

[0064] In this embodiment, the drain of the sixth MOS transistor PM5 serves as the output terminal for generating the room temperature current IREF.

[0065] In one specific implementation, Figure 3 The high-temperature slope control circuit or low-temperature slope control circuit shown may mainly include a reference current generation module, an exponential current generation module, and a current mirror module. The output of the reference current generation module is connected to the input of the exponential current generation module, and the output of the exponential current generation module is connected to the current mirror module.

[0066] Furthermore, such as Figure 6 The diagram shown is a schematic diagram of a high / low temperature slope control circuit provided in an embodiment of this application. The circuit structure includes a reference current generation module 201, an exponential current generation module 202, and a current mirror module 203, wherein:

[0067] The reference current generation module 201 includes a first transistor Mp1 and a second transistor Mp2, wherein Mp1 is mainly used to provide a reference current IREF. The gate of the first transistor Mp1 is connected to a first constant bias voltage VB1, the source of the first transistor is connected to the power supply terminal VDD, the drain of the first transistor Mp1 is connected to the source of the second transistor Mp2, the gate of the second transistor Mp2 is connected to a second constant bias voltage VB2, and the drain of the second transistor Mp2 is connected to the input of the exponential current generation module. Preferably, both the first transistor Mp1 and the second transistor Mp2 are PMOS transistors.

[0068] The exponential current generating module 202 includes a third transistor Mp3, a fourth transistor Mp4, a fifth transistor Mn1, a sixth transistor Mn2, a seventh transistor Mn3, and an eighth transistor Mn4. The sources of the third transistor Mp3 and the fourth transistor Mp4 are both connected to the drain of the second transistor Mp2. The drains of the third transistor Mp3 and the fourth transistor Mp4 are respectively connected to the drains of the fifth transistor Mn1 and the sixth transistor Mn2. The drains of the third transistor Mp3 and the fourth transistor Mp4 are also respectively connected to the gates of the seventh transistor Mn3 and the eighth transistor Mn4. The sources of the fifth transistor Mn1 and the sixth transistor Mn2 are respectively connected to the drains of the seventh transistor Mn3 and the eighth transistor Mn4. The sources of the seventh transistor Mn3 and the eighth transistor Mn4 are both grounded (GND). The gates of the third transistor Mp3 and the fourth transistor Mp4 are connected to either the first set of reference voltage signals or the second set of reference voltage signals. For example, when this circuit structure is applied to a high-temperature slope control circuit, the gate of the third transistor Mp3 is connected to VREF_CTAT and the gate of the fourth transistor Mp4 is connected to VREF_ZTAT1. When this circuit structure is applied to a low-temperature slope control circuit, the gate of the third transistor Mp3 is connected to VREF_PTAT and the gate of the fourth transistor Mp4 is connected to VREF_ZTAT2. Preferably, the third transistor Mp3 and the fourth transistor Mp4 are both PMOS transistors, and the fifth transistor Mn1, the sixth transistor Mn2, the seventh transistor Mn3, and the eighth transistor Mn4 are all NMOS transistors.

[0069] Further, in this embodiment, the current mirror module 203 includes a bias unit 2031, a first current mirror unit 2032, and a second current mirror unit 2033. The first current mirror unit 2032 is used to output a forward current I_Source, and the second current mirror unit 2033 is used to output a reverse current I_Sink. The forward current is superimposed on the reverse current to form the high-temperature current or the low-temperature current. For example, the high-temperature current IREF_HT output by the high-temperature slope control circuit is I_Source1 + I_Sink1, and the low-temperature current IREF_LT generated by the low-temperature slope control circuit is I_Source2 + I_Sink2, then IOUT = IREF_HT + IREF_LT + IREF.

[0070] The bias unit 2031 includes a ninth transistor Mp5, a tenth transistor Mp6, an eleventh transistor Mn5, and a twelfth transistor Mn5; the first current mirror unit 2032 includes multiple current mirrors. For example, as shown in the figure, the first current mirror unit includes current mirror ×1, current mirror ×2, current mirror ×4, ... composed of PMOS transistors; the second current mirror unit includes multiple current mirrors. For example, as shown in the figure, the second current mirror unit includes current mirror ×1, current mirror ×2, current mirror ×4, ... composed of NMOS transistors. The gates of the ninth transistor Mp5 and the tenth transistor Mp6 are respectively connected to the gates of the first transistor Mp1 and the second transistor Mp2. The gates of the ninth transistor Mp5 and the tenth transistor Mp6 are also connected to the input terminals of multiple PMOS current mirrors in the first current mirror unit. The output terminals of the multiple PMOS current mirrors are used to output the forward current I_Source. The gates of the eleventh transistor Mn5 and the twelfth transistor Mn6 are respectively connected to the gates of the fifth transistor Mn1 and the sixth transistor Mn2. The gates of the eleventh transistor Mn5 and the twelfth transistor Mn6 are also connected to the input terminals of multiple NMOS current mirrors in the second current mirror unit. The output terminals of the multiple NMOS current mirrors are used to output the reverse current I_Sink.

[0071] In this embodiment, based on Figure 6 The high / low temperature slope control circuit shown utilizes the temperature characteristics of the input voltage to control the current of differential pairs Mp3 and Mp4, thereby causing Mp3 to generate a temperature-dependent exponential current I_exp. Finally, a current mirror is used to replicate and invert I_exp, thus achieving independent control of the high and low temperature currents. Specifically, the first transistor Mp1 provides the reference current IREF, the input to the third transistor Mp3 is a temperature-varying voltage, and the input to the fourth transistor Mp4 is a constant-temperature reference voltage. During normal operation, Mp3 and Mp4 should be biased in the subthreshold region, so that the current they generate increases exponentially with the control voltage.

[0072] like Figure 7The diagram illustrates the principle of generating a high-temperature current IREF_HT based on the aforementioned high-temperature slope control circuit. The input voltages to Mp3 and Mp4 are VREF_CTAT, a voltage that decreases with increasing temperature, and VREF_ZTAT1, a constant-temperature voltage, respectively. At low temperatures, since the gate voltage of Mp4 is higher than that of Mp3, Mp3 is turned off, its current I_exp = 0, and I_4 = IREF. At this time, all the current flows through Mp4. As the temperature rises, Mp3 gradually turns on, and its current begins to increase exponentially. When the temperature rises to a certain level, I_exp reaches its maximum value IREF. Since the current of Mp3 is equal to the current of Mn3, the current of Mn3 is also temperature-dependent and increases exponentially. By replicating I_exp for this current, the magnitude and direction of the current can be controlled.

[0073] Similarly, such as Figure 8 The diagram shows the principle of generating the low-temperature current IREF_LT based on the aforementioned low-temperature slope control circuit. The voltages input to Mp3 and Mp4 are VREF_PTAT, which increases with temperature, and VREF_ZTAT2, a constant-temperature voltage, respectively. The intersection of the two input voltages is at low temperature. Therefore, at low temperatures, Mp3 is turned on, and its current I_exp decreases exponentially. At high temperatures, Mp3 is turned off, and its current I_exp drops to 0.

[0074] It should be understood that, Figure 7 and Figure 8 The diagram illustrates, only as an example, the control of the output of a positive high-temperature current or a low-temperature current. If the output of a negative high-temperature current or a low-temperature current is simultaneously controlled, then combining the output currents IREF_HT and IREF_LT of the high / low temperature slope control module with the reference current IREF yields the final current output IOUT of this invention, i.e., as shown below. Figure 4 The output effect shown demonstrates that the high and low temperature portions of the output current can be independently controlled via SPI, thereby enabling any combination of temperature compensation curves to meet the temperature compensation requirements of most circuits.

[0075] Furthermore, embodiments of this application also provide an radio frequency chip, including the temperature compensation circuit described in any of the above technical solutions.

[0076] It should be understood that since the various modules are only provided to illustrate the functional units of the circuits or devices described in this application, the physical devices corresponding to these modules may be one or more, and may be part of the software, part of the hardware, or a combination of software and hardware. Therefore, the number of modules shown in the figures is merely illustrative.

[0077] Those skilled in the art will understand that the various modules in the device can be adaptively split or merged. Such splitting or merging of specific modules will not cause the technical solution to deviate from the principles of this application; therefore, the technical solutions after splitting or merging will fall within the protection scope of this application.

[0078] The technical solutions of this application have been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A temperature compensation circuit, characterized in that, include: Bandgap reference circuit, high-temperature slope control circuit, low-temperature slope control circuit, and current adder; The bandgap reference circuit is used to generate a first set of reference voltage signals, a second set of reference voltage signals, and a room temperature current, and inputs the first set of reference voltage signals to the high temperature slope control circuit, inputs the second set of reference voltage signals to the low temperature slope control circuit, and outputs the room temperature current to the current adder. The high-temperature slope control circuit is used to generate a high-temperature current based on the first set of reference voltage signals and output the high-temperature current to the current adder. The low-temperature slope control circuit is used to generate a low-temperature current based on the second set of reference voltage signals and output the low-temperature current to the current adder. The current adder is used to generate a temperature compensation current based on the input high-temperature current, low-temperature current, and normal-temperature current.

2. The temperature compensation circuit according to claim 1, characterized in that, The temperature compensation current includes an exponentially decreasing or increasing current corresponding to the low temperature range, and an exponentially increasing or decreasing current corresponding to the high temperature range.

3. The temperature compensation circuit according to claim 1, characterized in that, The bandgap reference circuit includes a voltage generation circuit and a current generation circuit; the voltage generation circuit is used to generate a first zero temperature coefficient voltage, a second zero temperature coefficient voltage, a positive temperature coefficient voltage, and a negative temperature coefficient voltage, and the current generation circuit is used to generate a room temperature current. The first set of reference voltage signals includes the positive temperature coefficient voltage and the first zero temperature coefficient voltage; the second set of reference voltage signals includes the negative temperature coefficient voltage and the second zero temperature coefficient voltage.

4. The temperature compensation circuit according to claim 3, characterized in that, The voltage generation circuit includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a first transistor, a second transistor, a third transistor, a first operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor; The bases and collectors of the first, second, and third transistors are all connected to ground. The emitter of the first transistor is connected to the drain of the first MOSFET and the first input terminal of the first transport amplifier. The emitter of the second transistor is connected to the drain of the second MOSFET and the second input terminal of the first transport amplifier via the first resistor. The output terminal of the first transport amplifier is connected to the gates of the first and second MOSFETs. The emitter of the third transistor is connected to the drain of the third MOSFET via the second and third resistors. The drain of the fourth MOSFET is grounded via the fourth resistor. The gates of the third and fourth MOSFETs are both connected to the gates of the first and second MOSFETs. The sources of the first, second, third, and fourth MOSFETs are all connected to a power supply terminal. Wherein, the connection node between the emitter of the first transistor and the drain of the first MOS transistor serves as the output terminal for generating the negative temperature coefficient voltage, the connection node between the fourth resistor and the drain of the fourth MOS transistor serves as the output terminal for generating the positive temperature coefficient voltage, the connection node between the third resistor and the drain of the third MOS transistor serves as the output terminal for generating the first zero temperature coefficient voltage, and the connection node between the second resistor and the third resistor serves as the output terminal for generating the second zero temperature coefficient voltage.

5. The temperature compensation circuit according to claim 4, characterized in that, The current generation circuit includes a second operational amplifier, a fifth MOSFET, a sixth MOSFET, a fifth resistor, and a sixth resistor; The first input terminal of the second operational amplifier is connected to the output terminal that generates the first zero temperature coefficient voltage. The second input terminal of the second operational amplifier is connected to the connection node of the fifth resistor and the sixth resistor. The output terminal of the second operational amplifier is connected to the gate of the fifth MOS transistor and the sixth MOS transistor. The sources of the fifth MOS transistor and the sixth MOS transistor are both connected to the power supply terminal. The drain of the fifth MOS transistor is grounded through the sixth resistor and the fifth resistor connected in series. The drain of the sixth MOS transistor serves as the output terminal for generating the room temperature current.

6. The temperature compensation circuit according to claim 1, characterized in that, The high-temperature slope control circuit and / or the low-temperature slope control circuit include a reference current generation module, an exponential current generation module, and a current mirror module. The output of the reference current generation module is connected to the input of the exponential current generation module, and the output of the exponential current generation module is connected to the current mirror module. The current mirror module includes a bias unit, a first current mirror unit, and a second current mirror unit. The first current mirror unit is used to output a forward current, and the second current mirror unit is used to output a reverse current. The forward current is superimposed on the reverse current to form the high-temperature current or the low-temperature current.

7. The temperature compensation circuit according to claim 6, characterized in that, The reference current generation module includes a first transistor and a second transistor; The gate of the first transistor is connected to a first constant bias voltage, the source of the first transistor is connected to a power supply terminal, the drain of the first transistor is connected to the source of the second transistor, the gate of the second transistor is connected to a second constant bias voltage, and the drain of the second transistor is connected to the input of the exponential current generation module.

8. The temperature compensation circuit according to claim 7, characterized in that, The exponential current generating module includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The sources of the third and fourth transistors are both connected to the drain of the second transistor. The drains of the third and fourth transistors are respectively connected to the drains of the fifth and sixth transistors. The drains of the third and fourth transistors are also respectively connected to the gates of the seventh and eighth transistors. The sources of the fifth and sixth transistors are respectively connected to the drains of the seventh and eighth transistors. The sources of the seventh and eighth transistors are both grounded. The gates of the third transistor and the fourth transistor are connected to either the first set of reference voltage signals or the second set of reference voltage signals.

9. The temperature compensation circuit according to claim 8, characterized in that, The bias unit includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; both the first current mirror unit and the second current mirror unit include multiple current mirrors. The gates of the ninth transistor and the tenth transistor are respectively connected to the gates of the first transistor and the second transistor. The gates of the ninth transistor and the tenth transistor are also connected to the input terminals of multiple current mirrors in the first current mirror unit. The output terminals of the multiple current mirrors in the first current mirror unit are used to output the positive current. The gates of the eleventh transistor and the twelfth transistor are respectively connected to the gates of the fifth transistor and the sixth transistor. The gates of the eleventh transistor and the twelfth transistor are also connected to the input terminals of multiple current mirrors in the second current mirror unit. The output terminals of the multiple current mirrors in the second current mirror unit are used to output the reverse current.

10. A radio frequency chip, characterized in that, Includes the temperature compensation circuit described in any one of claims 1-9.

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