A four-loop on-chip integrated low-dropout linear regulator

Abstract

The application provides a four-loop on-chip integrated low-dropout linear voltage regulator, comprising an error amplifier configured to compare a reference voltage with an output voltage to provide a control signal; a common-source common-gate flip voltage follower configured to compare the control signal with the output voltage to generate a first regulating signal; a double-loop Class-AB error amplifier configured to compare the reference voltage with the output voltage to generate a second regulating signal; and a power tube; the power tube jointly regulates an output driving current based on the first regulating signal and the second regulating signal to output the output voltage through the voltage output terminal; and a biasing module configured to provide a biasing voltage for the double-loop Class-AB error amplifier, the error amplifier and the common-source common-gate flip voltage follower. The transient response performance of the voltage regulator can be improved without a large off-chip capacitor.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and particularly relates to a four-loop on-chip integrated low dropout linear regulator. BACKGROUND

[0002] With the rapid development of science and technology, portable electronic devices play an increasingly important role in people's daily life and work. From smartphones, wearable devices to Internet of Things terminals, these devices not only have higher requirements for functional diversity, but also bring unprecedented challenges to the performance of power management systems.

[0003] As a key component in modern power management systems, low dropout linear regulators (LDOs) are widely used in various miniaturized electronic devices. They have the advantages of low noise, high output accuracy, simple structure and easy integration, and are therefore favored in scenarios with high requirements for power stability and energy efficiency. However, traditional LDO design usually relies on external large-capacity capacitors to maintain output voltage stability, especially in the case of rapid load current changes, this dependence is more obvious. This feature not only increases the space occupation of the circuit board, but also increases the overall system cost, and may affect the response speed, making it difficult to meet the current demand for lightweight and high integration of portable devices.

[0004] However, existing on-chip integrated LDOs have insufficient transient response performance, which also limits the application of the device in high dynamic load application scenarios. SUMMARY

[0005] In view of the problems existing in the prior art, the present application provides a four-loop on-chip integrated low dropout linear regulator, which mainly solves the problems of large space occupation and insufficient transient response performance of the low dropout linear regulator in the related art.

[0006] In order to achieve the above-mentioned purposes and other purposes, the technical solutions adopted by the present application are as follows.

[0007] The application provides a four-loop on-chip integrated low-dropout linear regulator, which comprises: an error amplifier for comparing a reference voltage with an output voltage to provide a control signal; a common-source common-gate type flip voltage follower for comparing the control signal with the output voltage to generate a first regulating signal; a double-loop Class-AB error amplifier for comparing the reference voltage with the output voltage to generate a second regulating signal; a power tube with a gate connected to the first regulating signal and the second regulating signal, a source connected to a power supply voltage and a drain as a voltage output terminal; the power tube jointly adjusts an output driving current based on the first regulating signal and the second regulating signal to output the output voltage through the voltage output terminal, so that the response time of the circuit is shortened and the output voltage fluctuation when the load is switched is reduced; and a biasing module for providing biasing voltages for the double-loop Class-AB error amplifier, the error amplifier and the common-source common-gate type flip voltage follower.

[0008] In an embodiment of the application, the biasing module comprises: a current source, a first biasing transistor, a second biasing transistor and a third biasing transistor; the input terminal of the current source is connected to a power supply voltage, and the output terminal is connected to the drain of the first biasing transistor; the gate and the drain of the first biasing transistor are short-circuited and connected to the gate of the second biasing transistor to serve as an output node of a first biasing voltage; the source of the first biasing transistor and the source of the second biasing transistor are connected to ground; the drain of the second biasing transistor is connected to the drain of the third biasing transistor; the gate and the drain of the third biasing transistor are connected to serve as an output node of a second biasing voltage; and the source of the third biasing transistor is connected to the power supply voltage.

[0009] In an embodiment of the application, the double-loop Class-AB error amplifier comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor and a twenty-second transistor.

[0010] The source of the first transistor, the source of the second transistor, the source of the seventh transistor, the source of the eighth transistor, the source of the ninth transistor, the source of the tenth transistor, the source of the eleventh transistor, the source of the twelfth transistor, the source of the nineteenth transistor and the source of the twentieth transistor are grounded respectively; the source of the fifteenth transistor, the source of the sixteenth transistor, the source of the seventeenth transistor, the source of the eighteenth transistor, the source of the twenty-first transistor and the source of the twenty-second transistor are connected to the power supply voltage respectively; the gate of the first transistor, the gate of the second transistor, the gate of the eleventh transistor and the gate of the twelfth transistor are connected to the first bias voltage respectively; the drain of the first transistor is connected to the drain of the third transistor; the drain of the second transistor is connected to the drain of the fourth transistor; the gate and the drain of the third transistor are shorted and connected to the gate of the fifth transistor; the source of the third transistor is connected to the source of the sixth transistor, the source of the thirteenth transistor and the drain of the fifteenth transistor respectively; the drain and the gate of the fourth transistor are shorted and connected to the gate of the fifth transistor; the source of the fourth transistor is connected to the source of the fifth transistor, the source of the fourteenth transistor and the drain of the sixteenth transistor respectively; the drain of the fifth transistor is connected to the drain of the seventh transistor; the drain of the sixth transistor is connected to the drain of the eighth transistor; the gate and the drain of the seventh transistor are shorted and connected to the gate of the ninth transistor; the gate and the drain of the eighth transistor are shorted and connected to the gate of the tenth transistor; the drain of the ninth transistor is connected to the drain of the seventeenth transistor, the drain of the nineteenth transistor and the drain of the twenty-first transistor respectively, serving as the output terminal of the double-loop Class-AB error amplifier; the drain of the tenth transistor is connected to the drain of the twenty-second transistor; the gate and the drain of the twenty-second transistor are shorted and connected to the gate of the twenty-first transistor; the drain of the eleventh transistor is connected to the drain of the thirteenth transistor, the gate of the fifteenth transistor and the gate of the seventeenth transistor respectively; the gate of the thirteenth transistor serves as the non-inverting input terminal of the double-loop Class-AB error amplifier and is connected to the output voltage; the drain of the twelfth transistor is connected to the drain of the fourteenth transistor, the gate of the sixteenth transistor and the gate of the eighteenth transistor respectively; the gate of the fourteenth transistor serves as the inverting input terminal of the double-loop Class-AB error amplifier and is connected to the reference voltage; the drain of the eighteenth transistor is connected to the drain of the twentieth transistor, the gate of the twentieth transistor and the gate of the nineteenth transistor respectively.

[0011] In an embodiment of the present application, the common-source common-gate type flip voltage follower comprises a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor and a twenty-sixth transistor.

[0012] The source of the twenty-third transistor is connected to ground, the gate is connected to the second bias voltage, the drain is connected to the drain of the twenty-fourth transistor as the output terminal of the common-source common-gate type flip voltage follower and is connected to the output terminal of the double-loop Class-AB error amplifier; the gate of the twenty-fourth transistor is connected to the reference voltage, the source is connected to the drain of the twenty-fifth transistor and the drain of the twenty-sixth transistor respectively; the source of the twenty-fifth transistor is connected to the positive input terminal of the double-loop Class-AB error amplifier as the non-inverting input terminal of the common-source common-gate type flip voltage follower and is connected to the output voltage; the gate of the twenty-fifth transistor is connected to the output terminal of the error amplifier as the inverting input terminal of the common-source common-gate type flip voltage follower; the gate of the twenty-sixth transistor is connected to the first bias voltage, and the source is connected to ground.

[0013] In an embodiment of the present application, the error amplifier comprises a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor and a thirty-first transistor.

[0014] The source of the twenty-seventh transistor is connected to ground, the gate is connected to the first bias voltage, and the drain is connected to the source of the twenty-eighth transistor and the source of the twenty-ninth transistor respectively; the gate of the twenty-eighth transistor is connected to the positive input terminal of the double-loop Class-AB error amplifier as the inverting input terminal of the error amplifier and is connected to the output voltage; the drain of the twenty-eighth transistor is connected to the drain of the thirtieth transistor as the output terminal of the error amplifier; the source of the thirtieth transistor and the source of the thirty-first transistor are connected to the power supply voltage, the gate of the thirtieth transistor is connected to the gate of the thirty-first transistor, the drain of the thirty-first transistor and the drain of the twenty-ninth transistor respectively; the gate of the twenty-ninth transistor is connected to the reference voltage.

[0015] In an embodiment of the present application, the output terminal of the low-dropout linear regulator further comprises a frequency compensation module, which is arranged between the gate and the drain of the power transistor to provide frequency compensation so that the circuit remains stable.

[0016] In an embodiment of the present application, the frequency compensation module comprises a compensation capacitor, one end of which is connected to the gate of the power transistor and the other end of which is connected to the drain of the power transistor.

[0017] In an embodiment of the present application, the output end of the low-dropout linear voltage regulator further comprises a bandgap reference module for providing the reference voltage.

[0018] As described above, the four-loop on-chip integrated low-dropout linear voltage regulator has the following beneficial effects.

[0019] The biasing module provides biasing voltage for some transistors in the common-source common-gate inverting voltage follower, the double-loop Class-AB error amplifier and the error amplifier; the bandgap reference provides reference voltage VREF for some transistors in the common-source common-gate inverting voltage follower, the error amplifier and the double-loop Class-AB error amplifier; the frequency compensation module is connected to the output end of the four-loop on-chip integrated LDO and the gate of the power transistor MP, ensuring the stability of the entire voltage regulator circuit system; the error amplifier compares the reference voltage VREF and the output voltage VOUT and amplifies the generated error signal, providing a control signal for the subsequent common-source common-gate inverting voltage follower; the common-source common-gate inverting voltage follower compares the control signal and the output voltage, while the double-loop Class-AB error amplifier compares the reference voltage VREF and the output voltage, together providing an adjustment signal for the gate of the subsequent power transistor, adjusting the output drive current of the power transistor, so as to shorten the loop response time and reduce the output voltage fluctuation when the load is switched; based on the double-loop Class-AB error amplifier and the common-source common-gate inverting voltage follower, the gate of the power transistor is quickly charged and discharged, improving the transient response performance of the voltage regulator under the condition of no large off-chip capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 FIG. 1 is a schematic diagram of the overall architecture of the four-loop on-chip integrated low-dropout linear voltage regulator in an embodiment of the present application;

[0021] Figure 2 FIG. 2 is a circuit schematic diagram of the four-loop on-chip integrated low-dropout linear voltage regulator in an embodiment of the present application;

[0022] Figure 3 FIG. 3 is a schematic diagram of the LDO transient response adjustment mechanism in an embodiment of the present application;

[0023] Figure 4 FIG. 4 is a transient response curve diagram of the four-loop on-chip integrated low-dropout linear voltage regulator in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The present application is herein described, by way of example only, with the comprehension that the advantages and utility thereof are not confined to the specific embodiments hereinafter described, but extend to all of the embodiments falling within the scope of the present application. The present application can be implemented or applied in other different embodiments, and the details of the present application can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0025] It should be noted that the diagrams provided in the following examples only illustrate the basic concept of the present application in a schematic manner, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component can be arbitrarily changed in terms of shape, number and proportion, and the layout pattern of the components can be more complex.

[0026] The inventors have found that:

[0027] System on Chip (SoC) is a highly integrated microelectronic device that integrates multiple functional modules on a single chip, greatly improving the performance and efficiency of the system. For power management, transient response performance is an important indicator of the ability of a linear regulator to maintain stable output voltage when the load current changes. Good transient response means that the regulator can quickly and effectively respond to load changes, ensuring the stability and reliability of the system. This performance is usually affected by factors such as circuit bandwidth, feedback loop design, and internal compensation mechanism.

[0028] With the rapid development of technology, portable electronic devices have become an indispensable part of our daily life and work. From smartphones to wearable devices, these devices not only require more functional diversity, but also pose unprecedented challenges to power management systems. In order to meet the demand for stable and reliable power supply for portable devices, a variety of power supply solutions have emerged in the market, greatly enriching the electronic product ecosystem.

[0029] Low Dropout Regulator (LDO) is a highly efficient and stable voltage regulator widely used in small electronic devices. Its excellent noise suppression capability, compact design and easy integration make it the first choice for many applications. However, traditional LDO design usually relies on large external capacitors to ensure the stability of the output voltage, especially in the case of rapid load current changes. This dependence on large external capacitors leads to increased space occupation, increased cost and slower response speed, posing a major challenge to modern electronic devices that pursue thin and light design.

[0030] To address these issues, on-chip integrated LDOs have emerged. By optimizing circuit structures, on-chip integrated LDOs reduce the need for large external capacitors, enabling more compact and economical designs. Despite these advances in reducing component count, on-chip integrated LDOs still exhibit poor transient response performance, limiting their application scope in high dynamic load conditions.

[0031] Therefore, how to design a low-dropout linear regulator that can both reduce energy consumption and enhance transient response performance has become a key issue that needs to be addressed in the current technical field. The ideal solution not only overcomes the spatial limitations and cost challenges of traditional LDOs, but also finds the best balance between transient response, power consumption, and system stability. Through innovative circuit design and technical optimization, more efficient and energy-saving power management solutions can be achieved to meet the growing demand for high-performance power supplies in modern portable electronic devices.

[0032] Based on the problems existing in the above related technologies, the present application proposes a four-loop on-chip integrated low-dropout linear regulator. The technical solutions of the present application will be described in detail below in conjunction with specific embodiments.

[0033] Please refer to Figure 1 , Figure 1 The figure is a schematic diagram of the overall architecture of the four-loop on-chip integrated low-dropout linear regulator in an embodiment of the present application. The low-dropout linear regulator provided in the embodiment of the present application includes: an error amplifier for comparing a reference voltage with an output voltage to provide a control signal; a common-source common-gate inverting voltage follower for comparing the control signal with the output voltage to generate a first adjustment signal; a double-loop Class-AB error amplifier for comparing the reference voltage with the output voltage to generate a second adjustment signal; a power tube with its gate connected to the first adjustment signal and the second adjustment signal, its source connected to a power supply voltage, and its drain as a voltage output terminal; the power tube adjusts the output drive current based on the first adjustment signal and the second adjustment signal to output the output voltage through the voltage output terminal, so that the circuit response time is shortened and the output voltage fluctuation when the load is switched is reduced; a biasing module for providing bias voltages for the double-loop Class-AB error amplifier, the error amplifier, and the common-source common-gate inverting voltage follower. Through the double-loop Class-AB error amplifier and the common-source common-gate inverting voltage follower acting on the gate of the power tube, fast charging and discharging at the gate of the power tube can improve the transient response performance of the regulator without a large external capacitor. Through the biasing module, the common-source common-gate inverting voltage follower, the double-loop Class-AB error amplifier, the error amplifier, and the power tube MP, the LDO has a local fast loop and a push-pull structure at the gate of the power tube MP, thereby having good transient response performance.

[0034] Please see Figure 2 , Figure 2 This is a circuit schematic of a four-loop on-chip integrated low-dropout linear regulator according to an embodiment of this application. The bias module includes: a current source, a first bias transistor, a second bias transistor, and a third bias transistor; the input terminal of the current source is connected to the power supply voltage, and the output terminal is connected to the drain of the first bias transistor; the gate and drain of the first bias transistor are shorted and connected to the gate of the second bias transistor to serve as the output node of the first bias voltage; the sources of the first and second bias transistors are grounded; the drain of the second bias transistor is connected to the drain of the third bias transistor; the gate and drain of the third bias transistor are connected to serve as the output node of the second bias voltage; the source of the third bias transistor is connected to the power supply voltage. Specifically, the current source in the bias module provides a reference current I. bias In the first bias transistor M B1 The gate generates a first bias voltage V bias1 The second bias voltage V is generated at the gate of the third bias transistor MB3. bias2 The first bias voltage V is provided to the gates of the first transistor M1, the second transistor M2, the eleventh transistor M11, the twelfth transistor M12 in the dual-ring Class-AB error amplifier, the twenty-sixth transistor M26 in the cascode flip-flop voltage follower, and the twenty-seventh transistor M27 in the error amplifier, respectively. bias1 A second bias voltage V is provided to the gate of the twenty-third transistor M23 in the cascode flip-flop voltage follower. bias2 The specific magnitudes of the first and second bias voltages should be selected and adjusted according to actual application requirements; no restrictions are imposed here.

[0035] Please see Figure 2In an embodiment, the double-loop Class-AB error amplifier comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a twenty-second transistor; the source of the first transistor, the source of the second transistor, the source of the seventh transistor, the source of the eighth transistor, the source of the ninth transistor, the source of the tenth transistor, the source of the eleventh transistor, the source of the twelfth transistor, the source of the nineteenth transistor, and the source of the twentieth transistor are grounded; the source of the fifteenth transistor, the source of the sixteenth transistor, the source of the seventeenth transistor, the source of the eighteenth transistor, the source of the twenty-first transistor, and the source of the twenty-second transistor are connected to a power supply voltage; the gate of the first transistor, the gate of the second transistor, the gate of the eleventh transistor, and the gate of the twelfth transistor are connected to a first bias voltage; the drain of the first transistor is connected to the drain of the third transistor; the drain of the second transistor is connected to the drain of the fourth transistor; the gate and the drain of the third transistor are shorted and connected to the gate of the fifth transistor; the source of the third transistor is connected to the source of the sixth transistor, the source of the thirteenth transistor, and the drain of the fifteenth transistor; the drain and the gate of the fourth transistor are shorted and connected to the gate of the fifth transistor; the source of the fourth transistor is connected to the source of the fifth transistor, the source of the fourteenth transistor, and the drain of the sixteenth transistor; the drain of the fifth transistor is connected to the drain of the seventh transistor; the drain of the sixth transistor is connected to the drain of the eighth transistor; the gate and the drain of the seventh transistor are shorted and connected to the gate of the ninth transistor; the gate and the drain of the eighth transistor are shorted and connected to the gate of the tenth transistor; the drain of the ninth transistor is connected to the drain of the seventeenth transistor, the drain of the nineteenth transistor, and the drain of the twenty-first transistor as the output of the double-loop Class-AB error amplifier; the drain of the tenth transistor is connected to the drain of the twenty-second transistor; the gate and the drain of the twenty-second transistor are shorted and connected to the gate of the twenty-first transistor; the drain of the eleventh transistor is connected to the drain of the thirteenth transistor, the gate of the fifteenth transistor, and the gate of the seventeenth transistor; the gate of the thirteenth transistor is connected to an output voltage as the non-inverting input of the double-loop Class-AB error amplifier; the drain of the twelfth transistor is connected to the drain of the fourteenth transistor, the gate of the sixteenth transistor, and the gate of the eighteenth transistor; the gate of the fourteenth transistor is connected to a reference voltage as the inverting input of the double-loop Class-AB error amplifier; the drain of the eighteenth transistor is connected to the drain of the twentieth transistor, the gate of the twentieth transistor, and the gate of the nineteenth transistor. Specifically, please refer to Figure 3 , Figure 3Figure 1 is a schematic diagram of a mechanism for regulating transient response of an LDO according to an embodiment of the present application. A loop formed based on a double-loop Class-AB error amplifier includes a first loop and a second loop. The first loop passes through, in sequence, a drain of a power transistor MP, a gate of a thirteenth transistor, a source of the thirteenth transistor, a source of a sixth transistor, a drain of the sixth transistor, a gate of a tenth transistor, a drain of the tenth transistor, a gate of a twenty-first transistor, a drain of the twenty-first transistor, and a gate of the power transistor MP. The second loop passes through, in sequence, a drain of the power transistor, a gate of the thirteenth transistor, a drain of the thirteenth transistor, a gate of a seventeenth transistor, a drain of the seventeenth transistor, and a gate of the power transistor. In a case of rapid load change, the two loops can effectively suppress overshoot and undershoot of an output, and improve transient response performance of the LDO.

[0036] Referring to Figure 2 In an embodiment, the common-source common-gate inverting voltage follower includes a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, and a twenty-sixth transistor. A source of the twenty-third transistor is connected to ground, a gate of the twenty-third transistor is connected to a second bias voltage, and a drain of the twenty-third transistor is connected to a drain of the twenty-fourth transistor as an output terminal of the common-source common-gate inverting voltage follower and is connected to an output terminal of the double-loop Class-AB error amplifier. A gate of the twenty-fourth transistor is connected to a reference voltage, and a source of the twenty-fourth transistor is connected to a drain of the twenty-fifth transistor and a drain of the twenty-sixth transistor, respectively. A source of the twenty-fifth transistor is connected to a positive input terminal of the common-source common-gate inverting voltage follower and the double-loop Class-AB error amplifier as a positive input terminal of the common-source common-gate inverting voltage follower, and is connected to an output voltage. A gate of the twenty-fifth transistor is connected to an output terminal of the error amplifier as a negative input terminal of the common-source common-gate inverting voltage follower. A gate of the twenty-sixth transistor is connected to a first bias voltage, and a source of the twenty-sixth transistor is connected to ground. Specifically, referring to Figure 3 The common-source common-gate inverting voltage follower includes a local fast loop that passes through, in sequence, a drain of the power transistor, a source of the twenty-fifth transistor, a drain of the twenty-fifth transistor, a source of the twenty-fourth transistor, a drain of the twenty-fourth transistor, and a gate of the power transistor. The local fast loop can effectively improve transient response performance of the device.

[0037] Referring to Figure 2In an embodiment, the error amplifier comprises a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor and a thirty-first transistor; the source of the twenty-seventh transistor is connected to ground, the gate is connected to a first bias voltage, and the drain is connected to the source of the twenty-eighth transistor and the source of the twenty-ninth transistor respectively; the gate of the twenty-eighth transistor is connected to the non-inverting input of the error amplifier, the inverting input of the double-loop Class-AB error amplifier, and the output voltage; the drain of the twenty-eighth transistor and the drain of the thirtieth transistor are connected to the output of the error amplifier; the source of the thirtieth transistor and the source of the thirty-first transistor are connected to a power supply voltage, the gate of the thirtieth transistor is connected to the gate of the thirty-first transistor, the drain of the thirty-first transistor and the drain of the twenty-ninth transistor respectively; and the gate of the twenty-ninth transistor is connected to a reference voltage. Specifically, please refer to Figure 3 The error amplifier comprises a global slow loop which sequentially passes through the drain of the power transistor, the gate of the twenty-eighth transistor, the source of the twenty-eighth transistor, the source of the twenty-ninth transistor, the drain of the twenty-ninth transistor, the gate of the thirtieth transistor, the drain of the thirtieth transistor, the gate of the twenty-fifth transistor, and the drain of the power transistor.

[0038] In an embodiment, the output of the low-dropout linear voltage regulator further comprises a frequency compensation module which is arranged between the gate and the drain of the power transistor to provide frequency compensation so that the circuit remains stable. The frequency compensation module can employ a compensation capacitor which has one end connected to the gate of the power transistor and the other end connected to the drain of the power transistor. The compensation capacitor is connected between the output of the LDO and the output of the cascode voltage follower to ensure the stability of the voltage regulator circuit system.

[0039] In an embodiment, the output of the low-dropout linear voltage regulator further comprises a bandgap reference module for providing a reference voltage. The specific circuit structure of the bandgap reference module can be set and adjusted according to actual application requirements, which is not limited here.

[0040] Please refer to Figure 4 , Figure 4 is a transient response curve diagram of the four-loop on-chip integrated low-dropout linear voltage regulator in an embodiment of the present application. The first loop and the second loop are both global slow loops, and the gate of the power transistor MP is quickly pushed and pulled through a local fast loop, three global slow loops and the push-pull architecture of the double-loop Class-AB error amplifier, thereby improving the transient response performance of the on-chip integrated LDO; as Figure 4As shown, under the condition of the edge time 300 ns and the load capacitance 100 pF, when the load current jumps from 1 mA to 50 mA, the undershoot voltage is 16.3 mV, and the recovery time is less than 1 μs; when the load current jumps from 50 mA to 1 mA, the overshoot voltage is 13.2 mV, and the recovery time is also less than 1 μs. The overshoot voltage and the undershoot voltage are small, and the recovery time is short, effectively improving the transient response speed.

[0041] In an embodiment, the power supply voltage VIN is generally 1.5 V to 1.8 V, and 1.5 V is usually used as the power supply voltage of the low-drop linear regulator. If the load capacitance CL is set to 0-100 pF, the corresponding load driving current is 1-50 mA, so that the output voltage VOUT of the low-drop linear regulator is stabilized at 1.2 V. The first bias voltage V bias1 and the second bias voltage V bias2 are generated by the bias module; the bandgap reference module provides a reference voltage VREF for some transistors in the error amplifier, the common-source common-gate flip voltage follower, and the double-loop Class-AB error amplifier; the frequency compensation module is connected to the output end of the LDO and the output end of the common-source common-gate flip voltage follower, ensuring the stability of the entire regulator circuit system; the error amplifier compares the reference voltage VREF and the output voltage VOUT, and amplifies the generated error signal to provide a control signal Vset for the subsequent common-source common-gate flip voltage follower; the common-source common-gate flip voltage follower compares the control signal Vset and the output voltage VOUT, and amplifies the generated first adjustment signal to adjust the gate voltage of the power transistor MP; the double-loop Class-AB error amplifier compares the reference voltage VREF and the output voltage VOUT, and amplifies the generated second adjustment signal to jointly adjust the gate voltage of the power transistor MP with the common-source common-gate flip voltage follower, thereby adjusting the output driving current of the power transistor MP to shorten the loop response time and reduce the output voltage fluctuation when the load switches. The LDO involved in the present application improves the transient response performance of the regulator under the condition of no large off-chip capacitance by rapidly charging and discharging at the gate of the power transistor MP based on the double-loop Class-AB error amplifier and the common-source common-gate flip voltage follower. The four-loop on-chip integrated LDO regulator realizes a number of key technical breakthroughs in performance and integration. Not only does it support complete on-chip integration, effectively reducing the dependence on external components, but it also has a wide load current adjustment capability and can provide a high-precision output voltage. Its fast transient response characteristic can effectively cope with load mutations, ensuring the stability and reliability of system operation.

[0042] In terms of circuit design, the LDO achieves excellent stability and extremely low output voltage ripple while maintaining high gain and large bandwidth through efficient power tube area utilization. In addition, the regulator also introduces innovative thermal management mechanisms and optimized spatial layout design, significantly improving heat dissipation efficiency and chip area utilization.

[0043] These advantages make it an ideal power management solution for high-performance electronic products, especially for applications with stringent requirements for reliability, energy efficiency, and space constraints, such as smartphones, tablets, wearables, and other portable smart terminals.

[0044] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed by the present application should be covered by the claims of the present application.

Claims

1. A four-loop on-chip integrated low-dropout linear regulator, characterized by, The low dropout linear regulator comprises: an error amplifier for comparing a reference voltage with an output voltage to provide a control signal; a common-gate inverting voltage follower for comparing the control signal with the output voltage to generate a first regulating signal; a double-loop Class-AB error amplifier for comparing the reference voltage with the output voltage to generate a second regulating signal; a power transistor having a gate connected to the first regulating signal and the second regulating signal, a source connected to a power supply voltage, and a drain as a voltage output terminal; the power transistor adjusts an output driving current based on the first regulating signal and the second regulating signal to output the output voltage through the voltage output terminal, so that the response time of the circuit is shortened and the output voltage fluctuation when the load is switched is reduced; a biasing module for providing biasing voltages for the double-loop Class-AB error amplifier, the error amplifier, and the common-gate inverting voltage follower; the biasing module comprises a current source, a first biasing transistor, a second biasing transistor, and a third biasing transistor; an input terminal of the current source is connected to the power supply voltage, and an output terminal of the current source is connected to a drain of the first biasing transistor; a gate of the first biasing transistor is shorted with a drain of the first biasing transistor and connected to a gate of the second biasing transistor to serve as an output node of a first biasing voltage; a source of the first biasing transistor and a source of the second biasing transistor are connected to ground; a drain of the second biasing transistor is connected to a drain of the third biasing transistor; a gate of the third biasing transistor is connected to a drain of the third biasing transistor to serve as an output node of a second biasing voltage; a source of the third biasing transistor is connected to the power supply voltage; the double-loop Class-AB error amplifier comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a twenty-second transistor; The source of the first transistor, the source of the second transistor, the source of the seventh transistor, the source of the eighth transistor, the source of the ninth transistor, the source of the tenth transistor, the source of the eleventh transistor, the source of the twelfth transistor, the source of the nineteenth transistor and the source of the twentieth transistor are grounded respectively; the source of the fifteenth transistor, the source of the sixteenth transistor, the source of the seventeenth transistor, the source of the eighteenth transistor, the source of the twenty-first transistor and the source of the twenty-second transistor are connected to the power supply voltage respectively; the gate of the first transistor, the gate of the second transistor, the gate of the eleventh transistor and the gate of the twelfth transistor are connected to the first bias voltage respectively; the drain of the first transistor is connected to the drain of the third transistor; the drain of the second transistor is connected to the drain of the fourth transistor; the gate and the drain of the third transistor are shorted and connected to the gate of the fifth transistor; the source of the third transistor is connected to the source of the sixth transistor, the source of the thirteenth transistor and the drain of the fifteenth transistor respectively; the drain and the gate of the fourth transistor are shorted and connected to the gate of the fifth transistor; the source of the fourth transistor is connected to the source of the fifth transistor, the source of the fourteenth transistor and the drain of the sixteenth transistor respectively; the drain of the fifth transistor is connected to the drain of the seventh transistor; the drain of the sixth transistor is connected to the drain of the eighth transistor; the gate and the drain of the seventh transistor are shorted and connected to the gate of the ninth transistor; the gate and the drain of the eighth transistor are shorted and connected to the gate of the tenth transistor; the drain of the ninth transistor is connected to the drain of the seventeenth transistor, the drain of the nineteenth transistor and the drain of the twenty-first transistor respectively, serving as the output terminal of the double-loop Class-AB error amplifier; the drain of the tenth transistor is connected to the drain of the twenty-second transistor; the gate and the drain of the twenty-second transistor are shorted and connected to the gate of the twenty-first transistor; the drain of the eleventh transistor is connected to the drain of the thirteenth transistor, the gate of the fifteenth transistor and the gate of the seventeenth transistor respectively; the gate of the thirteenth transistor serves as the non-inverting input terminal of the double-loop Class-AB error amplifier and is connected to the output voltage; the drain of the twelfth transistor is connected to the drain of the fourteenth transistor, the gate of the sixteenth transistor and the gate of the eighteenth transistor respectively; the gate of the fourteenth transistor serves as the inverting input terminal of the double-loop Class-AB error amplifier and is connected to the reference voltage; the drain of the eighteenth transistor is connected to the drain of the twentieth transistor, the gate of the twentieth transistor and the gate of the nineteenth transistor respectively; The common source and common gate type flip voltage follower comprises a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor and a twenty-sixth transistor. The source of the twenty-third transistor is grounded, the gate is connected to the second bias voltage, the drain is connected to the drain of the twenty-fourth transistor as the output terminal of the common-source common-gate type flip voltage follower, and is connected to the output terminal of the double-loop Class-AB error amplifier; the gate of the twenty-fourth transistor is connected to the reference voltage, the source is connected to the drain of the twenty-fifth transistor and the drain of the twenty-sixth transistor respectively; the source of the twenty-fifth transistor is connected to the positive input terminal of the common-source common-gate type flip voltage follower and the positive input terminal of the double-loop Class-AB error amplifier as the positive input terminal of the common-source common-gate type flip voltage follower, and is connected to the output voltage; the gate of the twenty-fifth transistor is connected to the output terminal of the error amplifier as the reverse input terminal of the common-source common-gate type flip voltage follower; the gate of the twenty-sixth transistor is connected to the first bias voltage, and the source is grounded.

2. The four-loop on-chip integrated low-dropout linear regulator of claim 1, wherein, The error amplifier comprises a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor and a thirty-first transistor. The source of the twenty-seventh transistor is grounded, the gate is connected to the first bias voltage, and the drain is connected to the source of the twenty-eighth transistor and the source of the twenty-ninth transistor respectively; the gate of the twenty-eighth transistor is connected to the positive input terminal of the double-loop Class-AB error amplifier as the inverting input terminal of the error amplifier, and is connected to the output voltage; the drain of the twenty-eighth transistor is connected to the drain of the thirtieth transistor as the output terminal of the even error amplifier; the source of the thirtieth transistor and the source of the thirty-first transistor are connected to the power supply voltage, the gate of the thirtieth transistor is connected to the gate of the thirty-first transistor, the drain of the thirty-first transistor and the drain of the twenty-ninth transistor respectively; the gate of the twenty-ninth transistor is connected to the reference voltage.

3. The quad-loop on-chip integrated low-dropout linear regulator of claim 1, wherein, The output terminal of the low-dropout linear voltage regulator further comprises a frequency compensation module, which is arranged between the gate and the drain of the power transistor to provide frequency compensation so that the circuit remains stable.

4. The four-loop on-chip integrated low-dropout linear regulator of claim 3, wherein, The frequency compensation module comprises a compensation capacitor, one end of which is connected to the gate of the power transistor and the other end of which is connected to the drain of the power transistor.

5. The quad-loop on-chip integrated low-dropout linear regulator of claim 1, wherein, The output terminal of the low-dropout linear voltage regulator further comprises a bandgap reference module for providing the reference voltage. The output terminal of the low-dropout linear voltage regulator further comprises a bandgap reference module for providing the reference voltage.

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