Data protection circuit, integrated circuit, and electronic device

Abstract

The application discloses a data protection circuit, an integrated circuit and an electronic device. The data protection circuit comprises a first detection circuit configured to detect data integrity of first data and second data in a memory based on a first instruction of a control unit; a second detection circuit configured to detect data retention of the first data and the second data in the memory based on a first detection result of the first detection circuit; a data recovery circuit configured to recover the first data based on data state of the first data or data state of the second data, recover the second data based on default data of the control unit, or recover the second data based on the first data; and a data retention circuit coupled with the data recovery circuit and the memory and configured to refresh the first data or the second data based on the first detection result and a second detection result of the second detection circuit. The application has the technical effect of improving the reliability of non-volatile data storage in the memory.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of data storage, and in particular to a data protection circuit, an integrated circuit, and an electronic device. BACKGROUND

[0002] As a core controller in an embedded system, a microcontroller unit (MCU) is widely used in scenarios such as industry, automobile, and consumer electronics, which have very high requirements for stability. To ensure the continuity and persistence of system operation, the MCU usually relies on non-volatile memory to store key data. However, when the data is stored in the memory for a long time, it is easy to be affected by temperature, humidity, or the number of erasing and writing, resulting in a decrease in data retention capability, which may cause problems such as bit flipping, reading interference, high-temperature accelerated failure, and data disorder. In particular, during the startup process of the MCU, if the non-volatile data is damaged, it will directly affect the normal startup and function execution of the system. Therefore, the protection of non-volatile data in the memory is worth attention. SUMMARY

[0003] In view of this, embodiments of the present application provide a data protection circuit, an integrated circuit, and an electronic device to improve the reliability of non-volatile data storage in the memory. In a first aspect, a data protection circuit is provided for protecting non-volatile data in the memory, the non-volatile data including first data and second data that are backups of each other. The data protection circuit includes: a first detection circuit coupled to a control unit and a memory, configured to detect data integrity of the first data and the second data in the memory based on a first instruction of the control unit; a second detection circuit coupled to the first detection circuit and the memory, configured to detect data retention of the first data and the second data in the memory based on a first detection result of the first detection circuit; a data recovery circuit coupled to the first detection circuit and the memory, configured to recover the first data based on the second data according to a data state of the first data or a data state of the second data, or recover the second data based on a default data of the control unit, or recover the second data based on the first data; and a data retention circuit coupled to the data recovery circuit and the memory, configured to refresh the first data or the second data based on the first detection result and a second detection result of the second detection circuit.

[0004] Optionally, the first detection circuit includes a security sub-circuit coupled to the memory, configured to determine a check algorithm based on check area information of the non-volatile data, and detect the data integrity of the first data and the second data through the first detection circuit based on the check algorithm.

[0005] Optionally, the check algorithm includes a cyclic redundancy check algorithm or a hash check algorithm.

[0006] Optionally, the security sub-circuit is further configured to read header information of the non-volatile data, and determine a check value based on the check algorithm and the non-volatile data, compare the check value with a check value of the non-volatile data itself, and determine that the non-volatile data is complete data when the comparison result is consistent, wherein the header information contains the check algorithm corresponding to the non-volatile data and a data check length.

[0007] Optionally, the first detection circuit includes a first data detection circuit and a second data detection circuit; the first data detection circuit is configured to detect the integrity of the first data; the second data detection circuit is configured to detect the integrity of the second data; when the first data detection circuit determines that the first data is not complete, the data recovery circuit recovers the first data based on the second data; when the second data detection circuit determines that the second data is not complete, the data recovery circuit recovers the second data based on default data; when the first data detection circuit determines that the first data is complete and the second data detection circuit determines that the second data is not complete, the data recovery circuit recovers the second data based on the first data.

[0008] Optionally, the second detection circuit is further configured to test the data retention of the first data and the second data in the memory based on the read-write parameter and the evaluation data, and determine a second detection result; wherein the read-write parameter includes one or more of a programming voltage, a programming pulse, or a read voltage.

[0009] Optionally, the data retention circuit is further configured to refresh the first data or the second data when the second detection result determines that the data retention of the first data or the second data is lower than a preset retention threshold.

[0010] Optionally, the read-write parameter is a read voltage, and the evaluation data is a first evaluation value; when the second detection circuit adjusts the first voltage of the read voltage to a second voltage, and the first evaluation value does not change, it is determined that the data retention is qualified; when the second detection circuit adjusts the first voltage of the read voltage to a third voltage, and the first evaluation value changes, it is determined that the data retention is unqualified; wherein the second voltage is greater than the third voltage.

[0011] In a second aspect, an integrated circuit is provided, including a control unit and a memory; the data protection circuit provided in the first aspect is configured to detect or recover non-volatile data in the memory when the integrated circuit is started.

[0012] In a third aspect, an electronic device is provided, including the integrated circuit provided in the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0013] The following briefly introduces the drawings used in the description of the embodiments of the present disclosure:

[0014] Figure 1Fig. 1 shows a structural schematic diagram of a data protection circuit provided in some embodiments of the present application;

[0015] Figure 2 Fig. 2 shows a structural schematic diagram of another data protection circuit provided in some embodiments of the present application;

[0016] Figure 3 Fig. 3 shows a data composition schematic diagram of non-volatile data provided in some embodiments of the present application;

[0017] Figure 4 Fig. 4 shows an integrated circuit structural schematic diagram of an application data protection circuit provided in some embodiments of the present application;

[0018] Figure 5 Fig. 5 shows a flow schematic diagram of a data protection method provided in some embodiments of the present application. DETAILED DESCRIPTION

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will illustrate the embodiments of the present disclosure with reference to the drawings. The drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained from these drawings without creative labor, and other embodiments can be obtained without departing from the concept of the present disclosure, and the adjustments and improvements made under the condition of not departing from the concept of the present disclosure are within the protection scope of the present disclosure.

[0020] In order to make the drawing simple, each drawing only shows the part related to the embodiments, and it does not represent the actual structure of the product. In addition, in order to make the drawing simple and easy to understand, in some drawings, only part of the components with the same structure or function are shown, and there can be more or less components with the same structure or function.

[0021] In the present disclosure, unless explicitly specified and limited, ordinal words such as "first", "second", etc. are only used to distinguish the description of the associated objects, and cannot be understood as indicating or implying the relative importance or order between the associated objects; in addition, it also does not represent the number of the associated objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between the associated objects, which represents the "or" relationship between the associated objects. "And / or" is used to describe the relationship between the associated objects, which includes any combination relationship between the associated objects, for example, "a and / or b" includes: "a alone", "b alone", or "a and b". "One or more" or "at least one" of a plurality of objects refers to any object or any combination of a plurality of objects, for example, "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "a1 alone", "a2 alone", "a3 alone", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0022] Micro Control Unit (MCU) is widely used in automotive electronics, industrial control, consumer electronics and other fields, and undertakes key control, data acquisition and execution and other tasks. In order to realize the long-term preservation of system running logic, configuration parameters and state data, the MCU system usually relies on on-chip or off-chip Non-Volatile Memory (NVM) such as FLASH or EEPROM for storing firmware program, calibration parameters, configuration items and other key data. In the running life cycle of MCU, the integrity and reliability of non-volatile storage data are crucial for stable startup and continuous operation of the system. However, the existing technology generally has the following problems: on the one hand, during the power-on startup process of MCU, there is a lack of effective mechanism for checking, backing up and restoring key data, and when the data stored in FLASH is abnormal (for example, bit flipping, erase failure or illegal overwrite), it is easy to cause system startup failure or function abnormality; on the other hand, after long-term storage of non-volatile memory in high temperature environment or frequent erasing, its data retention capability will gradually decrease, which is manifested as charge leakage of storage bits, reading interference or high temperature accelerated aging, further leading to data reading error, system logic confusion and other problems. Especially in automotive electronics or industrial environment and other scenes with strict requirements on temperature and service life, the traditional FLASH data management mechanism is difficult to fully cope with the data reliability problems caused by the decrease of data retention capability. Therefore, there is an urgent need for a technical solution for data protection during the startup process of electronic products, which can complete the integrity checking and fault tolerance processing of key data at an early stage of chip startup, and at the same time has a dynamic evaluation mechanism for non-volatile data retention capability, so as to early warn potential failure risks and improve the overall reliability and stability of the system.

[0023] The following will be described with reference to the drawings:

[0024] Figure 1 A structure diagram of a data protection circuit provided in some embodiments of the present application is shown. The data protection circuit 100 is used to protect non-volatile data in the memory 20, the non-volatile data including first data and second data which are backups of each other. The data protection circuit 100 includes: a first detection circuit 110 coupled to the control unit 30 and the memory 20, configured to detect data integrity of the first data and the second data in the memory 20 based on a first instruction of the control unit 30; a second detection circuit 120 coupled to the first detection circuit 110 and the memory 20, configured to detect data retention of the first data and the second data in the memory 20 based on a first detection result of the first detection circuit 110; a data recovery circuit 130 coupled to the first detection circuit 110 and the memory 20, configured to recover the first data based on the second data according to a data state of the first data or a data state of the second data, or recover the second data based on a default data of the control unit 30, or recover the second data based on the first data; and a data retention circuit 140 coupled to the data recovery circuit 130 and the memory 20, configured to refresh the first data or the second data based on the first detection result and a second detection result of the second detection circuit 120.

[0025] In the above embodiment of the data protection circuit, the data protection circuit can be started when the integrated circuit where the control unit 30 is located is started, and first detects the non-volatile data stored in the memory 20 to determine its integrity, so as to prevent the product function from being unable to be realized due to the data damage in the memory 20 after the integrated circuit starts to work. In the memory 20, the non-volatile data includes first data and second data, wherein the first data and the second data are backed up to each other, and two copies of the same or related data stored in different physical positions of the memory 20 can be used to improve the reliability and security of the data. For example, the first data can be main data stored in a specific area of the memory 20, and the second data can be backup data stored in another independent area, which is used to restore the data when the main data is damaged or lost. Therefore, the first detection circuit 110 can first check the data integrity of the first data, and if it is determined that the first data is complete, the second data can be checked. The data integrity refers to that the non-volatile data in the memory 20 is successfully read without error code, tampering or damage, and the detection mainly detects whether the data content conforms to the expected value, which can be realized by mechanisms such as parity check, cyclic redundancy check, and hash comparison. Alternatively, in order to improve the starting efficiency of the electronic device where the data protection circuit is located, the integrity of the second data is no longer detected, and the data retention of the first data is directly detected by the second detection circuit 120. The data retention can refer to the ability of the non-volatile data to maintain the original content after being affected by factors such as memory aging, high temperature environment and erase count after long time storage, and the retention detection can include reading voltage margin, comparing historical value change trend and the like. After it is determined that the data retention of the second data is good, the data retention of the second data can be detected by the second detection circuit 120. If it is determined that the first data or the second data has data retention risk in the data retention detection process, the first data or the second data can be re-written in the storage area of the memory 20 by the data retention circuit 140, so as to ensure that the non-volatile data stored in the memory 20 always maintains high data retention, improves the reliability of the data storage of the electronic device, and prevents the memory 20 from having unexpected situations such as data loss, omission or damage in the case of long time data storage. In addition, after it is determined that the data retention of the first data is qualified, the data integrity of the second data can be detected by the first detection circuit 110, and after it is determined that the data integrity of the second data is good, the data retention of the second data is detected.In the detection process of data integrity, if the first detection circuit 110 judges that the first data has a problem, the second data as backup data can be written in the storage area of the first data through the data recovery circuit 130 (provided that the second data is complete), to realize the recovery after data damage, prevent affecting the normal start and operation of the integrated circuit, and improve the reliability of the integrated circuit and the electronic equipment applied thereto. When the second data is written as the first data, the first detection circuit 110 can be used to judge whether the second data has an integrity problem. If the second data is complete, it is written in the area of the first data to recover the first data; if the second data is not complete, the default data stored in the control unit 30 can be written into the storage area of the second data by using the data recovery circuit 130, and then the written second data is written into the storage area of the first data. The default data can be data or configuration set by the system in advance without user intervention or customization, thereby basically guaranteeing the normal operation of the integrated circuit and the electronic equipment or realizing the basic function, and providing support for subsequent equipment maintenance or program recovery. In some embodiments, when it is determined that the first data integrity is qualified, but the second data integrity has a problem, the second data can be recovered by using the first data, thereby realizing the mutual backup between the first data and the second data. The above data protection circuit can be embedded in the integrated circuit in the form of a hardware-level circuit, to ensure that the above protection process can be stably and reliably realized, and to establish stable and continuous protection of the data in the protected memory. At the same time, the firmware program in the integrated circuit can also belong to part of the protected non-volatile data, thereby ensuring the stable and reliable execution of the firmware program of the integrated circuit, and the firmware program can protect the user's storage data. Through the formation of a hardware-level trusted protection chain, the safe, stable and reliable data protection of the user's non-volatile data is realized in a software and hardware combined manner.

[0026] Figure 2 The structure of another data protection circuit provided in some embodiments of the application is shown. The first detection circuit 110 includes a security sub-circuit 113 coupled to the memory 20, configured to determine a verification algorithm based on the verification area information of the non-volatile data, and detect the data integrity of the first data and the second data based on the verification algorithm through the first detection circuit.

[0027] In the process of data integrity detection, the first data or the second data integrity can be checked by the security sub-circuit 113. The non-volatile data can be pre-set with check area information, which can identify the data check type, check strength, or version number of the check algorithm for the data segment. The security sub-circuit 113 can dynamically select or configure the corresponding check algorithm based on the read check area information, for example, including: parity check, cyclic redundancy check, hash function comparison, etc. Subsequently, the security sub-circuit 113 can call the selected check algorithm to perform check operations on the first data and the second data respectively, and output the obtained results to the first detection circuit 110 to generate the first detection result indicating the data integrity. If the check result indicates that a data item has errors, bit flips, or content tampering, the first detection circuit 110 will output the first detection result indicating that the data is not complete, for subsequent initiation of data retention detection and data recovery process. By introducing the security sub-circuit 113 and flexibly selecting the appropriate check mechanism through the check area information, not only can the fine-grained data integrity protection be achieved, but also the security controllability of the integrated circuit in complex application environment can be improved, which is suitable for industrial control, vehicle electronics, and other application scenarios with high requirements for data protection accuracy and flexibility.

[0028] In some embodiments, the check algorithm includes a cyclic redundancy check algorithm or a hash check algorithm. The security sub-circuit 113 can select a corresponding one from a plurality of preset check algorithms according to a field in the check area information of the non-volatile data that identifies the check method adopted by the current data segment. The cyclic redundancy check algorithm (CRC) can obtain a CRC check code by performing a specific polynomial division operation on a data bit sequence, and this algorithm is suitable for quickly detecting occasional errors in data. The hash check algorithm, such as the SHA-256 algorithm, can calculate a digest value from the data content and compare it with a preset hash value to achieve high-strength detection of data integrity and tampering. In actual operation, the security sub-circuit 113 executes check operations on the first data and the second data according to the selected check algorithm, and outputs the check result. The first detection circuit 110 judges whether the data is complete according to the check result, and transmits the first detection result to the subsequent circuit for data retention detection and necessary data recovery processing. Through the security sub-circuit 113, the application can implement a flexible and adaptive data integrity check strategy for different security levels and application requirements, while ensuring detection efficiency and improving the data protection capability of the control unit 30 in critical task scenarios. In addition, the check algorithm can not be limited to the above cyclic redundancy check algorithm or hash check algorithm, and other algorithms that can achieve data integrity check can also be applicable, which are not limited here.

[0029] Figure 3A schematic diagram of data composition of non-volatile data provided in some embodiments of the present application is shown. The security sub-circuit 113 is further configured to read the header information of the non-volatile data, and determine a check value based on the check algorithm and the non-volatile data, compare the check value with the non-volatile data itself, and when the comparison result is consistent, determine that the non-volatile data is complete data, wherein the header information contains the check algorithm corresponding to the non-volatile data and the data check length.

[0030] With continued reference to Figure 2 , the first detection circuit 110 includes: a first data detection circuit 111 and a second data detection circuit 112; the first data detection circuit 111 is configured to detect the integrity of the first data; the second data detection circuit 112 is configured to detect the integrity of the second data; wherein when the first data detection circuit 111 determines that the first data is not complete, the data recovery circuit 130 recovers the first data based on the second data; when the second data detection circuit 112 determines that the second data is not complete, the data recovery circuit 130 recovers the second data based on the default data; when the first data detection circuit 111 determines that the first data is complete and the second data detection circuit 112 determines that the second data is not complete, the data recovery circuit 130 recovers the second data based on the first data.

[0031] In the above data protection circuit, the first data detection circuit 111 can perform an integrity detection operation on the first data based on a preset check algorithm through the security sub-circuit 113 to determine whether there is a bit flip, content tampering or other data anomaly. If the first data detection circuit 111 determines that the first data is not complete, the content of the first data can be recovered based on the second data through the data recovery circuit 130, thereby realizing rollback repair of the main data and avoiding system startup anomalies due to single point failures. On the other hand, the second data detection circuit 112 can detect the integrity of the second data. When the second data detection circuit 112 determines that the second data is not complete, the default data pre-stored in the control unit 30 can be called through the data recovery circuit 130 to reconstruct the second data through the data recovery circuit 130, thereby ensuring the reliability and self-recovery capability of the backup data link. In addition, if the first data and the second data both fail the integrity detection, the second data formed by the default data can be used as the basis to form the first data through the data recovery circuit 130. In some embodiments, when the first data detection circuit 111 determines that the first data is complete, and the second data detection circuit 112 determines that the second data is not complete, the second data can also be recovered using the first data through the data recovery circuit 130, thereby realizing mutual backup between the first data and the second data. The embodiments of the present application can respectively realize independent checking and hierarchical recovery control of two data, thereby improving the stability and data security of the integrated circuit in complex application environments. The default data can be stored in the firmware area, ROM or independent protection storage unit of the MCU in a read-only manner, and can not be overwritten by normal write operations and is not affected by the number of erasing and writing times of the main memory 20. In order to recover the function of the integrated circuit as soon as possible in extreme cases, the content of the default data can be flexibly set according to requirements, for example, it can include: a basic version of the firmware program, a factory value of a general configuration parameter, a minimum data set required for secure startup, a redundant structure template consistent with the function of the first data and the second data, etc. When the second data detection circuit 112 detects that the second data is severely damaged (such as check failure or data loss) and cannot be effectively recovered from the first data, the default data can be written into the second data position in the memory 20 through the data recovery circuit 130, thereby realizing re-establishment of data storage.

[0032] In some embodiments of the present application, the second detection circuit 120 is further configured to test the data retention of the first data and the second data in the memory 20 based on the read-write parameters and the evaluation data, and determine a second detection result; wherein the read-write parameters include one or more of: a programming voltage, a programming pulse, or a read voltage.

[0033] In the above embodiments, the program voltage in the read-write parameters can be used as the burn-in voltage applied to the memory cell when writing data; the program pulse can be used to control the pulse duration or number of times of the write cycle, i.e., the burn-in voltage pulse width; and the read voltage can be used as the reference voltage applied when reading data. The second detection circuit 120, under the instruction of the control unit 30, calls the above parameters, performs read or write operations on the storage area where the first data and the second data in the memory 20 are located, and judges the data retention based on the returned evaluation data (such as voltage response, current value, readout delay, error rate, etc.). If the data retention of a certain data decreases (such as detecting a data bit flip trend, an error rate increase, or a higher voltage is required to stabilize reading), the second detection circuit 120 will generate a second detection result to identify that the data has a potential risk of failure. Subsequently, the system can determine whether to call the data recovery circuit 130 for early backup or rewriting to prevent the data from failing during long-term storage or high-temperature aging. The present application can predict the stability change of the data when it is still in a readable state, so as to intervene in repair in advance, improve the data persistence, and improve the overall reliability of the MCU system.

[0034] In some embodiments of the present application, the data retention circuit is further configured to refresh the first data or the second data when the second detection result determines that the data retention of the first data or the second data is lower than a preset retention threshold.

[0035] In some embodiments of the present application, the read-write parameter is a read voltage, and the evaluation data is a first evaluation value; when the second detection circuit adjusts the first voltage of the read voltage to a second voltage, and the first evaluation value does not change, it is determined that the data retention is qualified; when the second detection circuit adjusts the first voltage of the read voltage to a third voltage, and the first evaluation value changes, it is determined that the data retention is unqualified; wherein the second voltage is greater than the third voltage.

[0036] In a normal burn-in process, the programming voltage and the programming pulse use default values for data burn-in, and the data retention capability is in a good state, but under the influence of environmental temperature, storage time, memory erase times, etc., the data retention capability will gradually decrease until the data cannot be read out completely and accurately. By adjusting the programming voltage and the programming pulse, the burn-in intensity of the data of the memory can be adjusted, and the smaller the programming voltage and the programming pulse, the lower the burn-in intensity, and the weaker the corresponding data retention capability. The present application can use normal programming voltage and programming pulse parameters to burn-in the first data or the second data, while additionally burning-in a set of data for evaluating data retention. The evaluation data can be burned-in using different programming voltage and programming pulse parameters, thereby obtaining multiple sets of evaluation data with different data retention capabilities. The evaluation data is burned-in at the same time as the first data or the second data, and works in the same environment, so the data retention capability changes synchronously, thereby the data retention capability of the first data or the second data can be indirectly evaluated by tracking the change of the data retention of the evaluation data.

[0037] Due to the characteristics of the memory, such as FLASH, it is necessary to erase data before writing data, and the value of FLASH after erasing is all 1, and only 0 can be written into FLASH. Using different burn-in intensities to burn-in data, when the burn-in intensity is low, it will not be able to burn-in 1 to 0, and at the same time, the data burned-in by the lower burn-in intensity has weaker data retention capability, resulting in that when the data retention capability is lower than the threshold value (breaking the 0-1 limit), 0 cannot be read out, so the number of 0 of the evaluation data can be read out to judge the retention capability of the evaluation data. By adjusting the read-write parameters to burn-in multiple sets of evaluation data, each set of evaluation data corresponds to a different burn-in intensity, so the initial data retention capability of each set of evaluation data is also different. The evaluation data with weaker data retention capability will first appear 0 to 1 change after experiencing the same use environment, so the number of 0 read out from each set of evaluation data can be observed to infer the change of the data retention capability, when the evaluation data with a burn-in intensity close to that of the first data or the second data appears 0 to 1 change, it means that the data retention capability of the first data or the second data has decreased to a degree close to the threshold value, at this time, it is necessary to refresh and re-write the first data or the second data to maintain its data retention capability. Therefore, the more the number of sets of evaluation data, the more accurate the evaluation of the data retention capability.

[0038] In addition, since the logic used by the memory 20 to determine 0 and 1 can rely on an external reference voltage, i.e., a read voltage, by adjusting the read voltage, the reference voltage used by the memory 20 to determine 0 and 1 can be changed for data with good data retention capability. When a large variation occurs in the read voltage, the state of 0 can still be correctly read out. However, when the data retention capability is low or even close to the limit, a small fluctuation in the read voltage can not correctly read out the state of 0. Therefore, the data retention capability of the data stored in the memory 20 can be indirectly determined by adjusting the read voltage to count the number of 0s at different read voltages, which is used to assist in determining the data retention of the first data or the second data.

[0039] Figure 4 An integrated circuit structure diagram of an application data protection circuit is shown in some embodiments of the present application. The first detection circuit 110 in the above data protection circuit can be integrated in the memory controller 21 included in the memory itself, and the security sub-circuit 113 can be integrated in the security module of the integrated circuit or separately arranged to determine the data integrity of the first data or the second data with the first detection circuit 110. The data recovery circuit 130 and the data retention circuit 140 can also be integrated in the memory controller 21, thereby improving the integration of the memory 20.

[0040] Figure 5 A flowchart of a data protection method is shown in some embodiments of the present application. The data protection method is implemented by the data protection circuit provided in the above embodiments, and is applied to an MCU, for example, and includes the following steps:

[0041] S510: The MCU is powered on to activate the data protection circuit;

[0042] S520: The first detection circuit is used to detect the data integrity of the first data and the second data;

[0043] S530: Whether the data integrity of the first data and the second data is detected to fail; if yes, step S531 is performed, and if no, step S540 is performed.

[0044] S531: The data recovery circuit recovers the second data using default data;

[0045] S540: Whether the data integrity of the first data and the second data is detected to succeed; if yes, step S5550 is performed, and if no, step S541 is performed.

[0046] S541: The data recovery circuit recovers the data detected to fail;

[0047] S550: The second detection circuit detects the data retention of the first data and the second data;

[0048] S560: judging whether the data retention of the first data is normal; if yes, executing step S580, if not, executing step S570.

[0049] S570: the data retention circuit rewrites the first data.

[0050] S580: judging whether the data retention of the second data is normal; if yes, completing the data protection process, if not, executing step S590.

[0051] S590: the data retention circuit rewrites the second data.

[0052] The specific implementation of the above execution steps can refer to the content of the above data protection circuit related processes and methods, and will not be described in detail here.

[0053] Based on the same technical concept, the application also provides an electronic device comprising the integrated circuit provided in the above embodiments and provided with the data protection circuit.

[0054] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A data protection circuit, characterized in that, For protecting non-volatile data in memory, the non-volatile data includes first data and second data that are backups of each other, the data protection circuit includes: A first detection circuit is coupled to the control unit and the memory, and the first detection circuit includes: a first data detection circuit and a second data detection circuit; The first data detection circuit is configured to detect the integrity of the first data; The second data detection circuit is configured to detect the integrity of the second data; The first detection circuit is configured to detect the data integrity of the first data and the second data in the memory based on a first instruction from the control unit; A second detection circuit, coupled to the first detection circuit and the memory, is configured to detect the data retention of the first data and the second data in the memory based on a first detection result of the first detection circuit. A data recovery circuit, coupled to the first detection circuit and the memory, is configured to: when the first data detection circuit determines that the first data is incomplete, the data recovery circuit recovers the first data based on the second data; When the second data detection circuit determines that the second data is incomplete, the data recovery circuit recovers the second data based on the default data of the control unit; When the first data detection circuit determines that the first data is complete and the second data detection circuit determines that the second data is incomplete, the data recovery circuit recovers the second data based on the first data; A data retention circuit, coupled to the data recovery circuit and the memory, is configured to refresh the first data or the second data based on a second detection result from the second detection circuit.

2. The data protection circuit according to claim 1, characterized in that, The first detection circuit includes: A security sub-circuit, coupled to the memory, is configured to determine a verification algorithm based on the verification area information of the non-volatile data, and to detect the data integrity of the first data and the second data through the first detection circuit based on the verification algorithm.

3. The data protection circuit according to claim 2, characterized in that, The verification algorithm includes: cyclic redundancy check algorithm or hash check algorithm.

4. The data protection circuit according to claim 3, characterized in that, The security sub-circuit is further configured to read the header information of the non-volatile data, determine a check value based on the verification algorithm and the non-volatile data, compare the check value with the check value of the non-volatile data itself, and determine that the non-volatile data is complete data when the comparison results are consistent. The header information includes the verification algorithm and data verification length corresponding to the non-volatile data.

5. The data protection circuit according to claim 4, characterized in that, The second detection circuit is further configured to test the data retention of the first data and the second data in the memory based on read / write parameters and evaluation data, and determine the second detection result; The read / write parameters include one or more of the following: programming voltage, programming pulse, or read voltage.

6. The data protection circuit according to claim 5, characterized in that, The data holding circuit is further configured to refresh the first data or the second data when the second detection result determines that the data holding performance of the first data or the second data is lower than a preset holding threshold.

7. The data protection circuit according to claim 5, characterized in that, The read / write parameter is the read voltage, and the evaluation data is the first evaluation value; When the second detection circuit adjusts the first voltage of the reading voltage to the second voltage, and the first evaluation value does not change, it is determined that the data retention is qualified. When the second detection circuit adjusts the first voltage of the reading voltage to the third voltage, and the first evaluation value changes, it is determined that the data retention is unqualified. The second voltage is greater than the third voltage.

8. An integrated circuit, characterized in that, include: Control unit and memory; The data protection circuit according to any one of claims 1 to 7 is configured to detect or recover non-volatile data in the memory when the integrated circuit is started.

9. An electronic device, characterized in that, Includes the integrated circuit described in claim 8.

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