Asynchronous multi-granularity access control method in microprocessor, asynchronous circuit and access module

Abstract

The application discloses a kind of asynchronous multi-granularity memory access control method in microprocessor, asynchronous circuit, memory access module, and memory access control method uses asynchronous clockless control, introduces multi-granularity memory access control mechanism, and memory access granularity is divided into two categories of multi-word memory access and non multi-word memory access to be handled, can flexibly adjust access path and cache strategy according to different memory access granularity, reduce the redundant operation in access time, and greatly improve memory access efficiency.Asynchronous circuit uses delay limited type asynchronous circuit, including asynchronous controller and the asynchronous micro pipeline structure based on "send-relay-receive" structure.Based on the data interaction interface between memory access module of asynchronous circuit and write-back module, memory access state management module, data access update module, instruction / data cache and peripheral interaction interface are included.The application realizes lower dynamic power consumption and higher energy efficiency ratio, with high efficiency and low delay under large data volume operation.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of asynchronous processors, and particularly relates to an asynchronous multi-granularity memory access control method, an asynchronous circuit and a memory access module in a microprocessor. BACKGROUND

[0002] In the field of microprocessor design, an asynchronous architecture can not only alleviate a series of problems caused by a global clock, but also effectively reduce dynamic power consumption. Each module in an asynchronous processor can operate independently, and only when data arrives or interaction demand is generated, the relevant logic is activated, thereby realizing more flexible timing control and more optimal energy management. At the same time, the asynchronous circuit has stronger stability to changes in process, voltage and temperature, and does not need to frequently calibrate the clock frequency or adjust the voltage margin, and is more suitable for running in an uncertain environment.

[0003] In the design of a microprocessor under an asynchronous architecture, the design of memory access control is of great significance to improving system performance and stability. On the one hand, since the asynchronous processor does not rely on a global clock, the processor needs to redefine the control logic in multiple dimensions such as path selection, address confirmation and data synchronization when designing the memory access module; on the other hand, the types of memory access instructions are diversified, including access requirements of different data widths (such as Byte / Half / Word / Double) and high-bandwidth data block transmission, which requires the memory subsystem to have stronger multi-granularity adaptation capability.

[0004] However, the existing memory access control method has the following deficiencies:

[0005] 1. In a synchronous processor, the memory access scheduling method based on cycle alignment usually relies on a unified clock for stage division and signal latching, and the design logic is clear and the timing is controlled. However, in an asynchronous system, the memory access process needs to be driven by request-response events for dynamic path selection and data transmission, and the traditional memory mechanism cannot be directly applied to an asynchronous environment;

[0006] 2. Limited support in data access granularity, when facing multi-granularity memory access instructions in an asynchronous processor, redundant processing logic or alignment buffer often needs to be introduced, resulting in low access efficiency and increased resource overhead;

[0007] 3. Often relies on external Cache, bus bridge or MMU and other auxiliary modules for collaborative control, with high design complexity and poor adaptability. In an asynchronous architecture, the control interface of these auxiliary modules usually needs to be redesigned to have a handshake protocol, thereby increasing the system complexity. SUMMARY

[0008] In view of the problems in the above background art, the purpose of the present application is to provide an asynchronous multi-granularity memory access control method, an asynchronous circuit and a memory access module in a microprocessor.

[0009] To achieve the above object, the present application adopts the following technical solutions:

[0010] The asynchronous multi-granularity access control method in the microprocessor comprises the following steps:

[0011] S1, the received data is unpacked by using the access module, and it is judged whether the storage needs to be accessed; the data which does not need to access the storage is arranged and sent to the write-back module, and the access is ended; the data which needs to access the storage is judged whether it is multi-word access storage, if yes, step S2 is executed, if not, step S5 is executed;

[0012] S2, the list to be accessed is updated, and it is judged whether the access list is empty, if yes, the access is ended, if not, the data before access is integrated, and it is judged whether the access address is aligned, if yes, the access frequency register is set to 1; if not, the access frequency register is set to 2;

[0013] S3, after the access frequency register is reset, the access module and the DataRout interact with each other, the access counter is added by 1, and it is judged whether the access counter is less than the access frequency register, if yes, the DataRout is interacted with constantly, if not, step S4 is executed;

[0014] S4, the data after access is integrated, and it is judged whether it is a load type instruction, if yes, the data is arranged and sent to the write-back module, and step S2 is executed; if not, step S2 is directly executed;

[0015] S5, the data before access is integrated, and it is judged whether the access address is Icache, if yes, the Icache is read, and the access state is updated; if not, the access module and the DataRout interact with each other, and the access state is updated;

[0016] S6, after the access state is updated, it is judged whether the current access state is idle, if yes, step S7 is executed, if not, step S5 is executed;

[0017] S7, the data after access is integrated, and it is judged whether it is a load type instruction, if yes, the data is arranged and sent to the write-back module, and the access is ended; if not, the data is arranged and sent to the dispatch module, and the access is ended.

[0018] The application further provides an asynchronous circuit for implementing the asynchronous multi-granularity memory access control method in a microprocessor, which adopts a delay-limited asynchronous circuit, wherein a control path only needs an asynchronous controller, and a data path is formed by standard logic gate units.

[0019] Further, the asynchronous controller adopts a Click asynchronous controller.

[0020] Further, the "send-receive-relay" structure comprises a Sender, a Relay and a Receiver, wherein:

[0021] The Sender comprises a flip-flop, an inverter and a delay module, and when receiving a driving pulse signal i_drive, the Sender flips an output level signal, and an input pulse signal i_free is output as o_free after being delayed by the delay module;

[0022] The Relay is composed of an XOR gate, a XNOR gate, an AND gate, a D flip-flop, an inverter and a delay module, and is realized based on the Click asynchronous controller;

[0023] The Receiver comprises a flip-flop, and when receiving a lower pulse signal i_freeNext, the flip-flop is activated.

[0024] Further, in the asynchronous event structure:

[0025] The Source comprises an inverter and a delay unit, and generates a pulse event signal by using a phase difference;

[0026] The Trap comprises a delay unit, and outputs an input pulse after delaying;

[0027] The Splitter comprises a Contap, an AND gate, an OR gate and an NOR gate;

[0028] The Selector comprises a Sender, a Relay, a Receiver, an AND gate and a NOT gate;

[0029] The WaitMerge comprises a Contap, an AND gate and an OR gate;

[0030] The Wait comprises a Contap, an AND gate and an OR gate;

[0031] ArbMerge includes cFifo, cPmtFifo, Contap, AND gate, OR gate, inverter and flip-flop; cFifo includes Sender, Relay and Receiver, receives input event pulse signal, generates timing control signal, and outputs next stage event pulse signal; cPmtFifo includes Sender, Relay with permission mechanism, Receiver and delay unit, receives input event pulse signal, generates timing control signal when permission signal is high, and outputs next stage event pulse signal;

[0032] MutexMerge includes Contap, AND gate, OR gate and multiplexer;

[0033] The Contap adopts Sender without generating free signal, and the Contap includes flip-flop and inverter for converting pulse signal to level signal.

[0034] The application further provides a memory access module using the asynchronous circuit, which includes a memory state management module, a data access update module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory state management module and a write-back module; the memory state management module includes a Load-type memory control state machine and a Store-type memory control state machine, which are respectively used for describing state transition processes of Load instruction and Store instruction; the data access update module uses combination logic to perform corresponding update processing on old data according to control state bits output by the memory state management module; the old data refers to original data that needs to be processed in the data access update module.

[0035] Further, the instruction / data cache and peripheral interaction interface includes Selector and MutexMerge, the Selector is located at a memory request sending end, and is used for judging whether data flows to the instruction / data cache or the peripheral according to a memory address; and the MutexMerge is located at a return end, and is used for receiving data and events returned from the instruction / data cache or the peripheral.

[0036] Further, the data interaction interface between the memory state management module and the write-back module includes MutexMerge, which is used for receiving data and events of non-memory instruction or memory instruction to the write-back module.

[0037] Further, the control state bits include a memory type bit, a memory flag bit and an unaligned memory flag bit.

[0038] Compared with the defects and deficiencies of the prior art, the application has the following beneficial effects:

[0039] 1.The memory access control method of the present application adopts asynchronous clockless control, greatly reducing the invalid power consumption caused by clock rollover in synchronous systems, especially when the module is idle, avoiding fixed period clock rollover, thereby achieving lower dynamic power consumption and higher energy efficiency ratio; and completely avoiding the complexity and skew problem of global clock distribution, improving the scalability of the system, especially in large-scale integrated systems such as multi-core processors and system-on-chip (SoC), supporting more flexible heterogeneous integration and modular design;

[0040] 2.The present application adopts dynamic timing scheduling and on-demand activation mechanism, which can dynamically adjust the start-stop state of the module according to different loads and actual running conditions, thereby optimizing the power consumption management of the system, especially in low activity scenarios, which can greatly reduce unnecessary energy consumption;

[0041] 3.The present application introduces a multi-granularity memory access control mechanism, which supports memory access operations of different granularities, and can flexibly adjust the access path and cache strategy according to different memory granularities, reducing redundant operations during access and greatly improving memory efficiency. Through the fine control of the memory access process by the finite state machine (FSM), the stability and efficiency of data access are further improved;

[0042] 4.The asynchronous circuit of the present application reduces the complex clock tree and timing control circuit, reducing the complexity of the design. At the same time, due to the locality and loose coupling characteristics of the asynchronous control mechanism, the overall debugging process of the chip is more intuitive and easy to handle, especially in multi-core processor and heterogeneous integration application scenarios, the overall design of the chip is more flexible, and is easy to expand and modify;

[0043] 5.The asynchronous multi-granularity memory access control of the present application can effectively adapt to complex and diverse data access requirements, especially for high-bandwidth multi-word access and efficient data transmission, ensuring the efficiency and low delay of the system under large data operation, significantly improving the performance of the processor. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 is a structural schematic diagram of a delay-limited asynchronous circuit provided by an embodiment of the present application;

[0045] Figure 2 is a schematic diagram of an asynchronous event structure in an asynchronous micro-pipeline structure provided by an embodiment of the present application;

[0046] Figure 3 is a structural schematic diagram of a memory module provided by an embodiment of the present application;

[0047] Figure 4 is a flowchart of an asynchronous multi-granularity memory access control method in a microprocessor provided by an embodiment of the present application;

[0048] Figure 5 This is the non-multi-word memory access granularity type provided in the embodiments of the present invention;

[0049] Figure 6 This is a Load-type memory access control state machine provided in the embodiments of the present invention;

[0050] Figure 7 This is a Store-type memory access control state machine provided in the embodiments of the present invention;

[0051] Figure 8 This is a flowchart of the multi-word Load type memory access control provided in an embodiment of the present invention;

[0052] Figure 9 This is a flowchart of the multi-word Store type memory access control provided in the embodiments of the present invention. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0054] This invention employs customized asynchronous micropipelining technology to achieve multi-granularity control of the memory access module. After analyzing the design requirements of the microprocessor, this invention ultimately adopts a delay-limited asynchronous circuit as the core design scheme. The delay-limited asynchronous circuit is as follows: Figure 1 As shown, a modular design approach is adopted, requiring only asynchronous controllers for the control path, while the data path is constructed using standard logic gate units. When the first-level asynchronous controller receives a request event from the previous level, it immediately generates a control signal (fire) to latch the data from the previous level into a register and pass it to subsequent combinational logic for processing. After ensuring the data is latched, it sends a reply event to the previous level and simultaneously sends a request event to the next-level asynchronous controller to receive the data processed by the combinational logic. The actions taken by the next-level asynchronous controller are consistent with those of the previous level. The delay of request events between asynchronous controllers must strictly match the combinational logic timing of the data path to meet setup time requirements. Structurally, this design is similar to synchronous circuits, but it avoids the power consumption and timing problems caused by global clock distribution, making it more energy-efficient than synchronous circuits of the same size.

[0055] Delay-limited asynchronous circuits consist of two important parts: an asynchronous controller and an asynchronous micropipeline structure based on a "transmit-relay-receive" structure.

[0056] The asynchronous controller adopts a Click asynchronous controller, and the Click asynchronous controller comprises four key signal interfaces: inR (a front-stage request), inA (a front-stage response), outR (a rear-stage request) and outA (a rear-stage response). The working principle is as follows: when a level change of the inR signal is detected, the Click asynchronous controller generates a pulse fire, and the pulse fire synchronously triggers two operations: resetting the front-stage module through the inA signal and starting the rear-stage module through the outR signal. In order to ensure the reliability of data transmission, the controller has strict interlocking conditions: the generation of the next pulse fire must meet the conditions of an effective reset of the outA and a change of the inR again. If no effective outA reset signal is received, the system will remain in a blocked state, thereby avoiding data conflicts.

[0057] The asynchronous micro-pipeline structure is the core of the asynchronous circuit, and the asynchronous micro-pipeline structure is designed based on a “sending-repeating-receiving” structure. The timing characteristics of the pulse signal are accurately controlled, and the phase problem that may be caused by a traditional level triggering mechanism is effectively solved. The “sending-repeating-receiving” structure comprises a Sender, a Relay and a Receiver.

[0058] The Sender comprises a flip-flop, an inverter and a delay module. When a driving pulse signal i_drive is received, the Sender flips an output level signal, and an input pulse signal i_free is output as o_free after being delayed by the delay module.

[0059] The Relay is composed of an exclusive OR gate, an exclusive NOR gate, an AND gate, a D flip-flop, an inverter and a delay module, and is realized based on the Click asynchronous controller.

[0060] The Receiver comprises a flip-flop. When a lower-level pulse signal i_freeNext is received, the flip-flop is activated.

[0061] By analyzing a data path, the asynchronous event structure (refer to Figure 2 ) in the asynchronous micro-pipeline structure can be divided into the following categories:

[0062] The Source comprises an inverter and a delay unit, generates a pulse event signal by using a phase difference, is a starting node of the entire asynchronous flow, and is responsible for generating an initial triggering event.

[0063] The Trap comprises a delay unit, outputs an input pulse after delaying, is a termination node of the asynchronous flow, and ensures that an event is completely ended.

[0064] The Splitter comprises a Contap, an AND gate, an OR gate and an OR NOT gate.

[0065] Selector (choose a path) includes: Sender, Relay, Receiver, AND gate, NOT gate;

[0066] WaitMerge (converge) includes: Contap, AND gate, OR gate;

[0067] Wait (synchronization) includes: Contap, AND gate, OR gate;

[0068] ArbMerge (arbitration) includes: cFifo, cPmtFifo, ConTap, AND gate, OR gate, inverter and flip-flop; cFifo includes Sender, Relay and Receiver, receives input event pulse signal and generates timing control signal, and outputs next stage event pulse signal; cPmtFifo includes Sender, Relay with permission mechanism, Receiver and delay unit, receives input event pulse signal, generates timing control signal when the permission signal is high, and outputs next stage event pulse signal;

[0069] MutexMerge (mutual exclusion) includes: Contap, AND gate, OR gate, and multiplexer;

[0070] Among them, Contap uses Sender without generating free signal, Contap includes flip-flop and inverter, which is used to convert pulse signal to level signal.

[0071] The memory module mainly completes the read and write operation of data through Load and Store instructions. Overall, the memory module includes memory state management module, data access update module, instruction / data cache and peripheral interaction interface, and data interaction interface with the write-back module, such as Figure 3As shown, the access state management module includes a Load-type access control state machine and a Store-type access control state machine, which are respectively used to describe the state transition process of the Load instruction and the Store instruction. The data access update module uses combinational logic to perform corresponding update processing on old data according to the control state bits (such as Load / Store access flag bits i_isLoad_1 / i_isStore_1, access type bits i_lsuType_2, misaligned access flag bits o_misaligned_1, etc.) output by the access state management module; the old data refers to the original data that needs to be processed in the data access update module. The data obtained in the unpacking stage is the initial data without processing, but if the misaligned access occurs, two accesses may be needed, so the data access update module always takes the current old data (not necessarily the original data) to be processed as the object for operation. The instruction / data cache and peripheral interaction interface includes Selector and MutexMerge, the Selector is located at the access request sending end, and is used to determine whether the data flows to the instruction / data cache or the peripheral according to the access address; the MutexMerge is located at the return end, and is used to receive the data and events returned from the instruction / data cache or the peripheral; the Selector, the instruction / data cache, the peripheral and the MutexMerge constitute a data transfer center. The data interaction interface between the write-back module includes MutexMerge, which is used to receive the data and events of the non-access instruction or the access instruction to the write-back module.

[0072] The asynchronous multi-granularity access control method adopted by the application considers almost all types of access granularity control, and divides the access granularity into two categories of multi-word access and non-multi-word access for processing, and the overall access control flow is as shown in Figure 4 As shown, the specific process is as follows:

[0073] S1, using the access module to unpack the received data, and judging whether the data needs to access the storage; the data that does not need to access the storage is arranged and sent to the write-back module, and the access ends; the data that needs to access the storage is judged whether it is multi-word access storage, if yes, step S2 is executed, if not, step S5 is executed;

[0074] S2, updating the to-be-accessed list, and judging whether the access list is empty, if empty, the access ends, if not empty, integrating the pre-access data, and judging whether the access address is aligned, if aligned, the access frequency register is set to 1; if not aligned, the access frequency register is set to 2;

[0075] S3, after the memory access number register is reset, the memory access module interacts with the DataRout for data, the memory access counter is added by 1, and it is judged whether the memory access counter is less than the memory access number register, if yes, the DataRout is interacted for data constantly, if no, step S4 is executed;

[0076] S4, after the memory access is integrated, it is judged whether it is a load type instruction, if yes, the data is arranged and sent to the write-back module, and step S2 is executed, if no, step S2 is directly executed;

[0077] S5, the data before memory access is integrated, and it is judged whether the access address is Icache, if yes, the Icache is read, and the memory access state is updated, if no, the memory access module interacts with the DataRout for data, and the memory access state is updated;

[0078] S6, after the memory access state is updated, it is judged whether the current memory access state is the IDLE (idle) state, if yes, step S7 is executed, if no, step S5 is executed;

[0079] S7, after the data after memory access is integrated, it is judged whether it is a load type instruction, if yes, the data is arranged and sent to the write-back module, and the memory access is ended, if no, the data is arranged and sent to the dispatch module, and the memory access is ended.

[0080] The specific implementation method of the non-multiple word memory access control is as follows:

[0081] The traditional memory access instruction width has: byte, half word, single word and double word. After the execution module completes operation, the execution result is packaged together with the memory access related information and is transmitted to the memory access module, the information includes the memory access address, the memory access type, the instruction category (Load / Store) and the like. The memory access module first judges whether the current instruction is a memory access instruction according to the Load / Store instruction flag bit, if not, the subsequent memory access processing flow is skipped, and the write-back phase is directly entered, if it is judged as a memory access instruction, the memory access address generated by the execution module needs to be further verified whether it is legal, if the address exceeds the pre-defined memory access address space range, it is regarded as illegal access, the memory access module will generate a memory access address exception, and generates the corresponding exception code, the exception event is packaged and transmitted to the interrupt exception processing module for unified management. If the address is legal, the Load instruction or the Store instruction operation is continued, and two parts of state update and data update are handled according to the instruction type. The memory access state update mainly processes the address alignment problem under different data access granularity and the memory access rhythm control. Since the maximum memory access width of the processor designed in the application is 64 bits, and the instruction cache / data cache accesses in byte units, therefore, in addition to the byte-level access instruction, the rest such as half word, word, double word access and the like may appear the address misalignment condition. Figure 5As shown, taking 32-bit single-word access (lw / sw) as an example, if the starting address is not aligned, two consecutive accesses are required to completely obtain the target data, wherein different gray areas represent the lowest bytes of the starting access address of the instruction, and each square represents a byte. For double-word access instructions (such as ld / sd), it is specified that it must be aligned by word, so the unaligned case is relatively limited, and there is only a single mode.

[0082] To efficiently deal with multi-granularity access control and alignment, the present application designs two independent finite state machines for the access module: a Load-type access control state machine and a Store-type access control state machine, which are respectively used to describe the state transition process of Load instructions and Store instructions. The Load-type access control state machine is as shown in Figure 6 The Load / Store access flag (i_isLoad_1 / i_isStore_1) signal is used to identify the current instruction as a Load-type / Store-type instruction, the access type bit (i_lsuType_2) signal is used to identify the access type of the current instruction, and it is specified that i_lsuType_2 is 2’b00, 2’b01, 2’b10, and 2’b11, which are byte access, half-word access, double-word access, and single-word access, respectively. The unaligned access flag (o_misaligned_1) signal is used to identify whether the current access address is aligned, and the circular box represents the states of the control state machine, which are idle state (state_IDLE), reset state (reset), byte load end state (state_LoadByteEnd), unaligned half-word load transition state (state_LoadHwordmisa), half-word load end state (state_LoadHwordEnd), unaligned double-word load transition state (state_LoadDwordmisa), double-word load end state (state_LoadDwordEnd), unaligned single-word load transition state (state_LoadWordmisa), and single-word load end state (state_LoadWordEnd). For non-byte access Load instructions, if the address is not aligned, the state machine will enter the corresponding "unaligned processing state" (such as state_LoadWordMisa) from the initial state, and in this state, the access module completes the first incomplete data access, and then enters the "access end state" (such as state_LoadWordEnd) to continue the second access, until the target data is completely obtained; if the address is aligned, the intermediate state is directly skipped, and the access is completed once. The state transition logic of the Store instruction is basically the same as that of the Load instruction, except that the Store instruction does not require a write-back operation, so its state machine structure is slightly different. As shown in Figure 7As shown, the Store type memory access control state machine adopts similar strategy for address alignment and data segment processing logic, and completes data splitting and assembly for cross-border write operation through state transition, so as to ensure the correctness and consistency of memory access operation. The state-based memory access control method not only enhances the processing capacity of the memory access module for complex memory access behavior, but also effectively supports multi-granularity data access and efficient processing across address boundaries, and improves the system performance and reliability of the processor.

[0083] The specific implementation method of the multi-word memory access control is as follows:

[0084] The multi-word memory access control is more complex in processing mode compared with other memory controls due to the uncertainty of its access data size, so the present application processes it separately. The granularity memory can access up to 16 registers at the same time in theory, that is, the maximum data size can reach 16*32 bits. Since its state update and data transmission mechanism are significantly different from the other memory instructions, it needs to be designed separately in the asynchronous microprocessor design.

[0085] The multi-word Load type memory access control flow is as shown in Figure 8 The execution logic is mainly based on a 16-bit register flag bit, which indicates the current general register set to be written back. First, perform a bitwise OR operation on the flag bit to determine whether there are still registers to be accessed, which must be 1 in the initial state. Then, starting from the low bit, identify the lowest two values of 1 as the register numbers to be written back in the current cycle. After obtaining the register numbers, obtain the correct data through the data transfer center and update the data, which is consistent with the single-word Load instruction. In the presence of address misalignment and other special cases, it may only complete one register data write-back in a cycle. After completing a write-back, the 16-bit register flag bit needs to be updated to 0, and the current memory access address needs to be updated, since the system reads 64-bit data each time, so the address increment value is 8. Then enter the next cycle to continue to judge and process the read and write operations of the subsequent registers, until all bits of the 16-bit register flag bit are 0, which indicates that the execution of the current multi-word Load instruction is completed.

[0086] The multi-word Store type memory access control flow is as shown in Figure 9As shown, the multi-word Load type memory access control is consistent with the overall execution mechanism. The difference is that the data source is the general register file (GRF), and the data to be written needs to be read according to the state of the flag in the 16-bit register flag bit, and a batch access is performed in a group of 64 bits. After the data is read, the same data update operation as the single-word Store is performed, including address alignment check and access size calculation. After determining the specific write content and write size, the corresponding bit in the 16-bit register flag bit is modified to indicate that the register data has been delivered. The remaining operations are consistent with the multi-word Load type memory access control process, including updating the memory address, judging and executing the next round of loop until the instruction is completely finished.

[0087] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An asynchronous multi-granularity memory access control method in a microprocessor, characterized in that, Includes the following steps: S1. Use the memory access module to unpack the received data and determine whether memory access is required; organize the data that does not need memory access and send it to the write-back module, then the memory access ends; for the data that needs memory access, determine whether it is a multi-word memory access. If yes, proceed to step S2; otherwise, proceed to step S5. S2. Update the memory access list and check if the memory access list is empty. If it is empty, the memory access ends. If it is not empty, integrate the data before the memory access and check if the access address is aligned. If it is aligned, set the memory access count register to 1; if it is not aligned, set the memory access count register to 2. S3. After the memory access count register is reset, the memory access module interacts with DataRout, increments the memory access counter by 1, and determines whether the memory access counter is less than the memory access count register. If so, it continues to interact with DataRout; otherwise, it executes step S4. S4. Integrate the data after memory access and determine whether it is a load instruction. If so, organize the data and send it to the write-back module, and execute step S2; otherwise, execute step S2 directly. S5. Integrate the data before memory access and determine whether the access address is Icache. If it is, read Icache and update the memory access status. If not, the memory access module interacts with DataRout and updates the memory access status. S6. After the memory access status is updated, determine whether the current memory access status is idle. If yes, proceed to step S7; otherwise, proceed to step S5. S7. After integrating the data from the memory access, determine whether it is a load instruction. If so, organize the data and send it to the write-back module, and the memory access ends. If not, organize the data and send it to the dispatch module, and the memory access ends.

2. A memory access module, characterized in that, The memory access module employs a delay-limited asynchronous circuit to implement the asynchronous multi-granularity memory access control method in the microprocessor described in claim 1. The delay-limited asynchronous circuit includes an asynchronous controller and an asynchronous micropipeline structure based on a "transmit-relay-receive" structure. The asynchronous event structures in the asynchronous micropipeline structure include: Source, Trap, Splitter, Selector, WaitMerge, Wait, ArbMerge, and MutexMerge. The memory access module includes a memory access state management module, a data access update module, an instruction / data cache and peripheral interaction interface, and a data interaction interface with the write-back module. The memory access state management module includes a Load-type memory access control state machine and a Store-type memory access control state machine, respectively used to describe the state transition process of Load instructions and Store instructions. The data access update module updates the old data accordingly using combinational logic based on the control state bits output by the memory access state management module. The old data refers to the original data that needs to be processed in the data access update module.

3. The memory access module as described in claim 2, characterized in that, The asynchronous controller used is the Click asynchronous controller.

4. The memory access module as described in claim 2, characterized in that, The "send-relay-receive" structure includes Sender, Relay, and Receiver, where: Sender: Includes a flip-flop, an inverter, and a delay module. When it receives the drive pulse signal i_drive, Sender flips the output level signal. The input pulse signal i_free is delayed by the delay module and outputs as o_free. Relay: Composed of XOR gates, XNOR gates, AND gates, D flip-flops, inverters, and delay modules, it is implemented based on the Click asynchronous controller; Receiver: Includes a trigger that is activated when the next-level pulse signal i_freeNext is received.

5. The memory access module as described in claim 2, characterized in that, In the asynchronous event structure: The source includes an inverter and a delay unit, which use the phase difference to generate a pulse event signal; The Trap includes a delay unit that outputs the input pulse after a delay. Splitter includes: Contap, AND gate, OR gate, and NOR gate; Selectors include: Sender, Relay, Receiver, AND gate, and NOT gate; WaitMerge includes: Contap, AND gate, OR gate; Wait includes: Contap, AND gate, OR gate; ArbMerge includes: cFifo, cPmtFifo, ConTap, AND gate, OR gate, inverter, and flip-flop; cFifo includes Sender, Relay, and Receiver, which receives the input event pulse signal, generates timing control signals, and outputs the event pulse signal of the next stage; cPmtFifo includes Sender, Relay with enable mechanism, Receiver, and delay unit, which receives the input event pulse signal, generates timing control signals, and outputs the event pulse signal of the next stage when the enable signal is high. MutexMerge includes: Contap, AND gate, OR gate, and multiplexer; The Contap uses a sender that does not generate a free signal. The Contap includes a trigger and an inverter to convert pulse signals into level signals.

6. The memory access module as described in claim 2, characterized in that, The instruction / data cache and peripheral device interaction interface includes a Selector and a MutexMerge. The Selector is located at the memory access request issuing end and is used to determine whether the data flows to the instruction / data cache or the peripheral device based on the memory access address. The MutexMerge is located at the return end and is used to receive data and events returned from the instruction / data cache or the peripheral device.

7. The memory access module as described in claim 2, characterized in that, The data interaction interface with the write-back module includes MutexMerge, which is used to receive data and events sent to the write-back module by non-memory access instructions or memory access instructions.

8. The memory access module as described in claim 2, characterized in that, The control status bits include memory access type bits, memory access flag bits, and unaligned memory access flag bits.

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