Method and device for diagnosing basic input / output system, storage medium and server

Abstract

The application discloses a basic input and output system diagnosis method and device, a storage medium and a server, relates to the technical field of computers, and comprises the following steps: determining whether to use virtual topology information to acquire PCIe link information; in the case of determining yes, determining the hierarchical relationship of each node in the PCIe link according to the virtual topology information to obtain corresponding PCIe link information; and reporting the PCIe link information to a baseboard management controller to realize the diagnosis of the basic input and output system by the baseboard management controller. By introducing the concept of virtual topology information, since the virtual topology information simulates the link structure of actual PCIe devices, the function test of the basic input and output system is allowed to be performed without physical PCIe devices, the function of the basic input and output system for reporting PCIe link information is verified through the virtual topology information, and the problems of low development efficiency and poor flexibility of the basic input and output system are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of simulation development debugging, and particularly relates to a basic input output system diagnosis method and device, a storage medium and a server. BACKGROUND

[0002] In a server startup process, a BIOS (Basic Input Output System) is responsible for reporting asset information of a PCIe (Peripheral Component Interconnect Express) device to a BMC (Baseboard Management Controller), so that the BMC can locate to a specific PCIe device after a PCIe fault occurs.

[0003] A general development mode of the BIOS reporting asset information is as follows: first, BIOS code is developed, then the BIOS code is verified through a hardware entity device, if there is a problem, debugging is performed, the code is modified, until the design requirements are met. The verification of the PCIe asset information reporting function of the BIOS is heavily dependent on hardware devices, and in the absence of an entity PCIe device, the development and verification work of the BIOS is difficult to perform, which directly lengthens the development cycle of the BIOS scheme and limits the flexibility and efficiency of the development. SUMMARY

[0004] The present application provides a basic input output system diagnosis method and device, a storage medium and a server to at least solve the problem in the related art that the development of the BIOS is heavily dependent on hardware devices, resulting in low development efficiency.

[0005] The present application provides a basic input output system diagnosis method, comprising: determining whether to obtain PCIe link information by using virtual topology information, the virtual topology information being obtained by simulating a topology structure of a PCIe hardware device; in a case where it is determined to obtain the PCIe link information by using the virtual topology information, determining the PCIe link information corresponding to the virtual topology information according to the virtual topology information; and reporting the PCIe link information to a baseboard management controller, so that the baseboard management controller performs fault diagnosis on the basic input output system according to the PCIe link information.

[0006] The application further provides a diagnosis device of a basic input and output system, comprising: a first determination unit configured to determine whether to acquire PCIe link information by using virtual topology information, wherein the virtual topology information is obtained by simulating a topology structure of a PCIe hardware device; a second determination unit configured to, in a case where it is determined to acquire the PCIe link information by using the virtual topology information, determine the PCIe link information corresponding to the virtual topology information according to the virtual topology information; and a reporting unit configured to report the PCIe link information to a baseboard management controller, so that the baseboard management controller performs fault diagnosis on the basic input and output system according to the PCIe link information.

[0007] The application further provides a computer readable storage medium, wherein a computer program is stored in the computer readable storage medium, and the computer program is configured to implement the steps of any of the diagnosis methods of the basic input and output system when executed by a processor.

[0008] The application further provides a server, comprising: a basic input and output system, comprising: a memory configured to store a computer program; and a processor configured to implement the steps of any of the diagnosis methods of the basic input and output system when executing the computer program; and a baseboard management controller connected to the basic input and output system, configured to receive PCIe link information reported by the basic input and output system, and perform fault diagnosis on the basic input and output system according to the PCIe link information.

[0009] According to the application, it is firstly determined whether to acquire PCIe link information by using virtual topology information; in a case where it is determined to acquire the PCIe link information by using the virtual topology information, the hierarchical relationship of each node in a PCIe link is determined according to the virtual topology information, and corresponding PCIe link information is obtained; and finally, the obtained PCIe link information is reported to a baseboard management controller, so that the baseboard management controller performs diagnosis on a basic input and output system. By introducing the concept of virtual topology information, since the virtual topology information simulates the link structure of an actual PCIe device, the application allows functional testing of the basic input and output system without physical PCIe devices, realizes verification of the function of reporting PCIe link information by the basic input and output system through the virtual topology information, and does not need to rely on hardware PCIe devices, thereby solving the problems of low development efficiency and poor flexibility of the basic input and output system in a traditional mode. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the application, the drawings required to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0011] Figure 1 is a hardware structure block diagram of a method for performing a basic input / output system diagnosis according to an embodiment of the present application;

[0012] Figure 2 is a flowchart of a method for performing a basic input / output system diagnosis according to an embodiment of the present application;

[0013] Figure 3 is a schematic diagram of a structure chain table according to an embodiment of the present application;

[0014] Figure 4 is a flowchart of another method for performing a basic input / output system diagnosis according to an embodiment of the present application;

[0015] Figure 5 is a structure block diagram of a basic input / output system diagnosis apparatus according to an embodiment of the present application.

[0016] In the above drawings, reference numerals:

[0017] 102, processor; 104, memory; 106, transmission device; 108, input / output device. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0019] It should be noted that, in the description of the present application, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0020] In order to enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0021] In combination with the specific application environment architecture or specific hardware architecture on which the basic input / output system diagnosis method is dependent, the specific application environment architecture or specific hardware architecture is described here.

[0022] The method provided in the embodiments of the present application can be executed in a server device or similar computing device. Taking the case of running on a server device, Figure 1 is a hardware structure block diagram of the basic input / output system diagnosis method of the embodiments of the present application. As shown in Figure 1 , the server device can include one or more (only one is shown in Figure 1 ) processors 102 (the processor 102 can include, but is not limited to, a central processing unit CPU, a microprocessor MCU, or a programmable logic device FPGA, etc. processing device) and a memory 104 for storing data, wherein the above-mentioned server device can also include a transmission device 106 for communication function and an input / output device 108. Those skilled in the art can understand that Figure 1 The structure shown is only schematic, which does not limit the structure of the above-mentioned server device. For example, the server device can also include more or less components than Figure 1 shown, or have a different configuration than Figure 1 shown.

[0023] The memory 104 can be used to store computer programs, such as software programs of application software and modules, such as the computer program corresponding to the basic input / output system diagnosis method of the embodiments of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implements the above-mentioned method. The memory 104 can include a high-speed random access memory, and can also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 can further include a memory remotely arranged with respect to the processor 102, which can be connected to the server device through a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0024] The transmission device 106 is used to receive or send data via a network. The specific examples of the above-mentioned network can include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet in a wireless manner.

[0025] The embodiments of the present application provide a basic input / output system diagnosis method, which is described in detail in combination with the execution flow of the basic input / output system diagnosis method.

[0026] In the embodiment, a diagnosis method of a basic input and output system is provided, and the method can be applied to the BIOS. Figure 2 is a flowchart of a diagnosis method of a basic input and output system according to an embodiment of the application, as shown in the figure, the method comprises the following steps: Figure 2

[0027] In step S202, it is determined whether to obtain PCIe link information by using virtual topology information, wherein the virtual topology information is obtained by simulating the topology of PCIe hardware devices.

[0028] In step S204, in the case of determining to obtain the PCIe link information by using the virtual topology information, the PCIe link information corresponding to the virtual topology information is determined according to the virtual topology information.

[0029] In step S206, the PCIe link information is reported to a baseboard management controller, so that the baseboard management controller performs fault diagnosis on the basic input and output system according to the PCIe link information.

[0030] Through the above steps, firstly, it is determined whether to obtain PCIe link information by using virtual topology information; in the case of determining to do so, the hierarchical relationship of each node in the PCIe link is determined according to the virtual topology information to obtain corresponding PCIe link information; finally, the obtained PCIe link information is reported to a baseboard management controller to realize the diagnosis of the basic input and output system by the baseboard management controller. By introducing the concept of virtual topology information, since the virtual topology information simulates the link structure of the actual PCIe device, the application allows the functional test of the basic input and output system without physical PCIe devices, realizes the verification of the PCIe link information reporting function of the basic input and output system by the virtual topology information, and does not need to rely on hardware PCIe devices, solving the problems of low development efficiency and poor flexibility of the basic input and output system in the traditional mode.

[0031] The technology of the application can be applied to the development stage of the basic input and output system, so that the developer can verify the PCIe link information reporting function of the basic input and output system without relying on hardware devices, which can significantly shorten the development cycle of the basic input and output system and improve its code quality. In addition, based on the virtual topology information, the basic input and output system can be functionally tested at the development stage, which means that potential problems can be found and repaired at an early stage of code writing, avoiding complex errors that may be encountered in the later hardware debugging stage, greatly reducing the development cost and risk.

[0032] ​In the embodiment provided in step S202, the virtual topology information simulates the link structure of an actual PCIe device. Optionally, the virtual topology information can be configured based on known PCIe devices and their connections or imagined PCIe devices and their connections; it can also be generated by reading PCIe topology information from an existing system (possibly a system in a simulation environment); or it can be obtained by generating a random topology structure from a PCIe device database. For example, the virtual topology information can be generated according to the actual PCIe topology structure displayed by Lspci (command-line tool) under Linux OS (Operating System).

[0033] In the embodiment provided in step S204, the basic input / output system uses virtual topology information as the input parameter of the PCIe device information collection function, and feeds it to the PCIe layer processing and reporting function to extract and organize PCIe link information from the virtual topology information.

[0034] In the embodiment provided in step S206, the monitoring and management functions of the baseboard management controller are utilized, enabling it to diagnose the reporting function of the basic input / output system based on the received PCIe link information. Optionally, after the basic input / output system completes the collection and reporting of PCIe link information, the baseboard management controller receives the PCIe link information reported by the basic input / output system and compares it with pre-stored expected link information to determine whether the information reported by the basic input / output system matches the expected topology. If the reported PCIe link information includes all expected devices and correctly reflects their connection levels, then the PCIe link information reported by the basic input / output system can be judged to be correct, thereby achieving fault diagnosis of the basic input / output system's PCIe link information reporting function.

[0035] In other embodiments, virtual topology information of varying complexity can be constructed to cover the topologies of PCIe devices of different brands and models. This ensures that even when faced with complex PCIe topologies, the basic input / output system can accurately report link information, thereby enhancing the compatibility and robustness of the basic input / output system.

[0036] Since virtual topology information can simulate various topologies, the solution in this application can cover a variety of PCIe link scenarios, including those that are difficult to reproduce in real-world environments due to hardware limitations. This extensive test coverage helps ensure the compatibility and robustness of the BIOS with various PCIe devices.

[0037] As an optional implementation, the virtual topology information includes multiple nodes and attribute information of each node. The multiple nodes include a root port (RP), an end point (EP), and a downstream port (DSP) of a switch. The attribute information includes bus information, device information, and functional information. Based on the virtual topology information, the PCIe link information corresponding to the virtual topology information is determined, including: starting from the root node, traversing the bus information, device information, and functional information in the virtual topology information to determine the link length of the PCIe link; starting from the end point, traversing the bus information in the virtual topology information to determine the hierarchical relationship information representing the arrangement order of the multiple nodes. The PCIe link information includes the link length and the hierarchical relationship information.

[0038] In the aforementioned implementation scheme, a virtual environment containing root nodes, terminal nodes, and downstream nodes of the switch is constructed in the absence of actual hardware. By defining the attribute information of these nodes, such as bus information, device information, and functional information, a PCIe topology is simulated, providing significant flexibility and variability for BIOS testing. Furthermore, by traversing the node attribute information in the virtual topology information starting from the root node, and using the bus information, device information, and functional information in the virtual topology information to identify each node in the link, the link length can be determined. This accurately reflects the path length of data from the CPU (or root bridge) to each terminal device, helping the BIOS accurately assess the complexity of the PCIe link in the virtual environment and providing important basis for subsequent link information processing and reporting. By traversing the bus information in the virtual topology information backward from the terminal node, tracing the hierarchical relationship representing the arrangement order of multiple nodes, the PCIe link hierarchy structure from the terminal to the root node can be clearly and completely constructed.

[0039] Specifically, the aforementioned bus information describes the logical connections and hierarchy between PCIe devices, and the aforementioned device information describes the specific attributes of each PCIe device. The aforementioned functional information refers to the multiple functions or services supported by each PCIe device, each function having its own attributes. Optionally, the bus information of the aforementioned root node and the aforementioned terminal nodes may include bus number (i.e., bus ID), bus width, and bus speed, etc. The bus information of the downstream nodes of the aforementioned switch may include upstream bus range (i.e., the range of upstream primary bus IDs), downstream bus range (i.e., the range of downstream secondary bus IDs), subordinate bus range (i.e., the range of subordinate bus IDs), bus width, and bus speed, etc. The aforementioned device information may include device ID, vendor ID, device type, device function, class code, revision ID, and at least a portion of the configuration space. The aforementioned functional information may include at least a portion of the function ID, interrupt number, configuration registers, I / O, and memory space. Bus information, device information, and functional information together constitute a complete description of a PCIe device; they are interrelated and help the system identify and configure PCIe devices. In the BIOS and BMC, this information is used to initialize hardware, configure resources, monitor status, and diagnose faults. By accurately collecting and processing this information, the system can ensure the correct operation and efficient management of all PCIe devices.

[0040] In other embodiments, starting from the terminal node, traversing the bus information in the virtual topology information to determine the hierarchical relationship information representing the arrangement order of the multiple nodes includes: a first traversal step, starting from the terminal node, traversing the bus information to determine the parent node of the terminal node and obtaining a first node; a second traversal step, if the obtained first node is the downstream node, starting from the first node, traversing the bus information in the virtual topology information to determine the parent node of the first node and obtaining a new first node; a repetition step, repeating the second traversal step at least once until the obtained first node is the root node; and a determination step, if the obtained first node is the root node, determining the hierarchical relationship information.

[0041] The above embodiments utilize bus information as the basis for the association between nodes. Through a series of traversal steps, starting from the terminal node, the upper-level node is determined by comparing the bus information of the node, until the root node is reached. In this way, the hierarchical relationship of the nodes in the PCIe link can be determined step by step, ensuring the accurate construction of the hierarchical relationship information. Even when facing a multi-level PCIe topology, the integrity and accuracy of the hierarchical relationship information can be guaranteed.

[0042] In the above determination steps, if the first node obtained is the root node, the link from the terminal node, through or without passing through the downstream node, to the root node is sorted out throughout the traversal process to obtain the above hierarchical relationship information.

[0043] In other embodiments, the traversal process can be optimized, memory usage reduced, and processing speed improved by introducing auxiliary data structures such as stacks or queues.

[0044] Furthermore, the above embodiments only illustrate how to determine the hierarchical relationship information of a single PCIe link. When there are multiple PCIe links, the hierarchical relationship information of each PCIe link can be obtained by iteratively executing the above embodiments. Moreover, by traversing the bus information, device information, and functional information starting from the root node, the link length of each PCIe link can be obtained.

[0045] According to other embodiments of this application, the method of traversing the bus information in the virtual topology information can be to use a depth-first search algorithm or a breadth-first search algorithm to traverse all the bus information.

[0046] In some alternative embodiments, starting from the root node, the link length of the PCIe link is determined by traversing the bus information, device information, and function information in the virtual topology information. This includes: determining the bus corresponding to the root node based on the bus information of the root node, scanning all device information and function information on the bus to find the node connected to the bus, and setting the current link length to "1"; scanning all device information and function information on the downstream bus connected to the node based on the bus information of the node, finding new nodes, and updating the current link length to "2"; repeating the previous step until the found node is an end node, and updating the current link length to obtain the final link length of the PCIe link.

[0047] In some embodiments, the bus information of the downstream node includes an upstream bus range, a downstream bus range, and a slave bus range. The second traversal step includes: starting from the first node, traversing the bus information to determine a first target range, wherein the upstream bus range of the first node is located within the first target range, and the first target range is the downstream bus range and / or the slave bus range, that is, the first target range is the downstream bus range and / or the slave bus range that covers the upstream bus range of the first node; if there are multiple first target ranges, determining the downstream node corresponding to the smallest range among the multiple first target ranges as the new first node; if there is only one first target range, determining the downstream node corresponding to the first target range as the new first node.

[0048] In the above embodiments, bus range information is used to determine whether the current node is downstream of another node, thereby identifying its superior node. This method effectively avoids errors in constructing hierarchical relationship information, further improving the accuracy of PCIe link information reporting by the Basic Input / Output System (BIOS). Specifically, this embodiment utilizes the overlapping characteristics of bus ranges between nodes in a PCIe link, i.e., the upstream bus range of a downstream node must be located downstream of its superior node or within its subordinate bus range, to accurately find the superior node of the first node. This ensures that no node is missed during the construction of hierarchical relationship information, improving the completeness and reliability of information reporting. This embodiment also utilizes the uniqueness of bus ranges between nodes in a PCIe link. When the bus ranges of multiple nodes meet the conditions, the correct superior node is determined by the range size, i.e., the smallest range is selected as the new first node. This avoids ambiguity in the construction of hierarchical relationship information, further improving the accuracy and consistency of PCIe link information reporting. When only one node's bus range meets the conditions, it can be directly identified as the superior node, simplifying the construction process of hierarchical relationship information.

[0049] Optionally, the relationships between nodes can be further distinguished by adding additional bus information, such as bus ID and bus type; the determination of the first target range can be accelerated and the processing efficiency improved by introducing more efficient search algorithms, such as binary search and hash search; and the correctness of the minimum range nodes can be further confirmed and the robustness of the BIOS can be enhanced by adding correlation checks between nodes, such as device ID and function ID.

[0050] In other embodiments, the bus information of the terminal node includes a bus number, and the bus information of the downstream node includes a downstream bus range. The first traversal step includes: traversing the bus information starting from the terminal node to determine a second target range, wherein the second target range is the downstream bus range in which the bus number of the terminal node is located, that is, the bus number of the terminal node is located within the second target range, and the second target range is a downstream bus range; and determining the downstream node corresponding to the second target range as the first node. This solution, by starting from the terminal node and searching for the downstream bus range in which its bus number is located, can quickly determine the first node directly connected to the terminal node (usually a port of a Switch or Bridge). This process avoids a full traversal starting from the root node, significantly improving the speed and efficiency of locating the connection relationship between nodes.

[0051] As an optional implementation, after determining the link length of the PCIe link and before determining the hierarchical relationship information representing the arrangement order of the multiple nodes, the method further includes: creating a structure based on the link length, the structure including multiple elements; filling the structure with multiple attribute information according to the principle that one element corresponds to one node, the multiple nodes being arranged randomly in the structure; after determining the hierarchical relationship information representing the arrangement order of the multiple nodes, the method further includes: configuring the pointer field of the structure based on the hierarchical relationship information to obtain a first structure linked list of the PCIe link.

[0052] The above implementation method pre-creates a structure based on the link length and utilizes the array characteristics of the structure to fill the nodes and their corresponding attribute information into the structure in an unordered manner. This enables efficient storage and management of node information in the PCIe link and ensures the complete storage of node information. Furthermore, based on the hierarchical relationship information, the unordered node information is transformed into an ordered linked list structure by configuring the pointer fields of the structure. The pointer fields are used to link the elements in the structure to form a linked list that reflects the node hierarchical relationship. This method ensures the orderliness and consistency of PCIe link information and further improves the efficiency and accuracy of BIOS reporting PCIe link information.

[0053] In other embodiments, node information can also be stored using other data structures, such as linked lists or dictionaries, to adapt to dynamic changes in the number of nodes and improve the adaptability of the BIOS.

[0054] In practical applications, the virtual topology information mentioned above can be linked list information, which includes root node information, terminal node information, and downstream node information of each switch. Each downstream node includes information on the downstream bus range and the slave bus range. The nodes in the virtual topology information do not need to be arranged in order; only the bus number needs to meet the link requirements.

[0055] For example, based on the PCIe topology displayed by Lspci under Linux OS, one RP, four SWITCHDSPs, and one EP are needed to construct the virtual topology information. Based on this topology, the Basic Input / Output System (BIOS) constructs a structure in its code and then fills this structure with node information. The nodes in this structure do not need to be arranged according to the bus order; they can be randomly arranged, as long as the bus numbers are correct. Then, the structure is adjusted according to the hierarchical relationship information to obtain a linked list of structures reflecting the node hierarchy, such as... Figure 3 As shown, in the structure linked list, RootPort, ..., Switch DSP 2, Switch DSP 1, and End Point are arranged sequentially according to their bus numbers. The data structure of each Switch DSP includes BUS information, DEVICE information, FUNCTION information, Vendor ID, and Device ID.

[0056] As another optional implementation, after determining the hierarchical relationship information representing the arrangement order of the multiple nodes, the method further includes: creating an empty structure linked list; and filling the empty structure linked list according to the hierarchical relationship information and the virtual topology information, so that the multiple nodes are arranged in the structure according to the order represented by the hierarchical relationship information, thereby obtaining the second structure linked list of the PCIe link. This embodiment, by creating an empty structure linked list and filling the node information according to the hierarchical relationship information, can efficiently construct complete PCIe link information.

[0057] In other embodiments, other data structures, such as balanced trees and graph databases, can be used to further optimize the storage and access of node information, improve processing speed and space utilization, especially in large-scale PCIe topologies.

[0058] In specific applications, there are multiple PCIe links. Before reporting the PCIe link information to the baseboard management controller (BMC), the method further includes: setting a memory space based on the maximum value among the multiple link lengths; storing the PCIe link information in JSON format in the memory space; and adding a Cyclic Redundancy Check (CRC) code to the PCIe link information. In this embodiment, setting the memory space based on the longest link length ensures the complete storage of all PCIe link information. Furthermore, this application utilizes the flexibility and readability of the JSON format to store the link information in JSON format, facilitating the BMC's parsing and use of this information after it is reported to the BMC. Moreover, by adding a CRC code to the PCIe link information, the integrity of the information and the reliability of data transmission are ensured.

[0059] In other embodiments, efficient data encoding methods such as protobuf and msgpack can be used to further compress the storage space of PCIe link information and improve the transmission speed.

[0060] Optionally, the aforementioned basic input / output system has a predefined interface, and the method further includes: when it is determined that the aforementioned virtual topology information is used to obtain the aforementioned PCIe link information, receiving the aforementioned virtual topology information through the aforementioned predefined interface. This embodiment receives virtual topology information through a predefined interface, ensuring that the virtual topology information can be correctly parsed and used by the BIOS. Utilizing the standardized characteristics of the interface, even in different development environments, virtual topology information can be input through a unified interface, improving the convenience and flexibility of using virtual topology information and lowering the development and testing threshold.

[0061] In practical applications, the above-mentioned predefined interfaces are software interfaces, including but not limited to UI (User Interface) and programming interfaces.

[0062] The specific implementation methods of the above predefined interfaces include, but are not limited to, the following:

[0063] 1. Define a data linked list directly in the BIOS source code, and adjust the length and data content of the linked list in the code to construct different topology data structures. The BIOS can use this data linked list to simulate the traversal of PCIe link information during the boot process.

[0064] 2. Out-of-band transfer via shared memory of BMC: A shared memory region is allocated, and virtual topology information can be directly written into this region through BMC. Then, the content of this region is marked as valid. When the BIOS reads that the content of this region is valid, it uses this data for traversal.

[0065] 3. The BIOS builds a SETUP display input interface (i.e., UI), through which users can input virtual topology information.

[0066] Furthermore, the above method also includes: when it is determined that the PCIe link information will not be obtained using the virtual topology information, determining that the PCIe link information will be obtained through the PCIe hardware device, and scanning the PCIe hardware device; constructing a PCIe bridge device information table based on the scan results; and determining the PCIe link information based on the PCIe bridge device information table. This application also supports scanning actual PCIe hardware devices to determine PCIe link information. Based on the physical characteristics of the PCIe hardware devices, scanning can obtain attribute information of all connected PCIe devices, including bus information, device information, and functional information, ensuring that the BIOS can accurately obtain and report PCIe link information in a real environment.

[0067] Specifically, the aforementioned PCIe bridge device information table refers to a data structure or database used to describe the characteristics and connection attributes of bridging devices in a PCIe topology. Optionally, scanning the aforementioned PCIe hardware devices includes: scanning the aforementioned PCIe hardware devices through the aforementioned predefined interface to obtain scan results.

[0068] According to some optional embodiments of this application, determining whether to use virtual topology information to obtain PCIe link information includes: determining whether an access signal of the PCIe hardware device is received; if the access signal is received, obtaining the device information of the accessed PCIe hardware device and comparing whether the device information is consistent with the pre-stored device information; if the device information is consistent with the pre-stored device information, determining not to use the virtual topology information to obtain the PCIe link information. In this embodiment, by detecting the access status of PCIe hardware devices, once a signal indicating PCIe hardware device access is captured, the Basic Input / Output System (BIOS) reads and extracts the device information and compares it with pre-stored device information data to confirm the identity and consistency of the PCIe hardware device, enhancing system security. Based on the comparison result, the BIOS makes a decision on whether to use virtual topology information. That is, if the hardware device information matches the pre-stored information, it indicates that the actual hardware is in place, and therefore virtual topology information is not needed. This scheme allows the system to prioritize the use of real hardware to construct link information when PCIe hardware devices are available, making the acquisition and reporting of PCIe link information more direct and accurate. When the corresponding hardware is lacking, it automatically switches to virtual topology information. Virtual topology information provides a basis for testing and development, enabling development work to be carried out in advance, greatly saving waiting time for hardware and improving overall development efficiency.

[0069] According to some alternative embodiments of this application, determining whether to use virtual topology information to obtain PCIe link information includes: reading the virtual topology information; if the read virtual topology information is not empty, determining that the virtual topology information is used to obtain the PCIe link information; if the read virtual topology information is empty, determining that the virtual topology information is not used to obtain the PCIe link information. This embodiment can automatically determine whether to use virtual topology information to obtain PCIe link information by reading the state of the virtual topology information. Using the presence or absence of virtual topology information as the basis for judgment, when virtual topology information exists, it is used; when virtual topology information does not exist, the actual hardware device is used to obtain the PCIe link information. This method can automatically adapt to different stages of development and testing, improving the flexibility and practicality of the BIOS.

[0070] In other embodiments, the method of obtaining PCIe link information can be further optimized by introducing more judgment conditions, such as device type and operating system version, thereby improving the system's compatibility and stability.

[0071] According to some alternative embodiments of this application, determining whether to use virtual topology information to obtain PCIe link information includes: reading the switch state of a predefined switch, which indicates the method for obtaining the PCIe link information; and determining whether to use virtual topology information to obtain the PCIe link information based on the switch state. For example, if the switch is in the open state, it is determined that virtual topology information will be used to obtain the PCIe link information; if the switch is in the closed state, it is determined that virtual topology information will not be used, and the PCIe link information will be obtained through the PCIe hardware device instead. As another example, if the switch is in the closed state, it is determined that virtual topology information will be used to obtain the PCIe link information; if the switch is in the open state, it is determined that virtual topology information will not be used, and the PCIe link information will be obtained through the PCIe hardware device instead. The setting of the predefined switch allows system administrators or developers to dynamically select whether to use real hardware bus information or virtual topology information based on the current hardware configuration and requirements, enabling the system to immediately respond to different acquisition method commands during startup or runtime, switching acquisition modes without recompiling code or restarting the system. In the early stages of software and hardware development, physical PCIe devices may not yet be fully ready. By setting a predefined switch to point to virtual topology information, development teams can perform functional testing and code debugging without hardware, accelerating the development process and ensuring that the BIOS software reaches the expected maturity and stability before the hardware is in place. Even after the hardware devices are connected, this switch still helps developers verify the software's compatibility with different types of hardware. By toggling the switch state, testing can be conducted back and forth between real and virtual environments, ensuring that the BIOS code still works accurately when facing different PCIe devices, improving the overall system compatibility and robustness.

[0072] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the diagnostic method for the basic input / output system of this application will be described in detail below with reference to specific embodiments.

[0073] This embodiment relates to a specific diagnostic method for a basic input / output system, such as... Figure 4 As shown, it includes the following steps:

[0074] Step S1: The BIOS predefines virtual topology information and interfaces, and then executes step S2;

[0075] Step S2: The BIOS initializes the virtual topology information, and then proceeds to step S3;

[0076] Step S3: The BIOS determines whether to use virtual topology information. If yes, proceed to step S4; otherwise, proceed to step S6.

[0077] Step S4: The BIOS does not perform a PCIe device scan, and then proceeds to step S5;

[0078] Step S5: The BIOS uses the virtual topology information as an input parameter to the PCIe layer processing and reporting function, and then executes step S7;

[0079] Step S6: The BIOS scans PCIe devices, constructs a PCIe bridge device information table, and passes it as an input parameter to the PCIe layer processing and reporting function, and then executes step S7;

[0080] Step S7: The PCIe layer processing and reporting function processes the input parameters, and then executes step S8;

[0081] Step S8: The BIOS outputs PCIe link information according to the predetermined data format, and then executes step S9;

[0082] Step S9: The BIOS reports PCIe asset information, including PCIe link information, to the BMC.

[0083] In step S1, during the development phase, the BIOS pre-constructs a virtual PCIe topology linked list, which is the aforementioned virtual topology information. The PCIe device information collection function receives this linked list as an input parameter. When this linked list is empty, it indicates that actual hardware devices need to be scanned to construct the Bridge list, which depends on the hardware devices. When this linked list is not empty, it indicates that a virtual linked list is used, and hardware devices do not need to be scanned; this virtual linked list is directly used as the Bridge list.

[0084] In step S7, when using virtual topology information, the SWITCH DSPs are disorganized because it is necessary to start from EP and search upwards to find the SWITCH DSP closest to EP. Then, starting from the DSP, the search continues upwards to the next higher level until RP is finally found. The specific algorithm is as follows:

[0085] (1) First, traverse the length (also known as depth) of the entire PCIe link of the device, and use the depth of the longest link as the basis for requesting memory space;

[0086] (2) After knowing the link depth, start traversing the entire virtual topology information based on the entire depth. First, use the EP's Bus to query upwards which SWITCH DSP's Second Bus is consistent with the EP Bus. If they are consistent, it means that the EP's previous level has been found.

[0087] (3) After finding the upper layer of the EP, starting from the entire SWITCH DSP, search upward to see which range of the Second Bus and Subordinate Bus of a SWITCH the Primary Bus of the SWITCH falls into. There may be multiple SWITCHes that meet the requirements, and it is necessary to compare the sizes of the buses to find the SWITCH that falls within the smallest range as the upper layer. For example, if two SWITCH DSPs meet the requirements, then it is necessary to compare which of the two SWITCH DSPs has a smaller range and use the one with the smaller range as the upper layer. For example:

[0088] SWITCH DSP 1: Second Bus < Primary Bus < Subordinate Bus; SWITCH DSP 2: Second Bus < Primary Bus < Subordinate Bus; and SWITCH DSP 1 Second Bus < SWITCH DSP 2 Second Bus; then select SWITCH DSP 1 as the upper layer;

[0089] (4) Repeat the action in (3), continuously traverse and sort until the topmost RP is found, and then the link layer information of this EP is completed;

[0090] (5) Start traversing the link layers of other EPs again from the action in (1) until the link layers of all EPs are traversed.

[0091] In step S8, it is necessary to fill the information into a certain area, store it in JSON format, and write the CRC information.

[0092] In step S9, notify the BMC that all PCIe device link information is now completed and these information can be used for subsequent fault diagnosis.

[0093] This application proposes a method for pre-testing the BIOS's PCIe link asset information reporting function. The BIOS reserves an interface for transmitting PCIe topology information. This topology information can be obtained by traversing physical hardware devices or it can be virtual PCIe topology information. Once this topology information is available, subsequent BIOS development does not need to rely on hardware devices. Various PCIe topologies can be virtualized based on the virtual PCIe topology information, and the BIOS can then adapt to these topologies, finally outputting results according to a predetermined format. This improves development efficiency and significantly enhances the quality of BIOS development solutions. It reduces the time required for BIOS to adapt to PCIe devices, improves the development efficiency and quality of BIOS developers, and, most importantly, shortens the development cycle and saves development costs by reducing over-reliance on PCIe hardware devices.

[0094] The simulated detection method for server BIOS reporting PCIe asset information proposed in this application changes the traditional development model, which heavily relies on hardware devices for debugging, code modification, and further debugging. By using virtual PCIe topology information, it solves many problems of low development efficiency, heavy reliance on hardware devices for BIOS code verification (verification is impossible if the hardware is not in place), prolonged BIOS solution development cycle, inability to verify BIOS code in advance, inability to detect errors in advance, and incomplete coverage of BIOS code development scenarios. At the same time, virtual PCIe topology information is highly flexible and can simulate and construct arbitrary topology structures. Theoretically, it can verify information at any different PCIe device level, thereby greatly improving BIOS code development efficiency and significantly enhancing the quality of BIOS development solutions.

[0095] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0096] Embodiments of this application also provide a diagnostic device for a basic input / output system. Figure 5 This is a structural block diagram of a diagnostic device for a basic input / output system according to an embodiment of this application, such as... Figure 5 As shown, the device includes:

[0097] The first determining unit 802 is used to determine whether to use virtual topology information to obtain PCIe link information, wherein the virtual topology information is obtained by simulating the topology of the PCIe hardware device.

[0098] The second determining unit 804 is used to determine the PCIe link information corresponding to the virtual topology information based on the virtual topology information when it is determined that the PCIe link information is obtained by using the virtual topology information.

[0099] The reporting unit 806 is used to report the PCIe link information to the baseboard management controller so that the baseboard management controller can perform fault diagnosis on the basic input / output system based on the PCIe link information.

[0100] In the above embodiments, the first determining unit determines whether to use virtual topology information to obtain PCIe link information; if it is determined that virtual topology information should be used to obtain PCIe link information, the second determining unit determines the hierarchical relationship of each node in the PCIe link based on the virtual topology information, and obtains the corresponding PCIe link information; the reporting unit reports the obtained PCIe link information to the baseboard management controller, realizing the baseboard management controller's diagnosis of the basic input / output system. By introducing the concept of virtual topology information, since the virtual topology information simulates the link structure of the actual PCIe device, this application allows functional testing of the basic input / output system without physical PCIe devices, realizing the function of verifying the basic input / output system's reporting of PCIe link information through virtual topology information, without relying on hardware PCIe devices, solving the problems of low development efficiency and poor flexibility of the basic input / output system in the traditional mode.

[0101] The technology presented in this application can be applied to the development phase of a Basic Input / Output System (BIOS), enabling developers to verify the PCIe link information reporting function of the BIOS without relying on hardware devices. This significantly shortens the development cycle of the BIOS and improves its code quality. Furthermore, based on virtual topology information, functional testing of the BIOS can be performed during the development phase. This means that potential problems can be identified and fixed early in the code development process, avoiding complex errors that may be encountered in the later hardware debugging phase, and greatly reducing development costs and risks.

[0102] In the first determining unit, the aforementioned virtual topology information simulates the link structure of actual PCIe devices. Optionally, the virtual topology information can be configured based on known PCIe devices and their connections, or imagined PCIe devices and their connections; it can also be generated by reading PCIe topology information from an existing system (possibly a system in a simulation environment); or it can be obtained by generating a random topology structure from a PCIe device database. For example, the virtual topology information can be generated according to the actual PCIe topology structure displayed by Lspci (a command-line tool) under Linux OS.

[0103] In the second determining unit, the basic input / output system uses virtual topology information as the input parameter of the PCIe device information collection function, and feeds it to the PCIe layer processing and reporting function to extract and organize PCIe link information from the virtual topology information.

[0104] The reporting unit utilizes the monitoring and management functions of the baseboard management controller (BMC) to diagnose the reporting function of the Basic Input / Output System (BIOS) based on the received PCIe link information. Optionally, after the BIOS completes the collection and reporting of PCIe link information, the BMC receives the reported PCIe link information and compares it with pre-stored expected link information to determine whether the reported information matches the expected topology. If the reported PCIe link information includes all expected devices and correctly reflects their connection levels, then the reported PCIe link information can be considered correct, thereby achieving fault diagnosis of the BIOS's PCIe link information reporting function.

[0105] In other embodiments, virtual topology information of varying complexity can be constructed to cover the topologies of PCIe devices of different brands and models. This ensures that even when faced with complex PCIe topologies, the basic input / output system can accurately report link information, thereby enhancing the compatibility and robustness of the basic input / output system.

[0106] Since virtual topology information can simulate various topologies, the solution in this application can cover a variety of PCIe link scenarios, including those that are difficult to reproduce in real-world environments due to hardware limitations. This extensive test coverage helps ensure the compatibility and robustness of the BIOS with various PCIe devices.

[0107] As an optional implementation, the virtual topology information includes multiple nodes and attribute information of each node. The multiple nodes include a root node, terminal nodes, and downstream nodes of the switch. The attribute information includes bus information, device information, and functional information. The second determining unit includes: a first traversal module, used to traverse the bus information, device information, and functional information in the virtual topology information starting from the root node, to determine the link length of the PCIe link; and a second traversal module, used to traverse the bus information in the virtual topology information starting from the terminal node, to determine hierarchical relationship information representing the arrangement order of the multiple nodes. The PCIe link information includes the link length and the hierarchical relationship information.

[0108] In the aforementioned implementation scheme, a virtual environment containing root nodes, terminal nodes, and downstream nodes of the switch is constructed in the absence of actual hardware. By defining the attribute information of these nodes, such as bus information, device information, and functional information, a PCIe topology is simulated, providing significant flexibility and variability for BIOS testing. Furthermore, by traversing the node attribute information in the virtual topology information starting from the root node, and using the bus information, device information, and functional information in the virtual topology information to identify each node in the link, the link length can be determined. This accurately reflects the path length of data from the CPU (or root bridge) to each terminal device, helping the BIOS accurately assess the complexity of the PCIe link in the virtual environment and providing important basis for subsequent link information processing and reporting. By traversing the bus information in the virtual topology information backward from the terminal node, tracing the hierarchical relationship representing the arrangement order of multiple nodes, the PCIe link hierarchy structure from the terminal to the root node can be clearly and completely constructed.

[0109] Specifically, the aforementioned bus information describes the logical connections and hierarchy between PCIe devices, while the aforementioned device information describes the specific attributes of each PCIe device. The aforementioned functional information refers to the multiple functions or services supported by each PCIe device, each function having its own attributes. Optionally, the bus information of the aforementioned root node and the aforementioned terminal node may include the bus number, i.e., bus ID, bus width, and bus speed, etc. The bus information of the downstream nodes of the aforementioned switch may include the upstream bus range, i.e., the range of upstream bus IDs; the downstream bus range, i.e., the range of downstream bus IDs; the slave bus range, i.e., the range of slave bus IDs; the bus width; and the bus speed, etc. The aforementioned device information may include the device ID, vendor ID, device type, device function, class code, revision number, and at least a portion of the configuration space. The aforementioned functional information may include the function ID, interrupt number, configuration register, I / O, and at least a portion of the memory space. Bus information, device information, and functional information together constitute a complete description of a PCIe device; they are interrelated and help the system identify and configure PCIe devices. In the BIOS and BMC, this information is used to initialize hardware, configure resources, monitor status, and diagnose faults. By accurately collecting and processing this information, the system can ensure the proper operation and efficient management of all PCIe devices.

[0110] In other embodiments, the second traversal module includes: a first traversal submodule, used in the first traversal step to traverse the bus information starting from the terminal node, determine the parent node of the terminal node, and obtain a first node; a second traversal submodule, used in the second traversal step to traverse the bus information in the virtual topology information starting from the first node when the obtained first node is the downstream node, determine the parent node of the first node, and obtain a new first node; a repeating submodule, used in the repeating step to repeat the second traversal step at least once until the obtained first node is the root node; and a first determining submodule, used in the determining step to determine the hierarchical relationship information when the obtained first node is the root node.

[0111] The above embodiments utilize bus information as the basis for the association between nodes. Through a series of traversal steps, starting from the terminal node, the upper-level node is determined by comparing the bus information of the node, until the root node is reached. In this way, the hierarchical relationship of the nodes in the PCIe link can be determined step by step, ensuring the accurate construction of the hierarchical relationship information. Even when facing a multi-level PCIe topology, the integrity and accuracy of the hierarchical relationship information can be guaranteed.

[0112] In the above determination steps, if the first node obtained is the root node, the link from the terminal node, through or without passing through the downstream node, to the root node is sorted out throughout the traversal process to obtain the above hierarchical relationship information.

[0113] In other embodiments, the traversal process can be optimized, memory usage reduced, and processing speed improved by introducing auxiliary data structures such as stacks or queues.

[0114] Furthermore, the above embodiments only illustrate how to determine the hierarchical relationship information of a single PCIe link. When there are multiple PCIe links, the hierarchical relationship information of each PCIe link can be obtained by iteratively executing the above embodiments. Moreover, by traversing the bus information, device information, and functional information starting from the root node, the link length of each PCIe link can be obtained.

[0115] According to other embodiments of this application, the method of traversing the bus information in the virtual topology information can be to use a depth-first search algorithm or a breadth-first search algorithm to traverse all the bus information.

[0116] In some alternative embodiments, the first traversal module includes: a second determining submodule, configured to determine the bus corresponding to the root node based on the bus information of the root node, and scan all device information and function information on the bus to discover the node connected to the bus, and set the current link length to "1"; a scanning submodule, configured to scan all device information and function information on the downstream bus connected to the node based on the bus information of the node, discover new nodes, and update the current link length to "2"; and a looping submodule, configured to repeatedly execute the previous step until the discovered node is an end node, and update the current link length to obtain the final link length of the PCIe link.

[0117] In some embodiments, the bus information of the downstream node includes an upstream bus range, a downstream bus range, and a slave bus range. The second traversal submodule is further configured to: traverse the bus information starting from the first node to determine a first target range, wherein the upstream bus range of the first node is located within the first target range, and the first target range is the downstream bus range and / or the slave bus range, that is, the first target range is the downstream bus range and / or the slave bus range that covers the upstream bus range of the first node; if there are multiple first target ranges, determine the downstream node corresponding to the smallest range among the multiple first target ranges as the new first node; if there is only one first target range, determine the downstream node corresponding to the first target range as the new first node.

[0118] In the above embodiments, bus range information is used to determine whether the current node is downstream of another node, thereby identifying its superior node. This method effectively avoids errors in constructing hierarchical relationship information, further improving the accuracy of PCIe link information reporting by the Basic Input / Output System (BIOS). Specifically, this embodiment utilizes the overlapping characteristics of bus ranges between nodes in a PCIe link, i.e., the upstream bus range of a downstream node must be located downstream of its superior node or within its subordinate bus range, to accurately find the superior node of the first node. This ensures that no node is missed during the construction of hierarchical relationship information, improving the completeness and reliability of information reporting. This embodiment also utilizes the uniqueness of bus ranges between nodes in a PCIe link. When the bus ranges of multiple nodes meet the conditions, the correct superior node is determined by the range size, i.e., the smallest range is selected as the new first node. This avoids ambiguity in the construction of hierarchical relationship information, further improving the accuracy and consistency of PCIe link information reporting. When only one node's bus range meets the conditions, it can be directly identified as the superior node, simplifying the construction process of hierarchical relationship information.

[0119] Optionally, the relationships between nodes can be further distinguished by adding additional bus information, such as bus ID and bus type; the determination of the first target range can be accelerated and the processing efficiency improved by introducing more efficient search algorithms, such as binary search and hash search; and the correctness of the minimum range nodes can be further confirmed and the robustness of the BIOS can be enhanced by adding correlation checks between nodes, such as device ID and function ID.

[0120] In other embodiments, the bus information of the terminal node includes a bus number, and the bus information of the downstream node includes a downstream bus range. The first traversal submodule is further configured to: traverse the bus information starting from the terminal node, determine a second target range, wherein the second target range is the downstream bus range in which the bus number of the terminal node is located, that is, the bus number of the terminal node is located within the second target range, and the second target range is a downstream bus range; and determine the downstream node corresponding to the second target range as the first node. This solution, by starting from the terminal node and searching for the downstream bus range in which its bus number is located, can quickly determine the first node directly connected to the terminal node (usually a port of a Switch or Bridge). This process avoids a full traversal starting from the root node, significantly improving the speed and efficiency of locating the connection relationship between nodes.

[0121] As an optional implementation, the above apparatus further includes: a first creation unit, configured to create a structure based on the link length after determining the link length of the PCIe link and before determining the hierarchical relationship information representing the arrangement order of the plurality of nodes, the structure including a plurality of elements; a first filling unit, configured to fill the plurality of attribute information into the structure according to the principle that one of the elements corresponds to one of the nodes, the plurality of nodes being arranged in random order in the structure; the above apparatus further includes: a configuration unit, configured to configure the pointer field of the structure based on the hierarchical relationship information representing the arrangement order of the plurality of nodes after determining the hierarchical relationship information, to obtain a first structure linked list of the PCIe link.

[0122] The above implementation method pre-creates a structure based on the link length and utilizes the array characteristics of the structure to fill the value structure with nodes and their corresponding attribute information in an unordered manner. This enables efficient storage and management of node information in the PCIe link and ensures the complete storage of node information. Furthermore, based on the hierarchical relationship information, the unordered node information is transformed into an ordered linked list structure by configuring the pointer fields of the structure. The pointer fields are used to link the elements in the structure to form a linked list that reflects the node hierarchical relationship. This method ensures the orderliness and consistency of PCIe link information and further improves the efficiency and accuracy of BIOS reporting PCIe link information.

[0123] In other embodiments, node information can also be stored using other data structures, such as linked lists or dictionaries, to adapt to dynamic changes in the number of nodes and improve the adaptability of the BIOS.

[0124] In practical applications, the virtual topology information mentioned above can be linked list information, which includes root node information, terminal node information, and downstream node information of each switch. Each downstream node includes information on the downstream bus range and the slave bus range. The nodes in the virtual topology information do not need to be arranged in order; only the bus number needs to meet the link requirements.

[0125] For example, based on the PCIe topology displayed by Lspci under Linux OS, one RP, four SWITCHDSPs, and one EP are needed to construct the virtual topology information. Based on this topology, the Basic Input / Output System (BIOS) constructs a structure in its code and then fills this structure with node information. The nodes in this structure do not need to be arranged according to the bus order; they can be randomly arranged, as long as the bus numbers are correct. Then, the structure is adjusted according to the hierarchical relationship information to obtain a linked list of structures reflecting the node hierarchy, such as... Figure 3 As shown, in the structure linked list, RootPort, ..., Switch DSP 2, Switch DSP 1, and End Point are arranged sequentially according to their bus numbers. Each Switch DSP's data structure includes BUS information, DEVICE information, FUNCTION information, Vendor ID, and Device ID.

[0126] As another optional implementation, the above apparatus further includes: a second creation unit, configured to create an empty structure linked list after determining the hierarchical relationship information representing the arrangement order of the plurality of nodes; and a second filling unit, configured to fill the empty structure linked list according to the hierarchical relationship information and the virtual topology information, such that the plurality of nodes are arranged in the structure according to the order represented by the hierarchical relationship information, thereby obtaining the second structure linked list of the PCIe link. This embodiment, by creating an empty structure linked list and filling the node information according to the hierarchical relationship information, can efficiently construct complete PCIe link information.

[0127] In other embodiments, other data structures, such as balanced trees and graph databases, can be used to further optimize the storage and access of node information, improve processing speed and space utilization, especially in large-scale PCIe topologies.

[0128] In specific applications, there are multiple PCIe links. The device further includes: a setting unit, used to set a memory space based on the maximum value among the multiple link lengths before reporting the PCIe link information to the baseboard management controller; and a storage unit, used to store the PCIe link information in JSON format in the memory space and add a cyclic redundancy check (CRC) code to the PCIe link information. In this embodiment, setting the memory space based on the longest link length ensures the complete storage of all PCIe link information. Furthermore, this application utilizes the flexibility and readability of the JSON format to store the link information in JSON format, facilitating the parsing and use by the BMC after reporting this information to the BMC. Moreover, by adding a CRC code to the PCIe link information, the integrity of the information and the reliability of data transmission are ensured.

[0129] In other embodiments, efficient data encoding methods such as protobuf and msgpack can be used to further compress the storage space of PCIe link information and improve the transmission speed.

[0130] Optionally, the aforementioned basic input / output system has a predefined interface, and the aforementioned device further includes: a receiving unit, configured to receive the virtual topology information through the predefined interface when it is determined that the virtual topology information is used to obtain the PCIe link information. This embodiment receives virtual topology information through a predefined interface, ensuring that the virtual topology information can be correctly parsed and used by the BIOS. Utilizing the standardized characteristics of the interface, even in different development environments, virtual topology information can be input through a unified interface, improving the convenience and flexibility of using virtual topology information and lowering the development and testing threshold.

[0131] In practical applications, the above-mentioned predefined interfaces are software interfaces.

[0132] Furthermore, the aforementioned apparatus further includes: a third determining unit, configured to determine, when it is determined that the PCIe link information is obtained through the PCIe hardware device, and to scan the PCIe hardware device if it is determined that the virtual topology information is not used to obtain the PCIe link information; a construction unit, configured to construct a PCIe bridge device information table based on the scan results; and a fourth determining unit, configured to determine the PCIe link information based on the PCIe bridge device information table. This application also supports scanning actual PCIe hardware devices to determine PCIe link information. Based on the physical characteristics of the PCIe hardware devices, scanning can obtain attribute information of all connected PCIe devices, including bus information, device information, and functional information, ensuring that the BIOS can accurately obtain and report PCIe link information in a real-world environment.

[0133] Specifically, the aforementioned PCIe bridge device information table refers to a data structure or database used to describe the characteristics and connection attributes of bridging devices in a PCIe topology. Optionally, the aforementioned third determining unit includes a scanning module, used to scan the aforementioned PCIe hardware device through the aforementioned predefined interface to obtain scan results.

[0134] According to some optional embodiments of this application, the first determining unit includes: a first determining module, configured to determine whether an access signal from the PCIe hardware device is received; an acquiring module, configured to acquire device information of the accessed PCIe hardware device when the access signal is received, and compare the device information with pre-stored device information; and a second determining module, configured to determine that the virtual topology information is not used to acquire the PCIe link information when the device information is consistent with the pre-stored device information. In this embodiment, by detecting the access status of PCIe hardware devices, once a signal indicating PCIe hardware device access is captured, the Basic Input / Output System (BIOS) reads and extracts the device information and compares it with pre-stored device information data to confirm the identity and consistency of the PCIe hardware device, enhancing system security. Based on the comparison result, the BIOS makes a decision on whether to use virtual topology information. That is, if the hardware device information matches the pre-stored information, it indicates that the actual hardware is in place, and therefore virtual topology information is not needed. This scheme allows the system to prioritize the use of real hardware to construct link information when PCIe hardware devices are available, making the acquisition and reporting of PCIe link information more direct and accurate. When the corresponding hardware is lacking, it automatically switches to virtual topology information. Virtual topology information provides a basis for testing and development, enabling development work to be carried out in advance, greatly saving waiting time for hardware and improving overall development efficiency.

[0135] According to some alternative embodiments of this application, the first determining unit includes: a first reading module, used to read the virtual topology information; a third determining module, used to determine, when the read virtual topology information is not empty, to use the virtual topology information to obtain the PCIe link information; and a fourth determining module, used to determine, when the read virtual topology information is empty, not to use the virtual topology information to obtain the PCIe link information. This embodiment, by reading the state of the virtual topology information, can automatically determine whether to use the virtual topology information to obtain PCIe link information. Using the presence or absence of the virtual topology information as the basis for judgment, when the virtual topology information exists, it is used; when the virtual topology information does not exist, the actual hardware device is used to obtain the PCIe link information. This method can automatically adapt to different stages of development and testing, improving the flexibility and practicality of the BIOS.

[0136] In other embodiments, the method of obtaining PCIe link information can be further optimized by introducing more judgment conditions, such as device type and operating system version, thereby improving the system's compatibility and stability.

[0137] According to some alternative embodiments of this application, the first determining unit includes: a second reading module, configured to retrieve the switch state of a predefined switch, the predefined switch being used to indicate the method for obtaining the PCIe link information; and a fifth determining module, configured to determine, based on the switch state, whether to use the virtual topology information to obtain the PCIe link information. For example, if the switch state is open, it is determined that the virtual topology information will be used to obtain the PCIe link information; if the switch state is closed, it is determined that the virtual topology information will not be used, and the PCIe link information will be obtained through the PCIe hardware device instead. As another example, if the switch state is closed, it is determined that the virtual topology information will be used to obtain the PCIe link information; if the switch state is open, it is determined that the virtual topology information will not be used, and the PCIe link information will be obtained through the PCIe hardware device instead. The predefined switch settings allow system administrators or developers to dynamically choose between using real hardware bus information or virtual topology information based on current hardware configuration and requirements. This enables the system to respond immediately to different acquisition path commands during startup or runtime, switching acquisition modes without recompiling code or restarting the system. In the early stages of software and hardware development, physical PCIe devices may not yet be fully ready. By setting the predefined switch to virtual topology information, development teams can perform functional testing and code debugging without hardware, accelerating the development process and ensuring that the BIOS software reaches the expected maturity and stability before the hardware is available. Even after hardware devices are connected, this switch still helps developers verify software compatibility with different types of hardware. By switching the switch state, testing can be conducted back and forth between real and virtual environments, ensuring that the BIOS code still works accurately with different PCIe devices, improving the overall system compatibility and robustness.

[0138] For a description of the features in the embodiment corresponding to the diagnostic device for a basic input / output system, please refer to the relevant description in the embodiment corresponding to the diagnostic method for a basic input / output system, which will not be repeated here.

[0139] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the diagnostic method embodiments of the basic input / output system described above.

[0140] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the diagnostic method for a basic input / output system.

[0141] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0142] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described diagnostic method embodiments for a basic input / output system.

[0143] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described basic input / output system diagnostic method embodiments.

[0144] Embodiments of this application also provide a server, including:

[0145] A basic input / output system includes: a memory for storing a computer program; and a processor for executing the computer program to implement the diagnostic method of any of the basic input / output systems described above.

[0146] The baseboard management controller is connected to the basic input / output system and is used to receive PCIe link information reported by the basic input / output system and to perform fault diagnosis on the basic input / output system based on the PCIe link information.

[0147] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0148] The diagnostic method, apparatus, storage medium, and server for a basic input / output system provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A diagnostic method of a basic input / output system, characterized by, The method comprises: determining whether to obtain PCIe link information by using virtual topology information, wherein the virtual topology information is obtained by simulating a topology of a PCIe hardware device; in a case where it is determined to obtain the PCIe link information by using the virtual topology information, determining the PCIe link information corresponding to the virtual topology information according to the virtual topology information; reporting the PCIe link information to a baseboard management controller, so that the baseboard management controller performs fault diagnosis on the basic input / output system according to the PCIe link information, the virtual topology information comprises a plurality of nodes and attribute information of each node, the plurality of nodes comprise a root node, a terminal node and a downstream node of a switch, the attribute information comprises bus information, device information and function information, and the PCIe link information corresponding to the virtual topology information is determined according to the virtual topology information, comprising: taking the root node as a starting point, traversing the bus information, the device information and the function information in the virtual topology information, and determining a link length of a PCIe link; taking the terminal node as a starting point, traversing the bus information in the virtual topology information, and determining hierarchical relationship information representing an arrangement order of the plurality of nodes, wherein the PCIe link information comprises the link length and the hierarchical relationship information, taking the terminal node as a starting point, traversing the bus information in the virtual topology information, and determining hierarchical relationship information representing an arrangement order of the plurality of nodes, comprising: a first traversal step of taking the terminal node as a starting point, traversing the bus information, and determining a node at a higher level of the terminal node to obtain a first node; a second traversal step of taking the first node as a starting point, traversing the bus information in the virtual topology information, and determining a node at a higher level of the first node to obtain a new first node in a case where the obtained first node is the downstream node; repeating the second traversal step at least once until the obtained first node is the root node; a determination step of determining the hierarchical relationship information in a case where the obtained first node is the root node.

2. The method according to claim 1, wherein the bus information of the downstream node comprises an upstream bus range, a downstream bus range and a slave bus range, and the second traversal step comprises: taking the first node as a starting point, traversing the bus information, and determining a first target range, wherein the upstream bus range of the first node is located in the first target range, and the first target range is the downstream bus range and / or the slave bus range; in a case where there are a plurality of first target ranges, determining a downstream node corresponding to a smallest range in the plurality of first target ranges as a new first node; in a case where there is one first target range, determining a downstream node corresponding to the first target range as a new first node.

3. The method according to claim 1, wherein The bus information of the terminal node comprises a bus number, and the bus information of the downstream node comprises a downstream bus range, and the first traversal step comprises: starting from the terminal node, traversing the bus information, and determining a second target range, wherein the terminal node is located in the downstream bus range; determining that the downstream node corresponding to the second target range is the first node.

4. The diagnostic method of claim 1, wherein, after determining the link length of the PCIe link, before determining the hierarchical relationship information representing the arrangement order of the plurality of nodes, the method further comprises: creating a structure according to the link length, the structure comprising a plurality of elements; filling a plurality of attribute information into the structure according to the principle that one element corresponds to one node, and the plurality of nodes are arranged in the structure in disorder; after determining the hierarchical relationship information representing the arrangement order of the plurality of nodes, the method further comprises: configuring a pointer field of the structure according to the hierarchical relationship information, to obtain a first structure linked list of the PCIe link.

5. The diagnostic method of claim 1, wherein, after determining the hierarchical relationship information representing the arrangement order of the plurality of nodes, the method further comprises: creating an empty structure linked list; filling the empty structure linked list according to the hierarchical relationship information and the virtual topology information, so that the plurality of nodes are arranged in the structure according to the order represented by the hierarchical relationship information, to obtain a second structure linked list of the PCIe link.

6. The diagnostic method of claim 1, wherein, there are a plurality of PCIe links, and before reporting the PCIe link information to a baseboard management controller, the method further comprises: setting a memory space according to a maximum value in the plurality of link lengths; storing the PCIe link information in the form of JSON to the memory space, and adding a cyclic redundancy check code to the PCIe link information.

7. The diagnostic method of claim 1, wherein, the basic input and output system has a predefined interface, and the method further comprises: in a case where it is determined to obtain the PCIe link information using the virtual topology information, receiving the virtual topology information through the predefined interface.

8. The diagnostic method of claim 1, wherein, the method further comprises: in a case where it is determined not to obtain the PCIe link information using the virtual topology information, determining to obtain the PCIe link information through the PCIe hardware device, and scanning the PCIe hardware device; constructing a PCIe bridge device information table according to the scanning result; determining the PCIe link information according to the PCIe bridge device information table.

9. The diagnostic method of claim 1, wherein, determining whether to obtain PCIe link information using virtual topology information comprises: determining whether an access signal of the PCIe hardware device is received; In a case that the access signal is received, device information of the accessed PCIe hardware device is acquired, and whether the device information is consistent with pre-stored device information is compared; In a case that the device information is consistent with the pre-stored device information, it is determined that the PCIe link information is not acquired by using the virtual topology information.

10. The diagnostic method of claim 1, wherein determining whether to acquire PCIe link information by using virtual topology information comprises: reading the virtual topology information; in a case that the read virtual topology information is not empty, determining to acquire the PCIe link information by using the virtual topology information; in a case that the read virtual topology information is empty, determining not to acquire the PCIe link information by using the virtual topology information.

11. A diagnostic apparatus for a basic input / output system, characterized by comprising: comprises: a first determination unit configured to determine whether to acquire PCIe link information by using virtual topology information, the virtual topology information being obtained by simulating a topology structure of a PCIe hardware device; a second determination unit configured to, in a case that it is determined to acquire the PCIe link information by using the virtual topology information, determine, according to the virtual topology information, the PCIe link information corresponding to the virtual topology information; a reporting unit configured to report the PCIe link information to a baseboard management controller, so that the baseboard management controller performs fault diagnosis on the basic input / output system according to the PCIe link information, the virtual topology information comprises a plurality of nodes and attribute information of each node, the plurality of nodes comprising a root node, a terminal node and a downstream node of a switch, and the attribute information comprising bus information, device information and function information, and the second determination unit comprises: a first traversal module configured to take the root node as a starting point to traverse the bus information, the device information and the function information in the virtual topology information, and determine a link length of a PCIe link; a second traversal module configured to take the terminal node as a starting point to traverse the bus information in the virtual topology information, and determine hierarchical relationship information representing an arrangement order of the plurality of nodes, the PCIe link information comprising the link length and the hierarchical relationship information, the second traversal module comprises: a first traversal submodule configured to perform a first traversal step, take the terminal node as a starting point to traverse the bus information, and determine a next-level node of the terminal node to obtain a first node; a second traversal submodule configured to perform a second traversal step, in a case that the obtained first node is the downstream node, take the first node as a starting point to traverse the bus information in the virtual topology information, and determine a next-level node of the first node to obtain a new first node; a repeating submodule configured to perform the second traversal step repeatedly at least once until the obtained first node is the root node; a first determination submodule configured to perform a determination step, in a case that the obtained first node is the root node, determine the hierarchical relationship information.

12. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the basic input and output system diagnosis method according to any one of claims 1 to 10.

13. A server, characterized by Comprise: The basic input and output system comprises a memory for storing a computer program and a processor for executing the computer program to implement the steps of the basic input and output system diagnosis method according to any one of claims 1 to 10. The baseboard management controller is connected with the basic input and output system, receives the PCIe link information reported by the basic input and output system, and performs fault diagnosis on the basic input and output system according to the PCIe link information.

Images