Method and system for optimizing breakdown voltage of high electron mobility transistor

Abstract

The invention relates to the technical field of semiconductors, in particular to a breakdown voltage optimization method and system for a high-electron-mobility transistor, and the method comprises the following steps: obtaining heterojunction material energy band parameters of the high-electron-mobility transistor, and obtaining critical breakdown electric field correlation parameters based on the heterojunction material energy band parameters; optimizing a field plate structure of the high electron mobility transistor according to the critical breakdown electric field correlation parameter to obtain a field plate structure optimization parameter; establishing a buffer layer trap effect suppression model, and obtaining buffer layer superlattice structure optimization parameters according to the buffer layer trap effect suppression model; obtaining a breakdown voltage temperature compensation factor of the high electron mobility transistor; and establishing a breakdown voltage optimization model, and optimizing the breakdown voltage of the high electron mobility transistor according to the breakdown voltage optimization model. According to the invention, the breakdown voltage is optimized, so that the use efficiency of the high-electron-mobility transistor is remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and system for optimizing the breakdown voltage of a high electron mobility transistor. Background Technology

[0002] Currently, optimization techniques for the breakdown voltage of high electron mobility transistors (HMTs) mainly revolve around material selection, structural design, and process improvement. To enhance breakdown voltage, existing technologies include: at the material level, exploring novel semiconductor materials and wide-bandgap materials to leverage their high breakdown electric field characteristics and improve breakdown voltage; at the structural level, introducing field plate structures, buffer layer doping, and composite gate designs to suppress electric field concentration at the gate edge by optimizing electric field distribution and depletion layer expansion; and at the process level, employing in-situ silicon nitride passivation, precise control of epitaxial growth parameters, and carbon-doped buffer layer technology to reduce interface defects and trap effects, thereby improving breakdown voltage.

[0003] Despite progress in improving breakdown voltage, existing technologies still suffer from several drawbacks: First, the trade-off between breakdown voltage and on-resistance remains significant. Traditional methods often increase on-resistance while improving breakdown voltage, impacting device efficiency. Second, the dynamic resistance problem is not fully resolved. High electron mobility transistors experience increased dynamic resistance during switching due to trapping effects, leading to increased conduction losses, accelerated temperature rise, and even premature breakdown. While techniques such as in-situ silicon nitride passivation can alleviate this issue, material stability still needs improvement. Furthermore, significant process complexity and cost issues persist. The introduction of novel structures and materials increases manufacturing difficulty and cost. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a method and system for optimizing the breakdown voltage of high electron mobility transistors.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a method for optimizing the breakdown voltage of a high electron mobility transistor (HMT), the method comprising the following steps: obtaining the band structure parameters of the heterojunction material of the HMT; obtaining critical breakdown electric field correlation parameters based on the band structure parameters of the heterojunction material; optimizing the field plate structure of the HMT according to the critical breakdown electric field correlation parameters to obtain optimized field plate structure parameters; establishing a buffer layer trap effect suppression model based on the optimized field plate structure parameters; obtaining optimized buffer layer superlattice structure parameters based on the optimized buffer layer trap effect suppression model; obtaining a breakdown voltage temperature compensation factor of the HMT according to the optimized buffer layer superlattice structure parameters; establishing a breakdown voltage optimization model; and optimizing the breakdown voltage of the HMT according to the optimized breakdown voltage model. This invention accurately extracts critical breakdown electric field correlation parameters based on heterojunction band parameters, providing a theoretical basis for field plate structure optimization; it combines a buffer layer trap effect suppression model with superlattice structure design to simultaneously reduce leakage current and dynamic resistance; it introduces a temperature compensation factor to effectively balance on-resistance and withstand voltage performance, and achieves synergistic optimization of breakdown voltage through multi-dimensional parameter coupling, thereby improving the reliability of high electron mobility transistors.

[0006] Optionally, obtaining the band structure parameters of the heterojunction material of the high electron mobility transistor and obtaining the critical breakdown electric field correlation parameters based on the band structure parameters of the heterojunction material includes: constructing a parameter measurement experiment to obtain the band structure parameters of the heterojunction material; constructing a quantized two-dimensional electron gas concentration model based on the band structure parameters of the heterojunction material; obtaining the quantized energy level distribution of the high electron mobility transistor according to the quantized two-dimensional electron gas concentration model; and obtaining the critical breakdown electric field correlation parameters of the high electron mobility transistor by combining the quantized energy level distribution. This invention combines experimental data with theoretical modeling to quantize the two-dimensional electron gas concentration distribution and quantized energy level characteristics, providing a high-precision theoretical basis for the extraction of critical breakdown electric field correlation parameters. This not only improves the reliability of material parameter acquisition but also lays the foundation for subsequent field plate optimization and buffer layer trap suppression through band structure optimization.

[0007] Optionally, the step of optimizing the field plate structure of the high electron mobility transistor based on the critical breakdown electric field correlation parameters to obtain field plate structure optimization parameters includes: establishing an electric field reconstruction function based on the critical breakdown electric field correlation parameters; obtaining the reconstructed three-dimensional electric field distribution of the high electron mobility transistor based on the electric field reconstruction function; establishing an electric field peak position prediction model based on the reconstructed three-dimensional electric field distribution; obtaining the electric field peak position based on the established electric field peak position prediction model; constructing a multi-level field plate structure optimization function for the high electron mobility transistor based on the electric field peak position; and obtaining the field plate structure optimization parameters based on the multi-level field plate structure optimization function. This invention, based on the three-dimensional electric field distribution obtained by the electric field reconstruction function, accurately locates the electric field peak position; and, combined with the multi-level field plate structure optimization function, specifically adjusts the field plate layers and geometric parameters, effectively dispersing the concentrated electric field region, reducing the peak electric field intensity, and simultaneously reducing on-resistance, balancing withstand voltage and efficiency.

[0008] Optionally, the step of establishing a buffer layer trap effect suppression model based on the field plate structure optimization parameters, and obtaining buffer layer superlattice structure optimization parameters based on the buffer layer trap effect suppression model, includes: obtaining the longitudinal electric field distribution of the high electron mobility transistor based on the field plate structure optimization parameters, and obtaining the maximum electric field gradient of the buffer layer by combining the longitudinal electric field distribution; constructing a trap energy level ionization correction model by combining the trap ionization energy of the buffer layer and the maximum electric field gradient, and using the trap energy level ionization correction model as the buffer layer trap effect suppression model; and optimizing the buffer layer superlattice structure based on the buffer layer trap effect suppression model to obtain the buffer layer superlattice structure optimization parameters. This invention quantifies the trap activation threshold by constructing a correction model based on the maximum electric field gradient obtained from the longitudinal electric field distribution and combining it with the trap ionization energy; effectively disperses electric field stress through superlattice structure optimization, reducing the trap ionization probability; and improving the stability and lifespan of the device.

[0009] Optionally, the step of optimizing the buffer layer superlattice structure based on the buffer layer trap effect suppression model to obtain the optimized parameters of the buffer layer superlattice structure includes: obtaining a trap ionization energy correction amount based on the buffer layer trap effect suppression model to obtain the trap state density distribution; obtaining the superlattice period number and thickness ratio based on the trap state density distribution; and optimizing the buffer layer superlattice structure by combining the superlattice period number and the thickness ratio to obtain the optimized parameters of the buffer layer superlattice structure. The trap state density distribution obtained by this invention based on the trap ionization energy correction amount can quantify the influence of the superlattice period number and thickness ratio on the electric field dispersion; and effectively suppresses trap activation and reduces leakage current and dynamic resistance through structural parameter optimization.

[0010] Optionally, obtaining the breakdown voltage temperature compensation factor of the high electron mobility transistor based on the optimized parameters of the buffer layer superlattice structure includes: constructing a superlattice thermal resistance distribution model based on the optimized parameters of the buffer layer superlattice structure; obtaining the equivalent thermal conductivity of the superlattice interface based on the superlattice thermal resistance distribution model; performing thermally induced carrier ionization analysis based on the equivalent thermal conductivity of the superlattice interface to obtain the change in trap activation energy; and establishing a temperature compensation factor equation based on the change in trap activation energy to obtain the breakdown voltage temperature compensation factor. The present invention, based on the interface equivalent thermal conductivity obtained from the superlattice thermal resistance model, can quantify the influence of thermally induced carrier ionization on the trap activation energy; and by incorporating the temperature effect into the optimization model through the temperature compensation factor equation, it effectively corrects temperature-induced breakdown voltage fluctuations.

[0011] Optionally, the step of obtaining the trap activation energy change through thermally induced carrier ionization analysis based on the equivalent thermal conductivity of the superlattice interface includes: obtaining the phonon scattering rate through phonon transport spectrum analysis based on the equivalent thermal conductivity of the superlattice interface; obtaining the phonon-trap interaction energy based on the phonon scattering rate and combined with hot carrier energy transfer; and dynamically correcting the trap activation energy based on the phonon-trap interaction energy to obtain the trap activation energy change. This invention, based on the scattering rate obtained from phonon transport spectrum analysis and combined with hot carrier energy transfer to calculate the phonon-trap interaction energy, can accurately correct temperature-induced trap activation energy changes, effectively suppress thermally induced leakage current fluctuations, and significantly improve the stability of the breakdown voltage.

[0012] Optionally, establishing a breakdown voltage optimization model and optimizing the breakdown voltage of the high electron mobility transistor based on the breakdown voltage optimization model includes: constructing a multi-parameter coupled breakdown voltage optimization objective function by combining the critical breakdown electric field correlation parameters, the field plate structure optimization parameters, the buffer layer superlattice structure optimization parameters, and the breakdown voltage temperature compensation factor; establishing a set of dynamic constraints for the high electron mobility transistor; using the breakdown voltage optimization objective function and the set of dynamic constraints as the breakdown voltage optimization model; obtaining an optimization parameter package for the high electron mobility transistor based on the breakdown voltage optimization model; and optimizing the breakdown voltage based on the optimization parameter package. This invention constructs an objective function based on multiple parameters of the high electron mobility transistor and incorporates dynamic constraints to obtain a breakdown voltage optimization model. This allows the optimization process to balance theoretical accuracy and manufacturing feasibility, precisely balance withstand voltage performance and conduction losses, effectively improve the breakdown voltage, and reduce performance fluctuations caused by temperature, providing a breakdown voltage optimization framework for high electron mobility transistors.

[0013] Optionally, establishing the dynamic constraint set for the high electron mobility transistor includes: acquiring the electrical constraints, thermal constraints, and process constraints of the high electron mobility transistor, and using the electrical constraints, thermal constraints, and process constraints as the dynamic constraint set. This invention integrates electrical, thermal, and process constraints to construct a dynamic constraint set, ensuring that the breakdown voltage optimization parameters balance theoretical performance and engineering feasibility, avoiding over-design during the optimization process, and improving design practicality.

[0014] Secondly, this invention provides a breakdown voltage optimization system for high electron mobility transistors (HMTs). The system executes the breakdown voltage optimization method for HMTs provided by this invention. The system includes an input device, an output device, a processor, and a memory, all interconnected. The memory stores a computer program comprising program instructions, and the processor is configured to invoke these instructions. This invention, by integrating input, processing, storage, and output hardware, achieves systematic and efficient execution of multi-parameter coupled optimization, effectively optimizing the breakdown voltage and improving the performance of high electron mobility transistors. Attached Figure Description

[0015] Figure 1 This is a flowchart of a method for optimizing the breakdown voltage of a high electron mobility transistor according to an embodiment of the present invention; Figure 2 This is a system framework diagram for optimizing the breakdown voltage of a high electron mobility transistor according to an embodiment of the present invention. Detailed Implementation

[0016] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, software, or methods have not been specifically described to avoid obscuring the invention.

[0017] Throughout this specification, references to "an embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases "in an embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the illustrations provided herein are for illustrative purposes and are not necessarily drawn to scale.

[0018] Please see Figure 1 One embodiment of the present invention provides a method for optimizing the breakdown voltage of a high electron mobility transistor, the method comprising the following steps: S1. Obtain the band structure parameters of the heterojunction material of the high electron mobility transistor, and obtain the critical breakdown electric field correlation parameters based on the band structure parameters of the heterojunction material.

[0019] In this embodiment, a parameter measurement experiment is constructed to obtain the band structure parameters of the heterojunction material; a quantized two-dimensional electron gas concentration model is constructed based on the band structure parameters of the heterojunction material; the quantized energy level distribution of the high electron mobility transistor is obtained based on the quantized two-dimensional electron gas concentration model; and the critical breakdown electric field correlation parameters of the high electron mobility transistor are obtained by combining the quantized energy level distribution.

[0020] First, a parameter determination experiment was constructed. For typical heterojunction structures, key band parameters were obtained using multi-dimensional characterization methods. The experimental steps included: First, X-ray photoelectron spectroscopy or ultraviolet photoelectron spectroscopy was used to determine the valence band shift and conduction band shift at the heterojunction interface, combined with elliptic polarization spectroscopy to measure the band gap of each layer. Second, the carrier concentration and mobility of the two-dimensional electron gas were obtained through electrochemical capacitance-voltage method or low-temperature Hall effect testing. Third, high-resolution transmission electron microscopy was used to observe the interface roughness of the heterojunction, combined with atomic force microscopy to analyze the strain distribution caused by lattice mismatch. Fourth, the band parameters of the heterojunction material, including valence band shift, conduction band shift, band gap, polarization charge density, and interface trap state density, were obtained through data fitting.

[0021] Secondly, a quantized two-dimensional electron gas concentration model is constructed based on the band structure parameters of the heterojunction material to describe the carrier distribution characteristics and obtain the quantized energy level distribution. Combining the polarization charge density and the potential well depth, the quantized energy level distribution is derived: in the direction perpendicular to the heterojunction interface, the barrier layer and buffer layer are considered as quantum well structures, taking into account the built-in electric field generated by the polarization effect; the experimentally measured conduction band offset value is substituted to set the potential well depth, and the barrier height is corrected by incorporating the band bending effect caused by strain; the two-dimensional electron gas concentration model is discretized and solved using the finite element method, and the space charge distribution is iteratively calculated until the potential and carrier concentration converge. The model needs to consider the quantization effect of quantum confinement on carrier concentration. For example, when the barrier layer thickness increases from 10 nm to 30 nm, the increased width of the quantum well structure leads to a downward shift of the ground state energy level, and the carrier concentration increases from 1 × 10⁻⁶. 13 cm⁻ 2 Upgraded to 3×10 13cm⁻2 The final output shows the spatial mapping relationship between the quantized energy level distribution and the carrier concentration, providing a theoretical basis for the critical breakdown electric field analysis.

[0022] The above quantized two-dimensional electron gas concentration model satisfies the following relationship: in, For the surface density of two-dimensional electron gas, For the effective mass of electrons, Pi To reduce Planck's constant, For the number of subbands, For index variables, For the first The bottom energy of a sublevel The base of the natural logarithm, For the Fermi level position, For electron energy, Boltzmann's constant, Absolute temperature The polarization charge density, This is the interface defect compensation factor.

[0023] Then, the critical breakdown electric field correlation parameters are derived based on the quantized energy level distribution. First, combining the energy level spacing and the effective electron mass, a relationship between the electric field strength and the energy level transition probability is established using collisional ionization theory: when the electric field exceeds a threshold, the ground-state electron transitions to the conduction band continuous state, triggering avalanche breakdown. Second, Monte Carlo simulation is introduced to calculate the breakdown probability density function corresponding to different energy level structures, considering the competition mechanism between lattice scattering and ionization scattering. For example, when the energy level spacing decreases from 0.2 eV to 0.1 eV, the slope of the ionization rate with the increase of the electric field increases by a factor of 3, causing the critical breakdown electric field to decrease from 3.5 MV / cm to 2.0 MV / cm. Furthermore, the influence of the trap-assisted tunneling effect on breakdown is corrected by combining the experimentally measured interface trap state density value. When the interface trap state density value > 1 × 10⁻⁶, the effect is corrected. 12 cm⁻ 2 ·eV⁻ 1 When the proportion of trap-assisted breakdown paths exceeds 50%, a tunneling coefficient needs to be introduced for correction. Finally, through multiphysics coupling analysis, the quantitative relationship between the critical breakdown electric field and energy level parameters, trap state density, and polarization electric field is determined.

[0024] Finally, a closed loop was formed through experimental verification and parameter optimization. First, a variable parameter test structure was designed: semiconductor devices with different barrier layer thicknesses and aluminum compositions were fabricated, the breakdown voltage was measured, and the actual critical breakdown electric field was extracted simultaneously. The experimental data were compared with the predicted values ​​of the theoretical model, and the empirical coefficients in the model were corrected by fitting using the least squares method. Finally, the field plate structure parameters were determined as the critical breakdown electric field correlation parameters, providing input conditions for subsequent structure optimization.

[0025] S2. The field plate structure of the high electron mobility transistor is optimized based on the critical breakdown electric field correlation parameters to obtain the optimized field plate structure parameters.

[0026] In this embodiment, an electric field reconstruction function is established based on the critical breakdown electric field correlation parameters, and the reconstructed three-dimensional electric field distribution of the high electron mobility transistor is obtained based on the electric field reconstruction function; an electric field peak position prediction model is established in combination with the reconstructed three-dimensional electric field distribution, and the electric field peak position is obtained based on the established electric field peak position prediction model; a multi-level field plate structure optimization function of the high electron mobility transistor is constructed based on the electric field peak position; and the field plate structure optimization parameters are obtained based on the multi-level field plate structure optimization function.

[0027] An electric field reconstruction function is constructed to simulate the three-dimensional electric field distribution inside the device. The critical breakdown electric field correlation parameter reflects the voltage withstand characteristics of the material itself. The electric field reconstruction function is established by combining the heterojunction band structure parameters and geometric parameters. This model needs to consider the modulation effect of the field by the field plate structure: the field plate adjusts the high electric field region near the drain by changing the extension length and position of the metal electrode. The critical breakdown electric field parameter is used as the boundary condition input to simulate the electric field distribution under different field plate configurations. For example, when the field plate length increases, the electric field peak on the drain side will diffuse towards the buffer layer, thereby reducing the local electric field intensity. By iteratively adjusting the field plate parameters, the reconstructed three-dimensional electric field distribution covering the entire device region is obtained, clarifying the morphology and intensity of the electric field concentration region.

[0028] The above electric field reconstruction function satisfies the following relationship: in, For divergence operators, The position-dependent dielectric constant, For gradient operators, For spatial electric potential distribution, The amount of electron charge. The concentration of ionized impurities. For the surface density of two-dimensional electron gas, The base of the natural logarithm, For spatial location, This refers to the gate edge location. The characteristic length of carrier diffusion.

[0029] A model for predicting the peak electric field location is established based on the reconstructed three-dimensional electric field distribution to pinpoint the region most prone to breakdown. By analyzing the gradient changes in the electric field distribution, regions where the electric field intensity exceeds a critical value are identified, and their movement as the field plate structure changes is predicted. For example, in a single-stage field plate structure, the electric field peak is usually located near the drain edge; while in a multi-stage field plate structure, the peak may split into multiple secondary peaks distributed at the gaps between the field plates. The prediction model needs to combine the statistical characteristics of the electric field distribution and the geometric parameters of the field plate, establishing a mapping relationship through machine learning or regression analysis. To verify the model's accuracy, experiments are designed to test the actual breakdown voltage under different field plate structures, comparing the predicted peak location with the experimentally observed breakdown point. If the deviation exceeds a preset threshold, the weighting coefficients in the model need to be adjusted or a correction term introduced.

[0030] The above electric field peak location prediction model satisfies the following relationship: in, This is the location of the electric field peak. This refers to the gate edge location. The characteristic length of carrier diffusion. The amount of electron charge. For the surface density of two-dimensional electron gas, The gate metal length, The dielectric constant of the barrier layer is . The critical breakdown electric field strength, It is a horizontal unit vector. This is the correction amount for the field plate.

[0031] A multi-level field plate structure optimization function is constructed based on the peak electric field location to disperse electric field concentration. The multi-level field plates, through a stepped arrangement of metal electrodes, progressively reduce the electric field gradient on the drain side. The optimization function needs to comprehensively consider parameters such as the number of field plate levels, the length of each level, the spacing, and the distance from the gate. For example, increasing the number of field plate levels can decompose a single high electric field peak into multiple low-intensity peaks, but excessively dense field plate spacing may lead to enhanced capacitive coupling, which in turn reduces the device's frequency characteristics. The optimization process must balance the trade-off between improved breakdown voltage and high-frequency performance loss. Using a parameter scanning method, combinations of the number of field plate levels and the length of each level are set, and the electric field peak suppression effect under each configuration is calculated. Ultimately, the optimization function aims to maximize the breakdown voltage, with constraints including the total field plate area not exceeding the chip's allowable range and parasitic capacitance below a specific threshold, thus outputting the optimized field plate structure parameters.

[0032] Furthermore, the effectiveness of the optimized field plate structure parameters was verified. First, the breakdown characteristics of the device were simulated using the optimized field plate parameters to observe whether the peak electric field decreased below the critical breakdown electric field. If the simulation results met the requirements, test samples were fabricated for actual testing, the breakdown voltage was measured, and micrographs of the electric field distribution were observed. If the experimental breakdown voltage was lower than the simulation prediction, the cause needed to be analyzed: it might be due to local leakage caused by material defects, or electric field distortion caused by process errors at the field plate edges. In this case, a process fluctuation factor needed to be introduced into the optimization function, and the parameters readjusted. For example, the field plate spacing could be increased by 10% to compensate for edge effects, or a passivation layer could be added to the field plate surface to reduce the influence of surface traps. Through multiple iterations, the optimized parameters of the field plate structure were finally determined to ensure its stability under different temperature and bias conditions.

[0033] S3. Establish a buffer layer trap effect suppression model based on the field plate structure optimization parameters, and obtain the buffer layer superlattice structure optimization parameters according to the buffer layer trap effect suppression model.

[0034] Specifically, S3 includes the following steps: S31. Obtain the longitudinal electric field distribution of the high electron mobility transistor based on the field plate structure optimization parameters, and obtain the maximum electric field gradient of the buffer layer by combining the longitudinal electric field distribution.

[0035] In this embodiment, the optimized field plate structure parameters directly affect the electric field direction and intensity in the buffer layer region by modulating the electric field distribution inside the device. The simulation tools and experiments are used for verification: First, the optimized field plate geometric parameters are input into computer-aided design software to construct a three-dimensional device model. By setting boundary conditions, the electric field distribution inside the device under different bias conditions is simulated. The longitudinal electric field direction is perpendicular to the heterojunction interface, extending from the gate metal to the buffer layer, and its intensity exhibits a non-linear change with increasing depth. For example, in a single-level field plate structure, the longitudinal electric field reaches its peak at the surface of the buffer layer; while in a multi-level field plate, the peak value is dispersed to the gaps between the field plates through stepped electric field modulation, thereby reducing the local electric field gradient. To verify the accuracy of the simulation results, test samples need to be fabricated and electron beam induced current imaging technology is used to directly observe the electric field distribution morphology in the buffer layer region. By comparing the electric field profiles from simulation and experiment, material and process parameters are adjusted.

[0036] Furthermore, by analyzing the rate of change of electric field intensity with depth in the longitudinal electric field distribution, the maximum electric field gradient of the buffer layer can be determined. The electric field gradient is defined as the derivative of the electric field intensity with respect to location, reflecting the drastic change in the electric field. In the buffer layer region, the longitudinal electric field may exhibit multiple extreme points due to the modulation of the field plate structure. For example, the electric field gradient on the surface of the buffer layer may show a positive peak due to the capacitive coupling effect at the edge of the field plate, while in deeper regions, a reverse gradient is formed due to material doping or trap scattering. To locate the maximum electric field gradient, the longitudinal electric field distribution needs to be piecewise fitted: in the surface region of the buffer layer (0nm-50nm), the electric field intensity decreases rapidly with increasing depth, and the gradient is negative; in the middle region (50nm-150nm), the electric field intensity may plateau or slightly rebound due to trap-assisted conduction, causing the gradient to approach zero; in the deep region (below 150nm), the electric field intensity tends to stabilize, and the gradient approaches zero. By calculating the absolute values ​​of the slopes of the electric field intensities in each segment, it was determined that the maximum electric field gradient occurs near the surface of the buffer layer. This maximum gradient location highly coincides with the trap state density distribution of the buffer layer, indicating that the high electric field gradient region is prone to trap ionization, leading to increased leakage current and degradation of breakdown voltage. Therefore, the optimization of the buffer layer superlattice structure needs to be designed specifically for the region of maximum electric field gradient.

[0037] S32. Construct a trap level ionization correction model by combining the trap ionization energy of the buffer layer and the maximum electric field gradient, and use the trap level ionization correction model as the trap effect suppression model of the buffer layer.

[0038] In this embodiment, the trap energy level distribution at different depths of the buffer layer is obtained, and the correlation between the electric field gradient and the trap ionization energy is analyzed by combining the longitudinal electric field distribution data. For example, when the maximum electric field gradient exceeds 1×10⁻⁶, the trap energy level distribution is significantly increased. 6 V / cm 2In high-electric-field regions, carriers gain energy more rapidly, leading to a significant increase in the ionization probability of the trap level, which in turn causes an increase in leakage current and a degradation in breakdown voltage. To address this, an electric field gradient-dependent ionization correction term is introduced: by statistically analyzing trap ionization events under different electric field gradients, an empirical relationship between the ionization rate and the electric field gradient is established, and this empirical relationship is embedded into the traditional trap effect model to form a modified trap level ionization model. This model can quantitatively describe the enhancing effect of the electric field gradient on trap ionization, thus providing a basis for the design of buffer layer superlattice structures: for example, by using a superlattice layer with low trap density or adjusting the doping concentration of the buffer layer, the ionization probability in the region of maximum electric field gradient can be reduced, thereby suppressing the trap effect.

[0039] The above-mentioned trap level ionization correction model satisfies the following relationship: in, This is the correction amount for the trap ionization energy. Based on the ionization energy of the basic trap, The electric field-trap coupling coefficient is... The maximum electric field gradient in the longitudinal direction. The characteristic length of carrier diffusion. The efficiency factor of the plate. For superlattice modulation functions, To optimize trap density, This refers to the thickness ratio.

[0040] S33. Based on the buffer layer trap effect suppression model, the buffer layer superlattice structure is optimized to obtain the optimized parameters of the buffer layer superlattice structure.

[0041] In this embodiment, the trap ionization energy correction is obtained based on the buffer layer trap effect suppression model to obtain the trap state density distribution; the superlattice period number and thickness ratio are obtained based on the trap state density distribution; and the buffer layer superlattice structure is optimized by combining the superlattice period number and thickness ratio to obtain the optimized parameters of the buffer layer superlattice structure.

[0042] First, a correction factor for the trap ionization energy is extracted. This correction factor reflects the influence of the electric field gradient on the ionization probability of the trap energy levels: when the maximum electric field gradient of the buffer layer exceeds a threshold, the model outputs a decrease in the trap ionization energy, indicating that carriers in the traps are more easily excited to the conduction band by the electric field. The trap state density distribution at different depths of the buffer layer is obtained by using the corrected ionization energy. This provides a key input for superlattice structure design: a superlattice layer needs to be inserted in regions with high trap state density to block the trap-assisted conduction paths.

[0043] Secondly, the number of superlattice periods and the thickness ratio of each layer are determined based on the trapped state density distribution to achieve the best trap suppression effect. The number of superlattice periods refers to the number of repeating heterojunction units, while the thickness ratio refers to the proportion of the thickness of each layer of material. For example, in regions with high trapped state density, a denser superlattice period needs to be set to reduce the probability of carriers being trapped by the traps through periodic performance band modulation. At the same time, the thickness ratio needs to balance electric field modulation and carrier transport efficiency: an excessively thick barrier layer will hinder the formation of a two-dimensional electron gas, while an excessively thick well layer may weaken the quantum confinement effect. Using a parameter scanning method, the range of superlattice period number and thickness ratio is set, and the trapped state density suppression rate under each configuration is calculated. Finally, the configuration with a suppression rate exceeding 80% is selected as the candidate parameter.

[0044] Finally, the superlattice structure of the buffer layer was optimized by combining the number of superlattice periods and the thickness ratio. A superlattice period of 5 periods was used in the region of maximum electric field gradient, with a thickness ratio of 1:3 (2 nm for the barrier layer and 6 nm for the well layer). This reduced the trapped state density while maintaining the two-dimensional electron gas concentration. To verify the optimization effect, dual verification was required through simulation and experimental testing: the simulation observed whether the superlattice structure effectively dispersed the electric field gradient, and the experiment measured the increase in breakdown voltage and observed whether the leakage current decreased. If the simulation and experimental results were consistent, the superlattice parameters were determined to be the optimized parameters; if there were deviations, the number of periods or the thickness ratio needed to be adjusted and iterated again until the breakdown voltage temperature stability requirements were met. The final output optimized parameters of the superlattice structure include the number of superlattice periods, thickness ratio, material composition, and arrangement order.

[0045] S4. Obtain the breakdown voltage temperature compensation factor of the high electron mobility transistor based on the optimized parameters of the buffer layer superlattice structure.

[0046] Specifically, S4 includes the following steps: S41. Construct a superlattice thermal resistance distribution model based on the optimized parameters of the buffer layer superlattice structure, and obtain the equivalent thermal conductivity of the superlattice interface based on the superlattice thermal resistance distribution model.

[0047] In this embodiment, a superlattice thermal resistance distribution model is constructed based on the optimized parameters of the buffer layer superlattice structure. First, the geometry and material properties of the superlattice are defined. For example, if the number of superlattice periods is set to 5 and the thickness ratio of each layer is 1:3 (2nm for the barrier layer and 6nm for the well layer), the distribution of different materials within each period needs to be defined in three-dimensional space. The core of the thermal resistance distribution model is to quantify the thermal conduction resistance at each layer and interface: the thermal conductivity of aluminum gallium nitride (AlGaN) is lower than that of gallium nitride (GaN), and the superlattice interface may introduce additional interfacial thermal resistance due to lattice mismatch. The superlattice structure is divided into micro-units, boundary conditions are set, and the heat flow conduction path is simulated. The model needs to pay special attention to the cumulative thermal resistance effect in the vertical direction (i.e., the superlattice stacking direction): with each additional superlattice period, the vertical thermal resistance may increase by 5%-10% due to interfacial scattering, leading to a decrease in equivalent thermal conductivity.

[0048] Furthermore, the equivalent thermal conductivity is obtained based on the superlattice thermal resistance distribution model, simplifying the complex three-dimensional heat flow path into macroscopic parameters. To verify the accuracy of the model, test samples with different superlattice parameters are fabricated, and the actual thermal conductivity is measured by laser flash method. The deviation between simulation and experiment is compared. If the deviation is large, the interface thermal resistance coefficient or material thermal conductivity parameter in the model needs to be adjusted, and the calculation is iterated again until the predicted value of the equivalent thermal conductivity is consistent with the measured value. Finally, accurate equivalent thermal conductivity data is output.

[0049] The above superlattice thermal resistance distribution model satisfies the following relationship: in, The equivalent thermal conductivity of the superlattice interface, The total thickness of the superlattice is For cross-sectional area, The thermal resistance of aluminum gallium nitride is... The thermal resistance of gallium nitride, This represents the interfacial thermal resistance.

[0050] S42. Based on the equivalent thermal conductivity of the superlattice interface, thermally induced carrier ionization analysis is performed to obtain the change in trap activation energy.

[0051] In this embodiment, the phonon scattering rate is obtained by phonon transport spectrum analysis based on the equivalent thermal conductivity of the superlattice interface; the phonon-trap interaction energy is obtained by combining the phonon scattering rate with the thermal carrier energy transfer; and the trap activation energy is dynamically corrected according to the phonon-trap interaction energy to obtain the change in trap activation energy.

[0052] When performing phonon transport spectrum analysis based on the equivalent thermal conductivity of superlattice interfaces, firstly, the transport characteristics of phonons as hot carriers in the superlattice are clarified. The superlattice structure introduces phonon band gaps, which change the propagation mode of phonons. Subsequently, by combining the equivalent thermal conductivity data obtained experimentally with molecular dynamics simulations or Monte Carlo methods, the phonon scattering rate of phonons at different frequencies is obtained by tracing the scattering paths of phonons in each layer of the superlattice.

[0053] The phonon-trap interaction energy is quantified based on phonon scattering rate and the energy transfer process of hot carriers in a superlattice. Hot carriers gain kinetic energy under electric field acceleration and transfer this energy to the lattice through inelastic collisions with phonons. This process may activate trap levels in the buffer layer. The influence of phonon scattering rate on hot carrier energy is considered. For example, when the phonon scattering rate is high, hot carrier energy loss is accelerated, leading to a shorter interaction time with the trap level and a lower trap activation probability; conversely, at low scattering rates, hot carrier energy accumulates, increasing the probability of level activation. The average phonon-trap interaction energy is calculated by statistically analyzing the collision frequency and energy transfer amount between hot carriers and phonons at different temperatures.

[0054] By combining temperature data, the trap activation energy is dynamically corrected based on the phonon-trap interaction energy. The trap activation energy originally refers to the minimum energy required for a charge carrier to escape the trap, but the thermally induced carrier ionization effect reduces the actual required energy as temperature increases. Dynamic correction is achieved by incorporating the phonon-trap interaction energy into the correction term. For example, when the temperature rises from 300K to 400K, the interaction energy increases by 0.2 eV, causing the trap activation energy to be corrected from 1.5 eV to 1.3 eV, indicating that traps are more easily activated at higher temperatures. To verify the correction effect, variable-temperature testing is conducted, measuring leakage current and breakdown voltage at different temperatures, and comparing the deviations between the predicted and experimental activation energy values ​​before and after correction. If the deviation is large, the calculation parameters for phonon scattering rate or interaction energy need to be adjusted, and the correction process iterated again. The final output is the change in trap activation energy.

[0055] S43. Establish a temperature compensation factor equation based on the change in the trap activation energy to obtain the breakdown voltage temperature compensation factor.

[0056] In this embodiment, the dynamic correction amount of the activation energy is correlated with the temperature sensitivity of the breakdown voltage. The change in trap activation energy reflects the effect of thermally induced carrier ionization on the trap energy level; its value decreases with increasing temperature, leading to increased leakage current and degradation of the breakdown voltage. To counteract this effect, the temperature compensation factor equation needs to introduce an exponential term related to the change in trap activation energy. This equation compensates for the decrease in breakdown voltage caused by the reduction in activation energy by increasing the compensation factor value. To verify the effectiveness of the equation, the breakdown voltage before and after compensation is tested in the range of -50℃ to 150℃ to compare temperature stability. Finally, the temperature compensation factor is determined to ensure that the device has a stable breakdown voltage over a wide temperature range.

[0057] The above temperature compensation factor equation satisfies the following relationship: in, This is the breakdown voltage temperature compensation factor. This is the temperature reference compensation coefficient. The change in the activation energy of the trap. This represents the change in trap activation energy at a temperature of 300K. The equivalent thermal conductivity of the superlattice interface, The superlattice period number, This refers to the thickness ratio.

[0058] S5. Establish a breakdown voltage optimization model, and optimize the breakdown voltage of the high electron mobility transistor according to the breakdown voltage optimization model.

[0059] In this embodiment, a multi-parameter coupled breakdown voltage optimization objective function is constructed by combining critical breakdown electric field correlation parameters, field plate structure optimization parameters, buffer layer superlattice structure optimization parameters, and breakdown voltage temperature compensation factor; a dynamic constraint set for high electron mobility transistors is established; the breakdown voltage optimization objective function and the dynamic constraint set are used as a breakdown voltage optimization model; an optimization parameter package for high electron mobility transistors is obtained based on the breakdown voltage optimization model, and the breakdown voltage is optimized based on the optimization parameter package.

[0060] Specifically, the core of establishing the breakdown voltage optimization model is to construct a multi-parameter coupled breakdown voltage optimization objective function; the breakdown voltage optimization objective function satisfies the following relationship: in, For the optimized breakdown voltage value, The reference voltage value. This is a factor to compensate for interface defects. The characteristic length of carrier diffusion. The efficiency factor of the plate. To optimize trap density, This is the breakdown voltage temperature compensation factor. The equivalent thermal conductivity of the superlattice interface, This is the thermal conductivity calibration value.

[0061] Furthermore, the dynamic constraint set needs to cover three major categories of restrictions: electrical constraints, thermal constraints, and process constraints, to ensure that the optimization results meet actual manufacturing and reliability requirements. To dynamically quantify the constraints, a real-time monitoring mechanism is established: during the optimization process, when the number of field plate levels exceeds the process allowable value, the system automatically triggers a constraint alarm and adjusts the parameter range; when the junction temperature approaches the threshold, the temperature distribution is predicted through a thermal model, and the weighting coefficients in the objective function are corrected.

[0062] The above electrical constraints satisfy the following relationship: in, For electron mobility, This is the lower threshold of electron mobility. For process adaptation constants, The characteristic length of carrier diffusion. For thickness ratio, This is the correction amount for the trap ionization energy. Boltzmann's constant, This refers to absolute temperature.

[0063] The above thermal constraints satisfy the following relationship: in, For the junction temperature, This is the upper limit threshold for junction temperature. As the reference temperature, For process adaptation constants, The equivalent thermal conductivity of the superlattice interface, The above process constraints satisfy the following relationship: in, The length of the field plate, is the gate length.

[0064] Furthermore, based on the breakdown voltage optimization objective function and the set of dynamic constraints, the maximum breakdown voltage parameter combination satisfying all constraints is iteratively searched. The optimization process is divided into two stages: the coarse-tuning stage uses a global search algorithm to quickly locate the parameter range, and the fine-tuning stage switches to a local search algorithm to refine the optimal solution. For example, 100 sets of parameter combinations are randomly generated using the adaptive weighted particle swarm optimization algorithm. After iteration, the breakdown voltage of the optimal solution increases from 200V to 280V, while simultaneously satisfying the constraints. To verify the effectiveness of the model, test samples with corresponding parameters need to be fabricated for electrical testing, and the breakdown voltage deviation between simulation and experiment needs to be compared. If the deviation exceeds the standard, the weight coefficients or constraint thresholds in the objective function need to be adjusted, and the optimization is iterated again. The final output optimized parameter package is used for device manufacturing to achieve targeted optimization of the breakdown voltage.

[0065] Please see Figure 2 In an optional embodiment, the present invention provides a breakdown voltage optimization system for high electron mobility transistors. The system includes an input device, an output device, a processor, and a memory, all interconnected. The memory stores a computer program comprising program instructions, and the processor is configured to invoke the program instructions to execute specific steps as described in the embodiments of the high electron mobility transistor breakdown voltage optimization method provided by the present invention. The high electron mobility transistor breakdown voltage optimization system provided by the present invention has a complete and stable structure, enhancing the overall applicability and practical application capability of the present invention.

[0066] In summary, the present invention provides a method and system for optimizing the breakdown voltage of high electron mobility transistors. First, it determines the critical breakdown electric field correlation quantity based on the heterojunction bandgap parameters, and then optimizes the field plate structure to disperse the peak electric field. Subsequently, it constructs a buffer layer trap suppression model to optimize the superlattice structure, and combines a temperature compensation factor to correct the thermally induced carrier effect. Finally, it establishes a multi-physics coupling optimization model, integrating electrical, thermal, and process constraints, and outputs an optimized parameter package that balances breakdown voltage performance and manufacturing feasibility, significantly improving device reliability. The method of this invention is easy to understand, computationally simple, requires minimal workload, and is convenient for engineering applications, providing a theoretical foundation and technical support for the further development of the semiconductor technology field.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

Claims

1. A method for optimizing the breakdown voltage of a high electron mobility transistor, characterized in that, Includes the following steps: Obtain the band structure parameters of the heterojunction material of the high electron mobility transistor, and obtain the critical breakdown electric field correlation parameters based on the band structure parameters of the heterojunction material; The field plate structure optimization parameters of the high electron mobility transistor are obtained by optimizing the field plate structure based on the critical breakdown electric field correlation parameters. A buffer layer trap effect suppression model is established based on the field plate structure optimization parameters, and the buffer layer superlattice structure optimization parameters are obtained based on the buffer layer trap effect suppression model. The breakdown voltage temperature compensation factor of the high electron mobility transistor is obtained based on the optimized parameters of the buffer layer superlattice structure. A breakdown voltage optimization model is established, and the breakdown voltage of the high electron mobility transistor is optimized based on the breakdown voltage optimization model.

2. The method for optimizing the breakdown voltage of a high electron mobility transistor according to claim 1, characterized in that, The process of obtaining the bandgap parameters of the heterojunction material for high electron mobility transistors, and obtaining critical breakdown electric field correlation parameters based on the bandgap parameters of the heterojunction material, includes: A parameter measurement experiment was constructed to obtain the band structure parameters of the heterojunction material. A quantized two-dimensional electron gas concentration model is constructed based on the band parameters of the heterojunction material. The quantized energy level distribution of the high electron mobility transistor is obtained based on the quantized two-dimensional electron gas concentration model. The critical breakdown electric field correlation parameters of the high electron mobility transistor are obtained by combining the quantized energy level distribution.

3. The method for optimizing the breakdown voltage of a high electron mobility transistor according to claim 1, characterized in that, The optimization of the field plate structure of the high electron mobility transistor based on the critical breakdown electric field correlation parameters to obtain the field plate structure optimization parameters includes: An electric field reconstruction function is established based on the critical breakdown electric field correlation parameters, and the reconstructed three-dimensional electric field distribution of the high electron mobility transistor is obtained based on the electric field reconstruction function. A prediction model for the peak position of the electric field is established based on the reconstructed three-dimensional electric field distribution, and the peak position of the electric field is obtained based on the established prediction model. Based on the peak position of the electric field, a multi-level field plate structure optimization function for the high electron mobility transistor is constructed. The optimization parameters of the field plate structure are obtained based on the multi-level field plate structure optimization function.

4. The method for optimizing the breakdown voltage of a high electron mobility transistor according to claim 1, characterized in that, The step of establishing a buffer layer trap effect suppression model based on the field plate structure optimization parameters, and obtaining the buffer layer superlattice structure optimization parameters based on the buffer layer trap effect suppression model, includes: The longitudinal electric field distribution of the high electron mobility transistor is obtained based on the field plate structure optimization parameters, and the maximum electric field gradient of the buffer layer is obtained by combining the longitudinal electric field distribution. A trap level ionization correction model is constructed by combining the trap ionization energy of the buffer layer and the maximum electric field gradient, and the trap level ionization correction model is used as the trap effect suppression model of the buffer layer. The optimized parameters of the buffer layer superlattice structure are obtained by optimizing the buffer layer superlattice structure based on the buffer layer trap effect suppression model.

5. The method for optimizing the breakdown voltage of a high electron mobility transistor according to claim 4, characterized in that, The optimization parameters of the buffer layer superlattice structure are obtained by optimizing the buffer layer superlattice structure based on the buffer layer trap effect suppression model, including: Based on the buffer layer trap effect suppression model, the trap ionization energy correction is obtained to acquire the trap state density distribution; The superlattice period number and thickness ratio are obtained based on the aforementioned trap state density distribution; By combining the number of superlattice periods and the thickness ratio, the superlattice structure of the buffer layer is optimized to obtain the optimized parameters of the superlattice structure of the buffer layer.

6. The method for optimizing the breakdown voltage of a high electron mobility transistor according to claim 1, characterized in that, The step of obtaining the breakdown voltage temperature compensation factor of the high electron mobility transistor based on the optimized parameters of the buffer layer superlattice structure includes: A superlattice thermal resistance distribution model is constructed based on the optimized parameters of the buffer layer superlattice structure, and the equivalent thermal conductivity of the superlattice interface is obtained based on the superlattice thermal resistance distribution model. The change in trap activation energy was obtained by thermally induced carrier ionization analysis based on the equivalent thermal conductivity of the superlattice interface. A temperature compensation factor equation is established based on the change in the trap activation energy to obtain the breakdown voltage temperature compensation factor.

7. The method for optimizing the breakdown voltage of a high electron mobility transistor according to claim 6, characterized in that, The change in trap activation energy obtained by thermally induced carrier ionization analysis based on the equivalent thermal conductivity of the superlattice interface includes: Phonon scattering rate is obtained by phonon transport spectrum analysis based on the equivalent thermal conductivity of the superlattice interface. Based on the phonon scattering rate, the phonon-trap interaction energy is obtained by combining it with the hot carrier energy transfer. The change in trap activation energy is obtained by dynamically correcting the trap activation energy based on the phonon-trap interaction energy.

8. The method for optimizing the breakdown voltage of a high electron mobility transistor according to claim 1, characterized in that, The establishment of a breakdown voltage optimization model, and the optimization of the breakdown voltage of the high electron mobility transistor based on the breakdown voltage optimization model, includes: A multi-parameter coupled breakdown voltage optimization objective function is constructed by combining the critical breakdown electric field correlation parameters, the field plate structure optimization parameters, the buffer layer superlattice structure optimization parameters, and the breakdown voltage temperature compensation factor. Establish the set of dynamic constraints for the high electron mobility transistor; The breakdown voltage optimization objective function and the set of dynamic constraints are used as the breakdown voltage optimization model; The high electron mobility transistor is optimized based on the breakdown voltage optimization model, and the breakdown voltage is optimized based on the optimized parameter package.

9. The method for optimizing the breakdown voltage of a high electron mobility transistor according to claim 8, characterized in that, The set of dynamic constraints for establishing the high electron mobility transistor includes: Obtain the electrical constraints, thermal constraints, and process constraints of the high electron mobility transistor, and use the electrical constraints, thermal constraints, and process constraints as the set of dynamic constraint conditions.

10. A breakdown voltage optimization system for high electron mobility transistors, characterized in that, The system includes an input device, an output device, a processor, and a memory, which are interconnected. The memory stores a computer program, which includes program instructions. The processor is configured to invoke the program instructions to execute the breakdown voltage optimization method for high electron mobility transistors as described in any one of claims 1-9.

Images