Multilingual data interaction structure and chip verification IP and verification system comprising same

Abstract

The application relates to the technical field of chip verification, in particular to a multilingual data interaction structure, a chip verification IP and a verification system containing the same, and a first chip module and a second chip module carry out data interaction through the multilingual data interaction structure. The multilingual data interaction structure comprises a first sending module, a first receiving module, a second sending module, a second receiving module and a data interaction module; the first sending module, the first receiving module, the second sending module and the second receiving module are connected with the data interaction module respectively; the first chip module is connected with the first sending module and the second receiving module; and the second receiving module is connected with the second sending module and the first receiving module. The application improves the multilingual data interaction efficiency in the chip verification process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip verification, in particular to a multi-language data interaction structure, a chip verification IP containing the same and a verification system. BACKGROUND

[0002] In the process of chip verification, different levels of chip verification IPs (Verification Intellectual Property, VIP) may be involved, and different component modules are contained in the chip verification IPs. Data interaction is needed between chip verification IPs of different levels, and interaction is needed between different component modules in the chip verification IPs. However, chip verification IPs of different levels may be generated based on different languages, and different component modules in the chip verification IPs may also be generated based on different languages. Some different high-level languages can communicate directly, but high-level languages and hardware description languages usually cannot communicate directly and need to be converted. However, if the interaction is frequent, frequent conversion is needed, which greatly reduces the efficiency of data interaction, thereby affecting the efficiency of chip verification. Therefore, how to improve the efficiency of multi-language data interaction in the process of chip verification has become a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a multi-language data interaction structure, a chip verification IP containing the same and a verification system, which improves the efficiency of multi-language data interaction in the process of chip verification.

[0004] According to the first aspect of the present application, a multi-language data interaction structure is provided, a first chip module and a second chip module perform data interaction through the multi-language data interaction structure, and the multi-language data interaction structure comprises a first sending module, a first receiving module, a second sending module, a second receiving module and a data interaction module.

[0005] The first sending module, the first receiving module, the second sending module and the second receiving module are connected with the data interaction module respectively, the first chip module is connected with the first sending module and the second receiving module, and the second receiving module is connected with the second sending module and the first receiving module.

[0006] The first sending module comprises a first sending API and a first sending DPI.

[0007] The first receiving module comprises a first receiving API and a first receiving DPI.

[0008] The second sending module comprises a second sending API and a second sending DPI.

[0009] The second receiving module comprises a second receiving API and a second receiving DPI.

[0010] The data interaction module is generated based on a high-level language;

[0011] If the first chip module is generated based on a high-level language, the first chip module stores first data to the data interaction module directly through a first sending API and reads second data from the data interaction module directly through a second receiving API;

[0012] If the first chip module is generated based on a hardware description language, the first chip module stores first data to the data interaction module after converting the first data into a form described by a high-level language through a first sending DPI, and reads second data and converts the second data into a form of a hardware description language through a second receiving DPI;

[0013] If the second chip module is generated based on a high-level language, the second chip module stores second data to the data interaction module directly through a second sending API and reads first data from the data interaction module directly through a first receiving API;

[0014] If the second chip module is generated based on a hardware description language, the second chip module stores second data to the data interaction module after converting the second data into a form described by a high-level language through a second sending DPI, and reads first data and converts the first data into a form of a hardware description language through a first receiving DPI.

[0015] A chip verification IP includes a first chip module, a second chip module and a multi-language data interaction structure, the first chip module is generated based on a hardware description language, the second chip module is generated based on a high-level language, and the first chip module and the second chip module perform data interaction based on the multi-language data interaction structure.

[0016] A verification system includes a protocol layer, a conversion layer, a physical layer, a design under test and a multi-language data interaction structure, the protocol layer, the conversion layer, the physical layer and the design under test are in a hierarchical order from high to low, when two adjacent layers in the hierarchical order are set in a high-level language and a hardware description language respectively, the two adjacent layers are taken as a first chip module and a second chip module respectively, and the multi-language data interaction structure is set between the two adjacent layers, and the two adjacent layers perform data interaction based on the multi-language data interaction structure.

[0017] Compared with the prior art, the application has obvious advantages and beneficial effects. By means of the above technical scheme, the multi-language data interaction structure, the chip verification IP and the verification system provided by the application can achieve considerable technical progress and practicability, and have wide industrial utilization value, and at least have the following beneficial effects:

[0018] The application can realize bidirectional data interaction between two chip modules of different languages by setting the multi-language data interaction structure, storing the interaction data in the data interaction module first, and then reading according to the data interaction requirement, thereby improving the chip verification efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0020] Figure 1 The multi-language data interaction structure provided by the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present application.

[0022] The embodiments of the present application provide a multi-language data interaction structure, as shown in the figure. Figure 1 The first chip module and the second chip module perform data interaction through the multi-language data interaction structure. The multi-language data interaction structure comprises a first sending module, a first receiving module, a second sending module, a second receiving module and a data interaction module. The first sending module, the first receiving module, the second sending module and the second receiving module are connected with the data interaction module. The first sending module and the first receiving module correspond to each other, and the second sending module and the second receiving module correspond to each other. The first chip module is connected with the first sending module and the second receiving module, and the second receiving module is connected with the second sending module and the first receiving module.

[0023] The first sending module comprises a first sending Application Program Interface (API) and a first sending Direct Programming Interface (DPI). The first receiving module comprises a first receiving API and a first receiving DPI. The second sending module comprises a second sending API and a second sending DPI. The second receiving module comprises a second receiving API and a second receiving DPI.

[0024] The data interaction module is generated based on a high-level language, and can be generated based on a C++ language in particular. The first chip module and the second chip module are generated based on a C++ language, a Python language, or a SystemVerilog language.

[0025] If the first chip module is generated based on a high-level language, the first chip module directly stores first data to the data interaction module through a first sending API and directly reads second data from the data interaction module through a second receiving API. It should be noted that if the first chip module is generated based on a high-level language and the data interaction module is also generated based on a high-level language, the first chip module and the data interaction module can directly interact through corresponding APIs.

[0026] If the first chip module is generated based on a hardware description language, the first chip module stores first data to the data interaction module after converting the first data into a form described by a high-level language through a first sending DPI, and reads second data and converts the second data into a form of a hardware description language through a second receiving DPI. It should be noted that when the first chip module is generated based on a hardware description language, the first chip module cannot directly communicate with the data interaction module through an API, and needs to be converted through a corresponding DPI.

[0027] If the second chip module is generated based on a high-level language, the second chip module directly stores second data to the data interaction module through a second sending API and directly reads first data from the data interaction module through a first receiving API. It should be noted that if the second chip module is generated based on a high-level language and the data interaction module is also generated based on a high-level language, the second chip module and the data interaction module can directly interact through corresponding APIs.

[0028] If the second chip module is generated based on a hardware description language, the second chip module stores second data to the data interaction module after converting the second data into a form described by a high-level language through a second sending DPI, and reads first data and converts the first data into a form of a hardware description language through a first receiving DPI. It should be noted that when the second chip module is generated based on a hardware description language, the second chip module cannot directly communicate with the data interaction module through an API, and needs to be converted through a corresponding DPI.

[0029] The first chip module and the second chip module realize bidirectional communication through the multi-language data interaction structure.

[0030] As an embodiment, the data interaction module comprises a ring buffer, a chain buffer and a memory database, and one of the ring buffer, the chain buffer and the memory database is selected to work at the same time. When the first chip module and the second chip module interact based on fixed data length, the ring buffer is selected to work. When the first chip module and the second chip module interact based on non-fixed data length, the chain buffer or the memory database is selected to work. It should be noted that if the interaction data of the first chip module and the second chip module needs to be stored in a file database, the memory database needs to be selected to work, and the memory database needs to be converted to the file database.

[0031] As an embodiment, the memory database is a structured query language (SQL) database.

[0032] As an embodiment, the data interaction module comprises a first read pointer and a first write pointer. The first chip module writes first data to the ring buffer based on the first write pointer and reads second data from the ring buffer based on the first read pointer. The second chip module writes second data to the ring buffer based on the first write pointer and reads first data from the ring buffer based on the first read pointer. It should be noted that the read pointer circulates according to the order of the data interaction module, and the first chip module and the second chip module write data to the data interaction module according to the order of the read pointer circulation. When data needs to be read, it is not necessary to read in the order of storage, but the first read pointer is set according to the reading requirement, so that data can be read from the data interaction module as needed, greatly improving the data interaction efficiency of the first chip module and the second chip module. For example, when the first chip module needs to write first data to the ring buffer, the next position of the position pointed to by the current write pointer is determined as the target write position, and the first data to be written is written to the target write position. When the first chip module needs to read target data from the ring buffer, the first read pointer is pointed to the position corresponding to the target data, and the target data can be read through the first read pointer.

[0033] As an embodiment, the data interaction module comprises a second read pointer and a second write pointer. The first chip module writes first data to the chain buffer based on the second write pointer and reads second data from the chain buffer based on the second read pointer; the second chip module writes second data to the chain buffer based on the second write pointer and reads first data from the chain buffer based on the second read pointer. It should be noted that the size of the chain buffer is set according to the data interaction requirement of the first chip module and the second chip module, and the memory can be expanded according to the application requirement to improve the data interaction efficiency.

[0034] The embodiment of the present application also provides a chip verification IP, which comprises a first chip module, a second chip module and a multi-language data interaction structure, the first chip module is generated based on a hardware description language, and the second chip module is generated based on a high-level language; it is to be explained that, in the chip verification IP, the first chip module and the second chip module are component modules in the chip verification IP, and the first chip module and the second chip module perform data interaction based on the multi-language data interaction structure. It can be understood that the multi-language data interaction structure can be arranged between any two component modules of different languages in the chip verification IP, and the two component modules of different languages generally refer to one component module being generated based on a high-level language and the other component module being generated based on a hardware design language; and the component modules in the chip verification IP can be specifically algorithm modules for implementing preset algorithms.

[0035] The embodiment of the present application also provides a verification system, which comprises a protocol layer, a conversion layer, a physical layer, a design under test and a multi-language data interaction structure; the protocol layer, the conversion layer, the physical layer and the design under test are in descending order of level; generally, the upper layer is more likely to be implemented by using a high-level language, and the lower layer is more likely to be implemented by using a hardware description language, so that a situation that one of two adjacent levels is set by using a high-level language and the other is set by using a hardware description language can occur. When one of two adjacent levels is set by using a high-level language and the other is set by using a hardware description language, the two adjacent levels are taken as a first chip module and a second chip module respectively, and the multi-language data interaction structure is arranged between the two adjacent levels; the two adjacent levels perform data interaction based on the multi-language data interaction structure. It can be understood that, in the embodiment of the verification system, the first chip module and the second chip module are specifically component parts of different levels; the multi-language data interaction structure can be arranged between any two levels generated based on different languages in the verification system; and the levels generated based on different languages communicate based on the multi-language data interaction structure.

[0036] The embodiment of the present application can realize bidirectional data interaction between two chip modules of different languages by arranging the multi-language data interaction structure, store the interaction data in the data interaction module first, and then read according to the data interaction requirement, thereby improving the chip verification efficiency and further improving the chip verification efficiency.

[0037] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application. Any person skilled in the art, without departing from the technical solution of the present application, can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, as long as it does not deviate from the technical solution of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. A multilingual data interaction structure, characterized in that, The first chip module and the second chip module interact with each other through the multilingual data interaction structure, which includes a first sending module, a first receiving module, a second sending module, a second receiving module, and a data interaction module. The first transmitting module, the first receiving module, the second transmitting module, and the second receiving module are respectively connected to the data interaction module. The first chip module is connected to the first transmitting module and the second receiving module, and the second receiving module is connected to the second transmitting module and the first receiving module. The first sending module includes a first sending API and a first sending DPI; The first receiving module includes a first receiving API and a first receiving DPI; The second sending module includes a second sending API and a second sending DPI; The second receiving module includes a second receiving API and a second receiving DPI; The data interaction module is generated based on a high-level language; If the first chip module is generated based on a high-level language, then the first chip module directly stores the first data to the data interaction module through the first sending API, and directly reads the second data from the data interaction module through the second receiving API. If the first chip module is generated based on a hardware description language, then the first chip module converts the first data into a high-level language description form through a first transmitting DPI and stores it in the data interaction module, and reads the second data through a second receiving DPI and converts it into a hardware description language form; If the second chip module is generated based on a high-level language, then the second chip module directly stores the second data to the data interaction module through the second sending API, and directly reads the first data from the data interaction module through the first receiving API; If the second chip module is generated based on a hardware description language, then the second chip module converts the second data into a high-level language description form through the second transmitting DPI and stores it in the data interaction module. It reads the first data through the first receiving DPI and converts it into a hardware description language form.

2. The multilingual data interaction structure according to claim 1, characterized in that, The data interaction module includes a circular buffer, a chained buffer, and a memory database. At the same time, one task can be selected from the circular buffer, the chained buffer, and the memory database. When the first chip module and the second chip module interact based on a fixed data length, the circular buffer is selected. When the first chip module and the second chip module interact based on variable data length, a strung-chain buffer or a memory database is selected.

3. The multilingual data interaction structure according to claim 2, characterized in that, The in-memory database is an SQL database.

4. The multilingual data interaction structure according to claim 2, characterized in that, The data interaction module includes a first read pointer and a first write pointer; The first chip module writes first data to the circular buffer based on the first write pointer and reads second data from the circular buffer based on the first read pointer; The second chip module writes second data to the circular buffer based on the first write pointer and reads first data from the circular buffer based on the first read pointer.

5. The multilingual data interaction structure according to claim 2, characterized in that, The data interaction module includes a second read pointer and a second write pointer; The first chip module writes first data to the linked buffer based on the second write pointer and reads second data from the linked buffer based on the second read pointer; The second chip module writes second data to the chained buffer based on the second write pointer and reads first data from the chained buffer based on the second read pointer.

6. The multilingual data interaction structure according to claim 1, characterized in that, The data interaction module is generated based on the C++ language, and the first chip module and the second chip module are generated based on the C++, Python or SystemVerilog languages.

7. A chip verification IP, characterized in that, The system includes a first chip module, a second chip module, and a multilingual data interaction structure as described in any one of claims 1 to 6. The first chip module is generated based on a hardware description language, the second chip module is generated based on a high-level language, and the first chip module and the second chip module perform data interaction based on the multilingual data interaction structure.

8. A verification system, characterized in that, The system includes a protocol layer, a conversion layer, a physical layer, a design under test (DUT), and a multilingual data interaction structure as described in any one of claims 1 to 6. The protocol layer, conversion layer, physical layer, and DUT are arranged in descending order of hierarchy. When one of two adjacent layers is set using a high-level language and the other using a hardware description language, the two adjacent layers are respectively designated as a first chip module and a second chip module. The multilingual data interaction structure is then set between the two adjacent layers, and the two adjacent layers interact with each other based on the multilingual data interaction structure.

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