Bus coverage collection method based on verification component, electronic device and medium

Abstract

This invention relates to the field of integrated circuit technology, and more particularly to a bus coverage collection method, electronic device, and medium based on verification components. The method includes step S1: obtaining the nth group of test combinations A of the integrated circuit design. n And A n The corresponding coverage configuration file E n , where A n ={B n C n}; Steps S2 and D n According to E n Obtain the overlay group template from the preset overlay group template file, configure it, and generate A. n Corresponding target coverage group G n Steps S3 and C n To B n Send stimuli for simulation, D n Based on G n Perform coverage collection operations. This invention allows for flexible adjustment of the coverage collection logic, improving the efficiency and accuracy of integrated circuit verification.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a bus coverage collection method, electronic device, and medium based on verification components. Background Technology

[0002] In existing integrated circuit (IC) verification workflows, bus coverage collection plays a crucial role in ensuring design integrity and reliability. However, existing coverage collection methods have significant limitations, at least in the following two aspects: First, they are constrained by fixed coverage groups and coverage point definitions, making it difficult to flexibly adapt to diverse verification needs. This forces verification engineers to manually adjust the coverage collection logic when facing complex and ever-changing verification scenarios, which is not only inefficient but also prone to introducing errors. Second, they are limited to a single-platform verification environment, failing to meet the increasing demands for comprehensiveness and accuracy in integrated circuit design. With increasing design complexity, multi-platform co-simulation systems have become a development trend in the verification field, but existing coverage collection methods have not yet fully supported efficient and accurate cross-platform data collection and integration, thus hindering further verification work and resulting in low efficiency and poor accuracy in integrated circuit verification. Therefore, how to provide a coverage collection method that can flexibly adjust the coverage collection logic to improve the efficiency and accuracy of integrated circuit verification has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a bus coverage collection method, electronic device, and medium based on verification components, which can flexibly adjust the coverage collection logic and improve the efficiency and accuracy of integrated circuit verification.

[0004] According to a first aspect of the present invention, a bus coverage collection method based on a verification component is provided, comprising:

[0005] Step S1: Obtain the nth combination A to be verified in the integrated circuit design. n And A n The corresponding coverage configuration file E n , where A n ={B n C n}, B n For the nth object to be verified, C n For the nth verification component, C n It includes a preset coverage collection module D. n If B n If it is an IP module, then C n For simulation and B n Interactive bus verification component, if B n If it is the bus IP, then C n For simulation and Bn Interactive IP module verification component, E n Used to store A n The corresponding coverage collection configuration information, where n ranges from 1 to N, and N is the total number of combinations to be verified in the integrated circuit design;

[0006] Steps S2 and D n According to E n Obtain the overlay group template from the preset overlay group template file, configure it, and generate A. n Corresponding target coverage group G n ;

[0007] Steps S3 and C n To B n Send stimuli for simulation, D n Based on G n Perform coverage collection operations.

[0008] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0009] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0010] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the bus coverage collection method, electronic device, and medium provided by this invention based on verification components achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects:

[0011] This invention incorporates a pre-defined coverage collection module in each verification component and sets corresponding coverage configuration files for combinations without a verification group. The pre-defined coverage collection module directly retrieves a coverage group template from a pre-defined coverage group template file based on the configuration file. It can also adjust the coverage group template according to the coverage configuration file, thereby reusing the coverage group template and flexibly adjusting the coverage collection logic. This improves the efficiency and accuracy of coverage collection, thus enhancing the efficiency and accuracy of integrated circuit verification. Furthermore, this invention enables the reuse of combinations to be verified across multiple platforms, reducing verification costs and improving verification completeness. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A flowchart of a bus coverage collection method based on a verification component provided in an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] This invention provides a bus coverage collection method based on a verification component, such as... Figure 1 As shown, it includes:

[0016] Step S1: Obtain the nth combination A to be verified in the integrated circuit design. n And A n The corresponding coverage configuration file E n , where A n ={B n C n}, B n For the nth object to be verified, C n For the nth verification component, C n It includes a preset coverage collection module D. n If B n For the IP (Intellectual Property) module, then C n For simulation and B n Interactive bus verification component, if B n If it is the bus IP, then C n For simulation and B n Interactive IP module verification component, E n Used to store A n The corresponding coverage collection configuration information, where n ranges from 1 to N, and N is the total number of combinations to be verified in the integrated circuit design.

[0017] It should be noted that all C in the embodiments of the present invention nAll are generated based on a pre-defined general verification component architecture, which includes components such as a driver, monitor, sequencer, and reference model, as well as a pre-defined coverage collection module D. n B n This corresponds to the Register Transfer Level (RTL) code of the object to be verified, in C. n It is used for simulation and B n A validation component for interactive objects, C n Able to simulate and B n The object of interaction to B n Send stimuli for simulation verification, D n Based on E n Perform coverage collection. Coverage profile E n Specifically, the detailed configuration information for coverage collection can be flexibly set according to different verification requirements and the bus characteristics of the module under test, thereby improving the relevance and effectiveness of verification.

[0018] Steps S2 and D n According to E n Obtain the overlay group template from the preset overlay group template file, configure it, and generate A. n Corresponding target coverage group G n .

[0019] It should be noted that in existing technologies, each A needs to be considered. n Each target coverage group is written individually, but in this application, a preset coverage group template file is pre-set, D n According to E n Obtain the coverage group template from the preset coverage group template file, and then based on E n A can be generated by configuring it. n Corresponding target coverage group G n This significantly improves the efficiency of target coverage group generation. Furthermore, when dealing with highly integrated verification platforms and instantiating numerous generic verification components, this invention reduces code redundancy, lowers labor and time costs, and improves the efficiency and accuracy of coverage collection.

[0020] Steps S3 and C n To B n Send stimuli for simulation, D n Based on G n Perform coverage collection operations.

[0021] It should be noted that once the target coverage group is constructed, coverage collection can be performed directly based on the existing coverage collection operations, which will not be elaborated further here.

[0022] The embodiments of the present invention can dynamically select and enable different coverage group templates according to different verification characteristics and test points, and the coverage point definition in each selected coverage group template can also be flexibly adjusted according to the coverage collection strategy.

[0023] As one embodiment, the preset coverage group template file is used to store pre-built coverage group templates. Each coverage group template has a corresponding coverage group identifier. The coverage group template is set according to the functional characteristics of the integrated circuit. The coverage group template includes coverage group weights, multiple coverage point templates, and cross coverage point templates. Each coverage point template includes coverage point weights and multiple coverage module templates. Each coverage module template is set with one or more default values ​​among the corresponding coverage module weights, address boundaries, address bandwidth, data bit width, and read / write attributes. It should be noted that each parameter in each coverage group template is set with a default value. If the corresponding parameter value is set in the configuration file, the parameter value in the configuration file replaces the corresponding default value. If the corresponding parameter value is not set in the configuration file, the default value in the coverage group template can be used directly.

[0024] As one embodiment, step S1 includes:

[0025] Step S1: Obtain the nth combination A to be verified in the integrated circuit design. n .

[0026] Step S2, according to A n Corresponding integrated circuit functional characteristic setting A n The corresponding coverage configuration file E n E n Including A n The corresponding target coverage group identifier F n And for F n Configuration information.

[0027] It should be noted that A n The corresponding integrated circuit functional characteristics are known, and the mapping relationship between the functional characteristics and the coverage group template is also known. Therefore, according to A n The corresponding integrated circuit functional characteristics can be found in the coverage configuration file E. n Setting A in the middle n The corresponding target coverage group identifier F n For F n The configuration information can be set according to specific coverage collection requirements. For F n The configuration information can also be set to empty, when for F nWhen the configuration information is set to empty, the default value of the corresponding override group template can be used directly.

[0028] As one embodiment, step S2 includes:

[0029] Steps S21 and D n Analysis of E n Get A n The corresponding target coverage group identifier F n and F n Configuration information.

[0030] Steps S22 and D n According to F n Retrieve A from the preset overlay group template file n The corresponding overlay group template.

[0031] Steps S23 and D n F n The configuration information is configured in A n In the corresponding overlay group template, A n Parameters for which no corresponding configuration information exists in the corresponding overlay group template retain their default values, and A is generated. n Corresponding target coverage group G n .

[0032] As one embodiment, the step S3 is followed by:

[0033] Step S4, D n Analysis of G n The corresponding coverage report, obtain G n The corresponding coverage rate and coverage status information for each coverage bin, including covered and uncovered states, are provided. A first coverage tag is added to coverage bins with a covered status, and G is assigned to them. n The corresponding coverage rate and the coverage status information for each coverage bin are stored in A. n Corresponding Coverage Database H n middle.

[0034] It should be noted that during the coverage collection process, a corresponding coverage report will be generated. Based on the coverage report, the coverage status information for each coverage area can be determined. The first coverage tag is used to identify that the coverage area has been covered and was covered during the IP-level verification process.

[0035] As one embodiment, the step S4 is followed by:

[0036] Step S5: In the integrated circuit design SoC (System on Chip) verification stage, each SoC... n Mounted to the corresponding B in the SoCn superior.

[0037] It should be noted that during the SoC verification phase, each component module has corresponding RTL code, allowing direct interaction based on this code. No verification component is needed to provide stimuli; the verification component is used for coverage collection. The SoC verification phase can directly reuse all the Bs generated during the IP verification phase. n .

[0038] Step S6: Traverse H n Based on H n Coverage modules without a first coverage tag are generated as corresponding target coverage modules during the SoC verification stage of integrated circuit design.

[0039] It should be noted that during the IP verification phase, some overlay repositories are difficult to cover. This can be achieved by traversing the H... n It can accurately reflect coverage information not covered in the IP verification stage and feed it back to the SoC verification stage. The SoC verification stage can be based on H n Coverage modules without a first coverage tag are generated as corresponding target coverage modules during the SoC verification stage of integrated circuit design. This allows for further coverage of modules not covered during the IP verification stage. Furthermore, for coverage modules that are difficult to cover during the SoC stage, such as address boundaries, this information can be referenced when setting coverage group templates and configuration files during the IP verification stage. This achieves complementary coverage collection between the IP and SoC verification stages, further improving the efficiency of coverage collection.

[0040] Step S7, based on all B n Perform integrated circuit design SoC verification simulation, D n Monitoring will be conducted, if D n If the target coverage area is detected to be covered, then H will be... n The corresponding overlay repository in the middle is updated to an overlay status, and a second overlay tag is added. G is then updated. n The corresponding coverage rate.

[0041] It should be noted that the second overlay label is used to identify that the overlay has been covered and was covered during the SoC-level verification process.

[0042] The method described in this invention is not only applicable to the single-platform verification process of a single IP, but can also be seamlessly integrated into the multi-platform verification process at the SoC level, realizing the collection and integration of cross-platform coverage data.

[0043] As one embodiment, the method further includes:

[0044] Step S10: If the i-th group of combinations to be verified in the integrated circuit design is A i And the j-th group of unverified combinations A in integrated circuit design j B in i and B j For different instances of the same IP module, C i and C j For instances of the same bus verification component, and already based on A i The corresponding target coverage group G was generated. i Then A j Direct reuse of G i As A j Corresponding target coverage group G j The values ​​of i and j are both in the range of 1 to N, and i ≠ j.

[0045] It should be noted that reusing target coverage groups can further improve the efficiency of coverage collection.

[0046] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0047] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.

[0048] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.

[0049] This invention provides a preset coverage collection module in each verification component and a corresponding coverage configuration file for combinations to be verified that do not have a group. The preset coverage collection module directly obtains the coverage group template from the preset coverage group template file according to the configuration file, and can adjust the coverage group template according to the coverage configuration file, thereby reusing the coverage group template and flexibly adjusting the coverage collection logic, improving the efficiency and accuracy of coverage collection, and thus improving the efficiency and accuracy of integrated circuit verification. Furthermore, this invention enables the reuse of combinations to be verified across multiple platforms, reducing verification costs and improving verification completeness.

[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for bus coverage collection based on a verification component, characterized in that, Comprising: Step S1, obtaining an integrated circuit design n-th group of combinations to be verified A n and A n corresponding coverage profile E n , wherein A n ={B n ,C n}, B n is the n-th object to be verified, C n is the n-th verification component, C n includes a preset coverage collection module D n , if B n is an IP module, C n is a bus verification component simulating interaction with B n , if B n is a bus IP, C n is an IP module verification component simulating interaction with B n , E n is used for storing the coverage collection configuration information corresponding to A n , and n is in the range of 1 to N, N being the total number of combinations to be verified in the integrated circuit design; Step S2, D n According to E n From the preset coverage group template file, get the coverage group template, and configure to generate A n The corresponding target coverage group G n ; Step S3, C n To B n Send stimuli to simulate, D n Based on G n Perform coverage collection operation; Step S4, D n Parsing G n Corresponding coverage report, get G n Corresponding coverage and coverage state information corresponding to each coverage bin, the coverage state includes covered state and uncovered state, and add a first coverage label to the coverage bin with covered state, will G n Corresponding coverage and coverage state information corresponding to each coverage bin are stored in A n Corresponding coverage database H n In the middle; Step S5, in the integrated circuit design SoC verification stage, each C n mounted to the corresponding B n upper; Step S6, traversing H n , based on H n The cover bin without adding the first cover label in H generates a corresponding target cover bin in the integrated circuit design SoC verification stage. Step S7, based on all B n Performing integrated circuit design SoC verification simulation, D n Monitoring, if D n If the target coverage bin is covered, H n The corresponding coverage bin in the middle is updated to the coverage state, and a second coverage label is added, updating G n The corresponding coverage rate.

2. The method of claim 1, wherein, the preset coverage group template file is used to store a preset coverage group template, each coverage group template has a corresponding coverage group identifier, the coverage group template is set according to a function characteristic of an integrated circuit, and the coverage group template includes a coverage group weight, a plurality of coverage point templates, and a cross-coverage point template, each coverage point template includes a coverage point weight and a plurality of coverage bin templates, and each coverage bin template is provided with one or more default values of a corresponding coverage bin weight, an address boundary, an address bandwidth, a data bit width, and a read-write attribute.

3. The method of claim 1, wherein, the step S1 comprises: Step S1, acquiring the nth group of verification combinations A of the integrated circuit design n ; Step S2, according to A n Corresponding integrated circuit function feature setting A n Corresponding coverage configuration file E n , E n Including A n Corresponding target coverage group identifier F n And the configuration information of F n .

4. The method of claim 2, wherein, the step S2 comprises: Step S21, D n Parsing E n Acquisition A n Corresponding target coverage group identifier F n And F n Configuration information; Step S22, D n According to F n Obtain A n The corresponding coverage group template; Step S23, D n F n configuration information is configured in A n corresponding to the coverage group template, A n corresponding to the coverage group template does not exist The parameter corresponding to the configuration information is reserved as the default value, and A n corresponding to the target coverage group G n .

5. The method of claim 1, wherein, the method further comprises: Step S10: If the i-th group of combinations to be verified in the integrated circuit design is A i And the j-th group of unverified combinations A in integrated circuit design j B in i and B j For different instances of the same IP module, C i and C j For instances of the same bus verification component, and already based on A i The corresponding target coverage group G was generated. i Then A j Direct reuse of G i As A j Corresponding target coverage group G j The values ​​of i and j are both in the range of 1 to N, and i ≠ j.

6. An electronic device, comprising: Comprising: at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to perform the method of any one of claims 1-5.

7. A computer-readable storage medium, characterized in that, computer executable instructions for performing the method of any one of claims 1-5.

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