Display panel and electronic equipment

Abstract

The invention provides a display panel and electronic equipment. The display panel comprises a display area and a non-display area surrounding the display area. The display panel comprises a first initialization voltage wire located in a non-display area, and the first initialization voltage wire extends along at least one side edge of the display panel; the display panel comprises a pixel driving circuit located in a display area, and a preset initialization transistor in the pixel driving circuit is electrically connected with the first initialization voltage wire. The first initialization voltage wire extending along the edge of at least one side of the display panel is arranged in the non-display area, and the first initialization voltage wire is connected with the preset initialization transistor of the pixel driving circuit of the display area, so that the transmission resistance of the preset initialization voltage can be reduced; therefore, the difference of the preset initialization voltages obtained by the pixel driving circuits at different positions is reduced, and the problem that the brightness of the display panel is not uniform is solved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel and an electronic device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream of display devices.

[0003] However, the current manufacturing process of OLED display products needs improvement. Summary of the Invention

[0004] In order to overcome the above-mentioned shortcomings in the prior art, the purpose of this application is to provide a display panel, the display panel including a display area and a non-display area surrounding at least a portion of the display area;

[0005] The display panel includes a first initialization voltage trace located in the non-display area, the first initialization voltage trace extending along at least one edge of the display panel;

[0006] The display panel includes a pixel driving circuit located in the display area, and the preset initialization transistor in the pixel driving circuit is electrically connected to the first initialization voltage trace.

[0007] In some possible implementations, the gate of the preset initialization transistor is connected to the first scan signal, and at least one display cycle includes a first moment and a second moment. At the first moment, the turn-on pulse of the first scan signal is input to the gate of the preset initialization transistor in the M-row pixel driving circuit, and at the second moment, the turn-on pulse of the first scan signal is input to the gate of the preset initialization transistor in the N-row pixel driving circuit, where M and N are different positive integers.

[0008] Optionally, the display period includes an active phase and a passive phase, with the first moment in the active phase and the second moment in the passive phase, where M is greater than N.

[0009] In some possible implementations, the gate of the preset initialization transistor is connected to a first scan signal, and within at least one display cycle, the first scan signal connected to the gate of the same preset initialization transistor includes multiple conduction pulses;

[0010] The display cycle includes an active phase and a blank phase, with at least one conduction pulse of the first scan signal connected to the gate of at least one preset initialization transistor located in the blank phase.

[0011] In some possible implementations, the display panel also includes a light-emitting device located in the display area, the pixel driving circuit includes a first initialization transistor, the preset initialization transistor includes a first initialization transistor, and the first electrode of the light-emitting device is electrically connected to the first initialization voltage line via the first initialization transistor in the pixel driving circuit.

[0012] Alternatively, the pixel driving circuit includes a driving transistor and a second initialization transistor, the preset initialization transistor includes the second initialization transistor, and the second initialization transistor is electrically connected to the first or second terminal of the driving transistor.

[0013] Optionally, the pixel driving circuit includes a first light-emitting control transistor and / or a second light-emitting control transistor.

[0014] The first light-emitting control transistor is electrically connected between the first power supply line and the first electrode of the driving transistor, and the second light-emitting control transistor is electrically connected between the second electrode of the driving transistor and the first electrode of the light-emitting device.

[0015] Optionally, the first initialization transistor and the second initialization transistor are electrically connected to different initialization signal lines;

[0016] Optionally, the gate of the first initialization transistor and the gate of the second initialization transistor are connected to the first scan signal.

[0017] In some possible implementations, the display panel further includes a first connection trace located in the display area, and a preset initialization transistor is electrically connected to a first initialization voltage trace via the first connection trace; optionally, for the same length, the resistance of the first initialization voltage trace is less than the resistance of the first connection trace; optionally, the width of the first initialization voltage trace is greater than the width of the first connection trace.

[0018] In some possible implementations, the first initialization voltage trace includes a first portion and a second portion extending along a first direction, the first portion and the second portion being located on opposite sides of the display area;

[0019] Optionally, the first initialization voltage trace further includes a third portion extending along a second direction, the third portion connecting the first portion and the second portion, the first portion, the third portion and the second portion surrounding at least a portion of the display area; the second direction intersects the first direction;

[0020] Optionally, the display panel further includes a trace connection area located on the side of the display area away from the third portion, with the first portion and the second portion extending to the trace connection area; Optionally, the scan line connected to the gate of the preset initialization transistor extends along the second direction; Optionally, a plurality of first connection traces are arranged along the first direction, with the first connection traces connecting between the first portion and the second portion; Optionally, the display panel further includes a first connection trace located in the display area, with the preset initialization transistor electrically connected to a first initialization voltage trace via the first connection trace, and the first connection trace extending along the second direction; Optionally, the display panel further includes a plurality of second connection traces located in the display area, with the second connection traces extending along the first direction, and the plurality of second connection traces and the plurality of first connection traces arranged in a cross-shaped mesh structure; The second connection traces are electrically connected to the first initialization voltage trace; Optionally, the second connection traces and the first connection traces are electrically connected at their intersections; Optionally, the second direction is perpendicular to the first direction.

[0021] In some possible implementations, the display panel further includes a gate driving circuit located between the first initialization voltage trace and the display area; the gate driving circuit includes a scan driving circuit and / or a light emission control driving circuit.

[0022] In some possible implementations, the display panel includes:

[0023] Substrate;

[0024] The wiring layer is located on one side of the substrate, and the first initialization voltage wiring is located in the wiring layer;

[0025] The dam structure located on one side of the substrate has a first initialization voltage trace whose orthographic projection on the substrate at least partially coincides with the orthographic projection of the dam structure on the substrate.

[0026] Optionally, the orthographic projection of the side of the first initialization voltage trace away from the display area on the substrate lies within the orthographic projection of the dam structure on the substrate; Optionally, the dam structure includes a first dam and a second dam spaced apart along the direction away from the display area; Optionally, the orthographic projection of the side of the first initialization voltage trace away from the display area on the substrate lies within the orthographic projection of the second dam on the substrate; Optionally, the orthographic projection of the first initialization voltage trace on the substrate overlaps with the orthographic projections of the first dam and / or the second dam on the substrate.

[0027] In some possible implementations, the display panel includes:

[0028] Substrate;

[0029] A first wiring layer and a second wiring layer are stacked on one side of the substrate;

[0030] The first initialization voltage trace includes a first trace located in the first trace layer and a second trace located in the second trace layer, wherein the orthographic projection of the first trace on the substrate and the orthographic projection of the second trace on the substrate at least partially overlap.

[0031] Optionally, the first trace and the second trace extend in parallel; optionally, the first trace and the second trace contact at the gap between the first dam and the second dam; optionally, the dam structure includes multiple insulating layers stacked along the thickness direction of the substrate, the second trace is located between the multiple insulating layers in the dam structure, and the first trace is located on the side of the dam structure closer to the substrate; optionally, the display panel further includes a pixel defining layer located on the side of the dam structure and the second trace away from the substrate; optionally, the pixel defining layer is an inorganic insulating layer.

[0032] In some possible implementations, the display panel includes:

[0033] Substrate;

[0034] An isolation structure and a light-emitting device are located on one side of the substrate, with at least part of the isolation structure located between the light-emitting devices; the pixel driving circuit is electrically connected to the first electrode of the light-emitting device;

[0035] The isolation structure extends from one side of the display area to the non-display area and is electrically connected to the second power line.

[0036] In some possible implementations, the isolation structure includes an isolation opening; at least a portion of the light-emitting device is located within the isolation opening;

[0037] Optionally, the display panel further includes a pixel defining layer, which includes pixel openings, isolation openings, and pixel openings connected together; at least a portion of the light-emitting units are located in the pixel openings.

[0038] In some possible implementations, the isolation structure includes a support portion and a shielding portion stacked sequentially in a direction away from the substrate, wherein the orthographic projection of the support portion on the substrate is located within the orthographic projection of the shielding portion on the substrate; the orthographic projection area of ​​the support portion on the substrate is smaller than the orthographic projection area of ​​the shielding portion on the substrate; optionally, the material of the support portion includes aluminum, and / or the material of the shielding portion includes titanium.

[0039] Optionally, the isolation structure further includes a bottom located between the support and the substrate; optionally, the orthographic projection of the bottom on the substrate is within the orthographic projection of the shielding portion on the substrate; the orthographic projection area of ​​the bottom on the substrate is smaller than the orthographic projection area of ​​the shielding portion on the substrate; optionally, the material of the bottom includes molybdenum.

[0040] In some possible implementations, the light-emitting device includes a first electrode, a light-emitting unit, and a second electrode sequentially stacked along a direction away from the substrate; optionally, an isolation structure is electrically connected to the second electrode of the light-emitting device; optionally, the second electrode extends from within the isolation opening to the side of the isolation structure facing the isolation opening and contacts the isolation structure. Optionally, the second electrodes of multiple light-emitting devices are electrically connected.

[0041] In some possible implementations, the display panel further includes a first encapsulation layer located on the side of the second electrode away from the substrate, the first encapsulation layer extending from within the isolation opening to the side of the isolation structure away from the substrate; optionally, the first encapsulation layer corresponding to adjacent isolation openings is disconnected on the side of the isolation structure away from the substrate; optionally, the display panel further includes a second encapsulation layer and a third encapsulation layer located on the side of the first encapsulation layer away from the substrate and sequentially stacked in a direction away from the substrate; optionally, the materials of the first and third encapsulation layers include inorganic materials, and the material of the second encapsulation layer includes organic materials. Optionally, the display panel further includes a dam structure, the orthographic projection of the edge of the second encapsulation layer onto the substrate being located on the side of at least a portion of the orthographic projection of the dam structure onto the substrate closer to the display area.

[0042] Another object of this application is to provide an electronic device, which includes the display panel provided in this application.

[0043] Compared with the prior art, this application has the following beneficial effects:

[0044] The display panel and electronic device provided in this application reduce the transmission resistance of the preset initialization voltage by setting a first initialization voltage trace extending along at least one edge of the display panel in the non-display area and connecting the first initialization voltage trace to the preset initialization transistor of the pixel driving circuit in the display area. This reduces the difference in the preset initialization voltage obtained by the pixel driving circuit at different positions, thereby reducing the problem of uneven brightness in the display panel. Attached Figure Description

[0045] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1a This is a schematic diagram of the pixel driving circuit of the display panel;

[0047] Figure 1b This is a schematic diagram of the pixel driving circuit for another type of display panel;

[0048] Figure 2 This is a schematic diagram of the scanning state of the first scan signal corresponding to each row of pixel driving circuits in the display panel at the first moment during the effective phase.

[0049] Figure 3 This is a schematic diagram of the scanning state of the first scan signal corresponding to each row of pixel driving circuits in the display panel at the second moment during the blank phase.

[0050] Figure 4 One of the schematic diagrams of the display panel provided in this embodiment;

[0051] Figure 5 This is a second schematic diagram of the display panel provided in this embodiment;

[0052] Figure 6a A waveform diagram illustrating the driving timing of a pixel driving circuit provided in an embodiment of the present invention;

[0053] Figure 6b This is a timing diagram of at least a portion of the time period of the first scan signal corresponding to each row of pixel driving circuits in the display panel provided in this embodiment.

[0054] Figure 7a This is the third schematic diagram of the display panel provided in this embodiment;

[0055] Figure 7b This is the fourth schematic diagram of the display panel provided in this embodiment;

[0056] Figure 8 This is the fifth schematic diagram of the display panel provided in this embodiment;

[0057] Figure 9 This is the sixth schematic diagram of the display panel provided in this embodiment;

[0058] Figure 10a This is one of the cross-sectional schematic diagrams of the display panel provided in this embodiment;

[0059] Figure 10b This is a second cross-sectional schematic diagram of the display panel provided in this embodiment;

[0060] Figure 11 This is the third cross-sectional schematic diagram of the display panel provided in this embodiment;

[0061] Figure 12 This is the seventh schematic diagram of the display panel provided in this embodiment;

[0062] Figure 13 This is one of the schematic diagrams of the isolation structure provided in this embodiment;

[0063] Figure 14 This is the second schematic diagram of the isolation structure provided in this embodiment;

[0064] Figure 15 This is the fourth cross-sectional schematic diagram of the display panel provided in this embodiment.

[0065] Icons: AA - Display area; NA1 - Non-display area; NA2 - Trace connection area; 10 - First initialization voltage trace; 11 - First section; 12 - Second section; 13 - Third section; 20 - First connection trace; 40 - Second connection trace; 30 - Pixel driving circuit; D1 - First direction; D2 - Second direction; 50 - Gate driving circuit; 111 - Substrate; 112 - Intermediate film layer structure; 113 - First trace layer; 115 - Second... Trace layer; 114-First planarization layer; 116-Second planarization layer; 120-First electrode; 130-Pixel definition layer; 140-Isolation structure; 150-Light emission unit; 160-Second electrode; 170-First encapsulation layer; 180-Second encapsulation layer; 190-Third encapsulation layer; DAM-Dam structure; 141-Support part; 142-Shielding part; 143-Bottom; 60-Scan line; 70-Data line; 80-Second power line. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0067] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0068] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0069] In the description of this application, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0070] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0071] The inventors discovered that in some display panels, the traces transmitting the anode initialization voltage extend upwards from the bottom bezel of the display panel to the display area and connect with the anode initialization transistor in the pixel driving circuit. Alternatively, the traces transmitting the anode initialization voltage typically extend upwards from the bottom bezel of the display panel to the display area and form a mesh structure there. In this case, when the scanning signal controlling anode initialization is executed simultaneously across multiple lines within a frame, brightness stratification along the scanning direction can easily occur, affecting the display effect.

[0072] For example, see Figure 1a and Figure 1b In some display panels, an 8T1C pixel driving circuit is used. Under the control of the first scan signal SP2, the first initialization transistor T7 initializes the first electrode (e.g., anode) of the light-emitting device EL with a first initialization voltage Vrefn2. The first scan signal SP2, connected to the gate of the first initialization transistor T7, is also connected to the gate of the second initialization transistor T8. Under the control of the first scan signal SP2, the second initialization transistor T8 initializes the drain of the driving transistor T1 with a second initialization voltage Vrefp.

[0073] In scenarios where the source or drain of the driving transistor T1 needs to be reset at a high frequency, the source or drain of the driving transistor T1 needs to be voltage initialized multiple times within a frame. Correspondingly, the first electrode (e.g., the anode) of the light-emitting device EL also performs multiple voltage initializations within a frame.

[0074] For example, in a scheme requiring high-frequency reset of the source or drain of the driving transistor T1, a common approach is to simultaneously obtain the first scan signal SP2 in three lines within a frame, and output three pulses of the first scan signal SP2 within that frame. That is, please refer to [link to relevant documentation]. Figure 2During the display of one frame of image, three rows of pixel driving circuits simultaneously perform source or drain voltage initialization of driving transistor T1 and first electrode (e.g., anode) voltage initialization of light-emitting device EL under the control of the conduction pulse of the first scan signal SP2. For example, the pixel driving circuits of the first row, the nth row, and the 2nth row simultaneously receive the conduction pulse of the first scan signal SP2.

[0075] In this case, please see Figure 3 When a scan signal SP2 scans to the blank area BLANK outside the effective display area AA (the blank area BLANK has no pixel driving circuit; the blank area BLANK can be an area that does not actually exist, but is virtual for ease of understanding), the number of pixel rows that actually perform anode initialization simultaneously in the display area AA is reduced by 1 / 3 (for example, the pixel driving circuits of the 1+m and n+m rows simultaneously receive the conduction pulse of the first scan signal SP2, and the load changes from three rows of pixel driving circuits to two rows of pixel driving circuits). The load of the first initialization voltage Vrefn2 is reduced, which causes the anode voltage to be initialized to a lower potential when the pixel row performs anode voltage initialization, resulting in the subsequent displayed pixel rows being darker, and the display screen showing brightness and darkness stratification, producing a three-screen phenomenon.

[0076] For example, at the first moment, the conduction pulse of the first scan signal SP2 is simultaneously transmitted to the pixel driving circuits of the 1st, nth, and 2nth rows. These three pixel driving circuits simultaneously perform anode initialization. However, at the second moment, when the conduction pulse of the first scan signal SP2 is transmitted to the pixel driving circuits of the 1+m and n+m rows, since the 2n+m row is located outside the effective display area (the pixel driving circuit of the 2n+m row does not actually exist, and the actual scan circuit does not output the first scan signal corresponding to the pixel driving circuit of the 2n+m row), only the 1+m and n+m rows of pixel driving circuits are actually simultaneously anode initialized. Therefore, the load of the first initialization voltage Vrefn2 is reduced, resulting in the anode voltage in the pixel driving circuits of the 1+m and n+m rows being initialized to a lower potential compared to the pixel driving circuits of the 1st, nth, and 2nth rows. This leads to a dimmer brightness in subsequent displays, resulting in a three-screen phenomenon.

[0077] Similarly, at the first moment, the source or drain voltage of the driving transistor T1 in the pixel driving circuits of rows 1, n, and 2n is initialized simultaneously; at the second moment, the source or drain voltage of the driving transistor T1 in the pixel driving circuits of rows 1+m and n+m is initialized simultaneously; at the second moment, the load of the second initialization voltage Vrefp is reduced compared to the first moment, and the initialization degree of the source or drain voltage of the driving transistor T1 in the pixel driving circuits of rows 1+m and n+m is different from that of the source or drain voltage of the driving transistor T1 in the pixel driving circuits of rows 1, n, and 2n, thus causing display defects.

[0078] In view of this, this embodiment provides a solution to reduce the phenomenon of brightness layering in displays. The solution provided in this embodiment will be described in detail below.

[0079] Please see Figure 4 The display panel provided in this embodiment includes a display area AA and a non-display area NA1 surrounding the display area AA.

[0080] The display panel includes a first initialization voltage trace 10 located in a non-display area NA1, extending along at least one edge of the display panel. For example, the first initialization voltage trace 10 may extend along the edge of the display area AA in the non-display area NA1. The first initialization voltage trace 10 may extend along one or more of the left bezel area, right bezel area, and top bezel area of ​​the display panel. The first initialization voltage trace 10 may be electrically connected to bonding pads in the bottom bezel area. The first initialization voltage trace 10 may be located in at least two bezel areas, such as at least one of the left bezel area, right bezel area, and top bezel area, and the bottom bezel area. The at least two bezel areas include a first bezel area provided with bonding pads (which may be bonded to a chip and / or a flexible circuit board), and the at least two bezel areas also include a second bezel area adjacent to the first bezel area and / or a third bezel area opposite to the first bezel area. The first bezel area may be the bottom bezel area. The second bezel area may include one or more of the left bezel area and right bezel area. The second bezel area may include the top bezel area. The portion of the first initialization voltage trace 10 in the second frame area may extend along the length of the second frame area. The portion of the first initialization voltage trace 10 in the third frame area may extend along the length of the third frame area. The portion of the first initialization voltage trace 10 in the first frame area may extend away from the display area to electrically connect with the bonding pads.

[0081] The display panel includes multiple pixel driving circuits 30 located in the display area AA. For example, one pixel driving circuit 30 can be used to drive a light-emitting device to emit light.

[0082] The pixel driving circuit 30 may include a preset initialization transistor, which is electrically connected to the first initialization voltage trace 10. For example, the gate of the preset initialization transistor is connected to the first scan signal SP2.

[0083] In some possible implementations, the pixel driving circuit 30 can adopt, for example... Figure 1a or Figure 1b The pixel driving circuit may include a first initialization transistor T7. The display panel may also include a light-emitting device EL located in the display area, and the first electrode (e.g., anode) of the light-emitting device EL is connected to a first initialization voltage trace 10 via the first initialization transistor T7. The first initialization voltage trace 10 may be used to transmit a first initialization voltage Vrefn2, which may be used to perform voltage initialization on the first electrode (e.g., anode) of the light-emitting device EL. Optionally, the preset initialization transistor may include the first initialization transistor T7.

[0084] Optionally, the pixel driving circuit may include a driving transistor T1 and a second initialization transistor T8. For example, the preset initialization transistor includes the second initialization transistor T8. The second initialization transistor T8 is connected to the first terminal of the driving transistor T1 (e.g., Figure 1b ) or the second pole (such as Figure 1a Electrical connections can be made, for example, the first and second terminals of the driving transistor can be the source and drain, respectively. The first or second terminal of the driving transistor T1 can be electrically connected to a trace providing the second initialization voltage Vrefp via the second initialization transistor T8. One of the first and second terminals of the driving transistor can be the source, and the other can be the drain.

[0085] In some embodiments, the first initialization voltage trace 10 can be used to transmit the second initialization voltage Vrefp. The first or second terminal of the driving transistor T1 can be electrically connected to the first initialization voltage trace 10 via the second initialization transistor T8. Under the control of the conduction pulse of the first scan signal SP2, the second initialization transistor T8 performs voltage initialization on the first or second terminal of the driving transistor T1.

[0086] In some embodiments, the first initialization transistor T7 and the second initialization transistor T8 are electrically connected to different initialization signal lines. The first initialization voltage trace 10 electrically connected to one of the first initialization transistors T7 and T8 may be located in one or more of the left frame area, right frame area, and top frame area, while the initial voltage trace electrically connected to the other may not be located in the left frame area, right frame area, or top frame area. Optionally, the display panel may be provided with multiple first initialization voltage traces 10 for transmitting different initialization voltages.

[0087] In some embodiments, the first initialization transistor T7 and the second initialization transistor T8 are electrically connected to different first initial voltage traces 10. The first initial voltage traces 10 to which the first initialization transistor T7 and the second initialization transistor T8 are connected are located in one or more of the left frame region, the right frame region, and the top frame region.

[0088] In some embodiments, the gates of the first initialization transistor T7 and the second initialization transistor T8 are connected to the first scan signal SP2. The first initialization transistor T7 and the second initialization transistor T8 have the same switching state. The first initialization transistor T7 and the second initialization transistor T8 can be P-type transistors or N-type transistors.

[0089] Optionally, the pixel driving circuit may include a first light-emitting control transistor T5 and / or a second light-emitting control transistor T6.

[0090] The first light-emitting control transistor T5 is electrically connected between the first power supply line and the first electrode of the driving transistor T1. The first power supply line is used to transmit the first driving voltage ELVDD. The second light-emitting control transistor T6 is electrically connected between the second electrode of the driving transistor T1 and the first electrode (e.g., anode) of the light-emitting device EL. The second electrode (e.g., cathode) of the light-emitting device is electrically connected to the second power supply line that transmits the second driving voltage ELVSS.

[0091] Optionally, the pixel driving circuit may also include some or all of the data writing transistor T2, compensation transistor T3, third initialization transistor T4, and capacitor Cst.

[0092] Optionally, the pixel driving circuit may further include a data writing transistor T2. The gate of the data writing transistor T2 is connected to the second scan signal SP1, the first terminal of the data writing transistor T2 is connected to the data voltage Data, and the second terminal of the data writing transistor T2 is connected to the first terminal of the driving transistor T1.

[0093] Optionally, the pixel driving circuit may further include a compensation transistor T3. The gate of the compensation transistor T3 is connected to a third scan signal SN2, the first terminal of the compensation transistor T3 is connected to the second terminal of the driving transistor T1, and the second terminal of the compensation transistor T3 is connected to the gate of the driving transistor T1.

[0094] Optionally, the pixel driving circuit may further include a third initialization transistor T4. The gate of the third initialization transistor T4 is connected to a fourth scan signal SN1. The first terminal of the third initialization transistor T4 is connected to a second initialization signal line (which can be used to transmit the third initialization voltage Vrefn1). The second terminal of the third initialization transistor T4 is connected to the second terminal of the driving transistor T1, or the first terminal of the compensation transistor T3, or the gate of the driving transistor T1. Optionally, the preset initialization transistor includes the third initialization transistor T4. The first initialization voltage trace 10 may be electrically connected to the first terminal of the third initialization transistor T4 to reduce the transmission impedance of the third initialization voltage Vrefn1 and improve the consistency of the third initialization voltage Vrefn1 obtained by pixel driving circuits at different locations. The first initialization voltage trace 10 may be electrically connected to the second initialization signal line. The third initialization transistor T4, the first initialization transistor T7, and the second initialization transistor T8 may be electrically connected to different first initialization voltage traces 10.

[0095] The preset initialization transistor can be used to initialize the gate, source, drain, or first electrode of the light-emitting device of the driving transistor T1. The first initial voltage trace 10 can be used to transmit the initialization voltage required to initialize the gate, source, drain, or first electrode of the light-emitting device of the driving transistor T1. There can be multiple first initial voltage traces 10, each used to transmit the initialization voltage required to initialize multiple of the gate, source, drain, or first electrode of the light-emitting device of the driving transistor T1.

[0096] The gate of the first light-emitting control transistor T5 and / or the gate of the second light-emitting control transistor T6 are connected to the light-emitting control signal EM. The gates of both the first and second light-emitting control transistors T5 and T6 are connected to the light-emitting control signal line (which can be used to transmit the light-emitting control signal EM). The first terminal of the first light-emitting control transistor T5 is connected to the first driving voltage ELVDD. The second terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T1. The first terminal of the second light-emitting control transistor T6 is connected to the second terminal of the driving transistor T1. The second terminal of the second light-emitting control transistor T6 is also connected to the first terminal of the light-emitting device EL.

[0097] The second electrode of the light-emitting device EL is connected to the second driving voltage ELVSS.

[0098] Optionally, the pixel driving circuit may also include a capacitor Cst. The first terminal of the capacitor Cst is connected to the first driving voltage ELVDD, and the second terminal of the capacitor Cst is connected to the gate of the driving transistor T1.

[0099] It should be noted that in other implementations of this embodiment, the pixel driving circuit is not limited to the 8T1C driving circuit, and other circuit forms can also be used. No specific limitation is made in this embodiment. The aforementioned transistors can be P-type transistors or N-type transistors.

[0100] In some possible implementations, such as Figure 4 As shown, the display panel also includes a first connection trace 20 located in the display area AA, and a preset initialization transistor is connected to a first initialization voltage trace 10 via the first connection trace 20. The first connection trace 20 extends along the second direction D2.

[0101] For the same length, the resistance of the first initialization voltage trace 10 is less than the resistance of the first connection trace 20. For example, the width of the first initialization voltage trace 10 is greater than the width of the first connection trace 20.

[0102] Based on the above design, in this embodiment, by setting a first initialization voltage trace 10 extending along at least one edge of the display panel in the non-display area NA1, and connecting the first initialization voltage trace 10 to the preset initialization transistor of the pixel driving circuit 30 in the display area AA, the transmission resistance of the preset initialization voltage connected to the preset initialization transistor can be reduced, thereby reducing the difference in the preset initialization voltage obtained by the pixel driving circuit at different positions, and thus reducing the problem of uneven brightness in the display panel.

[0103] In some possible implementations, at least one display cycle (e.g., each display cycle in at least one display cycle) includes a first moment and a second moment, wherein at the first moment a conduction pulse of the first scan signal SP2 is input to the gate of the preset initialization transistor in the M-row pixel driving circuit, and at the second moment a conduction pulse of the first scan signal SP2 is input to the gate of the preset initialization transistor in the N-row pixel driving circuit, wherein M and N are different positive integers.

[0104] The display period can be the reciprocal of the refresh rate. For example, data is written once in each display period within at least one display period. The display panel may include a scan driving circuit that outputs a first scan signal SP2. The scan driving circuit may include multiple cascaded shift registers, each of which is electrically connected to the pixel driving circuit of the corresponding row. The first-stage shift register receives a start signal (which may be a pulse signal) output by the chip, and then the multiple-stage shift registers output pulse signals with the same or similar waveform as the start signal, serving as the turn-on pulses for the first scan signal SP2, which is equivalent to scanning the pixel driving circuit 30 row by row. In two adjacent shift register stages, the pulse signal output by the later stage shift register lags behind the pulse signal output by the earlier stage shift register. The turn-on pulses can control the preset initialization transistor to turn on.

[0105] For example, the display area may include k first regions and q second regions. k and q are different positive integers. The first regions and second regions may be arranged alternately along a first direction. At a first moment, a conduction pulse of the first scan signal SP2 is input to the gate of the preset initialization transistor in at least a portion of the row pixel driving circuits of the k first regions, and at a second moment, a conduction pulse of the first scan signal SP2 is input to the gate of the preset initialization transistor in at least a portion of the row pixel driving circuits of the q second regions. For example, k = q + 1. The first direction may be parallel to the column direction.

[0106] For example, the display cycle includes an active phase and a blank phase. The first moment is in the active phase, and the second moment is in the blank phase. M is greater than N.

[0107] Between the last row of pixel driving circuits in display area AA writing data from the previous frame to the first row of pixel driving circuits writing data for the next frame, there is a vertical blanking time interval, also known as the blank phase.

[0108] In some embodiments, at least one display cycle (e.g., each display cycle within at least one display cycle) includes a first time period and a second time period. At any moment during the first time period, a conduction pulse of the first scan signal SP2 is input to the gate of a preset initialization transistor in an M-row pixel driving circuit. At any moment during the second time period, a conduction pulse of the first scan signal SP2 is input to the gate of a preset initialization transistor in an N-row pixel driving circuit. M and N are different positive integers. The first time period is in an active phase, and the second time period is in a passive phase. At least a portion of the M-row pixel driving circuits corresponding to different moments during the first time period are different. At least a portion of the N-row pixel driving circuits corresponding to different moments during the second time period are different. The first time period may include a first moment. The second time period may include a second moment.

[0109] Specifically, taking the first scan signal SP2, which includes three conduction pulses connected to the gate of the same preset initialization transistor within a display cycle, as an example, please refer again to... Figure 2 In the display cycle of displaying one frame of image, the active phase begins. At the first moment of this phase, the pixel driving circuits of rows 1, n+1, and 2n+1 are scanned, receiving the conduction pulse of the first scan signal SP2. Simultaneously, the gates of the preset initialization transistors in these three pixel driving circuits receive the conduction pulse of the first scan signal SP2, i.e., M=3, equivalent to three first regions. The first scan signal SP2 continues scanning downwards line by line, scanning the pixel driving circuits after the pixel driving circuits of rows 1, n+1, and 2n+1.

[0110] As the scan continues, a blank phase begins. Please refer again. Figure 3 At the second moment, the first scan signal SP2 scans to the pixel driving circuits of rows 1+m and n+m. Since the actual number of pixel driving circuits in display area AA is less than 2n+m rows, row 2n+m is considered to have entered the blank area (BLANK) outside display area AA. This blank area (BLANK) is a logically virtual region and does not have actual pixel driving circuits. In this case, within display area AA, only the gates of the preset initialization transistors in two rows of pixel driving circuits receive the conduction pulse of the first scan signal SP2, i.e., N=2, equivalent to two second regions.

[0111] In some possible implementations, the gate of a preset initialization transistor is connected to a first scan signal SP2, and within at least one display cycle (e.g., each display cycle in at least one display cycle), the first scan signal SP2 connected to the gate of the same preset initialization transistor includes multiple turn-on pulses.

[0112] In some embodiments, the display cycle includes an active phase and a passive phase. In at least one display cycle, at least one conduction pulse of the first scan signal SP2, to which the gate of at least one preset initialization transistor is connected, is located in the passive phase. For example, in at least one display cycle, at least one conduction pulse of the first scan signal SP2, to which the gate of at least one preset initialization transistor is connected, is located in the active phase, and at least one conduction pulse is located in the passive phase.

[0113] Figure 6a A waveform diagram illustrating the driving timing of a pixel driving circuit provided in this embodiment of the invention is applicable to... Figure 1a or Figure 1b The pixel driving circuit shown is a reference. Figure 1a and Figure 6a The operation of the pixel driving circuit provided in this embodiment includes stages t1-t8.

[0114] In stage t1 (corresponding to the second initialization stage), the first scan signal SP2 is at the off level (e.g., high level), the second scan signal SP1 is at the off level (e.g., high level), the third scan signal SN2 is at the on level (e.g., high level), the fourth scan signal SN1 is at the on level (e.g., high level), and the light emission control signal EM is at the off level (e.g., high level). Therefore, the third initialization transistor T4 and the compensation transistor T3 are turned on. The third initialization voltage Vrefn1 on the second initialization signal line is transmitted to the gate of the driving transistor T1 via the third initialization transistor T4 and the compensation transistor T3, initializing the gate voltage of the driving transistor T1. The third initialization voltage Vrefn1 on the second initialization signal line is also transmitted to the second and first terminals of the driving transistor T1 via the third initialization transistor T4, initializing the second and first terminals of the driving transistor T1.

[0115] In stage t2 (corresponding to the data writing stage), the first scan signal SP2 is off (e.g., high level), the second scan signal SP1 is on (e.g., low level), the third scan signal SN2 is on (e.g., high level), the fourth scan signal SN1 is off (e.g., low level), and the light emission control signal EM is off (e.g., high level). Therefore, data writing transistor T2 and compensation transistor T3 are turned on. The data voltage Data on the data line is written to the gate of driving transistor T1 via data writing transistor T2, driving transistor T1, and compensation transistor T3. The gate voltage of driving transistor T1 is correlated with the data voltage Data and the threshold voltage of driving transistor T1, achieving threshold compensation for driving transistor T1. Capacitor Cst stores the gate voltage of driving transistor T1.

[0116] In stage t3 (corresponding to the first initialization stage), the first scan signal SP2 is at the on level (e.g., low level), the second scan signal SP2 is at the off level (e.g., high level), the third scan signal SN2 is at the off level (e.g., low level), the fourth scan signal SN1 is at the off level (e.g., low level), and the light emission control signal EM is at the off level (e.g., high level). Therefore, the first initialization transistor T7 and the second initialization transistor T8 are turned on. The first initialization voltage Vrefn2 is transmitted to the first electrode of the light-emitting device through the first initialization transistor T7 to initialize the first electrode of the light-emitting device. At the same time, the second initialization voltage Vrefp is transmitted to the first or second electrode of the driving transistor T1 through the second initialization transistor T8 to reset the voltage of the first electrode of the driving transistor T1, thereby changing the bias state of the driving transistor T1. This ensures that the threshold characteristics of the driving transistor T1 remain stable under different gray levels, thereby improving the uniformity of the driving current generated by the driving transistor T1.

[0117] During stage t4 (corresponding to the light-emitting stage), the first scan signal SP2 is at the off level (e.g., high level), the second scan signal SP1 is at the off level (e.g., high level), the third scan signal SN2 is at the off level (e.g., low level), the fourth scan signal SN1 is at the off level (e.g., low level), and the light-emitting control signal EM is at the on level (e.g., low level). Therefore, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, the connection path between the first power line and the second power line is completed, and the first driving transistor T1 generates a driving current to drive the light-emitting device (e.g., a light-emitting diode) to emit light.

[0118] The operating states of each component in stages t5 and t7 are the same as those of each component in stage t3.

[0119] The operating states of each component in stages t6 and t8 are the same as those of each component in stage t4.

[0120] It should be understood that, Figure 6a The driving timing of the pixel circuit shown is the driving timing of the corresponding row of pixel driving circuits within one display cycle frame. Within one display cycle frame, each row of pixel driving circuits sequentially performs the second initialization stage and the data writing stage. For the first scan signal SP2, there are multiple conduction pulses within one display cycle frame, for example, three conduction pulses.

[0121] For example Figure 6b The waveform may not be from the first display cycle (i.e., the first frame), but can be from a later display cycle (i.e., the second frame or a frame thereafter) after stable operation. For example... Figure 6b The waveform can be displayed as a partial time period of the first cycle (i.e., the first frame), rather than the complete waveform.

[0122] For example, see Figure 6b ,by Figure 6b Taking the illustrated scheme as an example, in a high-frequency reset scenario, three rows of pixel driving circuits simultaneously receive the conduction pulses of the first scan signal. Within one display cycle, the preset initialization transistors in the same row of pixel driving circuits can receive three conduction pulses of the first scan signal. Specifically, when scanning to the (1+m)th and (n+m)th rows, the display cycle enters a blank phase. In the (1+m)th row, some conduction pulses of the first scan signal are in the active phase, while others are in the blank phase. Similarly, in the (n+m)th row, some conduction pulses of the first scan signal are in the active phase, while others are in the blank phase.

[0123] For some possible implementations, please refer again. Figure 4The first initialization voltage trace 10 includes a first portion 11 and / or a second portion 12 extending along a first direction D1.

[0124] In some embodiments, the first initialization voltage trace 10 includes a first portion 11 and a second portion 12 extending along a first direction D1. The first portion 11 and the second portion 12 are located on opposite sides of the display area AA. The first portion 11 and the second portion 12 may be located in two opposite border areas along a second direction D2, such as the left border area and the right border area.

[0125] Optionally, the first connecting trace 20 extends along the second direction D2. The second direction D2 intersects the first direction D1, for example, the second direction D2 is perpendicular to the first direction D1.

[0126] In some embodiments, the first initialization voltage trace 10 includes a first portion 11 extending along a first direction D1. The first connection trace 20 is electrically connected to the first portion 11.

[0127] In some embodiments, the first initialization voltage trace 10 includes a second portion 12 extending along a first direction D1. The first connection trace 20 is electrically connected to the second portion 12. Optionally, see [link to relevant documentation]. Figure 5 The first initialization voltage trace 10 also includes a third portion 13 extending along the second direction D2.

[0128] Optionally, the first initialization voltage trace 10 further includes a third portion 13 extending along the second direction D2, and the first initialization voltage trace 10 also includes a first portion 11 or a second portion 12 extending along the first direction D1. The third portion 13 and the first portion 11 are located on adjacent sides of the display area AA. The third portion 13 and the first portion 11 may be located in two adjacent border areas, such as the right border area and the top border area. Alternatively, the third portion 13 and the second portion 12 are located on adjacent sides of the display area AA. The third portion 13 and the second portion 12 may be located in two adjacent border areas, such as the left border area and the top border area.

[0129] In some embodiments, the first initialization voltage trace 10 further includes a first portion 11, a third portion 13, and a second portion 12. The third portion 13 connects the first portion 11 and the second portion 12, and the first portion 11, the third portion 13, and the second portion 12 surround at least a portion of the display area AA.

[0130] In some embodiments, the first initialization voltage trace 10 includes one or more of a first portion 11, a third portion 13, and a second portion 12.

[0131] Furthermore, the display panel also includes a trace connection area NA2 located on the side of the display area AA away from the third part 13. The first part 11 and the second part 12 extend to the trace connection area NA2, and the trace connection area NA2 can be connected to the display driver chip.

[0132] In some possible implementations, multiple first connection traces 20 are arranged along a first direction D1, and the first connection traces 20 are connected between the first portion 11 and the second portion 12. That is, multiple first connection traces 20 are connected in parallel between the first portion 11 and the second portion 12. Each first connection trace 20 can transmit a preset initialization voltage (e.g., a first initialization voltage or a second initialization voltage) to multiple pixel driving circuits 30 in the same pixel row, and all multiple first connection traces 20 are connected to the first initialization voltage trace 10. Thus, since the first initialization voltage trace 10 itself has low resistance, the difference in the preset initialization voltage obtained by the first connection traces 20 at different locations from the first initialization voltage trace 10 can be reduced.

[0133] Alternatively, please refer to Figure 7a In this embodiment, the display panel further includes a plurality of second connection traces 40 located in the display area AA. The second connection traces 40 extend along the first direction D1, and the plurality of second connection traces 40 are arranged in a mesh structure with the plurality of first connection traces 20. Optionally, the second connection traces 40 are electrically connected to the first initialization voltage trace 10. That is, in this embodiment, in addition to transmitting the preset initialization voltage through the interwoven mesh structure of the first connection traces 20 and the second connection traces 40, a first initialization voltage trace 10 located in the non-display area NA1 is added to transmit the preset initialization voltage. In this way, the overall resistance of the preset initialization voltage transmission can be reduced, thereby reducing the difference in the preset initialization voltage obtained at different locations.

[0134] Optionally, the first connection trace 20 and the second connection trace 40 are electrically connected at their intersection. For example, the first connection trace 20 and the second connection trace 40 can be directly electrically connected, and / or the first connection trace 20 and the second connection trace 40 can be electrically connected through a via.

[0135] Optionally, the second connection trace 40 may be electrically connected to the third part 13. The second connection trace 40 may be electrically connected to the preset initialization transistor via the first connection trace 40. Alternatively, the second connection trace 40 may be directly electrically connected to the preset initialization transistor, rather than indirectly connected to the preset initialization transistor via the first connection trace 40.

[0136] In some other possible implementations, please participate. Figure 7bThe display panel may also include only a second connection trace 40 extending along the first direction D1. The second connection trace 40 may be electrically connected to the third part 13, and the second connection trace 40 may be directly electrically connected to the preset initialization transistor. That is, the preset initialization voltage transmitted by the first initialization voltage trace 10 is transmitted to the preset initialization transistor of each pixel driving circuit 30 through the second connection trace 40.

[0137] See also some possible implementations. Figure 8 , Figure 8 The enlarged view of the area circled by the dashed line in Figure 7 shows that the display panel may also include a gate driving circuit 50, which is located between the first initialization voltage trace 10 and the display area AA.

[0138] The gate drive circuit can be used to output one or more of the following: first scan signal SP2, second scan signal SP1, third scan signal SN2, fourth scan signal SN1, and light emission control signal EM.

[0139] In some embodiments, the gate driving circuit 50 is located between the first portion 11 and / or the second portion 12 and the display area AA. At least a portion of the gate driving circuit 50 is located between the first portion 11 and the display area AA. And / or, at least a portion of the gate driving circuit 50 is located between the second portion 12 and the display area AA. That is, the first portion 11 and / or the second portion 12 are located on the side of the gate driving circuit 50 away from the display area AA.

[0140] In some embodiments, each row of pixel driving circuits may correspond to a shift register in the gate driving circuit 50.

[0141] In some embodiments, the gate driving circuit 50 may include a scan driving circuit and / or a light emission control driving circuit. The scan driving circuit may be electrically connected to a scan line. The light emission control driving circuit may be electrically connected to a light emission control signal line. The scan driving circuit may output one or more of a first scan signal SP2, a second scan signal SP1, a third scan signal SN2, and a fourth scan signal SN1, which can then be transmitted to the pixel driving circuit via the corresponding scan line. The display panel may include multiple scan driving circuits. Multiple of the first scan signal SP2, the second scan signal SP1, the third scan signal SN2, and the fourth scan signal SN1 may share the same scan driving circuit. The light emission control driving circuit may output a light emission control signal EM, which can then be transmitted to the pixel driving circuit via the corresponding light emission control signal line. The light emission control driving circuit may be located between the first initialization voltage trace 10 and the scan driving circuit. The scan driving circuit may be located between the light emission control driving circuit and the display area.

[0142] Please refer to Figure 9In the display panel provided in this embodiment, the scan line 60, which connects to the gate driving circuit 50 to transmit scan signals (the first scan signal SP2 as shown in FIG1) to the pixel driving circuit, extends along the second direction D2. Optionally, the scan line 60 connected to the gate of the preset initialization transistor extends along the second direction D2.

[0143] Optionally, in the display panel provided in this embodiment, please refer to Figure 9 The display panel may also include a data line 70. The data line 70, which transmits the data voltage Data to the pixel driving circuit 30, extends along a first direction D1.

[0144] In some possible implementations, the display panel also includes a dam structure DAM located in the non-display area NA1; for details, please refer to [link to relevant documentation]. Figure 10a and Figure 10b , Figure 10b for Figure 10a A cross-sectional view of position AA in the middle. The display panel provided in this embodiment may include a substrate 111, a wiring layer and a dam structure DAM.

[0145] The wiring layer is located on one side of the substrate 111, and the first initialization voltage wiring 10 is located on the wiring layer (such as the first wiring layer 113 and / or the second wiring layer 115).

[0146] The dam structure DAM is located on the side of the trace layer away from the substrate 111. The dam structure DAM can be formed by stacking at least one planarization layer (such as the first planarization layer 114 and / or the second planarization layer 116) and the pixel defining layer 130. For example, the orthographic projection of the first initialization voltage trace 10 on the substrate 111 at least partially coincides with the orthographic projection of the dam structure DAM on the substrate 111, so as to reduce the impact of the first initialization voltage trace 10 on the bezel width.

[0147] In some possible implementations, the orthographic projection of the side of the first initialization voltage trace 10 away from the display area AA on the substrate 111 lies within the orthographic projection of the dam structure DAM on the substrate 111, in order to reduce the impact of the first initialization voltage trace 10 on the bezel width.

[0148] Optionally, in this embodiment, the dam structure DAM includes a first dam DAM1 and a second dam DAM2 arranged sequentially at intervals along a direction away from the display area AA.

[0149] Optionally, the orthographic projection of the side of the first initialization voltage trace 10 away from the display area AA on the substrate 111 lies within the orthographic projection of the second dam DAM2 on the substrate 111.

[0150] Optionally, the orthographic projection of the first initialization voltage trace 10 on the substrate 111 overlaps with the orthographic projection of the first dam DAM1 and / or the second dam DAM2 on the substrate 111.

[0151] Optionally, the orthographic projection of the first initialization voltage trace 10 on the substrate 111 overlaps with the orthographic projection of the first dam DAM1 on the substrate 111 to increase the width of the first initialization voltage trace 10 and reduce the impedance.

[0152] Optionally, the orthographic projection of the first initialization voltage trace 10 on the substrate 111 overlaps with the orthographic projection of the second dam DAM2 on the substrate 111 to increase the width of the first initialization voltage trace 10 and reduce the impedance.

[0153] Optionally, in this embodiment, the dam structure DAM can be used to block subsequent encapsulation layers that are fluid during the manufacturing process, such as the second encapsulation layer 180. That is, in the display panel, the orthographic projection of the edge of the second encapsulation layer 180 (the end away from the display area AA) onto the substrate 111 is located on the side of the orthographic projection of at least a portion of the dam structure DAM (such as the second dam DAM2) onto the substrate 111 that is closer to the display area AA.

[0154] In some possible implementations, the first initialization voltage trace 10 can be formed by traces in two or more trace layers. For example, please refer again... Figure 10a The display panel includes a substrate 111, a first wiring layer 113 and a second wiring layer 115.

[0155] The first wiring layer 113 and the second wiring layer 115 are located on one side of the substrate 111 and are stacked. The first initialization voltage wiring 10 includes a first wiring located on the first wiring layer 113 and a second wiring located on the second wiring layer 115. The orthographic projection of the first wiring on the substrate 111 and the orthographic projection of the second wiring on the substrate 111 at least partially overlap. For example, the first wiring and the second wiring extend in parallel along a first direction D1 in the first wiring layer 113 and the second wiring layer 115, respectively.

[0156] Specifically, an intermediate film layer structure 112 may be disposed on one side of the substrate 111. The intermediate film layer structure 112 may include a buffer layer, an active layer, multiple other conductive layers (e.g., metal layers), and multiple insulating layers. A first wiring layer 113 may be located on the side of the intermediate film layer structure 112 away from the substrate 111. A first planarization layer 114 may also be disposed on the side of the first wiring layer 113 away from the substrate 111. The first planarization layer 114 may have overlap holes that expose the first wiring located on the first wiring layer 113. A second wiring layer 115 is located on the side of the first planarization layer 114 away from the substrate 111. The second wiring located on the second wiring layer 115 may be electrically connected to the first wiring through the overlap holes.

[0157] Optionally, the side of the second wiring layer 115 away from the substrate 111 may further include a second planarization layer 116 and a pixel defining layer 130 stacked together. The dam structure DAM can be formed by stacking the first planarization layer 114, the second planarization layer 116, and the pixel defining layer 130.

[0158] Optionally, the first trace and the second trace contact at the gap between the first dam DAM2 and the second dam DAM1 to increase the contact area and reduce impedance. The first trace may be located in at least two border areas. The second trace may be located in at least two border areas. The first trace may extend along one or more of the left border area, right border area, and top border area. The second trace may extend along one or more of the left border area, right border area, and top border area. The positions of the first trace, the second trace, and the first initialization voltage trace 10 are the same or similar. The border areas where the first trace, the second trace, and the first initialization voltage trace 10 are located may be the same or different.

[0159] Optionally, the dam structure DAM includes multiple insulating layers stacked along the thickness direction of the substrate 111, with the second trace located between the multiple insulating layers in the dam structure DAM, and the first trace located on the side of the dam structure DAM closer to the substrate 111. The multiple insulating layers in the dam structure DAM may include multiple organic layers, such as multiple planarization layers, such as the first planarization layer 114 and the second planarization layer 115.

[0160] Optionally, the display panel may also include a pixel defining layer 130, for example, located on the side of the dam structure DAM and the second trace away from the substrate 111.

[0161] Optionally, the pixel defining layer 130 is an inorganic insulating layer, such as a silicon oxide layer and / or a silicon nitride layer, which helps improve the packaging effect and reduces the risk of the second trace being oxidized by moisture. The third packaging layer can contact the pixel defining layer 130 in the non-display area to improve the packaging effect.

[0162] See also some possible implementations. Figure 11 The display panel includes a substrate 111, an isolation structure 140, and a light-emitting device.

[0163] The substrate 111 and the isolation structure may also include multiple film layers such as an intermediate film layer structure 112, a first wiring layer 113, a first planarization layer 114, a second wiring layer 115, and a second planarization layer 116. In the display area AA, these multiple film layer structures form multiple thin film transistors (TFTs) at different locations, and the thin film transistors can cooperate with each other to form multiple pixel driving circuits 30.

[0164] The isolation structure 140 is located on one side of the substrate 111. See also... Figure 12 An isolation structure 140 extends from one side of the display area AA to the non-display area NA1 and is electrically connected to a second power line 80. At least a portion of the isolation structure 140 is located between the light-emitting devices. The second power line 80 can be used to transmit a second driving voltage ELVSS. One of the first power line and the second power line 80 is used to transmit a high voltage, and the other is used to transmit a low voltage. For example, the first power line is used to transmit a high voltage, and the second power line is used to transmit a low voltage. The pixel driving circuit is electrically connected to the first electrode of the light-emitting device. The isolation structure can be electrically connected to the second electrode of the light-emitting device. The isolation structure may include a conductive material.

[0165] Among them, patent applications PCT / CN2023 / 134518, 202310759370.2, 202310740412.8, 202310707209.0, and 202311346196.5 describe the relevant technical solutions of the isolation structure 140, the contents of which are incorporated herein by reference.

[0166] See also some possible implementations. Figure 11 The isolation structure 140 includes an isolation opening. At least a portion of the light-emitting device EL is located within the isolation opening.

[0167] Furthermore, the display panel also includes a pixel defining layer 130. For example, the pixel defining layer 130 is located between the isolation structure 140 and the substrate 111. The pixel defining layer 130 includes a pixel opening, an isolation opening, and the pixel opening is in communication. The pixel opening exposes a first electrode of a light-emitting device. Optionally, at least a portion of the light-emitting unit 1150 is located within the pixel opening.

[0168] Optionally, the pixel defining layer 130 may be provided with a clearance opening, and the isolation structure 140 may be located within the clearance opening. Alternatively, the isolation structure 140 may be located on the side of the pixel defining layer 130 away from the substrate 111.

[0169] See also some possible implementations. Figure 11 and Figure 13 The isolation structure 140 includes a support portion 141 and a shielding portion 142 stacked along a direction away from the substrate 111. The orthographic projection of the support portion 141 onto the substrate 111 lies within the orthographic projection of the shielding portion 142 onto the substrate 111, and the area of ​​the orthographic projection of the support portion 141 onto the substrate 111 is smaller than the area of ​​the orthographic projection of the shielding portion 142 onto the substrate 111. That is, the support portion 141 and the shielding portion 142 form an undercut structure. For example, the isolation structure 140 has a T-shaped structure. One or more of the support portion 141 and the shielding portion 142 include a conductive material.

[0170] Optionally, the corrosion resistance of the support portion 141 is lower than that of the shielding portion 142. For example, the material of the support portion 141 may include aluminum, and / or the material of the shielding portion 142 may include titanium. In this way, an undercut structure can be formed by side etching.

[0171] Alternatively, see [link to relevant documentation] for some possible implementations. Figure 14 The isolation structure 140 also includes a bottom 143 located between the support 141 and the substrate 111. The bottom 143 may include a conductive material. The material of the bottom 143 may include molybdenum.

[0172] Furthermore, the orthographic projection of the bottom 143 on the substrate 111 lies within the orthographic projection of the shielding portion 142 on the substrate 111, and the area of ​​the orthographic projection of the bottom 143 on the substrate 111 is smaller than the area of ​​the orthographic projection of the shielding portion 142 on the substrate 111. For example, the isolation structure 140 has an I-shaped structure.

[0173] In some possible implementations, the display panel also includes a first electrode 120, a light-emitting unit 150, and a second electrode 160 stacked in a direction away from the substrate 111.

[0174] The isolation structure 140 can enclose multiple isolation openings. This isolation structure 140 allows for the formation of multiple spaced-apart light-emitting units of different colors and corresponding second electrodes in the light-emitting functional layer and second electrode layer without the need for a fine metal mask, thereby reducing the manufacturing cost of the display panel. The isolation structure 140 isolates the light-emitting layer and second electrode in the light-emitting device, making different light-emitting devices independent, thus reducing crosstalk between adjacent light-emitting devices and improving display performance. Furthermore, the independence of adjacent light-emitting devices allows for independent packaging, improving packaging yield. Simultaneously, due to the presence of the isolation structure 140, the light-emitting layer and second electrode in each color light-emitting device in the display panel can be fabricated and patterned on a whole surface first, eliminating the need for a fine metal mask and saving on display panel manufacturing costs.

[0175] Optionally, the second electrode 160 extends from the isolation opening to contact the side of the isolation structure 140 facing the isolation opening. The isolation structure is electrically connected to the second electrode of the light-emitting device. Optionally, the second electrodes of multiple light-emitting devices are electrically connected. Optionally, the second electrodes of multiple light-emitting devices are electrically connected through the isolation structure to reduce the transmission impedance corresponding to the second driving voltage ELVSS. Optionally, the second electrodes of all light-emitting devices are electrically connected through the isolation structure. Optionally, the second power line is only provided in the first frame area, such as the lower frame area. The second power line is only provided in one frame area. The second power line is located outside the left frame area, right frame area, and upper frame area.

[0176] In this embodiment, the first electrode 120 can be connected to the pixel driving circuit 30, and the second electrode 160 can be connected to the second power line through the isolation structure 140. When there is a potential difference between the first electrode 120 and the second electrode 160, the light-emitting unit 150 located between the first electrode 120 and the second electrode 160 is driven to emit light. Based on the above design, in this embodiment, since the isolation structure 140 with high conductivity or high conductivity effect is adopted, for example, the film thickness of the isolation structure 140 is greater than the film thickness of the second electrode 160, and / or the conductivity of the isolation structure 140 is greater than the conductivity of the second electrode 160, the isolation structure 140 transmits the common voltage. Thus, it is not necessary to set the trace for transmitting the common voltage in the non-display area NA1 around the display area AA. Instead, the first initialization voltage trace 10 is set in the non-display area NA1 around the display area AA, thereby reducing the difference in the preset initialization voltage (e.g., the first initialization voltage Vrefn2) obtained by the pixel driving circuit at different positions, thereby reducing the problem of uneven brightness in the display panel.

[0177] In some possible implementations, such as Figure 11 and Figure 15 As shown, the display panel also includes a first encapsulation layer 170 located on the side of the second electrode 160 away from the substrate 111, the first encapsulation layer 170 extending from the isolation opening to the side of the isolation structure 140 away from the substrate 111.

[0178] Optionally, the first encapsulation layer 170 corresponding to the adjacent isolation opening is disconnected on the side of the isolation structure 140 away from the substrate 111.

[0179] See also some possible implementations. Figure 15 The display panel also includes a second encapsulation layer 180 and a third encapsulation layer 190 located on the side of the first encapsulation layer 170 away from the substrate 111 and stacked in a direction away from the substrate 111.

[0180] Optionally, the materials of the first encapsulation layer 170 and the third encapsulation layer 190 include inorganic materials, and the material of the second encapsulation layer 180 includes organic materials. For example, the first encapsulation layer 170 and the third encapsulation layer 190 can be formed by chemical vapor deposition (CVD), and the second encapsulation layer 180 can be formed by inkjet printing (IJP).

[0181] For example, see Figure 15In the display area, the display panel includes a substrate 111 and, in a direction away from the substrate 111, sequentially stacked layers: an active layer 1121, a gate insulating layer 1122, a gate layer 1123, a capacitor dielectric layer 1124, a capacitor electrode layer 1125, an interlayer insulating layer 1126, a source / drain layer (i.e., a first wiring layer 113), a first planarization layer 114, a second wiring layer 115, and a second planarization layer 116. The second planarization layer 116 may be located between the film layer containing the light-emitting device and the substrate 111. The second planarization layer 116 may also be located between the pixel defining layer 130 and the substrate 111.

[0182] In this process, the orthogonal projection of a portion of the traces in the gate layer 1124 onto the substrate 111 coincides with the orthogonal projection of the semiconductor portion of the semiconductor trace segment in the active layer 1121 onto the substrate 111, thereby forming the gate in the TFT.

[0183] The orthographic projection of a portion of the traces in the capacitor electrode layer 1125 onto the substrate 111 coincides with the orthographic projection of a portion of the traces in the gate layer 1123 onto the substrate 111, to form a structure as shown below. Figure 8 a and Figure 8 The capacitor Cst shown in b.

[0184] Part of the traces in the source-drain layer (i.e., the first trace layer 113) are electrically connected to the conductor portion of the semiconductor trace segment in the active layer 1121 through vias that pass through the first planarization layer 114, the interlayer insulating layer 1126, the capacitor dielectric layer 1124, and the gate insulating layer 1122, so as to form the source or drain of the TFT.

[0185] Each signal line or trace can extend along its direction in one or more combinations of straight lines, curves, and broken lines.

[0186] This application also provides an electronic device, which includes the display panel provided in this application. The electronic device may include mobile phones, tablets, smart wearable devices, televisions, laptops, monitors, and other devices with display functions.

[0187] This application also provides an electronic device, which includes the display panel provided in this application. The electronic device may include mobile phones, tablets, smart wearable devices, televisions, laptops, monitors, and other devices with display functions.

[0188] In summary, the display panel and electronic device provided in this application, by setting a first initialization voltage trace in the non-display area and connecting the first initialization voltage trace extending along at least one edge of the display panel to the anode initialization transistor of the pixel driving circuit in the display area, can reduce the transmission resistance of the first initialization voltage, thereby reducing the difference in preset initialization voltages (e.g., the first initialization voltage Vrefn2 and / or the second initialization voltage Vrefnp) obtained by the pixel driving circuits at different locations, and thus reducing the problem of uneven brightness in the display panel.

[0189] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0190] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area surrounding at least a portion of the display area; The display panel includes a first initialization voltage trace located in the non-display area, the first initialization voltage trace extending along at least one edge of the display panel; The display panel includes a pixel driving circuit located in the display area, and the preset initialization transistor in the pixel driving circuit is electrically connected to the first initialization voltage trace.

2. The display panel according to claim 1, characterized in that, The gate of the preset initialization transistor is connected to the first scan signal. At least one display cycle includes a first moment and a second moment. At the first moment, the conduction pulse of the first scan signal is input to the gate of the preset initialization transistor in the pixel driving circuit of row M. At the second moment, the conduction pulse of the first scan signal is input to the gate of the preset initialization transistor in the pixel driving circuit of row N. M and N are different positive integers. Preferably, the display cycle includes an active phase and a passive phase, the first moment is in the active phase, the second moment is in the passive phase, and M is greater than N.

3. The display panel according to claim 1, characterized in that, The gate of the preset initialization transistor is connected to a first scan signal. Within at least one display cycle, the first scan signal connected to the gate of the same preset initialization transistor includes multiple conduction pulses. The display cycle includes an active phase and a blank phase, and at least one of the conduction pulses of the first scan signal connected to the gate of at least one of the preset initialization transistors is located in the blank phase.

4. The display panel according to claim 1, characterized in that, The display panel further includes a light-emitting device located in the display area, the pixel driving circuit includes a first initialization transistor, the preset initialization transistor includes the first initialization transistor, and the first electrode of the light-emitting device is electrically connected to the first initialization voltage line through the first initialization transistor in the pixel driving circuit. Alternatively, the pixel driving circuit includes a driving transistor and a second initialization transistor, the preset initialization transistor includes a second initialization transistor, and the second initialization transistor is electrically connected to the first or second terminal of the driving transistor; Preferably, the pixel driving circuit includes a first light-emitting control transistor and / or a second light-emitting control transistor. The first light-emitting control transistor is electrically connected between the first power supply line and the first electrode of the driving transistor, and the second light-emitting control transistor is electrically connected between the second electrode of the driving transistor and the first electrode of the light-emitting device; Preferably, the first initialization transistor and the second initialization transistor are electrically connected to different initialization signal lines; Preferably, the gates of the first initialization transistor and the second initialization transistor are connected to the first scan signal.

5. The display panel according to claim 1, characterized in that, The display panel also includes a first connection trace located in the display area, and the preset initialization transistor is electrically connected to the first initialization voltage trace via the first connection trace. Preferably, for the same length, the resistance of the first initialization voltage trace is less than the resistance of the first connection trace; Preferably, the width of the first initialization voltage trace is greater than the width of the first connection trace.

6. The display panel according to claim 1, characterized in that, The first initialization voltage trace includes a first portion and a second portion extending along a first direction, the first portion and the second portion being located on opposite sides of the display area; Preferably, the first initialization voltage trace further includes a third portion extending along a second direction, the third portion connecting the first portion and the second portion, the first portion, the third portion and the second portion surrounding at least a portion of the display area; The second direction intersects with the first direction; Preferably, the display panel further includes a wiring connection area located on the side of the display area away from the third portion, and the first portion and the second portion extend to the wiring connection area; Preferably, the scan line connected to the gate of the preset initialization transistor extends along the second direction; Preferably, a plurality of the first connection traces are arranged along the first direction, and the first connection traces are connected between the first portion and the second portion; Preferably, the display panel further includes a first connection trace located in the display area, the preset initialization transistor being electrically connected to the first initialization voltage trace via the first connection trace, and the first connection trace extending along the second direction; Preferably, the display panel further includes a plurality of second connection traces located in the display area, the second connection traces extending along the first direction, and the plurality of second connection traces and the plurality of first connection traces being arranged in a mesh structure; the second connection traces are electrically connected to the first initialization voltage traces; Preferably, the second connection trace is electrically connected to the first connection trace at the intersection point; Preferably, the second direction is perpendicular to the first direction.

7. The display panel according to claim 1, characterized in that, The display panel further includes a gate driving circuit, which is located between the first initialization voltage trace and the display area. The gate driving circuit includes a scanning driving circuit and / or a light emission control driving circuit.

8. The display panel according to claim 1, characterized in that, The display panel includes: Substrate; A wiring layer located on one side of the substrate, wherein the first initialization voltage wiring is located in the wiring layer; A dam structure located on one side of the substrate, wherein the orthographic projection of the first initialization voltage trace on the substrate at least partially coincides with the orthographic projection of the dam structure on the substrate; Preferably, the orthographic projection of the side of the first initialization voltage trace away from the display area onto the substrate lies within the orthographic projection of the dam structure onto the substrate; Preferably, the dam structure includes a first dam and a second dam arranged at intervals along a direction away from the display area; Preferably, the orthographic projection of the side of the first initialization voltage trace away from the display area on the substrate is located within the orthographic projection of the second dam on the substrate; Preferably, the orthographic projection of the first initialization voltage trace on the substrate overlaps with the orthographic projection of the first dam and / or the second dam on the substrate.

9. The display panel according to claim 8, characterized in that, The display panel includes: Substrate; A first wiring layer and a second wiring layer are stacked on one side of the substrate; The first initialization voltage trace includes a first trace located in the first trace layer and a second trace located in the second trace layer, wherein the orthographic projection of the first trace on the substrate and the orthographic projection of the second trace on the substrate at least partially overlap. Preferably, the first trace and the second trace extend in parallel; Preferably, the first cable and the second cable contact each other at the gap between the first embankment and the second embankment; Preferably, the dam structure includes multiple insulating layers stacked along the thickness direction of the substrate, the second trace is located between the multiple insulating layers in the dam structure, and the first trace is located on the side of the dam structure closer to the substrate; Preferably, the display panel further includes a pixel defining layer located on the side of the dam structure and the second trace away from the substrate; Preferably, the pixel defining layer is an inorganic insulating layer.

10. The display panel according to claim 1, characterized in that, The display panel includes: Substrate; An isolation structure and a light-emitting device are located on one side of the substrate, with at least a portion of the isolation structure located between the light-emitting devices; the pixel driving circuit is electrically connected to the first electrode of the light-emitting device; The isolation structure extends from one side of the display area to the non-display area and is electrically connected to the second power line.

11. The display panel according to claim 10, characterized in that, The isolation structure includes an isolation opening; at least a portion of the light-emitting device is located within the isolation opening; Preferably, the display panel further includes a pixel defining layer, the pixel defining layer including a pixel opening, the isolation opening communicating with the pixel opening, and at least a portion of the light-emitting unit located in the pixel opening.

12. The display panel according to claim 10, characterized in that, The isolation structure includes a support portion and a shielding portion stacked sequentially along a direction away from the substrate, wherein the orthographic projection of the support portion on the substrate is located within the orthographic projection of the shielding portion on the substrate; The projected area of ​​the support portion on the substrate is smaller than the projected area of ​​the shielding portion on the substrate; Preferably, the material of the support portion includes aluminum, and / or the material of the shielding portion includes titanium; Preferably, the isolation structure further includes a bottom located between the support and the substrate; Preferably, the orthographic projection of the bottom on the substrate is located within the orthographic projection of the shielding portion on the substrate; The projected area of ​​the bottom on the substrate is smaller than the projected area of ​​the shielding portion on the substrate; Preferably, the material of the bottom includes molybdenum.

13. The display panel according to claim 10, characterized in that, The light-emitting device includes a first electrode, a light-emitting unit, and a second electrode, which are sequentially stacked along a direction away from the substrate. Preferably, the isolation structure is electrically connected to the second electrode of the light-emitting device; Preferably, the second electrode extends from the isolation opening to the side of the isolation structure facing the isolation opening and contacts the isolation structure; Preferably, the second electrodes of the plurality of light-emitting devices are electrically connected.

14. The display panel according to claim 13, characterized in that, The display panel further includes a first encapsulation layer located on the side of the second electrode away from the substrate, the first encapsulation layer extending from the isolation opening to the side of the isolation structure away from the substrate; Preferably, the first encapsulation layer corresponding to adjacent isolation openings is disconnected on the side of the isolation structure away from the substrate; Preferably, the display panel further includes a second encapsulation layer and a third encapsulation layer disposed sequentially on the side of the first encapsulation layer away from the substrate and in a direction away from the substrate; Preferably, the materials of the first encapsulation layer and the third encapsulation layer include inorganic materials, and the material of the second encapsulation layer includes organic materials; Preferably, the display panel further includes a dam structure, wherein the orthographic projection of the edge of the second encapsulation layer on the substrate is located on the side of at least a portion of the orthographic projection of the dam structure on the substrate closer to the display area.

15. An electronic device, characterized in that, The electronic device includes the display panel as described in any one of claims 1-14.

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