Temperature detection type ISPP algorithm for RRAM memory chip read-write circuit and hardware implementation method thereof

Abstract

The ISPP algorithm is applied to the RRAM chip read-write circuit, temperature detection is combined, the programmable characteristic of an FPGA is utilized, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC) and related peripheral hardware circuits are combined, and a hardware platform is built to perform read operation and write operation on the RRAM chip. In order to improve the writing speed while ensuring the accuracy of the written data, the ISPP algorithm is adopted to gradually increase the writing data voltage at the two ends of the RRAM device, and the data reading voltage is matched to verify whether the data written into the RRAM chip is correct or not. According to the read-write condition of the RRAM chip, the RRAM chip is divided into three states, namely reading RRAM chip data, writing data '1' and writing data '0'. According to the design, while the read-write efficiency of the RRAM chip is improved, the accuracy and reliability of written data are ensured, and the method has certain engineering value.

Description

Technical Field

[0001] This invention relates to RRAM chips, primarily focusing on data writing and reading operations for RRAM chips. The main innovation lies in providing a reading method and a writing method for RRAM chips. This improves writing efficiency while ensuring the reliability of data writing to RRAM memory chips. Background Technology

[0002] The most important device unit in an RRAM memory chip is the RRAM device unit itself. RRAM, or memristor, is a passive electronic component. Like a resistor, a memristor generates and maintains a safe current flowing through a device. However, unlike a resistor, a memristor can "remember" the amount of charge that passed through it even after the power is turned off. RRAM memory matrices can be divided into passive and active matrices. In a passive matrix, the memory cell consists of a resistive switching element and a non-linear element (usually a diode). The latter provides a suitable voltage divider for the resistive switching element, preventing data loss during read / write operations when the resistive switching element is in a low-resistance state. This method has the advantages of simpler design and better miniaturization, but passive matrices inevitably lead to interference between adjacent cells. Active cells use transistors to control the read / write and erase operations of the resistive switching element. While this effectively isolates interference between adjacent cells, the design is more complex, and the device has poorer miniaturization capabilities. Furthermore, the resistance of RRAM is easily affected by temperature. When reading and writing data, especially during writing, temperature variations caused by applied voltage and environmental influences can easily lead to changes in resistance, resulting in non-ideal conditions and data writing failures. Therefore, improving the reliability of RRAM chip data reading and writing is particularly important. Summary of the Invention

[0003] This invention relates to an algorithm and its hardware circuit implementation aimed at improving the reliability of read and write data in RRAM chips. Due to the unreliability of write data in RRAM chips, this invention proposes an algorithm that selects a base voltage based on temperature detected by a temperature sensor, gradually increases the write data voltage using the ISPP algorithm, and verifies the write data using the read data voltage. A hardware circuit platform for implementing this algorithm is also constructed. This invention effectively improves the reliability of write data in RRAM chips and increases the efficiency of read and write data. To achieve the above objectives, this invention adopts the following technical solution:

[0004] Firstly, this paper provides a reading system for an RRAM chip. This RRAM chip consists of 8 by 128 RRAM memory cells. Taking advantage of the characteristic that this RRAM chip can only operate on one cell at a time, an FPGA and peripherals such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are used to locate the specific memory cell and complete the reading by applying voltage.

[0005] Specifically, the FPGA controls the digital-to-analog converter (DAC), thereby enabling the voltage pulse control data selector to select and locate the specific RRAM cell.

[0006] Specifically, after selecting a specific cell, a voltage of 0.3V is added to the BL terminal of the selected cell, while the voltage on the BL terminals of the other cells remains at 0V and the voltage on the SL terminals remains at 0V, thereby reading the data stored in the current RRAM memory cell.

[0007] Specifically, the pulse width of the applied read voltage is 400ns, and the pulse width of the read voltage is adjustable from 400ns to 20us.

[0008] Secondly, this patent provides an algorithm for writing data "1" to an RRAM chip. Before writing data "1", a read data pulse is used to read the data currently stored in the memory cell. If the current state is not "1", the temperature before writing data is detected by a temperature sensor. Combined with the data in Table 1, the starting write voltage is selected through FPGA control. The selected write voltage is applied to the RRAM chip, and the read voltage is applied after the data writing is completed. If data "1" is written, the write voltage value is gradually increased using the ISPP algorithm, and a read data operation is applied after each write data operation, repeating this process until the write is successful. If the write voltage reaches the 5V upper limit and the data "1" is still not written, the write operation has failed.

[0009] Specifically, before writing the data "1", the current state is read through a data read operation. If the data is "1", the writing is terminated.

[0010] Specifically, before writing the data "1", the current temperature of the RRAM chip is detected by a temperature sensor, and the starting voltage value for writing the data is determined by referring to Table 1.

[0011] Specifically, before writing the data "1", the current state of the RRAM is read through a data read operation, and if the data is "1", the writing is terminated.

[0012] Specifically, the FPGA controls the digital-to-analog converter (DAC), which in turn controls the voltage pulse generation module and the voltage pulse ISPP algorithm module at BL; a pulse voltage is added at SL, and the same amplitude voltage is added to the BL of the unselected RRAM cells, while the selected RRAM cells remain at 0V.

[0013] Specifically, the current RRAM status is confirmed through a data read operation. If the data is "1", the data write operation is terminated. If it is not "]", a voltage pulse signal is applied. After the initial write operation is completed, the system switches to a data read operation to verify whether the current write is correct. If correct, the write operation is terminated; if it fails, the write voltage value is increased, and the write operation continues, in conjunction with the data read operation, until the 5V upper limit is reached and the write operation is still unsuccessful, at which point the write failure is declared.

[0014] Thirdly, this patent provides an algorithm for writing data "0" to an RRAM chip. Before writing data "0", the current state of the RRAM is read through a data read operation. If it is not data "0", the temperature of the chip before writing is detected by a temperature sensor. Combined with the data in Table 1, the starting write voltage is selected through FPGA control. The data read and write are completed and verified through the FPGA and related peripherals combined with the ISPP algorithm.

[0015] Specifically, before writing the data "0", the current state is read through a data read operation. If the data is "0", the writing is terminated.

[0016] Specifically, before writing the data "0", the current temperature of the RRAM chip is detected by a temperature sensor, and the starting voltage value for writing data is determined by referring to Table 1.

[0017] Specifically, before writing data "0", the current state of the RRAM is read through a data read operation. If the data is "0", the writing is terminated.

[0018] Specifically, the FPGA controls the digital-to-analog converter (DAC), which in turn controls the voltage pulse generation module to generate signal pulses. The pulse signal is used by a 7-bit gating encoder to select the row cell of the RRAM. By controlling the voltage pulse ISPP algorithm module at BL, a pulse voltage is added at BL. The unselected RRAM cell BL is 0V, and the voltage at SL is 0V.

[0019] Specifically, the current RRAM status is confirmed through a data read operation. If the data is "0", the data write operation is terminated. If the data is not "0", a voltage pulse signal is applied. After the initial write operation is completed, the system switches to a data read operation to verify whether the current write is correct. If correct, the write operation is terminated; if it fails, the write voltage value is increased, and the write operation continues, in conjunction with the data read operation, until the 5V upper limit is reached and the write operation is still unsuccessful, at which point the write operation is declared a failure.

[0020] In a preferred embodiment, the magnitude of the write voltage increases from 1.5V to 5V in increments.

[0021] In a preferred embodiment, the reading voltage has an amplitude of 0.3V.

[0022] In a preferred embodiment, the analog pulse width for writing data "1" is adjustable from 400ns to 20us.

[0023] In a preferred embodiment, the interval between the simulated pulses for writing data "0" is adjustable from 500ns to 20us.

[0024] Compared with existing technologies, this design has the following advantages:

[0025] 1. When performing a read operation, efficient reading of RRAM chip cell data can be achieved through FPGA control.

[0026] 2. During data write operations, after confirming the current state, the temperature is detected by a temperature sensor to preliminarily determine the basic voltage range, allowing for a reduction in the input voltage amplitude and thus lowering the power consumption of the RRAM chip during data write. After temperature detection, the write and read operations are performed cyclically using the ISPP algorithm, gradually increasing the write voltage value. This allows for obtaining accurate write results in a shorter time, ensuring the accuracy of RRAM data writes while minimizing voltage and power consumption.

[0027] 3. By controlling the timing through FPGA, not only can the read operation of the RRAM chip be realized, but also the cyclic write and read operations based on the ISPP algorithm combined with the read data operation can be effectively completed, so as to realize the accurate and efficient execution of the write data operation.

[0028] 4. Based on this method, accurate and efficient writing and reading of RRAM can be achieved. It is practical and efficient for reading and writing data to RRAM chips, and has certain reference value for RRAM and RAM of other materials and characteristics. Attached Figure Description

[0029] Figure 1 The overall structure diagram of the hardware circuit.

[0030] Figure 2 Schematic diagram of chip and temperature sensor

[0031] Figure 3 Flowchart for reading data

[0032] Figure 4 Flowchart for writing the data "1"

[0033] Figure 5 Flowchart for writing the data "0"

[0034] Figure 6 The flowchart for the ISPP algorithm, taking the writing of data "1" as an example. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Examples of the embodiments are listed in the accompanying drawings. The specific embodiments described in the following description of the present invention are merely illustrative examples of specific implementations of the present invention and are intended to explain the present invention, and are not intended to limit the present invention.

[0036] Those skilled in the art will understand that the hardware device mentioned in this invention refers to one or more of the steps, measures, or schemes in the related algorithm implementation circuit. The hardware device can be specifically designed and manufactured for the desired purpose. The FPGA used in this invention is an A7 100T, which has high-performance processing capabilities and multiple processing units; the analog-to-digital converter (ADC) used is an AD7928, which features high-precision signal acquisition and can achieve 16-bit analog-to-digital conversion, effectively ensuring the accuracy of signal conversion; the digital-to-analog converter (DAC) used is an SD2421, which also features high precision and can achieve high-precision analog signal output; the row selection of the chip is achieved by controlling the voltage pulse control module, and the voltage signal is applied to the BL port by controlling the voltage ISPP module, thereby supporting the ISPP read / write algorithm.

[0037] In this embodiment, the FPGA development board model is not limited, and the analog-to-digital converter chip and digital-to-analog converter chip only need to ensure an accuracy of 8 bits or more. Those skilled in the art can select different models of development boards and different models of digital-to-analog converter chips according to the actual situation.

[0038] This invention provides a hardware circuit implementation for RRAM read / write based on temperature detection using the ISPP algorithm. The specific circuit functional block diagram and its components are shown below. Figure 1 Based on different purposes, reading and writing can be divided into three aspects.

[0039] When performing a read RRAM status operation, execute Figure 3The process is as follows: The FPGA controls the digital-to-analog converter (DAC), which in turn controls the voltage pulse generation module to generate a pulse signal with a voltage amplitude of 3.5V. Based on the pulse combination of the 7-bit signal, the decoder is controlled to select the corresponding row. Simultaneously, the FPGA controls the DAC, which in turn controls the pulse signal at the BL terminal of the ISPP algorithm module, applying a pulse signal with an amplitude of 0.3V and a pulse width of 400ns to the desired RRAM memory cell. After the cell is selected, a current is formed on the memory cell through the voltage drop. The current is converted into a voltage signal by the current-to-voltage conversion module at the SL terminal, then converted into a digital signal by the analog-to-digital converter (ADC) and transmitted back to the FPGA. The FPGA then sends the signal to the host computer to obtain the current RRAM status.

[0040] When the operation of writing data "1" is performed, the following is executed: Figure 4 The process involves using a temperature sensor to measure the current chip temperature. To improve the efficiency of writing data "1", a read operation is performed first. The read operation process is detailed below. Figure 3 When the read data is "1", it indicates that the current RRAM state is already "1", and no write operation is needed; the current write state can be exited directly. When the read data state is not "1", the initial voltage is selected by looking up Table 1 based on the temperature detected by the temperature sensor. The recommended initial voltage values ​​for writing at the corresponding temperatures are shown in Table "1" below:

[0041] Table 1

[0042] Temperature (°C) The reference voltage (V) to write "1" Reference voltage (V) for writing "0" 25-30 1.5 1.5 30-40 1.55 1.5 40-50 1.58 1.55 50-60 1.6 1.58 60-70 1.62 1.6 70-80 1.66 1.66 80-90 1.7 1.7 90-100 1.8 1.75 100-110 2.2 2.0 110-125 2.4 2.4

[0043] Taking a temperature of 25 degrees Celsius as an example, an initial voltage of 1.5V is selected. The FPGA controls the digital-to-analog converter (DAC) to convert it into an analog signal. Then, the voltage pulse generation module controls the encoding, setting the voltage amplitude to 3.5V. While applying a 1.5V voltage pulse to the SL terminal, the power supply module simultaneously applies a voltage pulse of the same amplitude and pulse width to the unselected BL terminal. This creates a voltage drop across the selected RRAM cell, completing the initial write operation. To verify the correctness of the written data, a read operation is performed again. When the read detection status is "1", it indicates that the write operation is complete and successful. If the write operation is still unsuccessful, the original signal amplitude is increased by 40mV, while the pulse width remains 400ns. After completing the write operation, the read operation continues. The ISPP algorithm is executed repeatedly until data is successfully written. The algorithm flow diagram is shown below. Figure 6 .

[0044] When performing a write operation with data "0", the following is executed: Figure 4The process involves using a temperature sensor to detect the chip's temperature before writing data, and then measuring the current chip temperature. To improve the efficiency of writing data "0", a read operation is performed first. The read operation process is detailed below. Figure 3 When the read data is "0", it indicates that the current state is already "0" and no writing is needed; the current state can be skipped directly. When the read data is not "0", the initial voltage is selected based on the temperature detected by the temperature sensor using lookup table 1. Taking an RRAM memory chip temperature of 40 degrees Celsius as an example, the initial voltage is selected as 1.55V. The FPGA controls the digital-to-analog converter (DAC) to convert it into an analog signal, which is then encoded by the voltage pulse generation module, controlling the voltage amplitude to 3.5V. A 1.55V voltage pulse is applied to the BL terminal, while no voltage is applied to the unselected BL and SL terminals. In this way, a voltage drop is formed on the selected RRAM cell, completing the initial writing. To verify the correctness of the writing, the read program is re-executed. When the read detection state is "0", it indicates that the writing operation is complete and successful. When the detection is not "0", it indicates that the writing was unsuccessful, and 50mV is added to the original voltage signal, with the pulse width remaining at 600ns. The ISPP algorithm for writing data "1" is basically the same as that for writing data "0". The pulse width and time interval are adjustable. See [link to documentation]. Figure 6 The ISPP algorithm, following this process, performs a loop of read and write operations until the read and write operations are completed.

[0045] The embodiments of this invention effectively solve some problems existing in the prior art, such as unstable data writing to RRAM chips, significant temperature influence, insufficient reliability of written data, and low write efficiency. This invention utilizes a combination of temperature sensor detection and the ISPP algorithm to significantly improve write efficiency while ensuring data writing reliability. Furthermore, the voltage amplitude, voltage width, and voltage interval for RRAM read / write operations are programmable, making it applicable not only to the testing of this RRAM chip but also to the peripheral read / write circuit design of other types of RRAM chips. Leveraging the programmable characteristics of FPGAs, the algorithm's circuit implementation is very simple, efficient, and flexible, allowing for flexible code modification for testing of RRAM chips based on devices with different voltage-current characteristics, greatly improving testing flexibility and reducing testing costs.

[0046] The above description represents a preferred embodiment of the present invention. It should be noted that inventions using the same or similar algorithms and related hardware circuits as those used in this invention are also within the scope of protection of this patent.

Claims

1. A temperature-sensing ISPP algorithm for RRAM memory chip read / write circuits and its hardware implementation method, characterized in that, When reading data from an RRAM chip, a voltage drop is created across the RRAM device by applying an analog voltage pulse with a fixed voltage amplitude and width, thus completing the reading. When writing data to an RRAM chip, the current RRAM chip data is read in advance, and the temperature is detected by a temperature sensor. The writing voltage value is gradually increased using the ISPP algorithm in conjunction with the reading voltage pulse until the data is successfully written.

2. A read / write data circuit for an RRAM chip based on ISPP temperature detection, characterized in that, The system includes an RRAM chip, an FPGA, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a temperature sensor, a voltage pulse power supply module, a voltage ISPP module, and control and peripheral circuits. The RRAM chip has eight BL pins, one SL pin, an internal WL network, an I2C interface, and power supply pins. The FPGA acts as the read / write master controller, controlling the voltage pulse module and the read / write operation voltage ISPP module through the ADC and DAC, thereby adding voltage pulses to the RRAM chip. The temperature sensor detects the current temperature of the RRAM chip and transmits the temperature data to the FPGA.

3. As described in claim 2, characterized in that, The FPGA performs signal conversion via a digital-to-analog converter (DAC). Then, a voltage pulse generation module controls the 7-bit gating unit encoding combination to determine a specific row. The read / write operation voltage ISPP algorithm module controls the voltage distribution of the BL and SL terminals to determine a specific column.

4. As described in claim 1, characterized in that, Each read operation uses a voltage amplitude of 0.3V and a pulse width of 400ns.

5. As described in claim 4, characterized in that, The read operation voltage is 0.3V, while SL and the other cells BL remain at 0V.

6. As described in claim 1, characterized in that, When writing data "1", a read operation is performed first to confirm the current data status. If the current data is "1", the writing process is terminated. When the data is "0", the write voltage value is gradually increased using the ISPP algorithm, and a read voltage operation is added after each write voltage operation for verification. When the verification shows the data status as "1", it indicates that the write is successful and the writing process is terminated. When writing data "0", the writing process is terminated after the verification status is "0".

7. As described in claim 1, characterized in that, The write voltage range for writing data "1" is 1.5V-5V; the voltage increment is 40mV each time according to the ISPP algorithm; the pulse width is 400ns, and the interval is 400ns each time; the pulse width is adjustable from 400ns to 20us, and the interval is adjustable from 400ns to 30us. The write voltage range for writing data "0" is 1.5V-5V; the voltage increment is 50mV each time; the pulse width is 500ns each time, and the interval is 600ns each time; the pulse width is adjustable from 500ns to 20us, and the interval is adjustable from 600ns to 30us.

8. As described in claim 1, characterized in that, When writing data "1", the SL potential is pulled high. The BL potential of unselected RRAM cells is the same as SL, while the BL potential of selected cells remains at 0V. When writing data "0", the BL potential of the selected RRAM is pulled high, while the BL and SL potentials of the remaining cells are both 0V.

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