Semiconductor device

Abstract

A semiconductor device may include a first memory cell array including a first source line, a first bit line, a first memory string, and a first word line; a second memory cell array including a second source line, a second bit line, a second memory string, and a second word line; a first interconnect structure including a first via passing through the first memory cell array and commonly connected to the first bit line and the second bit line; a second interconnect structure including a second via passing through the first memory cell array and commonly connected to the first word line and the second word line; a page buffer selectively accessing the first memory string or the second memory string through the first interconnect structure; and a row decoder that collectively controls the first word line and the second word line through the second interconnect structure.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to semiconductor technology, and more specifically, to a semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as improvements in the integration density of semiconductor devices with memory cells formed in a single layer on a substrate have reached their limits, three-dimensional semiconductor devices with memory cells stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the Invention

[0003] In embodiments of this disclosure, a semiconductor device may include: a first memory cell array including a first source line, a first bit line, a first memory string including first memory cells connected between the first source line and the first bit line, and a first word line connected to the first memory cells; a second memory cell array located above the first memory cell array and including a second source line, a second bit line, a second memory string including second memory cells connected between the second source line and the second bit line, and a second word line connected to the second memory cells; a first interconnect structure including a first via through the first memory cell array and commonly connected to the first bit line and the second bit line; a second interconnect structure including a second via through the first memory cell array and commonly connected to the first word line and the second word line; a page buffer selectively accessing the first memory string or the second memory string through the first interconnect structure; and a row decoder jointly controlling the first word line and the second word line through the second interconnect structure.

[0004] In embodiments of this disclosure, a semiconductor device may include: a first gate structure including stacked first word lines; a second gate structure located above the first gate structure and including stacked second word lines; a first bit line located below the first gate structure; a first source line located between the first gate structure and the second gate structure; a second bit line located between the first source line and the second gate structure; a second source line located above the second gate structure; a first via passing through the first source line and the first gate structure and connecting the first bit line and the second bit line to each other; a second via passing through the first gate structure and connecting the first word line and the second word line to each other; a page buffer connected to the first word line and the second bit line via the first via; and a line decoder controlling the first word line and the second word line via the second via. Attached Figure Description

[0005] Figures 1A to 1C This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0006] Figures 2A to 2C This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figures 3A to 3C This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 4A and Figure 4B This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figures 5A to 5C This is a simplified diagram of the structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 6A and Figure 6B This is a simplified diagram of the structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 7A and Figure 7B This is a simplified diagram of the structure of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 8A and Figure 8B This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 9 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 10 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 11 This is a simplified diagram of a memory system according to an embodiment of the present disclosure.

[0016] Figure 12 This is a simplified diagram of a memory system according to an embodiment of the present disclosure.

[0017] Figure 13 This is a simplified diagram of a memory system according to an embodiment of the present disclosure.

[0018] Figure 14 This is a simplified diagram of a memory system according to an embodiment of the present disclosure.

[0019] Figure 15 This is a simplified diagram of a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0020] Various embodiments of this disclosure relate to a semiconductor device having a stable structure and improved properties.

[0021] By using three-dimensional stacked memory cells, the integration density of semiconductor devices can be improved. Semiconductor devices with stable structures and improved reliability can also be provided.

[0022] Hereinafter, embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0023] Figures 1A to 1C This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0024] Reference Figure 1A The semiconductor device may include a peripheral circuit PC, a first memory cell array CA1 disposed above the peripheral circuit PC, and a second memory cell array CA2 disposed above the first memory cell array. The semiconductor device may also include a first interconnect structure IC1, a second interconnect structure IC2, and a third interconnect structure IC3 connecting the first memory cell array CA1 and the second memory cell array CA2 to the peripheral circuit PC.

[0025] The first memory cell array CA1 may be located above the peripheral circuit PC. The first memory cell array CA1 may include a first source line SL1, a first bit line BL1, and a first memory string MS1 connected between the first source line SL1 and the first bit line BL1. The first memory string MS1 may include at least one first source select transistor SST1, a plurality of first memory cells MC1, and at least one first drain select transistor DST1. The first memory cell array CA1 may include a first source select line SSL1 connected to the first source select transistor SST1, a first word line WL1 connected to the first memory cell MC1, and a first drain select line DSL1 connected to the first drain select transistor DST1.

[0026] The second memory cell array CA2 may be located above the first memory cell array CA1. The second memory cell array CA2 may include a second source line SL2, a second bit line BL2, and a second memory string MS2 connected between the second source line SL2 and the second bit line BL2. The second memory string MS2 may include at least one second source select transistor SST2, a plurality of second memory cells MC2, and at least one second drain select transistor DST2. The second memory cell array CA2 may include a second source select line SSL2 connected to the second source select transistor SST2, a second word line WL2 connected to the second memory cell MC2, and a second drain select line DSL2 connected to the second drain select transistor DST2.

[0027] The first memory string MS1 of the first memory cell array CA1 and the second memory string MS2 of the second memory cell array CA2 can belong to the same memory block.

[0028] The peripheral circuitry PC may include a page buffer PB, a row decoder DEC, and a source control circuit SRC. The first bit line BL1 and the second bit line BL2 are interconnected via a first interconnect structure IC1, and the page buffer PB is connected to both the first memory string MS1 and the second memory string MS2 via the first interconnect structure IC1. Therefore, the page buffer PB can selectively access either the first memory string MS1 or the second memory string MS2. During programming operations, the page buffer PB can operate as a write driver and can input data to be stored in either the first memory cell array CA1 or the second memory cell array CA2. During read or verification operations, the page buffer PB can operate as a sense amplifier and can output data stored in either the first memory cell array CA1 or the second memory cell array CA2.

[0029] The line decoder DEC can be connected to the first word line WL1 and the second word line WL2 via the second interconnect structure IC2, and can jointly control the first word line WL1 and the second word line WL2. The line decoder DEC can enable the first word line WL1 and the second word line WL2 according to the address.

[0030] The line decoder DEC controls each of the first source select line SSL1, the second source select line SSL2, the first drain select line DSL1, and the second drain select line DSL2. Depending on the address, the line decoder DEC can enable either the first source select line SSL1 or the second source select line SSL2, or enable either the first drain select line DSL1 or the second drain select line DSL2. Therefore, the first memory string MS1 and the second memory string MS2, belonging to the same memory block MB, can be selectively driven.

[0031] The source control circuit SRC can be connected to the first source line SL1 and the second source line SL2 through the third interconnection structure IC3, and can jointly control the first source line SL1 and the second source line SL2.

[0032] Reference Figure 1BThe semiconductor device may include a peripheral circuit PC, a first memory cell array CA1 disposed above the peripheral circuit PC, and a second memory cell array CA2 disposed above the first memory cell array CA1. The first memory cell array CA1 may be located between the peripheral circuit PC and the second memory cell array CA2. The peripheral circuit PC and the first memory cell array CA1 may be electrically connected to each other via first bonding pads BP11, BP12, and BP13. The first memory cell array CA1 and the second memory cell array CA2 may be electrically connected to each other via second bonding pads BP21, BP22, and BP23.

[0033] The peripheral circuit PC may include a page buffer PB, a line decoder DEC, and a source control circuit SRC. As an example, the peripheral circuit PC may include a substrate 10 and at least one transistor located on the substrate 10. Vias V01, V02, and V03 and wirings M01, M02, and M03 may be connected to the peripheral circuit PC.

[0034] The first memory cell array CA1 may include a first gate structure GST1, a first channel structure CH1, a first bit line BL1, a first source line SL1, and a first slit structure SLS1. The first gate structure GST1 may include alternately stacked first conductive layers 11 and first insulating layers 12. The first conductive layer 11 may be a first source select line SSL1, a first word line WL1, or a first drain select line DSL1. The first gate structure GST1 may include a dummy region. The dummy region may include a first sacrificial layer 15, instead of the first conductive layer 11. The first sacrificial layer 15 may be a layer remaining after the first conductive layer 11 is not replaced during the manufacturing process.

[0035] The first slit structure SLS1 may extend through the first gate structure GST1 and may be connected to the first source line SL1. The first slit structure SLS1 may be a source contact structure or an insulating structure. When the first slit structure SLS1 is a source contact structure, the first slit structure SLS1 may include a conductive layer electrically connected to the first source line SL1 and insulating spacers surrounding the sidewalls of the conductive layer.

[0036] The first bit line BL1 may be located below the first gate structure GST1. The first source line SL1 may be located above the first gate structure GST1. The first channel structure CH1 may extend through the first gate structure GST1 and may be connected between the first bit line BL1 and the first source line SL1. The first source selection transistor SST1, the first memory cell MC1, or the first drain selection transistor DST1 may be located in the region where the first channel structure CH1 and the first conductive layer 11 intersect. The first source selection transistor SST1, the first memory cell MC1, and the first drain selection transistor DST1, which share the first channel structure CH1, may constitute the first memory string MS1.

[0037] The second memory cell array CA2 may include a second gate structure GST2, a second channel structure CH2, a second bit line BL2, a second source line SL2, and a second slit structure SLS2. The second gate structure GST2 may include alternately stacked second conductive layers 13 and second insulating layers 14. The second conductive layer 13 may be a second source select line SSL2, a second word line WL2, or a second drain select line DSL2. The second gate structure GST2 may include a dummy region. The dummy region may include a second sacrificial layer 16, instead of the second conductive layer 13. The second sacrificial layer 16 may be a layer remaining after the second conductive layer 13 was not replaced during the manufacturing process.

[0038] The second slit structure SLS2 may extend through the second gate structure GST2 and may be connected to the second source line SL2. The second slit structure SLS2 may be a source contact structure or an insulating structure. When the second slit structure SLS2 is a source contact structure, the second slit structure SLS2 may include a conductive layer electrically connected to the second source line SL2 and insulating spacers surrounding the sidewalls of the conductive layer.

[0039] The second bit line BL2 may be located below the second gate structure GST2. The second source line SL2 may be located above the second gate structure GST2. The second channel structure CH2 may extend through the second gate structure GST2 and may connect between the second bit line BL2 and the second source line SL2. The second source selection transistor SST2, the second memory cell MC2, or the second drain selection transistor DST2 may be located in the region where the second channel structure CH2 and the second conductive layer 13 intersect. The second source selection transistor SST2, the second memory cell MC2, and the second drain selection transistor DST2, which share the second channel structure CH2, may constitute the second memory string MS2.

[0040] The first slit structure SLS1 and the second slit structure SLS2 can be tapered, and their cross-sectional area decreases as the distance from the substrate 10 increases. Similarly, the first channel structure CH1 and the second channel structure CH2 can be tapered, and their cross-sectional area decreases as the distance from the substrate 10 increases.

[0041] The first interconnect structure IC1 may include a first via TV1. The first via TV1 may extend through the first memory cell array CA1 and through the first source line SL1 and the first gate structure GST1. The first via TV1 may be used to connect the first bit line BL1 and the second bit line BL2 to each other. The first via TV1 may also be used to connect the first memory string MS1 and the second memory string MS2 to each other.

[0042] Page buffer PB can be connected to first memory string MS1 and second memory string MS2 through first interconnect structure IC1. As an example, first interconnect structure IC1 may include via V01, wiring M01, first bonding pad BP11, first bit line BL1, first via V11, first through hole TV1, second bonding pad BP21, second bit line BL2 and second via V21.

[0043] The second interconnect structure IC2 may include a second via TV2. The second via TV2 may extend through the first memory cell array CA1 and through the first gate structure GST1. The first word line WL1 and the second word line WL2 may be connected to each other through the second via TV2. The second via TV2 may be connected together to the corresponding first word line WL1 and second word line WL2. As an example, the first word line WL1 located at layer n in the first gate structure GST1 and the second word line WL2 located at layer n in the second gate structure GST2 may be connected to each other. Here, n may be an integer.

[0044] The line decoder DEC can jointly control the first word line WL1 and the second word line WL2 through the second interconnect structure IC2. As an example, the second interconnect structure IC2 may include via V02, wiring M02, first bonding pad BP12, first wiring M12, first via V12, second through hole TV2, second bonding pad BP22, second wiring M22 and second via V22.

[0045] The third interconnect structure IC3 may include a first slit structure SLS1 and a second slit structure SLS2. The source control circuit SRC can be connected to the first source line SL1 and the second source line SL2 via the third interconnect structure IC3. As an example, the third interconnect structure IC3 may include a via V03, a wiring M03, a first bonding pad BP13, a first wiring M13, a first via V13, a first slit structure SLS1, a first source line SL1, a second bonding pad BP23, a second wiring M23, a second via V23, a second slit structure SLS2, and a second source line SL2.

[0046] Reference Figure 1C The third interconnect structure IC3 may include a third via TV3 and a fourth via TV4. The third via TV3 may extend through the first memory cell array CA1 and through the dummy region of the first gate structure GST1. The fourth via TV4 may extend through the second memory cell array CA2 and through the dummy region of the second gate structure GST2.

[0047] The source control circuit SRC can be connected to the first source line SL1 and the second source line SL2 through the third interconnect structure IC3. As an example, the third interconnect structure IC3 may include via V03, wiring M03, first bonding pad BP13, first wiring M13, first via V13, third through hole TV3, second bonding pad BP23, second wiring M23, second via V23, fourth through hole TV4, third via V3, third wiring M3, second source line SL2, second slit structure SLS2, second via V24, second wiring M24, second bonding pad BP24 and first source line SL1.

[0048] According to the above configuration, the first memory string MS1 and the second memory string MS2 can be jointly connected to the page buffer PB, and the page buffer PB can selectively access either the first memory string MS1 or the second memory string MS2. The first word line WL1 and the second word line WL2 can be jointly connected to the row decoder DEC, and the row decoder DEC can jointly control the first word line WL1 and the second word line WL2. The first source line SL1 and the second source line SL2 can be jointly connected to the source control circuit SRC, and the source control circuit SRC can jointly control the first source line SL1 and the second source line SL2. Therefore, the first memory cell array CA1 and the second memory cell array CA2 can share the peripheral circuit PC, and the area occupied by the peripheral circuit PC can be reduced.

[0049] Figures 2A to 2C This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure. Hereinafter, any content repeated from the previously described content may be omitted.

[0050] Reference Figure 2A and Figure 2B The semiconductor device may include peripheral circuitry PC, a first memory cell array CA1 disposed above the peripheral circuitry PC, and a second memory cell array CA2 disposed above the first memory cell array CA1. The peripheral circuitry PC and the first memory cell array CA1 are electrically connected to each other via bonding pads BP11, BP12, and BP13. The first memory cell array CA1 and the second memory cell array CA2 can be directly electrically and physically connected to each other without bonding pads.

[0051] The peripheral circuit PC may include a page buffer PB, a line decoder DEC, and a source control circuit SRC. As an example, the peripheral circuit PC may include a substrate 20 and at least one transistor located on the substrate 20. Vias V01, V02, and V03 and wirings M01, M02, and M03 may be connected to the peripheral circuit PC.

[0052] The first memory cell array CA1 may include a first gate structure GST1, a first channel structure CH1, a first bit line BL1, a first source line SL1, and a first slit structure SLS1. The first gate structure GST1 may include alternately stacked first conductive layer 21 and first insulating layer 22. The first gate structure GST1 may include a dummy region. The dummy region may include a first sacrificial layer 25 instead of the first conductive layer 21. The first slit structure SLS1 may extend through the first gate structure GST1 and may be connected to the first source line SL1.

[0053] The first bit line BL1 may be located below the first gate structure GST1. The first source line SL1 may be located above the first gate structure GST1. The first channel structure CH1 may extend through the first gate structure GST1 and may be connected between the first bit line BL1 and the first source line SL1.

[0054] The second memory cell array CA2 may include a second gate structure GST2, a second channel structure CH2, a second bit line BL2, a second source line SL2, and a second slit structure SLS2. The second gate structure GST2 may include alternately stacked second conductive layers 23 and second insulating layers 24. The second gate structure GST2 may include a dummy region. The dummy region may include a second sacrificial layer 26 instead of the second conductive layer 23. The second slit structure SLS2 may extend through the second gate structure GST2 and may be connected to the second source line SL2.

[0055] The second bit line BL2 may be located above the second gate structure GST2. The second source line SL2 may be located below the second gate structure GST2 and may be directly connected to the first source line SL1. The second channel structure CH2 may extend through the second gate structure GST2 and may be connected between the second bit line BL2 and the second source line SL2.

[0056] The first interconnect structure IC1 may include a first via TV1 and a third via TV3. The first via TV1 extends through the first memory cell array CA1 and passes through the first source line SL1 and the first gate structure GST1. The third via TV3 extends through the second memory cell array CA2 and passes through the second source line SL2 and the second gate structure GST2.

[0057] The first through-hole TV1 and the third through-hole TV3 can be directly connected to each other. The first through-hole TV1 can connect the first bit line BL1 and the third through-hole TV3 to each other, and the third through-hole TV3 can connect the first through-hole TV1 and the second bit line BL2 to each other. Through the first through-hole TV1 and the third through-hole TV3, the first bit line BL1 and the second bit line BL2 can be connected to each other, and the first memory string MS1 and the second memory string MS2 can be connected to each other.

[0058] Page buffer PB can be connected to first memory string MS1 and second memory string MS2 through first interconnect structure IC1. As an example, first interconnect structure IC1 may include via V01, wiring M01, bonding pad BP11, first bit line BL1, first via V11, first through hole TV1, third through hole TV3, second via V21 and second bit line BL2.

[0059] The second interconnect structure IC2 may include a second via TV2 and a fourth via TV4. The second via TV2 may extend through the first memory cell array CA1 and through the first gate structure GST1. The fourth via TV4 may extend through the second memory cell array CA2 and through the second gate structure GST2.

[0060] The second via TV2 and the fourth via TV4 can be directly connected to each other. The second via TV2 can connect the first word line WL1 and the fourth via TV4 to each other, and the fourth via TV4 can connect the second via TV2 and the second word line WL2 to each other. The first word line WL1 and the second word line WL2 can be connected to each other through the second via TV2 and the fourth via TV4. The first word line WL1 located in the nth layer of the first gate structure GST1 and the second word line WL2 located in the nth layer of the second gate structure GST2 can be connected to each other.

[0061] The line decoder DEC can jointly control the first word line WL1 and the second word line WL2 through the second interconnect structure IC2. As an example, the second interconnect structure IC2 may include via V02, wiring M02, bonding pad BP12, first wiring M12, first via V12, second through hole TV2, fourth through hole TV4, second wiring M22 and second via V22.

[0062] The third interconnect structure IC3 may include a fifth via TV5. The fifth via TV5 may extend through the first memory cell array CA1 and through the dummy region of the first gate structure GST1.

[0063] The source control circuit SRC can be connected to the first source line SL1 and the second source line SL2 through the third interconnect structure IC3. As an example, the third interconnect structure IC3 may include via V03, wiring M03, bonding pad BP13, first wiring M13, first via V13, fifth via TV5, first source line SL1 and second source line SL2.

[0064] Reference Figure 2A and Figure 2CThe third interconnect structure IC3 may include a first slit structure SLS1. As an example, the third interconnect structure IC3 may include a via V03, a wiring M03, a bonding pad BP13, a first wiring M13, a first via V13, a first slit structure SLS1, a first source line SL1, and a second source line SL2.

[0065] According to the above configuration, the first memory string MS1 and the second memory string MS2 can be jointly connected to the page buffer PB, and the page buffer PB can selectively access either the first memory string MS1 or the second memory string MS2. The first word line WL1 and the second word line WL2 can be jointly connected to the row decoder DEC, and the row decoder DEC can jointly control the first word line WL1 and the second word line WL2. The first source line SL1 and the second source line SL2 can be jointly connected to the source control circuit SRC, and the source control circuit SRC can jointly control the first source line SL1 and the second source line SL2. Therefore, the first memory cell array CA1 and the second memory cell array CA2 can share the peripheral circuit PC, and the area occupied by the peripheral circuit PC can be reduced.

[0066] Figures 3A to 3C This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure. Hereinafter, any content repeated from the previously described content may be omitted.

[0067] Reference Figure 3A and Figure 3B The semiconductor device may include peripheral circuitry PC, a first memory cell array CA1 disposed above the peripheral circuitry PC, and a second memory cell array CA2 disposed above the first memory cell array CA1. The peripheral circuitry PC and the first memory cell array CA1 are electrically connected to each other via first bonding pads BP11, BP12, and BP13. The first memory cell array CA1 and the second memory cell array CA2 are electrically connected to each other via second bonding pads BP21, BP22, and BP23.

[0068] The peripheral circuit PC may include a page buffer PB, a line decoder DEC, and a source control circuit SRC. As an example, the peripheral circuit PC may include a substrate 30 and at least one transistor located on the substrate 30. Vias V01, V02, and V03 and wirings M01, M02, and M03 may be connected to the peripheral circuit PC.

[0069] The first memory cell array CA1 may include a first gate structure GST1, a first channel structure CH1, a first bit line BL1, a first source line SL1, and a first slit structure SLS1. The first gate structure GST1 may include alternately stacked first conductive layer 31 and first insulating layer 32. The first gate structure GST1 may include a dummy region. The dummy region may include a first sacrificial layer 35 instead of the first conductive layer 31. The first slit structure SLS1 may extend through the first gate structure GST1 and may be connected to the first source line SL1.

[0070] The first bit line BL1 may be located above the first gate structure GST1. The first source line SL1 may be located below the first gate structure GST1. The first channel structure CH1 may extend through the first gate structure GST1 and may be connected between the first bit line BL1 and the first source line SL1.

[0071] The second memory cell array CA2 may include a second gate structure GST2, a second channel structure CH2, a second bit line BL2, a second source line SL2, and a second slit structure SLS2. The second gate structure GST2 may include alternately stacked second conductive layers 33 and second insulating layers 34. The second gate structure GST2 may include a dummy region. The dummy region may include a second sacrificial layer 36 instead of the second conductive layer 33. The second slit structure SLS2 may extend through the second gate structure GST2 and may be connected to the second source line SL2.

[0072] The second bit line BL2 may be located below the second gate structure GST2. The second source line SL2 may be located above the second gate structure GST2. The second channel structure CH2 may extend through the second gate structure GST2 and may connect between the second bit line BL2 and the second source line SL2.

[0073] The first interconnect structure IC1 may include a first via TV1. The first via TV1 extends through the first memory cell array CA1 and passes through the first source line SL1 and the first gate structure GST1. The first bit line BL1 and the first bonding pad BP11 can be connected to each other through the first via TV1. The first interconnect structure IC1 may include a second bonding pad BP21, and the first bit line BL1 and the second bit line BL2 can be connected to each other through the second bonding pad BP21. The page buffer PB can be connected to the first memory string MS1 and the second memory string MS2 through the first interconnect structure IC1. As an example, the first interconnect structure IC1 may include a via V01, wiring M01, the first bonding pad BP11, the first via TV1, the first via V11, the first bit line BL1, the second bonding pad BP21, the second bit line BL2, and the second via V21.

[0074] The second interconnect structure IC2 may include a second via TV2. The second via TV2 may extend through the first memory cell array CA1 and through the first gate structure GST1. The second via TV2 may be connected to the first word line WL1 and the second word line WL2. The first word line WL1 and the first bonding pad BP12 may be connected to each other through the second via TV2. The second interconnect structure IC2 may include a second bonding pad BP22, and the first word line WL1 and the second word line WL2 may be connected to each other through the second bonding pad BP22. The first word line WL1 located at the nth layer in the first gate structure GST1 and the second word line WL2 located at the nth layer in the second gate structure GST2 may be connected to each other. The row decoder DEC may jointly control the first word line WL1 and the second word line WL2 through the second interconnect structure IC2. As an example, the second interconnect structure IC2 may include via V02, wiring M02, first bonding pad BP12, second via TV2, first via V12, first wiring M12, second bonding pad BP22, second wiring M22 and second via V22.

[0075] The third interconnect structure IC3 may include a third via TV3 and a fourth via TV4. The third via TV3 may extend through the first memory cell array CA1 and through the dummy region of the first gate structure GST1. The fourth via TV4 may extend through the second memory cell array CA2 and through the dummy region of the second gate structure GST2.

[0076] The source control circuit SRC can be connected to the first source line SL1 and the second source line SL2 through the third interconnect structure IC3. As an example, the third interconnect structure IC3 may include via V03, wiring M03, first bonding pad BP13, first source line SL1, third via TV3, first via V13, first wiring M13, second bonding pad BP23, second wiring M23, second via V23, fourth via TV4, and second source line SL2.

[0077] Reference Figure 3A and Figure 3C The third interconnect structure IC3 may include a first slot structure SLS1 and a second slot structure SLS2. As an example, the third interconnect structure IC3 may include a via V03, a wiring M03, a first bonding pad BP13, a first source line SL1, a first slot structure SLS1, a first via V13, a first wiring M13, a second bonding pad BP23, a second wiring M23, a second via V23, a second slot structure SLS2, and a second source line SL2.

[0078] According to the above configuration, the first memory string MS1 and the second memory string MS2 can be jointly connected to the page buffer PB, and the page buffer PB can selectively access either the first memory string MS1 or the second memory string MS2. The first word line WL1 and the second word line WL2 can be jointly connected to the row decoder DEC, and the row decoder DEC can jointly control the first word line WL1 and the second word line WL2. The first source line SL1 and the second source line SL2 can be jointly connected to the source control circuit SRC, and the source control circuit SRC can jointly control the first source line SL1 and the second source line SL2. Therefore, the first memory cell array CA1 and the second memory cell array CA2 can share the peripheral circuit PC, and the area occupied by the peripheral circuit PC can be reduced.

[0079] Figure 4A and Figure 4B This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure. Hereinafter, any content repeated from the previously described content may be omitted.

[0080] Reference Figure 4A and Figure 4B The semiconductor device may include peripheral circuitry PC, a first memory cell array CA1, a second memory cell array CA2, and a third memory cell array CA3. The first memory cell array CA1, the second memory cell array CA2, and the third memory cell array CA3 may be stacked on top of the peripheral circuitry PC. The peripheral circuitry PC and the first memory cell array CA1 may be electrically connected to each other via first bonding pads BP11, BP12, and BP13. The first memory cell array CA1 and the second memory cell array CA2 may be electrically connected to each other via second bonding pads BP21, BP22, and BP23. The second memory cell array CA2 and the third memory cell array CA3 may be electrically connected to each other via third bonding pads BP31, BP32, and BP33.

[0081] The peripheral circuit PC may include a page buffer PB, a line decoder DEC, and a source control circuit SRC. As an example, the peripheral circuit PC may include a substrate 40 and at least one transistor located on the substrate 40. Vias V01, V02, and V03 and wirings M01, M02, and M03 may be connected to the peripheral circuit PC.

[0082] The first memory cell array CA1 may include a first gate structure GST1, a first channel structure CH1, a first bit line BL1, a first source line SL1, and a first slit structure SLS1. The first gate structure GST1 may include alternately stacked first conductive layer 41 and first insulating layer 42. The first gate structure GST1 may include a dummy region. The dummy region may include a first sacrificial layer 47 instead of the first conductive layer 41. The first slit structure SLS1 may extend through the first gate structure GST1 and may be connected to the first source line SL1.

[0083] The first bit line BL1 may be located below the first gate structure GST1. The first source line SL1 may be located above the first gate structure GST1. The first channel structure CH1 may extend through the first gate structure GST1 and may be connected between the first bit line BL1 and the first source line SL1.

[0084] The second memory cell array CA2 may include a second gate structure GST2, a second channel structure CH2, a second bit line BL2, a second source line SL2, and a second slit structure SLS2. The second gate structure GST2 may include alternately stacked second conductive layers 43 and second insulating layers 44. The second gate structure GST2 may include a dummy region. The dummy region may include a second sacrificial layer 48 instead of the second conductive layer 43. The second slit structure SLS2 may extend through the second gate structure GST2 and may be connected to the second source line SL2.

[0085] The second bit line BL2 may be located below the second gate structure GST2. The second source line SL2 may be located above the second gate structure GST2. The second channel structure CH2 may extend through the second gate structure GST2 and may connect between the second bit line BL2 and the second source line SL2.

[0086] The third memory cell array CA3 may include a third gate structure GST3, a third channel structure CH3, a third bit line BL3, a third source line SL3, and a third slit structure SLS3. The third gate structure GST3 may include alternately stacked third conductive layers 45 and third insulating layers 46. The third gate structure GST3 may include dummy regions. The dummy regions may include a third sacrificial layer 49, instead of the third conductive layer 45. The third slit structure SLS3 may extend through the third gate structure GST3 and may be connected to the third source line SL3.

[0087] The third bit line BL3 may be located below the third gate structure GST3. The third source line SL3 may be located above the third gate structure GST3. The third channel structure CH3 may extend through the third gate structure GST3 and may be connected between the third bit line BL3 and the third source line SL3.

[0088] The first interconnect structure IC1 may include a first via TV1. The first via TV1 may extend through the first memory cell array CA1 and through the first source line SL1 and the first gate structure GST1. Through the first via TV1, the first bit line BL1 and the second bit line BL2 may be connected to each other, and the first memory string MS1 and the second memory string MS2 may be connected to each other.

[0089] The first interconnect structure IC1 may include a third via TV3. The third via TV3 may extend through the second memory cell array CA2 and through the second source line SL2 and the second gate structure GST2. Through the third via TV3, the second bit line BL2 and the third bit line BL3 may be connected to each other, and the second memory string MS2 and the third memory string MS3 may be connected to each other.

[0090] Page buffer PB can be connected to first memory string MS1, second memory string MS2, and third memory string MS3 through first interconnect structure IC1. As an example, first interconnect structure IC1 may include via V01, wiring M01, first bonding pad BP11, first bit line BL1, first via V11, first through hole TV1, second bonding pad BP21, second bit line BL2, second via V21, third through hole TV3, third bonding pad BP31, third bit line BL3, and third via V31.

[0091] The second interconnect structure IC2 may include a second via TV2. The second via TV2 may extend through the first memory cell array CA1 and through the first gate structure GST1. The first word line WL1 and the second word line WL2 may be connected to each other through the second via TV2. The first word line WL1 located in the nth layer of the first gate structure GST1 and the second word line WL2 located in the nth layer of the second gate structure GST2 may be connected to each other.

[0092] The second interconnect structure IC2 may include a fourth via TV4. The fourth via TV4 may extend through the second memory cell array CA2 and through the second gate structure GST2. The second word line WL2 and the third word line WL3 may be connected to each other through the fourth via TV4. The second word line WL2 located in the nth layer of the second gate structure GST2 and the third word line WL3 located in the nth layer of the third gate structure GST3 may be connected to each other.

[0093] The line decoder (DEC) can jointly control the first word line WL1, the second word line WL2, and the third word line WL3 through the second interconnect structure IC2. As an example, the second interconnect structure IC2 may include via V02, wiring M02, a first bonding pad BP12, a first wiring M12, a first via V12, a second through-hole TV2, a second bonding pad BP22, a second wiring M22, a second via V22, a fourth through-hole TV4, a third bonding pad BP32, a third wiring M32, and a third via V32.

[0094] The third interconnect structure IC3 may include a fifth via TV5, a sixth via TV6, and a seventh via TV7. The fifth via TV5 extends through the first memory cell array CA1 and through the dummy region of the first gate structure GST1. The sixth via TV6 extends through the second memory cell array CA2 and through the dummy region of the second gate structure GST2. The seventh via TV7 extends through the third memory cell array CA3 and through the dummy region of the third gate structure GST3.

[0095] The source control circuit SRC can be connected to the first source line SL1, the second source line SL2, and the third source line SL3 through the third interconnect structure IC3. As an example, the third interconnect structure IC3 may include via V03, wiring M03, first bonding pad BP13, first wiring M13, first via V13, fifth via TV5, first source line SL1, second bonding pad BP23, second wiring M23, second via V23, sixth via TV6, second source line SL2, third bonding pad BP33, third wiring M33, third via V33, seventh via TV7, and third source line SL3.

[0096] According to the above configuration, the first memory string MS1, the second memory string MS2, and the third memory string MS3 can be jointly connected to the page buffer PB, and the page buffer PB can selectively access the first memory string MS1, the second memory string MS2, or the third memory string MS3. The first word line WL1, the second word line WL2, and the third word line WL3 can be jointly connected to the row decoder DEC, and the row decoder DEC can jointly control the first word line WL1, the second word line WL2, and the third word line WL3. The first source line SL1, the second source line SL2, and the third source line SL3 can be jointly connected to the source control circuit SRC, and the source control circuit SRC can jointly control the first source line SL1, the second source line SL2, and the third source line SL3. Therefore, the first memory cell array CA1, the second memory cell array CA2, and the third memory cell array CA3 can share the peripheral circuit PC, and the area occupied by the peripheral circuit PC can be reduced.

[0097] Figures 5A to 5CThis is a simplified diagram of the structure of a semiconductor device according to embodiments of the present disclosure. Hereinafter, any content repeated from the previously described content may be omitted.

[0098] Reference Figure 5A and Figure 5B The semiconductor device may include peripheral circuitry PC, a first memory cell array CA1 disposed above the peripheral circuitry PC, and a second memory cell array CA2 disposed above the first memory cell array CA1. The peripheral circuitry PC and the first memory cell array CA1 are electrically connected to each other via first bonding pads BP11, BP12, BP13, and BP14. The first memory cell array CA1 and the second memory cell array CA2 are electrically connected to each other via second bonding pads BP21, BP22, and BP24.

[0099] The peripheral circuit PC may include a page buffer PB, a line decoder DEC, and a source control circuit SRC. As an example, the peripheral circuit PC may include a substrate 50 and at least one transistor located on the substrate 50. Vias V01, V02, V03, and V04, as well as wirings M01, M02, M03, and M04, may be connected to the peripheral circuit PC.

[0100] The first memory cell array CA1 may include a first gate structure GST1, a first channel structure CH1, a first bit line BL1, a first source line SL1, and a first slit structure SLS1. The first gate structure GST1 may include alternately stacked first conductive layer 51 and first insulating layer 52. The first gate structure GST1 may include a dummy region. The dummy region may include a first sacrificial layer 55 instead of the first conductive layer 51. The first slit structure SLS1 may extend through the first gate structure GST1 and may be connected to the first source line SL1.

[0101] The first bit line BL1 may be located below the first gate structure GST1. The first source line SL1 may be located above the first gate structure GST1. The first channel structure CH1 may extend through the first gate structure GST1 and may be connected between the first bit line BL1 and the first source line SL1.

[0102] The second memory cell array CA2 may include a second gate structure GST2, a second channel structure CH2, a second bit line BL2, a second source line SL2, and a second slit structure SLS2. The second gate structure GST2 may include alternately stacked second conductive layers 53 and second insulating layers 54. The second gate structure GST2 may include a dummy region. The dummy region may include a second sacrificial layer 56 instead of the second conductive layer 53. The second slit structure SLS2 may extend through the second gate structure GST2 and may be connected to the second source line SL2.

[0103] The second bit line BL2 may be located below the second gate structure GST2. The second source line SL2 may be located above the second gate structure GST2. The second channel structure CH2 may extend through the second gate structure GST2 and may connect between the second bit line BL2 and the second source line SL2.

[0104] The first interconnect structure IC1 may include a first via TV1, and the page buffer PB may be connected to the first memory string MS1 and the second memory string MS2 through the first interconnect structure IC1.

[0105] The second interconnect structure IC2 may include a second via TV2, and the line decoder DEC can jointly control the first word line WL1 and the second word line WL2 through the second interconnect structure IC2.

[0106] The third interconnect structure IC3 may include a third via TV3. The third via TV3 may pass through the dummy region of the first gate structure GST1 and may be connected to the first source line SL1. The source control circuit SRC can control the first source line SL1 through the third interconnect structure IC3. As an example, the third interconnect structure IC3 may include a via V03, wiring M03, a first bonding pad BP13, a first wiring M13, a first via V13, a third via TV3, and a first source line SL1.

[0107] The fourth interconnect structure IC4 may include a fourth via TV4 and a fifth via TV5. The fourth via TV4 may pass through the dummy region of the first gate structure GST1, and the fifth via TV5 may pass through the dummy region of the second gate structure GST2. The source control circuit SRC can control the second source line SL2 through the fourth interconnect structure IC4. As an example, the fourth interconnect structure IC4 may include a via V04, a wiring M04, a first bonding pad BP14, a first wiring M14, a first via V14, a fourth via TV4, a second bonding pad BP24, a second wiring M24, a second via V24, a fifth via TV5, and a second source line SL2.

[0108] Reference Figure 5A and Figure 5C The third interconnect structure IC3 may include a first slit structure SLS1. The source control circuit SRC can control the first source line SL1 through the third interconnect structure IC3. As an example, the third interconnect structure IC3 may include a via V03, a wiring M03, a first bonding pad BP13, a first wiring M13, a first via V13, a first slit structure SLS1, and a first source line SL1.

[0109] The fourth interconnect structure IC4 may include a fourth via TV4 and a fifth via TV5. The fourth via TV4 may pass through the dummy region of the first gate structure GST1, and the fifth via TV5 may pass through the dummy region of the second gate structure GST2. The source control circuit SRC can control the second source line SL2 through the fourth interconnect structure IC4. As an example, the fourth interconnect structure IC4 may include a via V04, a wiring M04, a first bonding pad BP14, a first wiring M14, a first via V14, a fourth via TV4, a second bonding pad BP24, a second wiring M24, a second via V24, a fifth via TV5, a third via V3, a third wiring M3, and a second source line SL2.

[0110] According to the above configuration, the first source line SL1 and the second source line SL2 can be connected to the source control circuit SRC, and the source control circuit SRC can independently control the first source line SL1 and the second source line SL2. Therefore, the memory block can be divided into sub-memory block units, and erase operations can be performed on a sub-memory block basis.

[0111] Figure 6A and Figure 6B This is a simplified diagram of the structure of a semiconductor device according to embodiments of the present disclosure. Hereinafter, any content repeated from the previously described content may be omitted.

[0112] Reference Figure 6A and Figure 6B The semiconductor device may include peripheral circuitry PC, a first memory cell array CA1 disposed above the peripheral circuitry PC, and a second memory cell array CA2 disposed above the first memory cell array CA1. The peripheral circuitry PC and the first memory cell array CA1 may be electrically connected to each other via first bonding pads BP11, BP12, BP13, and BP14. The first memory cell array CA1 and the second memory cell array CA2 may be electrically connected to each other via through-holes TV1, TV2, TV3, TV4, TV5, and TV6 without bonding pads.

[0113] The peripheral circuit PC may include a page buffer PB, a line decoder DEC, and a source control circuit SRC. As an example, the peripheral circuit PC may include a substrate 60 and at least one transistor located on the substrate 60. Vias V01, V02, V03, and V04, as well as wirings M01, M02, M03, and M04, may be connected to the peripheral circuit PC.

[0114] The first memory cell array CA1 may include a first gate structure GST1, a first channel structure CH1, a first bit line BL1, a first source line SL1, and a first slit structure SLS1. The first gate structure GST1 may include alternately stacked first conductive layer 61 and first insulating layer 62. The first gate structure GST1 may include a dummy region. The dummy region may include a first sacrificial layer 65 instead of the first conductive layer 61. The first slit structure SLS1 may extend through the first gate structure GST1 and may be connected to the first source line SL1.

[0115] The first bit line BL1 may be located below the first gate structure GST1. The first source line SL1 may be located above the first gate structure GST1. The first channel structure CH1 may extend through the first gate structure GST1 and may be connected between the first bit line BL1 and the first source line SL1.

[0116] The second memory cell array CA2 may include a second gate structure GST2, a second channel structure CH2, a second bit line BL2, a second source line SL2, and a second slit structure SLS2. The second gate structure GST2 may include alternately stacked second conductive layers 63 and second insulating layers 64. The second gate structure GST2 may include a dummy region. The dummy region may include a second sacrificial layer 66 instead of the second conductive layer 63. The second slit structure SLS2 may extend through the second gate structure GST2 and may be connected to the second source line SL2.

[0117] The second bit line BL2 may be located above the second gate structure GST2. The second source line SL2 may be located below the second gate structure GST2. The second channel structure CH2 may extend through the second gate structure GST2 and may connect between the second bit line BL2 and the second source line SL2.

[0118] The first interconnect structure IC1 may include a first via TV1 and a third via TV3, and the page buffer PB can be connected to the first memory string MS1 and the second memory string MS2 through the first interconnect structure IC1.

[0119] The second interconnect structure IC2 may include a second through-hole TV2 and a fourth through-hole TV4, and the line decoder DEC can jointly control the first word line WL1 and the second word line WL2 through the second interconnect structure IC2.

[0120] The third interconnect structure IC3 may include a first slit structure SLS1. The source control circuit SRC can control the first source line SL1 through the third interconnect structure IC3. As an example, the third interconnect structure IC3 may include a via V03, a wiring M03, a first bonding pad BP13, a first wiring M13, a first via V13, a first slit structure SLS1, and a first source line SL1.

[0121] The fourth interconnect structure IC4 may include a fifth via TV5 and a sixth via TV6. The fifth via TV5 may pass through the dummy region of the first gate structure GST1, and the sixth via TV6 may pass through the dummy region of the second gate structure GST2. The source control circuit SRC may control the second source line SL2 through the fourth interconnect structure IC4. As an example, the fourth interconnect structure IC4 may include a via V04, wiring M04, a first bonding pad BP14, a first wiring M14, a first via V14, a fifth via TV5, a sixth via TV6, a second via V24, a second wiring M24, a third via V3, a third wiring M3, a second wiring M23, a second via V23, a second slit structure SLS2, and a second source line SL2.

[0122] According to the above configuration, the first source line SL1 and the second source line SL2 can be connected to the source control circuit SRC, and the source control circuit SRC can independently control the first source line SL1 and the second source line SL2. Therefore, the memory block can be divided into sub-memory block units, and erase operations can be performed on a sub-memory block basis.

[0123] Figure 7A and Figure 7B This is a simplified diagram of the structure of a semiconductor device according to embodiments of the present disclosure. Hereinafter, any content repeated from the previously described content may be omitted.

[0124] Reference Figure 7A and Figure 7B The semiconductor device may include peripheral circuitry PC, a first memory cell array CA1 disposed above the peripheral circuitry PC, and a second memory cell array CA2 disposed above the first memory cell array CA1. The peripheral circuitry PC and the first memory cell array CA1 are electrically connected to each other via first bonding pads BP11, BP12, BP13, and BP14. The first memory cell array CA1 and the second memory cell array CA2 are electrically connected to each other via second bonding pads BP21, BP22, and BP24.

[0125] The peripheral circuit PC may include a page buffer PB, a line decoder DEC, and a source control circuit SRC. As an example, the peripheral circuit PC may include a substrate 70 and at least one transistor located on the substrate 70. Vias V01, V02, V03, and V04, as well as wirings M01, M02, M03, and M04, may be connected to the peripheral circuit PC.

[0126] The first memory cell array CA1 may include a first gate structure GST1, a first channel structure CH1, a first bit line BL1, a first source line SL1, and a first slit structure SLS1. The first gate structure GST1 may include alternately stacked first conductive layer 71 and first insulating layer 72. The first gate structure GST1 may include a dummy region. The dummy region may include a first sacrificial layer 75 instead of the first conductive layer 71. The first slit structure SLS1 may extend through the first gate structure GST1 and may be connected to the first source line SL1.

[0127] The first bit line BL1 may be located above the first gate structure GST1, and the first source line SL1 may be located below the first gate structure GST1. The first channel structure CH1 may extend through the first gate structure GST1 and may be connected between the first bit line BL1 and the first source line SL1.

[0128] The second memory cell array CA2 may include a second gate structure GST2, a second channel structure CH2, a second bit line BL2, a second source line SL2, and a second slit structure SLS2. The second gate structure GST2 may include alternately stacked second conductive layers 73 and second insulating layers 74. The second gate structure GST2 may include a dummy region. The dummy region may include a second sacrificial layer 76 instead of the second conductive layer 73. The second slit structure SLS2 may extend through the second gate structure GST2 and may be connected to the second source line SL2.

[0129] The second bit line BL2 may be located below the second gate structure GST2, and the second source line SL2 may be located above the second gate structure GST2. The second channel structure CH2 may extend through the second gate structure GST2 and may be connected between the second bit line BL2 and the second source line SL2.

[0130] The first interconnect structure IC1 may include a first via TV1, and the page buffer PB may be connected to the first memory string MS1 and the second memory string MS2 through the first interconnect structure IC1.

[0131] The second interconnect structure IC2 may include a second via TV2, and the line decoder DEC can jointly control the first word line WL1 and the second word line WL2 through the second interconnect structure IC2.

[0132] The source control circuit SRC can control the first source line SL1 through the third interconnect structure IC3. As an example, the third interconnect structure IC3 may include a via V03, a wiring M03, a first bonding pad BP13, and the first source line SL1.

[0133] The fourth interconnect structure IC4 may include a third via TV3 and a fourth via TV4. The third via TV3 may pass through the dummy region of the first gate structure GST1, and the fourth via TV4 may pass through the dummy region of the second gate structure GST2. The source control circuit SRC may control the second source line SL2 through the fourth interconnect structure IC4. As an example, the fourth interconnect structure IC4 may include a via V04, a wiring M04, a first bonding pad BP14, a third via TV3, a first via V14, a first wiring M14, a second bonding pad BP24, a second wiring M24, a second via V24, a fourth via TV4, and a second source line SL2.

[0134] According to the above configuration, the first source line SL1 and the second source line SL2 can be connected to the source control circuit SRC, and the source control circuit SRC can independently control the first source line SL1 and the second source line SL2. Therefore, the memory block can be divided into sub-memory block units, and erase operations can be performed on a sub-memory block basis.

[0135] Figure 8A and Figure 8B This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure. Hereinafter, any content repeated from the previously described content may be omitted.

[0136] Reference Figure 8A The semiconductor device may include a first memory block MB1 and a second memory block MB2. For example, as shown, the first memory block MB1 and the second memory block MB2 may be located on the same plane. In the first memory block MB1 and the second memory block MB2, the word line WL may extend in a first direction I, and the bit line BL may extend in a second direction II that intersects the first direction I. The first memory block MB1 and the second memory block MB2 may be adjacent to each other in the second direction II. In an embodiment, the first direction and the second direction may be orthogonal to each other.

[0137] Reference Figure 8B The semiconductor device may include a first memory block MB1 and a second memory block MB2. The first memory block MB1 may include a first sub-memory block MB11 and a second memory block MB12. The second memory block MB2 may include a third sub-memory block MB21 and a fourth sub-memory block MB22.

[0138] The first sub-block MB11 and the second sub-block MB12 may be stacked on a third direction III. Here, the third direction III may be a direction perpendicular to the plane defined by the first direction I and the second direction II. The first word line WL11 of the first sub-block MB11 and the second word line WL12 of the second sub-block MB12 may be connected together and may share a line decoder with each other. The first bit line BL11 of the first sub-block MB11 and the second bit line BL12 of the second sub-block MB12 may be connected together and may share a page buffer with each other.

[0139] The third sub-block MB21 and the fourth sub-block MB22 can be stacked on the third-to-III layer. The third word line WL21 of the third sub-block MB21 and the fourth word line WL22 of the fourth sub-block MB22 can be connected together and can share the line decoder. The third bit line BL21 of the third sub-block MB21 and the fourth bit line BL22 of the fourth sub-block MB22 can be connected together and can share the page buffer.

[0140] Will Figure 8A and Figure 8B When compared to each other, Figure 8A The memory capacity of the semiconductor device shown is Figure 8B When the memory capacities of the semiconductor devices shown are the same, Figure 8B The bit line length and / or word line length can be less than Figure 8A The bit line length and / or word line length. By reducing this length, the bit line load and / or word line load can be reduced.

[0141] The structure and manufacturing method according to the above embodiments can be applied to semiconductor devices with various structures. Figure 9 and Figure 10 A schematic configuration of a semiconductor device to which the above embodiments are applicable is shown.

[0142] Figure 9 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0143] Reference Figure 9 The semiconductor device may include a substrate SUB, peripheral circuitry PC, and memory cell array CA. Here, the peripheral circuitry PC and memory cell array CA may be formed on the same substrate.

[0144] The substrate SUB may include a semiconductor material. As an example, the semiconductor material may include at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Here, group IV semiconductors may include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. Group II-VI compound semiconductors may include ZnS, ZnO, or CdS.

[0145] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include organic materials. As an example, the substrate SUB may include graphene.

[0146] The substrate SUB can be a bulk wafer or an epitaxial layer grown using a selective epitaxial growth (SEG) method. The substrate SUB can be a layer formed using a metal-induced lateral crystallization (MILC) method and may partially comprise a metal. The substrate SUB can be monocrystalline, polycrystalline, or amorphous. The substrate SUB may include Group II, III, IV, V, or VI impurities. As an example, the substrate SUB may include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0147] The peripheral circuitry PC may be located between the substrate SUB and the memory cell array CA. The peripheral circuitry PC may include row decoders, column decoders, page buffers, logic circuits, control circuits, sense amplifiers, input / output circuits, etc. As an example, the peripheral circuitry PC may include N-channel metal-oxide-semiconductor (NMOS) transistors, P-channel metal-oxide-semiconductor (PMOS) transistors, resistors, capacitors, etc. The peripheral circuitry PC may also include interconnect structures. These interconnect structures can serve as paths for transmitting operating voltages and may include contact plugs, wiring, etc.

[0148] A memory cell array (CA) may include memory cells. As an example, the memory cell array (CA) may include memory strings connected between source lines and bit lines, and each memory string may include stacked memory cells. As an example, the memory cell array (CA) may include memory cells connected between word lines and bit lines. The memory cell array (CA) may also include interconnect structures.

[0149] Figure 10 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0150] Reference Figure 10The semiconductor device may include a substrate SUB, peripheral circuitry PC, bonding structure BS, and memory cell array CA. Here, the peripheral circuitry PC and memory cell array CA may be formed on separate substrates and then bonded together. The semiconductor device may also include a support base SP_B.

[0151] The substrate SUB can be used as a support in the process of forming the peripheral circuit PC. The support base SP_B can be used as a support in the process of forming the memory cell array CA. As an example, a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC can be fabricated separately and then electrically connected to each other via a bonding structure BS. After the first wafer and the second wafer are bonded together, the support base SP_B of the first wafer can be at least partially removed. The support base SP_B can be completely removed or can be partially retained on the memory cell array CA.

[0152] The support substrate SP_B can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The support substrate SP_B can be a bulk wafer, an epitaxial layer grown by selective epitaxial growth (SEG), or a layer formed by metal-induced lateral crystallization (MILC). The support substrate SP_B can be monocrystalline, polycrystalline, or amorphous. The support substrate SP_B can include Group II, Group III, Group IV, Group V, or Group VI impurities.

[0153] A bonding structure BS can be used to connect a memory cell array (CA) and peripheral circuitry (PC) to each other. As an example, the bonding structure BS can bond the memory cell array (CA) and peripheral circuitry (PC) to each other using wafer stacking bonding methods, chip-on-wafer bonding methods, chip stacking bonding methods, etc. The bonding structure BS may include bonding pads, bonding layers, bonding interfaces, etc. Bonding pads may include metals such as copper or aluminum and / or alloys thereof. Bonding interfaces may include non-metal-to-non-metal interfaces, metal-to-metal interfaces, etc. The memory cell array (CA) and peripheral circuitry (PC) can be electrically connected to each other through the bonding structure BS.

[0154] For reference, interconnect structures included in the memory cell array (CA) and / or peripheral circuitry (PC) can also be directly connected to each other without bonding pads. As an example, bonding layers included in the memory cell array (CA) and bonding layers included in the peripheral circuitry (PC) can be bonded to each other to form a bonding interface, and interconnect structures included in the memory cell array (CA) and interconnect structures included in the peripheral circuitry (PC) can be directly connected to each other. Thus, contact plugs, wiring, etc., formed on different wafers can be electrically connected to each other without separate bonding pads.

[0155] Other configurations can be referenced above. Figure 9 Those described are the same or similar.

[0156] Semiconductor devices may also have the above reference. Figure 9 and Figure 10 The described embodiments are structures that combine with each other, or structures with partial modifications. (Refer to...) Figure 9 and Figure 10 In the described implementation, the positions of the memory cell array CA and the peripheral circuitry PC can be changed. (Refer to...) Figure 9 In the described implementation, at least one memory cell array CA and / or at least one peripheral circuit PC may be additionally connected. As an example, a portion of the peripheral circuit PC may be located within the memory cell array CA.

[0157] Figure 11 This is a simplified diagram of a memory system according to an embodiment of the present disclosure.

[0158] Reference Figure 11 The memory system 1000 may include a memory device 1200 for storing data and a controller 1100 for communicating between the memory device 1200 and the host 2000.

[0159] The host 2000 can be a device or system that stores data in or retrieves data from the memory system 1000. The host 2000 can generate requests for various operations and output these requests to the memory system 1000. Requests may include programming requests for programming operations, read requests for read operations, erase requests for erase operations, etc. The host 2000 can communicate with the memory system 1000 through various interfaces such as PCIe, Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), NVMe high-speed non-volatile memory (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Form Factor Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0160] The host 2000 may include at least one of a computer, a portable digital device, a portable personal computer (PC), a digital camera, a digital audio player, a television, a wireless communication device, and a cellular phone, but embodiments of the present disclosure are not limited thereto.

[0161] Controller 1100 controls the overall operation of memory system 1000. Controller 1100 can control memory device 1200 upon request from host 2000. Controller 1100 can control memory device 1200 to perform programming operations, read operations, erase operations, etc., upon request from host 2000. Alternatively, even without receiving a request from host 2000, controller 1100 can perform background operations to improve the performance characteristics of memory system 1000.

[0162] The controller 1100 can send control signals and data signals to the memory device 1200 to control the operation of the memory device 1200. The control signals and data signals can be sent to the memory device 1200 via different input / output lines. Data signals may include commands, addresses, or data. Control signals can be used to distinguish segments of input data signals from each other.

[0163] The memory device 1200 can perform programming operations, read operations, erase operations, etc., under the control of the controller 1100. The memory device 1200 can be implemented as a volatile memory device where the stored data is lost when power is interrupted, or as a non-volatile memory device that retains the stored data even when power is interrupted. The memory device 1200 can have the features described above. Figures 1A to 10 A semiconductor device with the described structure. As an example, the semiconductor device may include: a first memory cell array including a first source line, a first bit line, a first memory string connected between the first source line and the first bit line and including first memory cells, and a first word line connected to the first memory cells; a second memory cell array located above the first memory cell array and including a second source line, a second bit line, a second memory string connected between the second source line and the second bit line and including second memory cells, and a second word line connected to the second memory cells; a first interconnect structure including a first via through the first memory cell array and commonly connected to the first bit line and the second bit line; a second interconnect structure including a second via through the first memory cell array and commonly connected to the first word line and the second word line; a page buffer selectively accessing the first memory string or the second memory string through the first interconnect structure; and a row decoder jointly controlling the first word line and the second word line through the second interconnect structure.

[0164] Figure 12 This is a simplified diagram of a memory system according to an embodiment of the present disclosure.

[0165] Reference Figure 12The memory system 30000 can be implemented as a cellular phone, smartphone, tablet PC, personal computer (PC), personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 2200 and a controller 2100 capable of controlling the operation of the memory device 2200.

[0166] The controller 2100 can control the data access operations (e.g., programming operations, erasing operations, or reading operations) of the memory device 2200 under the control of the processor 3100.

[0167] The data programmed in the memory device 2200 can be output through the display 3200 under the control of the controller 2100.

[0168] The radio transceiver 3300 can transmit and receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and send the processed signals to the controller 2100 or the display 3200. The controller 2100 can send the signals processed by the processor 3100 to the memory device 2200. Alternatively, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 is a device capable of inputting control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100, and can be implemented as a pointing device such as a touchpad and computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200 so that data output from the controller 2100, the radio transceiver 3300, or the input device 3400 can be output through the display 3200.

[0169] According to the implementation, the controller 2100, which is capable of controlling the operation of the memory device 2200, may be implemented as part of the processor 3100 or as a chip separate from the processor 3100.

[0170] Figure 13 This is a simplified diagram of a memory system according to an embodiment of the present disclosure.

[0171] Reference Figure 13 The memory system 40000 can be implemented as a PC, tablet PC, netbook, e-reader, PDA, portable multimedia player (PMP), MP3 player or MP4 player.

[0172] The memory system 40000 may include a memory device 2200 and a controller 2100 capable of controlling data processing operations of the memory device 2200.

[0173] Based on the data input via the input device 4200, the processor 4100 can output the data stored in the memory device 2200 via the display 4300. For example, the input device 4200 can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard.

[0174] The processor 4100 can control the overall operation of the memory system 40000 and control the operation of the controller 2100. According to the embodiment, the controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 4100 or as a chip separate from the processor 4100.

[0175] Figure 14 This is a simplified diagram of a memory system according to an embodiment of the present disclosure.

[0176] Reference Figure 14 The memory system 50000 can be implemented as an image processing device, such as a digital camera, a cellular phone with a digital camera, a smartphone with a digital camera, or a tablet PC with a digital camera.

[0177] The memory system 50000 may include a memory device 2200 and a controller 2100 capable of controlling data processing operations (e.g., programming operations, erasing operations, or read operations) of the memory device 2200.

[0178] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals, and the converted digital signals can be sent to the processor 5100 or the controller 2100. Under the control of the processor 5100, the converted digital signals can be output through the display 5300 or stored in the memory device 2200 through the controller 2100. In addition, data stored in the memory device 2200 can be output through the display 5300 under the control of the processor 5100 or the controller 2100.

[0179] According to the implementation, the controller 2100, which is capable of controlling the operation of the memory device 2200, may be implemented as part of the processor 5100 or as a chip separate from the processor 5100.

[0180] Figure 15 This is a simplified diagram of a memory system according to an embodiment of the present disclosure.

[0181] Reference Figure 15The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 2200, a controller 2100, and a card interface 7100 that are operatively interconnected.

[0182] The controller 2100 controls the data exchange between the memory device 2200 and the card interface 7100. According to embodiments, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but the embodiments are not limited thereto.

[0183] Card interface 7100 can interface for data exchange between host 60000 and controller 2100 according to the protocol of host 60000. Depending on the implementation, card interface 7100 may support Universal Serial Bus (USB) protocol or IC-USB protocol. Here, card interface 7100 may refer to hardware capable of supporting the protocol used by host 60000, software installed in the hardware, or signal transmission method.

[0184] When the memory system 70000 is connected to the host interface 6200 of a host 60000 such as a PC, tablet PC, digital camera, digital audio player, cellular phone, video game console hardware or digital set-top box, the host interface 6200 can perform data communication with the memory device 2200 through the card interface 7100 and the controller 2100 under the control of the microprocessor 6100.

[0185] Although various embodiments of the present disclosure have been described above with reference to the accompanying drawings, these are merely illustrative of various embodiments based on the technical concept of the present disclosure. Furthermore, the embodiments of the present disclosure are not limited to those described above. Various substitutions, modifications, alterations, and combinations of various types can be made to the embodiments by those skilled in the art to which this disclosure pertains without departing from the technical concept and scope of the present disclosure as defined in the claims, and such substitutions, modifications, alterations, and combinations should be interpreted as falling within the scope of the present disclosure. In addition, these embodiments can be combined to form additional embodiments.

[0186] Cross-references to related applications

[0187] This application claims priority to Korean Patent Application No. 10-2024-0057300, filed on April 30, 2024, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A first memory cell array includes a first source line, a first bit line, a first memory string connected between the first source line and the first bit line, and a first word line connected to the first memory cell. The first memory string includes the first memory cell. A second memory cell array is located above the first memory cell array, and the second memory cell array includes a second source line, a second bit line, a second memory string connected between the second source line and the second bit line, and a second word line connected to the second memory cell, wherein the second memory string includes the second memory cell. A first interconnect structure, the first interconnect structure including a first via through the first memory cell array and commonly connected to the first bit line and the second bit line; A second interconnect structure includes a second via that passes through the first memory cell array and is commonly connected to the first word line and the second word line; A page buffer that selectively accesses either the first memory string or the second memory string through the first interconnect structure; as well as The line decoder controls the first word line and the second word line together through the second interconnect structure.

2. The semiconductor device according to claim 1, wherein, The first memory cell array includes: A first gate structure, the first gate structure including the first word line; The first bit line, the first bit line being located below the first gate structure; and The first source line is located above the first gate structure. The first via passes through the first gate structure and the first source line.

3. The semiconductor device according to claim 2, wherein, The second memory cell array includes: A second gate structure, the second gate structure including the second word line; The second bit line, the second bit line being located below the second gate structure; and The second source line is located above the second gate structure.

4. The semiconductor device of claim 3, further comprising a third memory cell array located above the second memory cell array, and the third memory cell array including a third source line, a third bit line, a third memory string connected between the third source line and the third bit line and including third memory cells, and a third word line connected to the third memory cells.

5. The semiconductor device according to claim 4, wherein, The first interconnect structure further includes a third via passing through the second memory cell array and connecting the second bit line and the third bit line to each other, and The second interconnect structure further includes a fourth via that passes through the second memory cell array and connects the second word line and the third word line to each other.

6. The semiconductor device according to claim 2, wherein, The second memory cell array includes: A second gate structure, the second gate structure including the second word line; The second source line is located below the second gate structure; and The second bit line is located above the second gate structure.

7. The semiconductor device according to claim 6, wherein, The first interconnect structure further includes a third via that passes through the second memory cell array and connects the second bit line and the first via to each other. The second interconnect structure further includes a fourth via that passes through the second memory cell array and connects the second word line and the second via to each other.

8. The semiconductor device according to claim 7, wherein, The first through hole and the third through hole are directly connected to each other, and The second through hole and the fourth through hole are directly connected to each other.

9. The semiconductor device according to claim 1, wherein, The first memory cell array includes: A first gate structure, the first gate structure including the first word line; The first source line is located below the first gate structure; and The first bit line is located above the first gate structure.

10. The semiconductor device according to claim 9, wherein, The second memory cell array includes: A second gate structure, the second gate structure including the second word line; The second bit line, the second bit line being located below the second gate structure; and The second source line is located above the second gate structure.

11. The semiconductor device according to claim 1, wherein, The first interconnect structure includes bonding pads that electrically connect the first memory cell array and the second memory cell array to each other.

12. The semiconductor device according to claim 1, wherein, The first memory string and the second memory string are included in the same memory block.

13. The semiconductor device of claim 1, further comprising a third interconnect structure including a third via passing through the first memory cell array and commonly connected to the first source line and the second source line.

14. The semiconductor device of claim 13, further comprising a source control circuit that controls the first source line and the second source line together through the third interconnect structure.

15. The semiconductor device of claim 1, further comprising a source control circuit that separately controls the first source line and the second source line.

16. A semiconductor device comprising: A first gate structure, the first gate structure including stacked first word lines; A second gate structure is located above the first gate structure and includes stacked second word lines; The first line is located below the first gate structure; A first source line is located between the first gate structure and the second gate structure; The second bit line is located between the first source line and the second gate structure; The second source line is located above the second gate structure; A first via passes through the first source line and the first gate structure and connects the first bit line and the second bit line to each other. A second via passes through the first gate structure and connects the first word line and the second word line to each other. A page buffer, which is connected to the first bit line and the second bit line through the first via; as well as The line decoder controls the first word line and the second word line together through the second via.

17. The semiconductor device of claim 16, further comprising: A third gate structure is located above the second gate structure and includes stacked third word lines; The third bit line is located between the third gate structure and the second gate structure; as well as A third via passes through the second gate structure and connects the second bit line and the third bit line to each other.

18. The semiconductor device of claim 17, further comprising a fourth via through the second gate structure and connecting the second word line and the third word line to each other.

19. The semiconductor device of claim 16, further comprising a third via through a dummy region of the first gate structure and connecting the first source line and the second source line to each other.

20. The semiconductor device of claim 19, further comprising a source control circuit that controls the first source line and the second source line together through the third via.

21. The semiconductor device of claim 16, further comprising source control circuitry for separately controlling the first source line and the second source line.

22. A semiconductor device comprising: A first memory cell array, the first memory cell array including a first source line, a first bit line, a first memory string connected between the first source line and the first bit line and including first memory cells, and a first word line connected to the first memory cells. A second memory cell array is electrically connected to the first memory cell array, and the second memory cell array includes a second source line, a second bit line, a second memory string connected between the second source line and the second bit line and including second memory cells, and a second word line connected to the second memory cells. as well as The peripheral circuitry is electrically connected to the first memory cell array via bonding pads and includes a page buffer for selectively accessing the first memory string or the second memory string, a row decoder that jointly controls the first word line and the second word line, and a source control circuitry that jointly controls the first source line and the second source line.

Images